WO2018133148A1 - 薄膜晶体管及其制作方法、液晶面板 - Google Patents

薄膜晶体管及其制作方法、液晶面板 Download PDF

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Publication number
WO2018133148A1
WO2018133148A1 PCT/CN2017/073802 CN2017073802W WO2018133148A1 WO 2018133148 A1 WO2018133148 A1 WO 2018133148A1 CN 2017073802 W CN2017073802 W CN 2017073802W WO 2018133148 A1 WO2018133148 A1 WO 2018133148A1
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source
film transistor
thin film
layer
drain
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PCT/CN2017/073802
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English (en)
French (fr)
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黄贵华
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深圳市华星光电技术有限公司
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Priority to US15/509,506 priority Critical patent/US20180231816A1/en
Publication of WO2018133148A1 publication Critical patent/WO2018133148A1/zh

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    • H—ELECTRICITY
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    • H01L29/78651—Silicon transistors
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    • H01L29/78663—Amorphous silicon transistors
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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Definitions

  • the invention relates to the field of display technology, in particular to a thin film transistor based on an IPS structure, a manufacturing method thereof and a liquid crystal panel.
  • the semiconductor channel of the TFT device in the TFT (Thin Film Transistor) array substrate mostly adopts a two-dimensional planar structure, and the channel length is relatively long, thereby limiting the switching ratio of the TFT device; the size of the TFT device in the TFT array substrate It will be made larger, resulting in a lower aperture ratio; in the TFT manufacturing process, multiple masks (generally at least 5 masks) are required, which is cumbersome and costly. These all restrict the development of TFT array substrates.
  • the present invention provides a thin film transistor, a method of fabricating the same, and a liquid crystal panel, thereby improving the switching ratio of the TFT device and also increasing the aperture ratio.
  • the present invention provides a thin film transistor including a substrate on which a patterned source and a common electrode are deposited, and a source layer and a common electrode are covered with a liner layer, the source being away from the side of the common electrode Forming a bare portion outside the pad layer, depositing a drain on the pad layer and patterning a pixel electrode, the pixel electrode being deposited on one side of the source, the exposed portion, and the side of the substrate on the source.
  • the patterned semiconductor layer, the gate insulating layer, and the patterned gate electrode form a semiconductor channel having a stepped structure, and the pixel electrode is connected to the source through the semiconductor layer.
  • drain and the pad layer have a slope angle of 45-60 degrees.
  • the liner layer is made of SiOx or SiNx.
  • the liner layer has a thickness of 300 to 1200 nm.
  • the semiconductor layer is one of IGZO or a-Si materials.
  • the source and the drain are composed of a metal layer or a metal laminate structure composed of a plurality of metal layers.
  • the source and drain have a thickness of 100-400 nm.
  • the invention also provides a method for fabricating a thin film transistor, comprising the following steps:
  • Step 1 depositing a source and a common electrode on the substrate, respectively, and patterning the source and the common electrode respectively;
  • Step 2 depositing a pad layer and a drain on the source and the common electrode, and the side of the source away from the common electrode is formed by etching the pad layer and the drain to make the source away from the side of the common electrode. a bare portion, the drain electrode is patterned to form a pixel electrode;
  • Step 3 depositing a semiconductor layer on one side of the substrate on the substrate, the exposed portion of the source, and the side of the pixel electrode on the source, and patterning the semiconductor layer to deposit a gate insulating layer on the semiconductor layer; A gate electrode is deposited on the gate insulating layer and patterned to obtain a semiconductor channel having a stepped structure, and the source is connected to the pixel electrode through the semiconductor layer.
  • slope angles of the drain and the pad layer in the first step and the second step are 45-60 degrees.
  • the present invention also provides a liquid crystal panel comprising a TFT array substrate, the TFT array substrate comprising the thin film transistor.
  • the present invention improves the switching ratio of the thin film transistor and the aperture ratio by setting the semiconductor channel of the thin film transistor to a stepped structure, and forms an IPS structure by using the drain as a pixel electrode, thereby enabling application.
  • the thin film transistor is fabricated through three processes, which reduces the process flow and saves costs.
  • FIG. 1 is a schematic structural view of the first step of the method for fabricating a thin film transistor of the present invention
  • FIG. 2 is a schematic structural view of the second step of the method for fabricating a thin film transistor of the present invention
  • FIG. 3 is a schematic structural view of the third step of the method for fabricating a thin film transistor of the present invention.
  • Figure 4 is a plan view of the present invention.
  • a thin film transistor of the present invention includes a substrate 1 on which a patterned source 2 and a patterned common electrode (COM) 3 are deposited.
  • the source 2 and the common electrode 3 are disposed in the same layer, and the source 2 and the common electrode 3 are covered with a spacer 4, which is away from the side of the common electrode 3 (left side of FIG. 3)
  • a bare portion 5 is formed outside the liner layer 4, a drain is deposited on the liner layer 4 and patterned to form a pixel electrode 6, which is located on one side of the source 2 (left side of FIG.
  • the exposed portion 5 and the substrate 1 are disposed on one side of the source 2 with a patterned semiconductor layer 8, a gate insulating layer 9, and a patterned gate 10, thereby forming a semiconductor channel 7 having a stepped structure.
  • the pixel electrode 6 is connected to the source 2 through the semiconductor layer 8.
  • the present invention forms the semiconductor channel 7 into a stepped structure 7 having a vertical plane, which improves the switching ratio and aperture ratio of the thin film transistor, and simultaneously uses the drain as an IPS.
  • the structured pixel electrode can be applied to high resolution panels.
  • the semiconductor layer 8, the gate insulating layer 9, and the gate electrode 10 are higher than the surface of the pixel electrode 6.
  • the drain 2 and the liner layer 4 have a slope angle of 45-60 degrees for subsequent deposition of the film layer.
  • the pad layer 4 is made of SiOx or SiNx, and the pad layer 4 has a thickness of 300-1200 nm;
  • the semiconductor layer 8 is one of IGZO or a-Si materials;
  • the drain 6 is composed of a metal layer or a metal laminate structure composed of a plurality of metal layers, such as a metal laminate made of a material such as Mo, Mo/Al/Mo, Mo/Ti, and the like, and has a thickness of 100 to 400 nm.
  • a method of fabricating a thin film transistor of the present invention comprises the following steps:
  • Step 1 as shown in FIG. 1 , the source 2 and the common electrode 3 are respectively deposited on the substrate 1 by using the prior art, and the source 2 and the common electrode 3 are respectively patterned;
  • Step 2 as shown in FIG. 2, the pad layer 4 and the drain are deposited on the source 2 and the common electrode 3 by the prior art, and the source 2 is separated from the side of the common electrode 3 (on the left side of FIG. 2). Etching the pad layer 4 and the drain to form a bare portion 5 on the side of the source 2 away from the common electrode 3; forming a pixel electrode 6 after patterning the drain;
  • Step 3 as shown in FIG. 3 and FIG. 4, a semiconductor layer 8 is deposited on one side of the substrate 1 on the source 2, the exposed portion 5 of the source 2, and the pixel electrode 6 on one side of the source 2.
  • Semiconductor layer 8 After patterning, a gate insulating layer 9 is deposited on the semiconductor layer 8; a gate electrode 10 is deposited on the gate insulating layer 9 and patterned to obtain a semiconductor channel 7 having a stepped structure, the source 2 passing through the semiconductor The layer 8 is connected to the pixel electrode 6.
  • the slope angle of the drain and the liner layer 4 in the first step and the second step is 45-60 degrees.
  • the pad layer 4 is made of SiOx or SiNx, and the pad layer 4 has a thickness of 300-1200 nm;
  • the semiconductor layer 8 is one of IGZO or a-Si materials;
  • the drain 6 is composed of a metal layer or a metal laminate structure composed of a plurality of metal layers, such as a metal laminate made of a material such as Mo, Mo/Al/Mo, Mo/Ti, and the like, and has a thickness of 100 to 400 nm.
  • the etching of the drain and liner layer 4 is performed by an etching process using a dry humidification method.
  • the method for fabricating the thin film transistor of the invention can produce a thin film transistor in three processes, which reduces the process flow and saves cost.
  • the present invention also discloses a liquid crystal panel comprising the above-mentioned thin film transistor, which will not be described herein.

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Abstract

本发明提供了一种薄膜晶体管，包括基板，所述基板上沉积有图案化的源极以及公共电极，在源极以及公共电极上覆盖有衬垫层，所述源极远离公共电极的一侧裸露在衬垫层外形成裸露部，在衬垫层上沉积漏极并图案化形成像素电极，所述像素电极位于源极的一侧、裸露部以及基板位于源极的一侧上依次沉积有图案化的半导体层、栅极绝缘层以及图案化的栅极，从而形成截面为阶梯结构的半导体沟道，所述像素电极通过半导体层与源极连接。本发明还提供了一种薄膜晶体管的制作方法以及液晶面板与现有技术相比，提高了薄膜晶体管的开关比，也提高了开口率；能够应用于高解析度面板上；减少了工艺流程，节约成本。

Description

薄膜晶体管及其制作方法、液晶面板 技术领域
本发明涉及一种显示技术领域，特别是一种基于IPS结构的薄膜晶体管及其制作方法、液晶面板。
背景技术
目前TFT(薄膜晶体管)阵列基板中TFT器件的半导体沟道大多采用二维平面结构，沟道长度均会做得比较长，从而限制了TFT器件的开关比；TFT阵列基板中的TFT器件的尺寸会做得比较大，导致降低了开口率；TFT制作过程中，需要使用多道光罩(一般至少5道光罩)，制程繁琐且成本较高。这些都制约了TFT阵列基板的发展。
发明内容
为克服现有技术的不足，本发明提供一种薄膜晶体管及其制作方法、液晶面板，从而提高TFT器件的开关比，而且也提高了开口率。
本发明提供了一种薄膜晶体管，包括基板，所述基板上沉积有图案化的源极以及公共电极，在源极以及公共电极上覆盖有衬垫层，所述源极远离公共电极的一侧裸露在衬垫层外形成裸露部，在衬垫层上沉积漏极并图案化形成像素电极，所述像素电极位于源极的一侧、裸露部以及基板位于源极的一侧上依次沉积有图案化的半导体层、栅极绝缘层以及图案化的栅极，从而形成截面为阶梯结构的半导体沟道，所述像素电极通过半导体层与源极连接。
进一步地，所述漏极以及衬垫层的坡度角为45-60度。
进一步地，所述衬垫层采用SiOx或SiNx制成。
进一步地，所述衬垫层的厚度为300-1200nm。
进一步地，所述半导体层为IGZO或a-Si材料中的一种。
进一步地，所述源极及漏极由一层金属层构成或由多层金属层构成的金属叠层结构。
进一步地，所述源极及漏极的厚度为100-400nm。
本发明还提供了一种薄膜晶体管的制作方法，包括如下步骤：
步骤一、在基板上分别沉积源极及公共电极，并对源极和公共电极分别进行图案化；
步骤二、在源极以及公共电极上沉积衬垫层以及漏极，所述源极远离公共电极的一侧通过对衬垫层以及漏极进行刻蚀，使源极远离公共电极的一侧形成裸露部，对漏极图形化后形成像素电极；
步骤三、在基板上位于源极的一侧、源极的裸露部以及像素电极位于源极的一侧上沉积有半导体层，对半导体层进行图案化后在半导体层上沉积栅极绝缘层；在栅极绝缘层上沉积栅极并进行图案化，得到截面为阶梯结构的半导体沟道，所述源极通过半导体层与像素电极连接。
进一步地，所述步骤一以及步骤二中漏极以及衬垫层的坡度角为45-60度。
本发明还提供了一种液晶面板，包括TFT阵列基板，所述TFT阵列基板包括所述的薄膜晶体管。
本发明与现有技术相比，通过将薄膜晶体管的半导体沟道设置为阶梯结构，提高了薄膜晶体管的开关比，也提高了开口率；而将漏极作为像素电极形成IPS结构，使得能够应用于高解析度面板上；而通过三道工序制作薄膜晶体管，减少了工艺流程，节约成本。
附图说明
图1是本发明的薄膜晶体管制作方法步骤一的结构示意图；
图2是本发明的薄膜晶体管制作方法步骤二的结构示意图；
图3是本发明的薄膜晶体管制作方法步骤三的结构示意图；
图4是本发明平面投影图。
具体实施方式
下面结合附图和实施例对本发明作进一步详细说明。
如图3和图4所示，本发明的一种薄膜晶体管，包括基板1，所述基板1上沉积有图案化的源极(Source)2以及图案化的公共电极(COM)3，所述源极2以及公共电极3设于同一层，在源极2以及公共电极3上覆盖有衬垫层(Spacer)4，所述源极2远离公共电极3的一侧(图3的左侧)裸露在衬垫层4外形成裸露部5，在衬垫层4上沉积漏极(Drain)并图案化形成像素电极6，所述像素电极6位于源极2的一侧(图3的左侧)、裸露部5以及基板1位于源极2的一侧上依次沉积有图案化的半导体层8、栅极绝缘层9以及图案化的栅极10，从而形成截面为阶梯结构的半导体沟道7，所述像素电极6通过半导体层8与源极2连接，本发明将半导体沟道7制作成具有垂直面的阶梯结构7，提高了薄膜晶体管的开关比以及开口率；同时利用漏极作为IPS结构的像素电极，可以应用于高解析度面板上。
本发明中半导体层8、栅极绝缘层9以及栅极10高于像素电极6的表面。
所述漏极2以及衬垫层4的坡度角为45-60度，以便后续膜层的沉积。
具体地，所述衬垫层4采用SiOx或SiNx制成，衬垫层4的厚度为300-1200nm；所述半导体层8为IGZO或a-Si材料中的一种；所述源极2及漏极6由一层金属层构成或由多层金属层构成的金属叠层结构，如Mo、Mo/Al/Mo、Mo/Ti等材料构成的金属叠层，厚度为100-400nm。
本发明的一种薄膜晶体管的制作方法，包括如下步骤：
步骤一、如图1所示，在基板1上分别采用现有技术沉积源极2及公共电极3，并对源极2和公共电极3分别进行图案化；
步骤二、如图2所示，在源极2以及公共电极3上通过现有技术沉积衬垫层4以及漏极，所述源极2远离公共电极3的一侧(图2左侧)通过对衬垫层4以及漏极的刻蚀使源极2远离公共电极3的一侧形成裸露部5；对漏极图形化后形成像素电极6；
步骤三、如图3和图4所示，在基板1上位于源极2的一侧、源极2的裸露部5以及像素电极6位于源极2的一侧上沉积有半导体层8，对半导体层8 进行图案化后在半导体层8上沉积栅极绝缘层9；在栅极绝缘层9上沉积栅极10并进行图案化，得到截面为阶梯结构的半导体沟道7，所述源极2通过半导体层8与像素电极6连接。
所述步骤一以及步骤二中漏极以及衬垫层4的坡度角为45-60度。
具体地，所述衬垫层4采用SiOx或SiNx制成，衬垫层4的厚度为300-1200nm；所述半导体层8为IGZO或a-Si材料中的一种；所述源极2及漏极6由一层金属层构成或由多层金属层构成的金属叠层结构，如Mo、Mo/Al/Mo、Mo/Ti等材料构成的金属叠层，厚度为100-400nm。
所述漏极及衬垫层4的蚀刻采用干法加湿法的刻蚀工艺进行。
本发明的薄膜晶体管的制作方法只需三道工序即可制作出薄膜晶体管，减少了工艺流程，节约了成本。
本发明还公开了一种液晶面板，所述TFT阵列基板包括上述的薄膜晶体管，在此不在赘述。
虽然已经参照特定实施例示出并描述了本发明，但是本领域的技术人员将理解：在不脱离由权利要求及其等同物限定的本发明的精神和范围的情况下，可在此进行形式和细节上的各种变化。

Claims (20)

  1. 一种薄膜晶体管，包括基板，其中：所述基板上沉积有图案化的源极以及公共电极，在源极以及公共电极上覆盖有衬垫层，所述源极远离公共电极的一侧裸露在衬垫层外形成裸露部，在衬垫层上沉积漏极并图案化形成像素电极，所述像素电极位于源极的一侧、裸露部以及基板位于源极的一侧上依次沉积有图案化的半导体层、栅极绝缘层以及图案化的栅极，从而形成截面为阶梯结构的半导体沟道，所述像素电极通过半导体层与源极连接。
  2. 根据权利要求1所述的薄膜晶体管，其中：所述漏极以及衬垫层的坡度角为45-60度。
  3. 根据权利要求1所述的薄膜晶体管，其中：所述衬垫层采用SiOx或SiNx制成。
  4. 根据权利要求1所述的薄膜晶体管，其中：所述衬垫层的厚度为300-1200nm。
  5. 根据权利要求2所述的薄膜晶体管，其中：所述衬垫层的厚度为300-1200nm。
  6. 根据权利要求1所述的薄膜晶体管，其中：所述半导体层为IGZO或a-Si材料中的一种。
  7. 根据权利要求1所述的薄膜晶体管，其中：所述源极及漏极由一层金属层构成或由多层金属层构成的金属叠层结构。
  8. 根据权利要求1所述的薄膜晶体管，其中：所述源极及漏极的厚度为100-400nm。
  9. 根据权利要求6所述的薄膜晶体管，其中：所述源极及漏极的厚度为100-400nm。
  10. 一种薄膜晶体管的制作方法，其中：包括如下步骤：
    步骤一、在基板上分别沉积源极及公共电极，并对源极和公共电极分别进 行图案化；
    步骤二、在源极以及公共电极上沉积衬垫层以及漏极，所述源极远离公共电极的一侧通过对衬垫层以及漏极进行刻蚀，使源极远离公共电极的一侧形成裸露部，对漏极图形化后形成像素电极；
    步骤三、在基板上位于源极的一侧、源极的裸露部以及像素电极位于源极的一侧上沉积有半导体层，对半导体层进行图案化后在半导体层上沉积栅极绝缘层；在栅极绝缘层上沉积栅极并进行图案化，得到截面为阶梯结构的半导体沟道，所述源极通过半导体层与像素电极连接。
  11. 根据权利要求10所述的薄膜晶体管的制作方法，其中：所述步骤一以及步骤二中漏极以及衬垫层的坡度角为45-60度。
  12. 一种液晶面板，包括TFT阵列基板，其中：所述TFT阵列基板包括薄膜晶体管，所述薄膜晶体管包括基板，所述基板上沉积有图案化的源极以及公共电极，在源极以及公共电极上覆盖有衬垫层，所述源极远离公共电极的一侧裸露在衬垫层外形成裸露部，在衬垫层上沉积漏极并图案化形成像素电极，所述像素电极位于源极的一侧、裸露部以及基板位于源极的一侧上依次沉积有图案化的半导体层、栅极绝缘层以及图案化的栅极，从而形成截面为阶梯结构的半导体沟道，所述像素电极通过半导体层与源极连接。
  13. 根据权利要求12所述的薄膜晶体管，其中：所述漏极以及衬垫层的坡度角为45-60度。
  14. 根据权利要求12所述的薄膜晶体管，其中：所述衬垫层采用SiOx或SiNx制成。
  15. 根据权利要求12所述的薄膜晶体管，其中：所述衬垫层的厚度为300-1200nm。
  16. 根据权利要求13所述的薄膜晶体管，其中：所述衬垫层的厚度为300-1200nm。
  17. 根据权利要求12所述的薄膜晶体管，其中：所述半导体层为IGZO 或a-Si材料中的一种。
  18. 根据权利要求12所述的薄膜晶体管，其中：所述源极及漏极由一层金属层构成或由多层金属层构成的金属叠层结构。
  19. 根据权利要求12所述的薄膜晶体管，其中：所述源极及漏极的厚度为100-400nm。
  20. 根据权利要求14所述的薄膜晶体管，其中：所述源极及漏极的厚度为100-400nm。
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