WO2023044950A1 - 薄膜晶体管、显示面板及其制备方法 - Google Patents

薄膜晶体管、显示面板及其制备方法 Download PDF

Info

Publication number
WO2023044950A1
WO2023044950A1 PCT/CN2021/121819 CN2021121819W WO2023044950A1 WO 2023044950 A1 WO2023044950 A1 WO 2023044950A1 CN 2021121819 W CN2021121819 W CN 2021121819W WO 2023044950 A1 WO2023044950 A1 WO 2023044950A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
layer
insulating layer
active layer
gate
Prior art date
Application number
PCT/CN2021/121819
Other languages
English (en)
French (fr)
Inventor
卢马才
柳铭岗
刘念
Original Assignee
Tcl华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tcl华星光电技术有限公司 filed Critical Tcl华星光电技术有限公司
Priority to US17/611,118 priority Critical patent/US20240047537A1/en
Priority to JP2021560071A priority patent/JP2024504881A/ja
Publication of WO2023044950A1 publication Critical patent/WO2023044950A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate

Definitions

  • the present application relates to the field of display technology, in particular to a thin film transistor, a display panel and a preparation method thereof.
  • Embodiments of the present application provide a thin film transistor, a display panel and a manufacturing method thereof, which can effectively improve the comprehensive electrical performance of the thin film transistor.
  • An embodiment of the present application provides a thin film transistor, including: a gate; a gate insulating layer disposed on one side of the gate; an active layer disposed on a side of the gate insulating layer away from the gate , the active layer is disposed opposite to the gate; a first electrode is disposed on a side of the active layer away from the gate; an interlayer insulating layer is disposed on the first electrode and the active
  • the source layer insulates the first electrode from the active layer, and the interlayer insulating layer is provided with a first via hole penetrating through the interlayer insulating layer and extending to the surface of the first electrode, so
  • the active layer is connected to the first electrode through the first via hole, the thickness of the interlayer insulating layer is greater than the thickness of the gate insulating layer; and the second electrode is connected to the active layer, The second electrode is located at the same layer as the active layer.
  • the thin film transistor further includes: an auxiliary electrode disposed opposite to the active layer, and the interlayer insulating layer is disposed between the auxiliary electrode and the active layer between.
  • the first electrode and the auxiliary electrode are located on the same layer, and the active layer is connected to the first electrode through the first via hole.
  • the active layer includes a semiconductor part and a first electrode contact part, and the conductivity of the first electrode contact part is smaller than that of the first electrode, so The conductivity of the first electrode contact portion is greater than the conductivity of the semiconductor portion; the first electrode contact portion is connected to the first electrode through the first via hole.
  • the embodiment of the present application also provides a display panel, including: a first electrode located on the first metal layer; an interlayer insulating layer disposed on the first electrode, and an interlayer insulating layer is opened on the interlayer insulating layer.
  • the interlayer insulating layer extends to the first via hole on the surface of the first electrode; the active layer is arranged on the interlayer insulating layer, and the active layer passes through the first via hole and the first electrode connected; a second electrode connected to the active layer; a gate insulating layer disposed on the active layer; and a gate located on a second metal layer disposed on the gate insulating layer and connected to the gate insulating layer
  • the active layer is arranged opposite to each other; the thickness of the interlayer insulating layer is greater than the thickness of the gate insulating layer.
  • the display panel further includes: an auxiliary electrode disposed opposite to the active layer, and the interlayer insulating layer is disposed between the auxiliary electrode and the active layer between; the first electrode is a drain, and the second electrode is a source; and/or, the first electrode is a source, and the second electrode is a drain.
  • the auxiliary electrode is located on the first metal layer, and the interlayer insulating layer covers the first electrode and the auxiliary electrode.
  • the active layer includes a semiconductor part and a first electrode contact part, and the conductivity of the first electrode contact part is smaller than that of the first electrode, so The conductivity of the first electrode contact portion is greater than the conductivity of the semiconductor portion; the first electrode contact portion is connected to the first electrode through the first via hole.
  • a pixel electrode is also included, the pixel electrode is arranged on the same layer as the active layer, the pixel electrode is electrically connected to the active layer, and the active layer
  • the layers include metal oxide semiconductors.
  • the display panel further includes: a substrate on which the first metal layer is disposed, and the first metal layer further includes data lines; scan lines located on the the second metal layer, the scanning line intersects the data line to define a plurality of sub-pixel units, the gate, the second electrode, the first electrode, the thin film transistor composed of the active layer and The pixel electrodes connected to the thin film transistors are located in the sub-pixel unit; the passivation layer is arranged on the second metal layer, covering the gate and the pixel electrodes; the common electrode is arranged on the On the passivation layer, the common electrode is disposed opposite to the pixel electrode.
  • side edges of the gate, the gate insulating layer, and the semiconductor part of the active layer are flush.
  • the thickness of the interlayer insulating layer is greater than or equal to twice the thickness of the gate insulating layer.
  • the first metal layer further includes a touch signal line;
  • the display panel further includes: a first touch electrode, the first touch electrode and the The active layer is disposed on the same layer, the first touch electrode is connected to the active layer; and the second touch electrode is insulated from the first touch electrode and arranged opposite to each other.
  • the embodiment of the present application also provides a method for preparing a display panel, including:
  • the active layer is connected to the first electrode through the first via hole, and the active layer includes a metal oxide semiconductor
  • the thickness of the interlayer insulating layer is greater than or equal to twice the thickness of the gate insulating layer; patterning the second metal layer to form a gate, so that the gate is disposed opposite to the active layer; the gate insulating layer is patterned using the patterned gate as a mask to expose the gate insulating layer located above the first electrode. the active layer; using the patterned gate as a mask to metallize the exposed active layer to form a second electrode connected to the active layer and a first electrode contact part, the first electrode contact part is connected to the first electrode through the first via hole.
  • the first electrode and the gate of the thin film transistor are arranged on both sides of the active layer, by placing the gate insulation layer between the gate and the active layer and the first electrode and the active layer
  • the interlayer insulating layer is set independently, so that the thickness of the gate insulating layer between the gate and the active layer and the thickness of the interlayer insulating layer between the first electrode and the active layer can be adjusted independently.
  • the withstand voltage characteristics between the gate and the drain (first electrode) can be increased by increasing the thickness of the interlayer insulating layer, and the increase in the thickness of the interlayer insulating layer It can also reduce the capacitance between the gate and the drain (first electrode), and can significantly improve various electrical properties of the thin film transistor.
  • the patterning of the gate insulating layer and the metallization of the active layer are completed through the self-alignment process of the gate, which reduces two photomasks and reduces the production cost.
  • FIG. 1 is a schematic cross-sectional view of a specific embodiment of a thin film transistor provided by the present application
  • FIG. 2 is a schematic cross-sectional view of the display area of the display panel in the first embodiment provided by the present application;
  • FIG. 3 is a schematic cross-sectional view of the display area of the display panel in the second embodiment provided by the present application.
  • 4A to 4G are schematic structural diagrams of the display panel in FIG. 2 during the manufacturing process.
  • the present application provides a thin film transistor, which includes a gate, a gate insulating layer, an active layer, an auxiliary electrode, an interlayer insulating layer, a first electrode and a second electrode.
  • the gate insulation layer is disposed on one side of the gate.
  • the active layer is arranged on the side of the gate insulation layer away from the gate.
  • the active layer is arranged opposite to the gate.
  • the auxiliary electrode is arranged opposite to the active layer.
  • the interlayer insulating layer is disposed between the auxiliary electrode and the active layer to insulate the auxiliary electrode and the active layer.
  • the thickness of the interlayer insulating layer is greater than that of the gate insulating layer.
  • the first electrode and the auxiliary electrode are located on the same layer.
  • a first via hole penetrating through the interlayer insulating layer and extending to the surface of the first electrode is opened on the interlayer insulating layer.
  • the active layer is connected to the first electrode through the first via hole.
  • the second electrode is connected to the active layer.
  • the second electrode is located on the same layer as the active layer.
  • a thin film transistor is disposed on a substrate 1 .
  • the substrate 1 is an array substrate.
  • the substrate 1 is a rigid substrate.
  • the rigid substrate 1 can be made of glass. It can be understood that the substrate 1 may also be a flexible substrate.
  • the flexible substrate 1 can be polyimide (Polyimide, PI) and/or polyethylene terephthalate (Polyethylene terephthalate) that can isolate water vapor and oxygen. Terephthalate, PET) and other organic insulating materials, which are not specifically limited here.
  • the first metal layer 2 is disposed on the substrate 1 .
  • the first metal layer 2 forms the first electrode 21 and the auxiliary electrode 22 of the thin film transistor through a patterning process.
  • the first metal layer 2 can be made of one or more common conductive metals or alloys such as Mo, Al, Ti and Cu.
  • the first metal layer 2 may be a single-layer conductive layer structure composed of a single metal, or a multi-layer conductive layer structure composed of multiple metals, which is not specifically limited here.
  • the first electrode 21 is a source or a drain. In this embodiment, the first electrode 21 is a drain connected to the data line.
  • the interlayer insulating layer 3 is disposed on the first metal layer 2 .
  • the interlayer insulating layer 3 covers the first electrode 21 and the auxiliary electrode 22 .
  • a first via hole 31 penetrating through the interlayer insulating layer 3 and extending to the surface of the first electrode 21 is opened on the interlayer insulating layer 3 .
  • the interlayer insulating layer 3 is generally formed by deposition or sputtering of one or more common inorganic materials such as SiNx, SiOx, Al2O3, which can isolate water vapor and oxygen.
  • the interlayer insulating layer 3 can also be prepared using an organic insulating layer to obtain a flat surface.
  • Active layer 4 is provided on interlayer insulating layer 3 .
  • the active layer 4 can be made of common semiconductor materials such as metal oxide, amorphous silicon and polysilicon.
  • the middle area of the active layer 4 is arranged corresponding to the auxiliary electrode 22 .
  • the active layer 4 includes a semiconductor portion 41 and a first electrode contact portion 42 .
  • the conductivity of the first electrode contact portion 42 is smaller than that of the first electrode 21 .
  • the conductivity of the first electrode contact portion 42 is greater than that of the semiconductor portion 41 .
  • the first electrode contact part 42 is connected with the first electrode 21 through the first via hole 31 .
  • the second electrode 5 is connected to the active layer 4 .
  • the second electrode 5 is connected to the semiconductor portion 41 .
  • the second electrode 5 is a drain or a source.
  • the second electrode 5 is connected to a pixel electrode or a source of other circuits.
  • the second electrode 5 is located at the same layer as the active layer 4 .
  • the second electrode 5 and the first electrode contact portion 42 are provided on both sides of the semiconductor portion 41, respectively.
  • a gate insulating layer 6 is provided on the active layer 4 .
  • the gate insulating layer 6 covers the semiconductor portion 41 .
  • the gate insulating layer 6 is generally formed by deposition or sputtering of one or several common inorganic materials such as SiNx, SiOx, Al2O3, which can isolate water vapor and oxygen.
  • a single insulating layer can meet the yield requirements of the display panel, but in display panels that use polysilicon or metal oxide as the active layer, in order to improve the yield, multiple insulating layers are also overlapped. structure to ensure effective isolation of water vapor and oxygen, the gate insulating layer 6 in this embodiment is a single-layer SiO2 or single-layer SiNx structure.
  • the gate electrode 71 is provided on the gate insulating layer 6 .
  • the gate electrode 71 is provided opposite to the semiconductor portion 41 .
  • the gate 71 can be made of one or more of common conductive metals or alloys such as Mo, Al, Ti and Cu.
  • the gate 71 may be a single-layer conductive layer structure composed of a single metal, or a multi-layer conductive layer structure composed of multiple metals, which is not specifically limited here.
  • the auxiliary electrode 22 is an auxiliary grid and/or a light-shielding electrode.
  • the auxiliary electrode 22 is provided opposite to the semiconductor portion 41 .
  • the auxiliary electrode 22 can be made of conductive materials such as metal or ITO, and the auxiliary electrode 22 is opposed to the semiconductor part 41 to effectively improve the electrical performance of the thin film transistor.
  • the auxiliary electrode 22 is made of metal or other opaque materials, it can be used as a light-shielding electrode.
  • the auxiliary electrode 22 is opposite to the semiconductor part 41 so as to prevent light from irradiating the semiconductor part 41 from affecting the electrical performance of the thin film transistor.
  • the first electrode 21 and the gate 71 are arranged on both sides of the active layer 4, the first electrode 21 and the active layer 4 are insulated by the interlayer insulating layer 3, and the gate 71 and the active layer 4 are insulated.
  • the source layers 4 are insulated by a gate insulating layer 6 .
  • the thickness of the thickness and the thickness of the interlayer insulating layer 3 between the source and drain electrodes and the active layer 4 can be adjusted independently, which can avoid thinning when the gate and the source and drain electrodes are arranged on the same side of the active layer in the prior art.
  • the thickness of the gate insulating layer is reduced to reduce Vgs, other electrical properties of the thin film transistor will be reduced.
  • the thickness of interlayer insulating layer 3 is set to be larger than the thickness of gate insulating layer 6 .
  • the thickness of the gate insulating layer 6 is thinned according to the Vgs target setting value of the thin film transistor. Since the thickness of the interlayer insulating layer 3 can be kept constant or increased at the same time, not only the gate 71 and the drain (first electrode 21 ) can be guaranteed ) is not affected by the thinning of the gate insulating layer 6, and the distance between the gate 71 and the drain (first electrode 21) can be reduced by appropriately increasing the thickness of the interlayer insulating layer 3. capacitance. Through the above design, various electrical properties of the thin film transistor can be greatly improved.
  • the thickness of the interlayer insulating layer 3 is greater than or equal to twice the thickness of the gate insulating layer 6 .
  • the thickness of the gate insulating layer 6 is one third of the thickness of the interlayer insulating layer 3 , the overall electrical performance of the thin film transistor is better.
  • the active layer 4 includes a metal oxide semiconductor, such as IGZO or IGZTO.
  • the gate insulating layer 6 is patterned by using the patterned gate 71 as a mask to expose the active layer 4 above the first electrode 21 .
  • the exposed active layer 4 is metallized by using the patterned gate 71 as a mask to form the second electrode 5 connected to the active layer 4 and the first electrode contact portion 42 .
  • the first electrode contact part 42 is connected with the first electrode 21 through the first via hole 31 .
  • the patterning of the gate insulating layer 6 and the metallization of the active layer 4 are completed through the self-alignment process of the gate 71 , which reduces two photomasks and reduces the production cost.
  • the present application also provides a first embodiment of a display panel.
  • the display panel includes a substrate 1 and a first metal layer 2 disposed on the substrate 1, an interlayer insulating layer 3, an active layer 4, a second electrode 5, a gate insulating layer 6, a second metal layer 7, a pixel electrode 8, Passivation layer 9 and common electrode layer 10.
  • the substrate 1 is an array substrate.
  • the substrate 1 is a rigid substrate.
  • the rigid substrate 1 can be made of glass. It can be understood that the substrate 1 may also be a flexible substrate.
  • the flexible substrate 1 can be made of organic insulating materials such as polyimide and/or polyethylene terephthalate capable of isolating water vapor and oxygen, and is not specifically limited here.
  • the first metal layer 2 is disposed on the substrate 1 .
  • the first metal layer 2 forms data lines (not shown in the figure), first electrodes 21 and auxiliary electrodes 22 of thin film transistors, and common electrode lines 23 through a patterning process.
  • the first metal layer 2 can be made of one or more common conductive metals or alloys such as Mo, Al, Ti and Cu.
  • the first metal layer 2 may be a single-layer conductive layer structure composed of a single metal, or a multi-layer conductive layer structure composed of multiple metals, which is not specifically limited here.
  • the first electrode 21 is a source or a drain. In this embodiment, the first electrode 21 is a drain connected to the data line.
  • the auxiliary electrode 22 is an auxiliary grid and/or a light-shielding electrode.
  • the auxiliary electrode 22 is provided opposite to the semiconductor portion 41 .
  • the auxiliary electrode 22 can be made of conductive materials such as metal or ITO, and the auxiliary electrode 22 is opposed to the semiconductor part 41 to effectively improve the electrical performance of the thin film transistor.
  • the auxiliary electrode 22 is made of metal or other opaque materials, it can be used as a light-shielding electrode.
  • the auxiliary electrode 22 is opposite to the semiconductor part 41 so as to prevent light from irradiating the semiconductor part 41 from affecting the electrical performance of the thin film transistor.
  • the interlayer insulating layer 3 is disposed on the first metal layer 2 .
  • the interlayer insulating layer 3 covers the data lines, the first electrodes 21 , the auxiliary electrodes 22 and the common electrode lines 23 .
  • a first via hole 31 penetrating through the interlayer insulating layer 3 and extending to the surface of the first electrode 21 is opened on the interlayer insulating layer 3 .
  • the interlayer insulating layer 3 is generally formed by deposition or sputtering of one or more common inorganic materials such as SiNx, SiOx, Al2O3, which can isolate water vapor and oxygen.
  • the interlayer insulating layer 3 in this embodiment is a single-layer SiO2 or single-layer SiNx structure.
  • the active layer 4 is provided on interlayer insulating layer 3 .
  • the active layer 4 can be made of common semiconductor materials such as metal oxide, amorphous silicon and polysilicon. In this embodiment, the active layer 4 is made of metal oxide semiconductor.
  • the middle area of the active layer 4 is arranged corresponding to the auxiliary electrode 22 .
  • the active layer 4 includes a semiconductor portion 41 and a first electrode contact portion 42 .
  • the conductivity of the first electrode contact portion 42 is smaller than that of the first electrode 21 .
  • the conductivity of the first electrode contact portion 42 is greater than that of the semiconductor portion 41 .
  • the first electrode contact part 42 is connected with the first electrode 21 through the first via hole 31 .
  • the second electrode 5 is connected to the active layer 4 .
  • the second electrode 5 is connected to the semiconductor portion 41 .
  • the second electrode 5 is a drain or a source.
  • the second electrode 5 is located at the same layer as the active layer 4 .
  • the second electrode 5 and the first electrode contact portion 42 are provided on both sides of the semiconductor portion 41, respectively.
  • a gate insulating layer 6 is provided on the active layer 4 .
  • the gate insulating layer 6 covers the semiconductor portion 41 .
  • the gate insulating layer 6 is generally formed by deposition or sputtering of one or several common inorganic materials such as SiNx, SiOx, Al2O3, which can isolate water vapor and oxygen.
  • a single insulating layer can meet the yield requirements of the display panel, but in display panels that use polysilicon or metal oxide as the active layer, in order to improve the yield, multiple insulating layers are also overlapped. structure to ensure effective isolation of water vapor and oxygen, the gate insulating layer 6 in this embodiment is a single-layer SiO2 or single-layer SiNx structure.
  • the second metal layer 7 is disposed on the gate insulating layer 6 .
  • the second metal layer 7 forms gates 71 and scanning lines of thin film transistors (not shown in the figure) through a patterning process.
  • the gate electrode 71 is provided opposite to the semiconductor portion 41 .
  • the second metal layer 7 can be made of one or more common conductive metals or alloys such as Mo, Al, Ti and Cu.
  • the second metal layer 7 may be a single-layer conductive layer structure composed of a single metal, or a multi-layer conductive layer structure composed of multiple metals, which is not specifically limited here.
  • the pixel electrode 8 is provided on the interlayer insulating layer 3 .
  • the pixel electrode 8 is disposed on the same layer as the active layer 4 and the second electrode 5 .
  • the pixel electrode 8 and the second electrode 5 are formed by performing metal doping on the active layer 4 .
  • the pixel electrode 8 and the second electrode 5 are integrally formed.
  • One end of the second electrode 5 is connected to the semiconductor portion 41 .
  • the other end of the second electrode 5 is connected to the pixel electrode 8 .
  • Both the pixel electrode 8 and the second electrode 5 are obtained by doping the oxide semiconductor layer with metal.
  • the second electrode 5 can be omitted or can be regarded as a part of the pixel electrode 8 , which is specifically determined according to the pattern of the pixel electrode 8 .
  • a passivation layer 9 is arranged on the second metal layer 7 .
  • the passivation layer 9 covers the gate electrode 71 , the scan line, the first electrode contact portion 42 , the second electrode 5 and the pixel electrode 8 .
  • a second via hole 91 penetrating through the passivation layer 9 and the interlayer insulating layer 3 and extending to the surface of the common electrode line 23 is opened on the passivation layer 9 .
  • the passivation layer 9 is generally formed by deposition or sputtering of one or several common inorganic materials such as SiNx, SiOx, Al2O3, which can isolate water vapor and oxygen.
  • a single insulating layer can meet the yield requirements of the display panel, but in display panels that use polysilicon or metal oxide as the active layer, in order to improve the yield, multiple insulating layers are also overlapped. structure to ensure effective isolation of water vapor and oxygen.
  • the common electrode 10 is disposed on the passivation layer 9 .
  • the common electrode 10 can be made of transparent ITO material.
  • the common electrode 10 is connected to the common electrode line 23 through the second via hole 91 .
  • the display panel in this embodiment is an FFS display panel, and the horizontal fringe electric field is generated to drive the liquid crystal to deflect by stacking the planar pixel electrodes 8 and the patterned common electrodes 10 one above the other.
  • the interlayer insulating layer 3 under the pixel electrodes 8 needs to be set as an organic insulating flat layer, so as to ensure that the pixel electrodes 8 are formed on the same horizontal plane as possible.
  • the common electrode 10 and the pixel electrode 8 are oppositely arranged to generate a horizontal electric field to drive the liquid crystal. It can be understood that the common electrode 10 may be in a "meter" shape, a comb shape or other patterns, which are not specifically limited here.
  • the first alignment layer (not shown in the figure) is disposed on the common electrode 10 to adjust the deflection angle of the liquid crystal.
  • the display panel further includes a substrate 11 , a color filter layer 12 , a light shielding layer 13 and a second alignment layer (not shown in the figure) disposed on the substrate 11 .
  • the substrate 11 is arranged opposite to the substrate 1 .
  • the material of the substrate 11 is the same as that of the substrate 1 and will not be repeated here.
  • the color filter layer 12 includes a plurality of filters 121 .
  • a filter 121 is disposed in each sub-pixel area.
  • the filter 121 is opposite to the pixel electrode 8 .
  • the light shielding layer 13 is disposed between two adjacent filters 121 to avoid color mixing.
  • the light-shielding layer 13 is generally made of black resin material.
  • the second alignment layer covers the color filter layer 12 and the light-shielding layer 13 to adjust the deflection angle of the liquid crystal.
  • the display panel further includes a liquid crystal layer (not shown in the figure) and a spacer (not shown in the figure) arranged between the substrate 1 and the substrate 11 .
  • the display area of the display panel is provided with a plurality of scan lines extending along the first direction and a plurality of data lines approximately extending along the second direction. The intersections of the scan lines and the data lines define a plurality of array-arranged sub-pixel regions.
  • the gate 71 , the second electrode 5 , the first electrode 21 , the thin film transistor composed of the active layer 4 and the pixel electrode 8 connected to the thin film transistor are all located in the sub-pixel unit.
  • the auxiliary electrode 22 is an auxiliary grid and/or a light-shielding electrode.
  • the auxiliary electrode 22 is provided opposite to the semiconductor portion 41 .
  • the auxiliary electrode 22 can be made of conductive materials such as metal or ITO, and the auxiliary electrode 22 is opposed to the semiconductor part 41 to effectively improve the electrical performance of the thin film transistor.
  • the auxiliary electrode 22 is made of metal or other opaque materials, it can be used as a light-shielding electrode.
  • the auxiliary electrode 22 is opposite to the semiconductor part 41 so as to prevent light from irradiating the semiconductor part 41 from affecting the electrical performance of the thin film transistor.
  • the first electrode 21 and the gate 71 of the thin film transistor are arranged on both sides of the active layer 4, and the first electrode 21 and the active layer 4 are insulated by the interlayer insulating layer 3,
  • the gate 71 is insulated from the active layer 4 by the gate insulating layer 6 .
  • the thickness of the thickness and the thickness of the interlayer insulating layer 3 between the source and drain electrodes and the active layer 4 can be adjusted independently, which can avoid thinning when the gate and the source and drain electrodes are arranged on the same side of the active layer in the prior art.
  • the thickness of the gate insulating layer is reduced to reduce Vgs, other electrical properties of the thin film transistor will be reduced.
  • the thickness of interlayer insulating layer 3 is set to be larger than the thickness of gate insulating layer 6 .
  • the thickness of the gate insulating layer 6 is thinned according to the Vgs target setting value of the thin film transistor. Since the thickness of the interlayer insulating layer 3 can be kept constant or increased at the same time, not only the gate 71 and the drain (first electrode 21 ) can be guaranteed ) is not affected by the thinning of the gate insulating layer 6, and the distance between the gate 71 and the drain (first electrode 21) can be reduced by appropriately increasing the thickness of the interlayer insulating layer 3. capacitance. Through the above design, various electrical properties of the thin film transistor can be greatly improved.
  • the thickness of the interlayer insulating layer 3 is greater than or equal to twice the thickness of the gate insulating layer 6 .
  • the thickness of the gate insulating layer 6 is one third of the thickness of the interlayer insulating layer 3 , the overall electrical performance of the thin film transistor is better.
  • the gate insulating layer 6 is patterned using the patterned gate 71 as a mask to expose the active layer 4 above the first electrode 21 .
  • the exposed active layer 4 is metallized by using the patterned gate 71 as a mask to form the second electrode 5 connected to the active layer 4 and the first electrode contact portion 42 .
  • the first electrode contact part 42 is connected with the first electrode 21 through the first via hole 31 .
  • the patterning of the gate insulating layer 6 and the metallization of the active layer 4 are completed through the self-alignment process of the gate 71 , which reduces two photomasks and reduces the production cost.
  • the present application also provides a second embodiment of the display panel.
  • the difference between this embodiment and the first embodiment includes:
  • the first metal layer 2 also includes touch signal lines.
  • the first metal layer 2 forms first electrodes 21 , auxiliary electrodes 22 , common electrode lines 23 and touch signal lines 24 through a patterning process.
  • the passivation layer 9 is opened with a second via hole 91 penetrating the passivation layer 9 and the interlayer insulating layer 3 and extending to the surface of the common electrode line 23, and penetrating the passivation layer 9 and the interlayer insulating layer 3 and extending to the touch signal
  • the third via hole 92 on the surface of the line 24.
  • the display panel When the display panel has a mutual capacitive touch structure, it further includes a first touch electrode 14 and a second touch electrode 15 .
  • the first touch electrode 14 is disposed on the same layer as the active layer 4 .
  • the first touch electrode 14 is connected to the active layer 4 .
  • the second touch electrode 15 is insulated from and opposite to the first touch electrode 14 .
  • the second touch electrode 15 is located on the same layer as the common electrode 10 .
  • the second touch electrode 15 is connected to the touch signal line 24 through the third via hole 92 .
  • the display panel When the display panel has a self-capacitive touch structure, it only includes a second touch electrode 15 on the same layer as the common electrode.
  • the second touch electrode 15 is connected to the touch signal line 24 through the third via hole 92 .
  • the present application also provides a specific embodiment of a manufacturing method of a display panel.
  • the preparation method of the display panel includes:
  • a substrate 1 is provided.
  • the first metal layer 2 is patterned to form a first electrode 21 .
  • step B2 includes forming a first metal layer 2 on the substrate 1 .
  • the first metal layer 2 is patterned to form first electrodes 21 , auxiliary electrodes 22 , common electrode lines 23 and data lines (not shown in the figure).
  • FIG. 4B disposing an interlayer insulating layer 3 on the first metal layer 2 .
  • the insulating interlayer 3 is patterned to form a first via hole 31 .
  • the first via hole 31 penetrates the interlayer insulating layer 3 and extends to the surface of the first electrode 21 .
  • the active layer 4 is connected to the first electrode 21 through the first via hole 31 .
  • the active layer 4 is an oxide semiconductor layer.
  • the thickness of interlayer insulating layer 3 is greater than or equal to twice the thickness of gate insulating layer 6 .
  • the second metal layer 7 is patterned to form a gate 71 and a scanning line (not shown in the figure), so that the gate 71 is disposed opposite to the active layer 4 .
  • the grid 71 is disposed opposite to the auxiliary electrode 22 .
  • the gate insulating layer 6 is patterned using the patterned gate 71 as a mask to expose the active layer 4 above the first electrode 21 , so that the side edges of the gate 71 and the gate insulating layer 6 are flush. Using the gate 71 as a mask to pattern the gate insulating layer 6 can save a photomask.
  • the patterned gate 71 as a mask to perform metallization and doping treatment on the exposed active layer 4 to form the pixel electrode 8, the second electrode 5 connected to the semiconductor part 41 and the first electrode contact part 42, so that Side edges of the gate electrode 71, the gate insulating layer 6, and the semiconductor portion 41 are flush.
  • the first electrode contact part 42 is connected with the first electrode 21 through the first via hole 31 .
  • the second electrode 5 is connected to the active layer 4 .
  • the second electrode 5 is connected to the semiconductor portion 41 .
  • the second electrode 5 is a drain or a source.
  • the second electrode 5 is located on the same layer as the semiconductor portion 41 .
  • the second electrode 5 and the first electrode contact portion 42 are provided on both sides of the semiconductor portion 41, respectively.
  • the second electrode 5 and the pixel electrode 8 have the same material.
  • the pattern of the pixel electrode 8 is planar.
  • the second electrode 5 and the pixel electrode 8 are integrally formed. Both the pixel electrode 8 and the second electrode 5 are obtained by doping the oxide semiconductor layer with metal.
  • the second electrode 5 can be omitted or can be regarded as a part of the pixel electrode 8 , which is specifically determined according to the pattern of the pixel electrode 8 .
  • the passivation layer 9 covers the gate electrode 71 , the scan line, the first electrode contact portion 42 , the second electrode 5 and the pixel electrode 8 .
  • the passivation layer 9 is patterned to open a second via hole 91 penetrating through the passivation layer 9 and the interlayer insulating layer 3 and extending to the surface of the common electrode line 23 on the passivation layer 9 .
  • the common electrode layer is patterned to form the common electrode 10 .
  • the common electrode 10 can be made of transparent ITO material.
  • the common electrode 10 is a comb pattern.
  • the planar pixel electrode 8 and the patterned common electrode 10 are stacked up and down to generate a horizontal fringe electric field to drive the liquid crystal to deflect.
  • the common electrode 10 is connected to the common electrode line 23 through the second via hole 91 .
  • the present application proposes to arrange the first electrode 21 and the gate 71 of the thin film transistor on both sides of the active layer 4, by connecting the gate insulating layer 6 and the first electrode 21 between the gate 71 and the active layer 4
  • the interlayer insulating layer 3 between the source layers 4 is provided independently, realizing the thickness of the gate insulating layer 6 between the gate 71 and the active layer 4 and the interlayer insulation between the first electrode 21 and the active layer 4
  • the thickness of the layer 3 can be adjusted independently, and the gate 71 and the drain (the first electrode 21 ), and the increase in the thickness of the interlayer insulating layer 3 can also reduce the capacitance between the gate 71 and the drain (the first electrode 21 ), which can significantly improve various electrical properties of the thin film transistor.
  • the patterning of the gate insulating layer 6 and the metallization of the active layer 4 are completed through the gate 71 self-alignment process, which reduces two photomasks and reduces production costs.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Thin Film Transistor (AREA)

Abstract

本申请实施例公开了一种薄膜晶体管、显示面板及其制备方法，其中，薄膜晶体管包括：栅极、栅极绝缘层、有源层、第一电极、层间绝缘层以及第二电极；层间绝缘层设置在第一电极与有源层之间，层间绝缘层上开设有第一过孔，有源层通过第一过孔与第一电极连接，层间绝缘层的厚度大于栅极绝缘层的厚度；第二电极与有源层连接。

Description

薄膜晶体管、显示面板及其制备方法 技术领域
本申请涉及显示技术领域，具体涉及一种薄膜晶体管、显示面板及其制备方法。
 背景技术
现有的背沟道蚀刻型（BCE）薄膜晶体管中，为提高电性能需要尽量降低Vgs电压，具体可通过减薄栅极绝缘层的厚度来实现，但栅极绝缘层厚度的降低不仅会造成栅极与漏极之间的耐压性下降，还会增大栅极和源漏极之间的电容，影响薄膜晶体管的综合电性能。
 技术问题
本申请实施例提供一种薄膜晶体管、显示面板及其制备方法，能有效改善薄膜晶体管综合电性能。
 技术解决方案
本申请实施例提供一种薄膜晶体管，包括：栅极；栅极绝缘层，设置在所述栅极的一侧；有源层，设置在所述栅极绝缘层远离所述栅极的一侧，所述有源层与所述栅极相对设置；第一电极，设置在所述有源层远离所述栅极的一侧；层间绝缘层，设置在所述第一电极与所述有源层之间使所述第一电极和所述有源层绝缘，所述层间绝缘层上开设有贯穿所述层间绝缘层并延伸至所述第一电极表面的第一过孔，所述有源层通过所述第一过孔与所述第一电极连接，所述层间绝缘层的厚度大于所述栅极绝缘层的厚度；以及第二电极，与所述有源层连接，所述第二电极与所述有源层位于同一层。
可选的，在本申请的一些具体实施例中，薄膜晶体管还包括：辅助电极，与所述有源层相对设置，所述层间绝缘层设置在所述辅助电极与所述有源层之间。
可选的，在本申请的一些具体实施例中，所述第一电极与所述辅助电极位于同一层，所述有源层通过所述第一过孔与所述第一电极连接。
可选的，在本申请的一些具体实施例中，所述有源层包括半导体部分和第一电极接触部分，所述第一电极接触部分的导电能力小于所述第一电极的导电能力，所述第一电极接触部分的导电能力大于所述半导体部分的导电能力；所述第一电极接触部分通过所述第一过孔与所述第一电极连接。
本申请实施例还提供一种显示面板，包括：第一电极，位于第一金属层；层间绝缘层，设置在所述第一电极上，所述层间绝缘层上开设有贯穿所述层间绝缘层并延伸至所述第一电极表面的第一过孔；有源层，设置在所述层间绝缘层上，所述有源层通过所述第一过孔与所述第一电极连接；第二电极，与所述有源层连接；栅极绝缘层，设置在所述有源层上；以及栅极，位于设置在所述栅极绝缘层上的第二金属层，与所述有源层相对设置；所述层间绝缘层的厚度大于所述栅极绝缘层的厚度。
可选的，在本申请的一些具体实施例中，显示面板还包括：辅助电极，与所述有源层相对设置，所述层间绝缘层设置在所述辅助电极与所述有源层之间；所述第一电极为漏极，所述第二电极为源极；和/或，所述第一电极为源极，所述第二电极为漏极。
可选的，在本申请的一些具体实施例中，所述辅助电极位于所述第一金属层，所述层间绝缘层覆盖所述第一电极和所述辅助电极。
可选的，在本申请的一些具体实施例中，所述有源层包括半导体部分和第一电极接触部分，所述第一电极接触部分的导电能力小于所述第一电极的导电能力，所述第一电极接触部分的导电能力大于所述半导体部分的导电能力；所述第一电极接触部分通过所述第一过孔与所述第一电极连接。
可选的，在本申请的一些具体实施例中，还包括像素电极，所述像素电极与所述有源层同层设置，所述像素电极与所述有源层电连接，所述有源层包括金属氧化物半导体。
可选的，在本申请的一些具体实施例中，显示面板还包括：基板，所述第一金属层设置在所述基板上，所述第一金属层还包括数据线；扫描线，位于所述第二金属层，所述扫描线与所述数据线交叉以限定多个子像素单元，所述栅极、所述第二电极、所述第一电极、所述有源层组成的薄膜晶体管和与所述薄膜晶体管连接的所述像素电极均位于所述子像素单元内；钝化层，设置在所述第二金属层上，覆盖所述栅极和所述像素电极；公共电极，设置在所述钝化层上，所述公共电极与所述像素电极相对设置。
可选的，在本申请的一些具体实施例中，所述栅极、所述栅极绝缘层以及所述有源层的半导体部分的侧边缘齐平。
可选的，在本申请的一些具体实施例中，所述层间绝缘层的厚度大于或等于所述栅极绝缘层的厚度的两倍。
可选的，在本申请的一些具体实施例中，所述第一金属层还包括触控信号线；所述显示面板还包括：第一触控电极，所述第一触控电极与所述有源层同层设置，所述第一触控电极与所述有源层连接；以及第二触控电极，所述第二触控电极与所述第一触控电极绝缘且相对设置。
本申请实施例还提供一种显示面板的制备方法，包括：
B1、提供一基板；
B2、在所述基板上形成第一金属层，图案化所述第一金属层以形成第一电极；
B3、在所述第一金属层上设置层间绝缘层，图案化所述层间绝缘层以形成第一过孔；
B4、在所述层间绝缘层上设置图案化的有源层，所述有源层通过所述第一过孔与所述第一电极连接，所述有源层包括金属氧化物半导体；
B5、在所述有源层上形成栅极绝缘层和第二金属层，所述层间绝缘层的厚度大于或等于所述栅极绝缘层的厚度的两倍；图案化所述第二金属层以形成栅极，使所述栅极与所述有源层相对设置；以图案化后的所述栅极作为掩模板图案化所述栅极绝缘层以裸露出位于所述第一电极上方的所述有源层；以图案化后的所述栅极作为掩模板对裸露出的所述有源层进行金属化处理以形成与所述有源层连接的第二电极和第一电极接触部分，所述第一电极接触部分通过所述第一过孔与所述第一电极连接。
 有益效果
本申请的有益效果：将薄膜晶体管的第一电极与栅极设置在有源层的两侧，通过将栅极和有源层之间的栅极绝缘层与第一电极和有源层之间的层间绝缘层独立设置，实现了栅极和有源层之间的栅极绝缘层的厚度与第一电极和有源层之间的层间绝缘层的厚度可分别独立调整，在减薄栅极绝缘层的厚度以减小Vgs的同时可通过增大层间绝缘层的厚度来增大栅极和漏极（第一电极）之间的耐压特性，且层间绝缘层厚度的增加还可以降低栅极和漏极（第一电极）之间的电容，能显著提升薄膜晶体管的各项电性能。
此外，本申请在显示面板的制备方法中，通过栅极自对准工艺完成栅极绝缘层的图案化以及有源层的金属化处理，减少了两道光罩，降低了生产成本。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请提供的薄膜晶体管一具体实施例的剖面示意图；
图2是本申请提供的第一实施例中显示面板的显示区的剖面示意图；
图3是本申请提供的第二实施例中显示面板的显示区的剖面示意图；
图4A至图4G示出了图2中的显示面板在制备过程中的结构示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
本申请提供了一种薄膜晶体管，包括栅极、栅极绝缘层、有源层、辅助电极、层间绝缘层、第一电极以及第二电极。栅极绝缘层设置在栅极的一侧。有源层设置在栅极绝缘层远离栅极的一侧。有源层与栅极相对设置。辅助电极与有源层相对设置。层间绝缘层设置在辅助电极与有源层之间使辅助电极和有源层绝缘。层间绝缘层的厚度大于栅极绝缘层的厚度。第一电极与辅助电极位于同一层。层间绝缘层上开设有贯穿层间绝缘层并延伸至第一电极表面的第一过孔。有源层通过第一过孔与第一电极连接。第二电极与有源层连接。第二电极与有源层位于同一层。
具体的，如图1所示，薄膜晶体管设置在基板1上。
基板1为阵列基板。基板1是刚性基板。刚性的基板1可采用玻璃制得。可以理解的是，基板1也可以是柔性基板。柔性的基板1可采用能隔离水汽、氧气的聚酰亚胺（Polyimide，PI）和/或聚对苯二甲酸乙二醇酯（Polyethylene Terephthalate，PET）等的有机绝缘材料制得，这里不作具体限定。
第一金属层2设置在基板1上。第一金属层2通过图案化工艺形成薄膜晶体管的第一电极21和辅助电极22。第一金属层2可采用Mo、Al、Ti以及Cu等常见导电金属或合金中的一种或几种制得。第一金属层2可以是单一金属构成的单层导电层结构，也可以是多种金属构成的多层导电层结构，这里不作具体限定。第一电极21为源极或漏极。在本实施例中，第一电极21为连接数据线的漏极。
层间绝缘层3设置在第一金属层2上。层间绝缘层3覆盖第一电极21和辅助电极22。层间绝缘层3上开设有贯穿层间绝缘层3并延伸至第一电极21表面的第一过孔31。层间绝缘层3一般采用能隔离水汽、氧气的SiNx、SiOx、Al2O3等常见的无机材料中的一种或几种沉积或溅射形成。层间绝缘层3也可以采用有机绝缘层制备以获得平坦的表面。
有源层4设置在层间绝缘层3上。有源层4可以采用金属氧化物、非晶硅及多晶硅等常见半导体材料。有源层4的中间区域与辅助电极22对应设置。有源层4包括半导体部分41和第一电极接触部分42。第一电极接触部分42的导电能力小于第一电极21的导电能力。第一电极接触部分42的导电能力大于半导体部分41的导电能力。第一电极接触部分42通过第一过孔31与第一电极21连接。
第二电极5与有源层4连接。第二电极5与半导体部分41连接。第二电极5为漏极或源极。在本实施例中，第二电极5为连接像素电极或其他电路的源极。第二电极5与有源层4位于同一层。第二电极5和第一电极接触部分42分别设置在半导体部分41的两侧。
栅极绝缘层6设置在有源层4上。栅极绝缘层6覆盖半导体部分41。栅极绝缘层6一般采用能隔离水汽、氧气的SiNx、SiOx、Al2O3等常见的无机材料中的一种或几种沉积或溅射形成。通常情况下单层的绝缘层即可满足显示面板的良率要求，但在采用多晶硅或金属氧化物作为有源层的显示面板中，为提升良率，也会采用多层绝缘层重叠设置的结构来确保对水汽、氧气的有效隔离，本实施例中栅极绝缘层6为单层SiO2或单层SiNx结构。
栅极71设置在栅极绝缘层6上。栅极71与半导体部分41相对设置。栅极71可采用Mo、Al、Ti以及Cu等常见导电金属或合金中的一种或几种制得。栅极71可以是单一金属构成的单层导电层结构，也可以是多种金属构成的多层导电层结构，这里不作具体限定。
辅助电极22为辅助栅极和/或遮光电极。辅助电极22与半导体部分41相对设置。辅助电极22作为辅助栅极时，辅助电极22可采用金属或ITO等导电材料制成，辅助电极22与半导体部分41相对可有效提升薄膜晶体管的电性能。辅助电极22采用金属或其他不透光材料时可作为遮光电极，辅助电极22与半导体部分41相对可防止光线照射半导体部分41影响薄膜晶体管的电性能。
本实施例提供的薄膜晶体管将第一电极21与栅极71设置在有源层4的两侧，第一电极21与有源层4之间通过层间绝缘层3绝缘，栅极71与有源层4之间通过栅极绝缘层6绝缘。通过将栅极71和有源层4之间的绝缘层与源漏极和有源层4之间的绝缘层独立设置，实现了栅极71和有源层4之间的栅极绝缘层6的厚度以及源漏极和有源层4之间的层间绝缘层3的厚度可分别独立调整，可避免现有技术中栅极和源漏极均设置在有源层的同侧时减薄栅极绝缘层厚度以减小Vgs的同时会降低薄膜晶体管的其他电性能。
将层间绝缘层3的厚度设置为大于栅极绝缘层6的厚度。根据薄膜晶体管的Vgs目标设定值来减薄栅极绝缘层6的厚度，由于层间绝缘层3的厚度可以同时不变或增大，不仅能确保栅极71和漏极（第一电极21）之间的耐压特性不受栅极绝缘层6厚度减薄的影响，还能通过适当增大层间绝缘层3的厚度来降低栅极71和漏极（第一电极21）之间的电容。通过上述设计，薄膜晶体管的各项电性能都能得到较大提升。
可选的，层间绝缘层3的厚度大于或等于栅极绝缘层6的厚度的两倍。栅极绝缘层6的厚度为层间绝缘层3的厚度的三分之一时，薄膜晶体管的整体电性能较佳。
可选的，栅极71、栅极绝缘层6以及有源层4中的半导体部分41的侧边缘齐平。该结构可以减少薄膜晶体管的光罩数量。具体的，有源层4包括金属氧化物半导体，比如IGZO或IGZTO等。以图案化后的栅极71作为掩模板图案化栅极绝缘层6以裸露出位于第一电极21上方的有源层4。以图案化后的栅极71作为掩模板对裸露出的有源层4进行金属化处理以形成与有源层4连接的第二电极5和第一电极接触部分42。第一电极接触部分42通过第一过孔31与第一电极21连接。通过栅极71自对准工艺完成栅极绝缘层6的图案化以及有源层4的金属化处理，减少了两道光罩，降低了生产成本。
如图2所示，本申请还提供了显示面板的第一实施例。显示面板包括基板1和设置在基板1上的第一金属层2、层间绝缘层3、有源层4、第二电极5、栅极绝缘层6、第二金属层7、像素电极8、钝化层9以及公共电极层10。
基板1为阵列基板。基板1是刚性基板。刚性的基板1可采用玻璃制得。可以理解的是，基板1也可以是柔性基板。柔性的基板1可采用能隔离水汽、氧气的聚酰亚胺和/或聚对苯二甲酸乙二醇酯等的有机绝缘材料制得，这里不作具体限定。
第一金属层2设置在基板1上。第一金属层2通过图案化工艺形成数据线（图中未示出）、薄膜晶体管的第一电极21和辅助电极22以及公共电极线23。第一金属层2可采用Mo、Al、Ti以及Cu等常见导电金属或合金中的一种或几种制得。第一金属层2可以是单一金属构成的单层导电层结构，也可以是多种金属构成的多层导电层结构，这里不作具体限定。第一电极21为源极或漏极。在本实施例中，第一电极21为连接数据线的漏极。
辅助电极22为辅助栅极和/或遮光电极。辅助电极22与半导体部分41相对设置。辅助电极22作为辅助栅极时，辅助电极22可采用金属或ITO等导电材料制成，辅助电极22与半导体部分41相对可有效提升薄膜晶体管的电性能。辅助电极22采用金属或其他不透光材料时可作为遮光电极，辅助电极22与半导体部分41相对可防止光线照射半导体部分41影响薄膜晶体管的电性能。
层间绝缘层3设置在第一金属层2上。层间绝缘层3覆盖数据线、第一电极21、辅助电极22和公共电极线23。层间绝缘层3上开设有贯穿层间绝缘层3并延伸至第一电极21表面的第一过孔31。层间绝缘层3一般采用能隔离水汽、氧气的SiNx、SiOx、Al2O3等常见的无机材料中的一种或几种沉积或溅射形成。通常情况下单层的绝缘层即可满足显示面板的良率要求，但在采用多晶硅或金属氧化物作为有源层的显示面板中，为提升良率，也会采用多层绝缘层重叠设置的结构来确保对水汽、氧气的有效隔离，本实施例中层间绝缘层3为单层SiO2或单层SiNx结构。
有源层4设置在层间绝缘层3上。有源层4可以采用金属氧化物、非晶硅及多晶硅等常见半导体材料。在本实施例中，有源层4采用金属氧化物半导体制备。有源层4的中间区域与辅助电极22对应设置。有源层4包括半导体部分41和第一电极接触部分42。第一电极接触部分42的导电能力小于第一电极21的导电能力。第一电极接触部分42的导电能力大于半导体部分41的导电能力。第一电极接触部分42通过第一过孔31与第一电极21连接。
第二电极5与有源层4连接。第二电极5与半导体部分41连接。第二电极5为漏极或源极。第二电极5与有源层4位于同一层。第二电极5和第一电极接触部分42分别设置在半导体部分41的两侧。
栅极绝缘层6设置在有源层4上。栅极绝缘层6覆盖半导体部分41。栅极绝缘层6一般采用能隔离水汽、氧气的SiNx、SiOx、Al2O3等常见的无机材料中的一种或几种沉积或溅射形成。通常情况下单层的绝缘层即可满足显示面板的良率要求，但在采用多晶硅或金属氧化物作为有源层的显示面板中，为提升良率，也会采用多层绝缘层重叠设置的结构来确保对水汽、氧气的有效隔离，本实施例中栅极绝缘层6为单层SiO2或单层SiNx结构。
第二金属层7设置在栅极绝缘层6上。第二金属层7通过图案化工艺形成薄膜晶体管的栅极71和扫描线（图中未示出）。栅极71与半导体部分41相对设置。第二金属层7可采用Mo、Al、Ti以及Cu等常见导电金属或合金中的一种或几种制得。第二金属层7可以是单一金属构成的单层导电层结构，也可以是多种金属构成的多层导电层结构，这里不作具体限定。
像素电极8设置在层间绝缘层3上。像素电极8与有源层4和第二电极5同层设置。像素电极8和第二电极5是通过有源层4进行金属掺杂处理形成。像素电极8和第二电极5一体成形。第二电极5的一端与半导体部分41连接。第二电极5的另一端与像素电极8连接。像素电极8和第二电极5都是通过对氧化物半导体层金属掺杂获得。在一些具体实施例中，第二电极5可省略或可视为像素电极8的一部分，具体根据像素电极8的图案确定。
钝化层9设置在第二金属层7上。钝化层9覆盖栅极71、扫描线、第一电极接触部分42、第二电极5以及像素电极8。钝化层9上开设有贯穿钝化层9和层间绝缘层3并延伸至公共电极线23表面的第二过孔91。钝化层9一般采用能隔离水汽、氧气的SiNx、SiOx、Al2O3等常见的无机材料中的一种或几种沉积或溅射形成。通常情况下单层的绝缘层即可满足显示面板的良率要求，但在采用多晶硅或金属氧化物作为有源层的显示面板中，为提升良率，也会采用多层绝缘层重叠设置的结构来确保对水汽、氧气的有效隔离。
公共电极10设置在钝化层9上。公共电极10可采用透明ITO材料制成。公共电极10通过第二过孔91与公共电极线23连接。本实施例中的显示面板为FFS显示面板，通过面状铺设的像素电极8和图案化的公共电极10上下叠置以产生水平边缘电场驱动液晶偏转。为确保显示质量，需要将像素电极8下方的层间绝缘层3设置为有机绝缘的平坦层，以保证像素电极8尽量在同一水平面形成。公共电极10和像素电极8相对设置，产生水平电场以驱动液晶。可以理解的是，公共电极10可以是“米”形、梳形等其他图案，这里不作具体限定。
第一配向层（图中未示出）设置在公共电极10上以调整液晶的偏转角度。
显示面板还包括衬底11和设置在衬底11上的彩膜层12、遮光层13以及第二配向层（图中未示出）。
衬底11与基板1相对设置。衬底11的材料与基板1相同，这里不再赘述。
彩膜层12包括多个滤光片121。每一子像素区内设置有一滤光片121。滤光片121与像素电极8相对设置。
遮光层13设置在相邻两个滤光片121之间以避免混色。遮光层13一般采用黑色树脂材料制成。
第二配向层覆盖彩膜层12和遮光层13以调整液晶的偏转角度。
显示面板还包括设置在基板1和衬底11之间的液晶层（图中未示出）和间隔件（图中未示出）。
显示面板的显示区设置有多条沿第一方向延伸的扫描线和多条大致沿第二方向延伸的数据线。扫描线与数据线交叉限定出多个阵列排布的子像素区域。栅极71、第二电极5、第一电极21、有源层4组成的薄膜晶体管和与所述薄膜晶体管连接的像素电极8均位于子像素单元内。
辅助电极22为辅助栅极和/或遮光电极。辅助电极22与半导体部分41相对设置。辅助电极22作为辅助栅极时，辅助电极22可采用金属或ITO等导电材料制成，辅助电极22与半导体部分41相对可有效提升薄膜晶体管的电性能。辅助电极22采用金属或其他不透光材料时可作为遮光电极，辅助电极22与半导体部分41相对可防止光线照射半导体部分41影响薄膜晶体管的电性能。
本实施例提供的显示面板中，将薄膜晶体管的第一电极21与栅极71设置在有源层4的两侧，第一电极21与有源层4之间通过层间绝缘层3绝缘，栅极71与有源层4之间通过栅极绝缘层6绝缘。通过将栅极71和有源层4之间的绝缘层与源漏极和有源层4之间的绝缘层独立设置，实现了栅极71和有源层4之间的栅极绝缘层6的厚度以及源漏极和有源层4之间的层间绝缘层3的厚度可分别独立调整，可避免现有技术中栅极和源漏极均设置在有源层的同侧时减薄栅极绝缘层厚度以减小Vgs的同时会降低薄膜晶体管的其他电性能。
将层间绝缘层3的厚度设置为大于栅极绝缘层6的厚度。根据薄膜晶体管的Vgs目标设定值来减薄栅极绝缘层6的厚度，由于层间绝缘层3的厚度可以同时不变或增大，不仅能确保栅极71和漏极（第一电极21）之间的耐压特性不受栅极绝缘层6厚度减薄的影响，还能通过适当增大层间绝缘层3的厚度来降低栅极71和漏极（第一电极21）之间的电容。通过上述设计，薄膜晶体管的各项电性能都能得到较大提升。
可选的，层间绝缘层3的厚度大于或等于栅极绝缘层6的厚度的两倍。栅极绝缘层6的厚度为层间绝缘层3的厚度的三分之一时，薄膜晶体管的整体电性能较佳。
可选的，栅极71、栅极绝缘层6以及有源层4中的半导体部分41的侧边缘齐平。该结构可以减少薄膜晶体管的光罩数量。具体的，以图案化后的栅极71作为掩模板图案化栅极绝缘层6以裸露出位于第一电极21上方的有源层4。以图案化后的栅极71作为掩模板对裸露出的有源层4进行金属化处理以形成与有源层4连接的第二电极5和第一电极接触部分42。第一电极接触部分42通过第一过孔31与第一电极21连接。通过栅极71自对准工艺完成栅极绝缘层6的图案化以及有源层4的金属化处理，减少了两道光罩，降低了生产成本。
如图3所示，本申请还提供了显示面板的第二实施例。本实施例与第一实施例的区别包括：
第一金属层2还包括触控信号线。第一金属层2通过图案化工艺形成第一电极21、辅助电极22、公共电极线23和触控信号线24。
钝化层9上开设有贯穿钝化层9和层间绝缘层3并延伸至公共电极线23表面的第二过孔91以及贯穿钝化层9和层间绝缘层3并延伸至触控信号线24表面的第三过孔92。
显示面板为互电容触控结构时，还包括第一触控电极14和第二触控电极15。第一触控电极14与有源层4同层设置。第一触控电极14与有源层4连接。第二触控电极15与第一触控电极14绝缘且相对设置。第二触控电极15与公共电极10位于同一层。第二触控电极15通过第三过孔92与触控信号线24连接。
显示面板为自电容触控结构时仅包括一层与公共电极位于同一层的第二触控电极15。第二触控电极15通过第三过孔92与触控信号线24连接。
本实施例的其他结构与实施例一相同，这里不再赘述。
如图4A至图4G所示，本申请还提供了显示面板的制备方法的具体实施例。显示面板的制备方法包括：
B1、提供一基板1。
B2、如图4A所示，在基板1上形成第一金属层2。图案化第一金属层2以形成第一电极21。
可选的，步骤B2包括在基板1上形成第一金属层2。图案化第一金属层2以形成第一电极21、辅助电极22、公共电极线23以及数据线（图中未示出）。
B3、如图4B所示，在第一金属层2上设置层间绝缘层3。图案化层间绝缘层3以形成第一过孔31。第一过孔31贯穿层间绝缘层3并延伸至第一电极21的表面。
B4、如图4C所示，在层间绝缘层3上设置图案化的有源层4。有源层4通过第一过孔31与第一电极21连接。有源层4为氧化物半导体层。
B5、如图4D所示，在有源层4上形成栅极绝缘层6和第二金属层7。层间绝缘层3的厚度大于或等于栅极绝缘层6的厚度的两倍。图案化第二金属层7以形成栅极71和扫描线（图中未示出），使栅极71与有源层4相对设置。可选的，栅极71与辅助电极22相对设置。
以图案化后的栅极71作为掩模板图案化栅极绝缘层6以裸露出位于第一电极21上方的有源层4，使栅极71和栅极绝缘层6的侧边缘齐平。利用栅极71作为掩模版图案化栅极绝缘层6可以节省一道光罩。
以图案化后的栅极71作为掩模板对裸露出的有源层4进行金属化掺杂处理以形成像素电极8、与半导体部分41连接的第二电极5和第一电极接触部分42，使栅极71、栅极绝缘层6和半导体部分41的侧边缘齐平。第一电极接触部分42通过第一过孔31与第一电极21连接。
第二电极5与有源层4连接。第二电极5与半导体部分41连接。第二电极5为漏极或源极。第二电极5与半导体部分41位于同一层。第二电极5和第一电极接触部分42分别设置在半导体部分41的两侧。
第二电极5和像素电极8具有相同的材料。像素电极8的图案为平面状。第二电极5和像素电极8一体成型。像素电极8和第二电极5都是通过对氧化物半导体层金属掺杂获得。在一些具体实施例中，第二电极5可省略或可视为像素电极8的一部分，具体根据像素电极8的图案确定。
B6、如图4E所示，在第二金属层7上形成钝化层9。钝化层9覆盖栅极71、扫描线、第一电极接触部分42、第二电极5以及像素电极8。图案化钝化层9以在钝化层9上开设贯穿钝化层9和层间绝缘层3并延伸至公共电极线23表面的第二过孔91。
B7、如图4F所示，在钝化层9上形成公共电极层。图案化公共电极层以形成公共电极10。公共电极10可采用透明ITO材料制成。公共电极10为梳状图案。面状铺设的像素电极8和图案化的公共电极10上下叠置以产生水平边缘电场驱动液晶偏转。公共电极10通过第二过孔91与公共电极线23连接。
B8、如图4G所示，在公共电极10上方盖设彩膜基板，将液晶密封在公共电极10与彩膜基板上的滤光片121之间。
本申请提出将薄膜晶体管的第一电极21与栅极71设置在有源层4的两侧，通过将栅极71和有源层4之间的栅极绝缘层6与第一电极21和有源层4之间的层间绝缘层3独立设置，实现了栅极71和有源层4之间的栅极绝缘层6的厚度与第一电极21和有源层4之间的层间绝缘层3的厚度可分别独立调整，在减薄栅极绝缘层6的厚度以减小Vgs的同时可通过增大层间绝缘层3的厚度来增大栅极71和漏极（第一电极21）之间的耐压特性，且层间绝缘层3厚度的增加还可以降低栅极71和漏极（第一电极21）之间的电容，能显著提升薄膜晶体管的各项电性能。
此外，本申请在显示面板的制备方法中，通过栅极71自对准工艺完成栅极绝缘层6的图案化以及有源层4的金属化处理，减少了两道光罩，降低了生产成本。
以上对本申请实施例所提供的一种薄膜晶体管、显示面板及其制备方法进行了详细的介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种薄膜晶体管，其中，包括：
    栅极；
    栅极绝缘层，设置在所述栅极的一侧；
    有源层，设置在所述栅极绝缘层远离所述栅极的一侧，所述有源层与所述栅极相对设置；
    第一电极，设置在所述有源层远离所述栅极的一侧；
    层间绝缘层，设置在所述第一电极与所述有源层之间使所述第一电极和所述有源层绝缘，所述层间绝缘层上开设有贯穿所述层间绝缘层并延伸至所述第一电极表面的第一过孔，所述有源层通过所述第一过孔与所述第一电极连接，所述层间绝缘层的厚度大于所述栅极绝缘层的厚度；以及
    第二电极，与所述有源层连接，所述第二电极与所述有源层位于同一层。
  2. 根据权利要求1所述的薄膜晶体管，其中，还包括：
    辅助电极，与所述有源层相对设置，所述层间绝缘层设置在所述辅助电极与所述有源层之间。
  3. 根据权利要求2所述的薄膜晶体管，其中，所述第一电极与所述辅助电极位于同一层，所述有源层通过所述第一过孔与所述第一电极连接。
  4. 根据权利要求1所述的薄膜晶体管，其中，所述有源层包括半导体部分和第一电极接触部分，所述第一电极接触部分的导电能力小于所述第一电极的导电能力，所述第一电极接触部分的导电能力大于所述半导体部分的导电能力；所述第一电极接触部分通过所述第一过孔与所述第一电极连接。
  5. 根据权利要求4所述的薄膜晶体管，其中，所述栅极、所述栅极绝缘层以及所述有源层的半导体部分的侧边缘齐平。
  6. 根据权利要求1所述的薄膜晶体管，其中，所述层间绝缘层的厚度大于或等于所述栅极绝缘层的厚度的两倍。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述层间绝缘层的厚度为所述栅极绝缘层的厚度的三倍。
  8. 一种显示面板，其中，包括：
    第一电极，位于第一金属层；
    层间绝缘层，设置在所述第一电极上，所述层间绝缘层上开设有贯穿所述层间绝缘层并延伸至所述第一电极表面的第一过孔；
    有源层，设置在所述层间绝缘层上，所述有源层通过所述第一过孔与所述第一电极连接；
    第二电极，与所述有源层连接；
    栅极绝缘层，设置在所述有源层上；以及
    栅极，位于设置在所述栅极绝缘层上的第二金属层，与所述有源层相对设置；
    所述层间绝缘层的厚度大于所述栅极绝缘层的厚度。
  9. 根据权利要求8所述的显示面板，其中，还包括：
    辅助电极，与所述有源层相对设置，所述层间绝缘层设置在所述辅助电极与所述有源层之间。
  10. 根据权利要求8所述的显示面板，其中，所述第一电极为漏极，所述第二电极为源极；和/或，所述第一电极为源极，所述第二电极为漏极。
  11. 根据权利要求9所述的显示面板，其中，所述辅助电极位于所述第一金属层，所述层间绝缘层覆盖所述第一电极和所述辅助电极。
  12. 根据权利要求8所述的显示面板，其中，所述有源层包括半导体部分和第一电极接触部分，所述第一电极接触部分的导电能力小于所述第一电极的导电能力，所述第一电极接触部分的导电能力大于所述半导体部分的导电能力；所述第一电极接触部分通过所述第一过孔与所述第一电极连接。
  13. 根据权利要求8所述的显示面板，其中，还包括像素电极，所述像素电极与所述有源层同层设置，所述像素电极与所述有源层电连接，所述有源层包括金属氧化物半导体。
  14. 根据权利要求13所述的显示面板，其中，还包括：
    基板，所述第一金属层设置在所述基板上，所述第一金属层还包括数据线；
    扫描线，位于所述第二金属层，所述扫描线与所述数据线交叉以限定多个子像素单元，所述栅极、所述第二电极、所述第一电极、所述有源层组成的薄膜晶体管和与所述薄膜晶体管连接的所述像素电极均位于所述子像素单元内；
    钝化层，设置在所述第二金属层上，覆盖所述栅极和所述像素电极；以及
    公共电极，设置在所述钝化层上，所述公共电极与所述像素电极相对设置。
  15. 根据权利要求8所述的显示面板，其中，所述栅极、所述栅极绝缘层以及所述有源层的半导体部分的侧边缘齐平。
  16. 根据权利要求8所述的显示面板，其中，所述层间绝缘层的厚度大于或等于所述栅极绝缘层的厚度的两倍。
  17. 根据权利要求16所述的显示面板，其中，所述层间绝缘层的厚度为所述栅极绝缘层的厚度的三倍。
  18. 根据权利要求8所述的显示面板，其中，所述第一金属层还包括触控信号线；所述显示面板还包括：
    第一触控电极，所述第一触控电极与所述有源层同层设置，所述第一触控电极与所述有源层连接。
  19. 根据权利要求8所述的显示面板，其中，所述显示面板还包括第二触控电极，所述第二触控电极与所述第一触控电极绝缘且相对设置。
  20. 一种显示面板的制备方法，其中，包括：
    B1、提供一基板；
    B2、在所述基板上形成第一金属层，图案化所述第一金属层以形成第一电极；
    B3、在所述第一金属层上设置层间绝缘层，图案化所述层间绝缘层以形成第一过孔；
    B4、在所述层间绝缘层上设置图案化的有源层，所述有源层通过所述第一过孔与所述第一电极连接，所述有源层包括金属氧化物半导体；
    B5、在所述有源层上形成栅极绝缘层和第二金属层，所述层间绝缘层的厚度大于或等于所述栅极绝缘层的厚度的两倍；
    图案化所述第二金属层以形成栅极，使所述栅极与所述有源层相对设置；
    以图案化后的所述栅极作为掩模板图案化所述栅极绝缘层以裸露出位于所述第一电极上方的所述有源层；
    以图案化后的所述栅极作为掩模板对裸露出的所述有源层进行金属化处理以形成与所述有源层连接的第二电极和第一电极接触部分，所述第一电极接触部分通过所述第一过孔与所述第一电极连接。
PCT/CN2021/121819 2021-09-24 2021-09-29 薄膜晶体管、显示面板及其制备方法 WO2023044950A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US17/611,118 US20240047537A1 (en) 2021-09-24 2021-09-29 Thin-film transistor, display panel, and manufacturing method of the display panel
JP2021560071A JP2024504881A (ja) 2021-09-24 2021-09-29 薄膜トランジスタ、表示パネル及びその製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202111120728.4 2021-09-24
CN202111120728.4A CN113871401A (zh) 2021-09-24 2021-09-24 薄膜晶体管、显示面板及其制备方法

Publications (1)

Publication Number Publication Date
WO2023044950A1 true WO2023044950A1 (zh) 2023-03-30

Family

ID=78993743

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/121819 WO2023044950A1 (zh) 2021-09-24 2021-09-29 薄膜晶体管、显示面板及其制备方法

Country Status (4)

Country Link
US (1) US20240047537A1 (zh)
JP (1) JP2024504881A (zh)
CN (1) CN113871401A (zh)
WO (1) WO2023044950A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114721553B (zh) * 2022-06-06 2022-12-13 惠科股份有限公司 触控结构、oled触控显示面板及制作方法
CN115241208A (zh) * 2022-07-08 2022-10-25 武汉华星光电技术有限公司 显示面板
CN115483277A (zh) * 2022-09-30 2022-12-16 惠科股份有限公司 薄膜晶体管、显示面板及其制备方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170294464A1 (en) * 2016-04-07 2017-10-12 Samsung Display Co., Ltd. Transistor display panel, manufacturing method thereof, and display device including the same
US20200096799A1 (en) * 2017-11-22 2020-03-26 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Va type tft array substrate and the manufacturing method thereof
CN111682033A (zh) * 2020-07-07 2020-09-18 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN112490254A (zh) * 2020-12-03 2021-03-12 Tcl华星光电技术有限公司 一种阵列基板、显示面板及其制备方法
CN113345837A (zh) * 2021-05-26 2021-09-03 深圳市华星光电半导体显示技术有限公司 一种显示面板的制作方法及显示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170294464A1 (en) * 2016-04-07 2017-10-12 Samsung Display Co., Ltd. Transistor display panel, manufacturing method thereof, and display device including the same
US20200096799A1 (en) * 2017-11-22 2020-03-26 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Va type tft array substrate and the manufacturing method thereof
CN111682033A (zh) * 2020-07-07 2020-09-18 深圳市华星光电半导体显示技术有限公司 显示面板及其制作方法
CN112490254A (zh) * 2020-12-03 2021-03-12 Tcl华星光电技术有限公司 一种阵列基板、显示面板及其制备方法
CN113345837A (zh) * 2021-05-26 2021-09-03 深圳市华星光电半导体显示技术有限公司 一种显示面板的制作方法及显示面板

Also Published As

Publication number Publication date
CN113871401A (zh) 2021-12-31
US20240047537A1 (en) 2024-02-08
JP2024504881A (ja) 2024-02-02

Similar Documents

Publication Publication Date Title
WO2023044950A1 (zh) 薄膜晶体管、显示面板及其制备方法
JP4767242B2 (ja) Ｔｆｔ−ｌｃｄアレイ基板及びその製造方法
CN103489826A (zh) 阵列基板、制备方法以及显示装置
CN106932990A (zh) 显示面板、显示装置及显示面板的制作方法
TW201926661A (zh) 畫素陣列基板
WO2015096371A1 (zh) 一种电极引出结构、阵列基板以及显示装置
WO2013166831A1 (zh) 薄膜晶体管阵列基板及制作方法和显示装置
WO2018209761A1 (zh) 阵列基板及其制造方法、液晶显示面板
US20230178560A1 (en) Thin-film transistor and method for manufacturing same, and array substrate and display panel
WO2019205235A1 (zh) 薄膜晶体管阵列基板及其制备方法
WO2015085719A1 (zh) 像素单元、阵列基板及其制造方法和显示装置
WO2021258933A1 (zh) 薄膜晶体管及其制备方法、移位寄存器和栅极驱动电路
US20180231816A1 (en) Thin film transistor and manufacturing method thereof, liquid crystal panel
CN104347641A (zh) 薄膜晶体管阵列基板
WO2021114368A1 (zh) 显示面板及其制备方法
WO2015021720A1 (zh) 一种阵列基板及其制备方法及显示装置
WO2024027397A1 (zh) 阵列基板及显示面板
CN101150091A (zh) 像素结构及其制造方法
TWI490615B (zh) 用於邊緣電場切換模式液晶顯示裝置的陣列基板及其製造方法
TW543198B (en) Liquid crystal displays
CN104335113A (zh) 用于mofet的掩膜层级减少
WO2024036766A1 (zh) 阵列基板及显示面板
CN109411545A (zh) 一种薄膜晶体管及其制造方法
WO2023044957A1 (zh) 阵列基板及其制备方法和显示面板
WO2023108762A1 (zh) 薄膜晶体管及其制作方法、显示面板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 2021560071

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 17611118

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21801407

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 2021801407

Country of ref document: EP

ENP Entry into the national phase

Ref document number: 2021801407

Country of ref document: EP

Effective date: 20240424