WO2024036766A1 - 阵列基板及显示面板 - Google Patents

阵列基板及显示面板 Download PDF

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Publication number
WO2024036766A1
WO2024036766A1 PCT/CN2022/130242 CN2022130242W WO2024036766A1 WO 2024036766 A1 WO2024036766 A1 WO 2024036766A1 CN 2022130242 W CN2022130242 W CN 2022130242W WO 2024036766 A1 WO2024036766 A1 WO 2024036766A1
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Prior art keywords
active layer
layer
doped region
array substrate
region
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PCT/CN2022/130242
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English (en)
French (fr)
Inventor
李治福
刘广辉
艾飞
宋德伟
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武汉华星光电技术有限公司
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Priority to US17/998,999 priority Critical patent/US20240222379A1/en
Publication of WO2024036766A1 publication Critical patent/WO2024036766A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the technical field of manufacturing display panels, and in particular, to an array substrate and a display panel.
  • low-temperature polysilicon thin film transistors are liquid crystal displays (Liquid Crystal Display (LCD) and organic light emitting diode (Organic Light Emitting Diode (OLED) and other display devices are key components in active drivers and peripheral circuits.
  • LCD Liquid Crystal Display
  • OLED Organic Light Emitting Diode
  • other display devices are key components in active drivers and peripheral circuits.
  • structures such as lightly doped drains and raised source drains are usually formed inside the thin film transistors. By lightly doping drains and raised source drain structures, the performance of thin film transistor devices can be improved. Stability and reliability. Therefore, the device prepared with the above structure can improve the performance of the thin film transistor to a certain extent.
  • the above structure will also introduce a new series resistance structure, which can easily lead to a reduction in the on-state current and equivalent carrier mobility inside the thin film transistor, thereby affecting the performance of the thin film transistor and not conducive to the synthesis of the thin film transistor. Further improvements in performance.
  • the on-state current and equivalent carrier mobility of the thin film transistor inside the display panel are low, which is not conducive to further improvement of the overall performance of the display panel.
  • embodiments of the present invention provide an array substrate and a display panel. It can effectively improve the on-state current and carrier mobility of the thin film transistor inside the display panel, and improve the overall performance of the device.
  • the array substrate includes:
  • a first active layer is disposed on the substrate, the first active layer includes a first channel region and first doping regions disposed on both sides of the first channel region;
  • a gate electrode is provided on the first active layer
  • a gate insulating layer is disposed on the first active layer and covers the gate
  • a second active layer is disposed on the gate insulating layer, the second active layer includes a second channel region and second doping regions disposed on both sides of the second channel region; and ,
  • the first doped region and the second doped region are arranged correspondingly, the source/drain metal layer is electrically connected to the second active layer in the second doped region, and the The first active layer in the first doped region is correspondingly electrically connected to the second active layer in the second doped region;
  • the length of the first active layer is greater than or equal to the length of the second active layer.
  • the length of the orthographic projection of the second doped region on the substrate is greater than the length of the orthogonal projection of the first doped region on the substrate.
  • the first doped region and the second doped region each include a heavily doped region and a lightly doped region, and the lightly doped region is adjacent to the heavily doped region, And the heavily doped region is located away from the channel region;
  • the heavily doped region of the first active layer corresponds to the heavily doped region of the second active layer
  • the lightly doped region of the first active layer corresponds to the heavily doped region of the first active layer
  • the lightly doped region of the second active layer corresponds to the source/drain metal layer and is electrically connected to the corresponding second active layer in the heavily doped region.
  • an array substrate which includes:
  • a first active layer is disposed on the substrate, the first active layer includes a first channel region and first doping regions disposed on both sides of the first channel region;
  • a gate electrode is provided on the first active layer
  • a gate insulating layer is disposed on the first active layer and covers the gate
  • a second active layer is disposed on the gate insulating layer, the second active layer includes a second channel region and second doping regions disposed on both sides of the second channel region; and ,
  • the first doped region and the second doped region are arranged correspondingly, the source/drain metal layer is electrically connected to the second active layer in the second doped region, and the The first active layer in the first doped region is correspondingly electrically connected to the second active layer in the second doped region.
  • the length of the orthographic projection of the second doped region on the substrate is greater than the length of the orthogonal projection of the first doped region on the substrate.
  • the first doped region and the second doped region each include a heavily doped region and a lightly doped region, and the lightly doped region is adjacent to the heavily doped region, And the heavily doped region is located away from the channel region;
  • the heavily doped region of the first active layer corresponds to the heavily doped region of the second active layer
  • the lightly doped region of the first active layer corresponds to the heavily doped region of the first active layer
  • the lightly doped region of the second active layer corresponds to the source/drain metal layer and is electrically connected to the corresponding second active layer in the heavily doped region.
  • the array substrate further includes a first via hole and a second via hole, and the heavily doped region of the first active layer passes through the first via hole and the second via hole.
  • a hole is connected to the heavily doped region of the second active layer.
  • the array substrate further includes a conductor layer, the conductor layer is disposed in the first via hole and the second via hole, and the first active layer passes through the conductor layer in parallel with the second active layer.
  • the material of the conductor layer is the same as the material of the corresponding second active layer in the heavily doped region.
  • the array substrate further includes a third via hole and a fourth via hole
  • the source/drain metal layer is disposed on the surface of the heavily doped region of the second active layer
  • the source/drain metal layer is electrically connected to the heavily doped region of the first active layer through the third via hole and the fourth via hole.
  • the third via hole and the fourth via hole penetrate the heavily doped region of the second active layer.
  • the source/drain metal layer is disposed on the upper surface of the heavily doped region of the second active layer, and the source/drain metal layer is electrically connected to the second active layer. , and is electrically connected to the first active layer through corresponding via holes.
  • the array substrate further includes a connection metal layer, and the connection metal layer is disposed in a corresponding film layer between the first active layer and the second active layer.
  • connection metal layer and the gate electrode are arranged in the same layer, and the connection metal layer and the source/drain metal layer and the heavily doped region of the first active layer Electrical connection.
  • connection metal layer and the gate electrode are made of the same material.
  • the length of the lightly doped region of the first active layer is smaller than the length of the lightly doped region of the second active layer.
  • the first channel region and the second channel region are arranged corresponding to the gate electrode.
  • the orthographic projection of the second channel region on the substrate is located within the orthographic projection of the first channel region on the substrate.
  • the array substrate further includes a light-shielding layer, the light-shielding layer is disposed on the substrate, and the first active layer is disposed on the light-shielding layer.
  • the orthographic projection of the first channel region of the first active layer on the substrate is located within the orthographic projection of the light-shielding layer on the substrate.
  • a display panel including:
  • a pixel expression layer is provided on the array substrate
  • At least two active layers are provided in the array substrate, the active layers are connected in parallel, and the array substrate is the array substrate provided in the embodiment of the present application.
  • Embodiments of the present application provide an array substrate and a display panel.
  • the array substrate includes a first active layer, a gate, a gate insulating layer, a second active layer, and a source/drain metal layer.
  • the array substrate also includes a conductor layer, the conductor layer being disposed between the first active layer and the source/drain metal layer. between the second active layers, and the first active layer is connected in parallel with the second active layer through the conductor layer.
  • the double-layer parallel active layer structure is arranged vertically, which effectively reduces the layout area of the active layer and further improves the overall performance of the array substrate.
  • Figure 1 is a schematic diagram of the film structure of the first array substrate provided by the embodiment of the present application.
  • Figure 2 is a schematic diagram of the film structure of the second array substrate provided by the embodiment of the present application.
  • Figure 3 is a schematic diagram of the film structure of the third array substrate provided by the embodiment of the present application.
  • Figure 4 is a schematic diagram of the film structure of the fourth array substrate provided by the embodiment of the present application.
  • Figure 5 is a schematic diagram of the film structure of the fifth array substrate provided by the embodiment of the present application.
  • Figure 6 is a schematic diagram of the film structure of the sixth array substrate provided by the embodiment of the present application.
  • FIGS 7 to 13 are schematic diagrams of the film structure of the array substrate shown in Figure 1 during different preparation processes
  • Figure 14 is a simplified plan view corresponding to some film layers in the array substrate provided in Figure 1;
  • FIG. 15 is a side view of the array substrate provided in FIG. 1 .
  • the performance of a display device is closely related to the performance of its internal components.
  • the performance of the obtained thin film transistor is usually not ideal.
  • the on-state current and carrier mobility of the prepared thin film transistor are not ideal, thereby reducing the performance of the device.
  • the quality and effect are not conducive to improving the overall performance of display equipment.
  • Embodiments of the present application provide an array substrate and a display panel to effectively improve the overall performance of the display panel.
  • Figure 1 is a schematic diagram of the film structure of the first array substrate provided by an embodiment of the present application. Specifically, it includes a substrate 101, a light-shielding layer 110, a buffer layer 102, a first active layer 31, a first gate insulating layer 103, a gate 222, a second gate insulating layer 104, a second active layer 32, The interlayer insulating layer 105, and the source electrode 201 and the drain electrode 202.
  • the light-shielding layer 110 is disposed on the substrate 101, and at the same time, the buffer layer 102 is disposed on the substrate 101 and completely covers the light-shielding layer 110.
  • the first active layer 31 is disposed on the buffer layer 102
  • the first gate insulating layer 103 is disposed on the first active layer 31 .
  • the first gate insulating layer 103 completely covers the first active layer 31 .
  • the gate 222 is disposed on the first gate insulating layer 103
  • the second gate insulating layer 104 is disposed on the first gate insulating layer 103
  • the second gate insulating layer 104 completely covers the gate 222
  • the second active layer 32 is disposed on the second gate insulating layer 104
  • the interlayer insulating layer 105 is disposed on the second gate insulating layer 104
  • the interlayer insulating layer 105 completely covers the second active layer 32 .
  • the source electrode 201 and the drain electrode 202 are provided on the interlayer insulating layer 105 .
  • the source/drain metal layers correspond to the source electrode 201 and the drain electrode 202 respectively.
  • the source electrode 201 and the drain electrode 202 are respectively disposed at positions corresponding to the first active layer 31 and the second active layer 32, and the source electrode 201 and the drain electrode 202 are at least connected to the second active layer through corresponding via holes.
  • the active layer 32 is electrically connected.
  • the array substrate further includes a planarization layer 106.
  • the planarization layer 106 is disposed on the interlayer insulating layer 105, and the planarization layer 106 completely covers the source electrode 201 and the drain electrode 202.
  • the first electrode layer 107 and the passivation layer 108 are provided on the planarization layer 106.
  • the first electrode layer 107 is disposed on the planarization layer 106, and the passivation layer 108 completely covers the first electrode layer 107, where the first electrode layer 107 can be a first pixel electrode.
  • the array substrate also includes a second electrode layer 109.
  • the second electrode layer 109 is disposed on the passivation layer 108, and the second electrode layer 109 is electrically connected to the drain electrode 202 through corresponding via holes, wherein the The second electrode layer 109 may be a second pixel electrode.
  • the first active layer 31, the gate electrode 222, the second active layer 32, the source electrode 201, the drain electrode 202 and the corresponding interlayer dielectric layers form a thin film transistor.
  • Driving and control signals are provided to the display device through the thin film transistor 203 .
  • the thin film transistor 203 includes a first active layer 31 and a second active layer 32, and the first active layer 32 and the second active layer 32 are in a parallel structure, thereby effectively improving the performance of the thin film transistor 203. On-state current and other properties.
  • the thin film transistor 203 is formed by at least two active layers connected in parallel, and the active layers are described using the first active layer 31 and the second active layer 32 as an example.
  • the two active layers are arranged in a stacked structure between each film layer.
  • the orthographic projections of each active layer on the substrate correspond to each other or are located in the same area.
  • the orthographic projection of the second active layer 32 on the substrate is located in the area corresponding to the orthographic projection of the first active layer 31 on the substrate. If the orthographic projections of the two completely coincide. Alternatively, the orthographic projection of the second active layer is located within the orthographic projection area of the first active layer. When the projection of the first active layer 31 completely coincides with the orthographic projection of the second active layer 32, the second active layer 32 is disposed directly above the first active layer 31, thereby effectively saving space in the array substrate. Layout space for different active layers to improve device performance.
  • the first active layer 31 includes a first doping region 316 and a first channel region 313.
  • the first doping region 316 is correspondingly disposed on both sides of the first channel region 313.
  • the second active layer 32 includes a second doped region 317 and a second channel region 323.
  • the second doped region 317 is correspondingly disposed on both sides of the second channel region 323.
  • the first doped region 316 and the second doped region 317 are arranged correspondingly, and the first channel region 313 and the second channel region 323 are arranged correspondingly.
  • the second doped region 317 is disposed directly above the first doped region 316
  • the second channel region 323 is disposed directly above the first channel region 313 .
  • the projection length of the orthographic projection of the second doped region 317 on the substrate is greater than the projection length of the orthographic projection of the first doped region 316 on the substrate.
  • the first doped region 316 of the first active layer 31 and the second doped region 317 of the second active layer 32 may be doped regions of the active layer.
  • the first doped region 316 and the second doped region 317 are described using doped regions as examples.
  • the first doped region 316 includes the lightly doped region 312 and the heavily doped region 311 of the first active layer 31 .
  • the lightly doped region 312 is disposed adjacent to the heavily doped region 311 , and the lightly doped region 312 is disposed on a side close to the first channel region 313 .
  • the lightly doped region 312 and the heavily doped region 311 of the first active layer 31 are arranged symmetrically with respect to the first channel region 313 .
  • the second doped region 317 includes the lightly doped region 322 and the heavily doped region 321 of the second active layer 32 .
  • the lightly doped region 322 is disposed adjacent to the heavily doped region 321 , and the lightly doped region 322 is disposed on a side close to the second channel region 323 .
  • the lightly doped region 322 and the heavily doped region 321 are arranged symmetrically with respect to the second channel region 323 .
  • the lightly doped region 312 of the first active layer 31 and the lightly doped region 322 of the second active layer 32 are arranged correspondingly.
  • the heavily doped region 311 of the first active layer 31 and the heavily doped region 321 of the second active layer 32 are arranged correspondingly. Preferably, they are all arranged directly above the corresponding area.
  • the source/drain metal layer is disposed at a position corresponding to the second doped region 317 and is electrically connected to the second active layer 32 .
  • the source electrode 201 is disposed above the heavily doped region 321 of the second doped region 317
  • the drain electrode 202 is disposed above the heavily doped region 321 of the second doped region 317 on the other side.
  • the array substrate also includes a first via hole 250 and a second via hole 251.
  • the first via hole 250 and the second via hole 251 are disposed above the doped region of the first active layer 31, and the first via hole 250 and the second via hole 251 penetrate the second active layer 32 and are in A through hole structure is formed in the doped region 321 of the second active layer 32 .
  • the source-drain metal layer is electrically connected to the first active layer 31 and the second active layer 32 through the first via hole 250 and the second via hole 251.
  • the first active layer 31 and the second active layer 32 form a parallel structure.
  • FIG. 14 is a simplified plan view corresponding to some film layers in the array substrate provided in FIG. 1
  • FIG. 15 is a side view of the array substrate provided in FIG. 1
  • the gate electrode 222 in the thin film transistor is disposed on the first active layer.
  • the first active layer includes a heavily doped region 311, a lightly doped region 312 and a channel region 313.
  • the gate 222 is correspondingly disposed above the channel region 313 .
  • the three layers may be located in the same vertical direction.
  • Figure 2 is a schematic diagram of the film structure of the second array substrate provided by an embodiment of the present application.
  • a conductor layer 45 is also provided in the array substrate.
  • the conductor layer 45 is disposed in the corresponding film layer between the first active layer 31 and the second active layer 32, and the first active layer 31 is connected to the second active layer 32 through the conductor layer 45, And the first active layer 31 and the second active layer 32 form a parallel structure.
  • the conductor layer 45 is described by taking the first conductor layer 451 and the second conductor layer 452 as examples.
  • the first conductor layer 451 and the second conductor layer 452 are respectively disposed in the regions between the heavily doped region 311 of the first active layer 31 and the heavily doped region 321 of the second active layer 32 .
  • one end of the first conductor layer 451 is electrically connected to the heavily doped region 311 of the first active layer 31
  • the other end of the first conductor layer 451 is electrically connected to the heavily doped region of the second active layer 32 .
  • Area 321 is electrically connected.
  • two ends of the second conductor layer 452 are electrically connected to the heavily doped region of the active layer on the other side.
  • the conductor layer when the conductor layer is electrically connected to the second active layer 32, it can be connected through direct contact. That is, the conductor layer is directly disposed at the heavily doped region of the second active layer 32, etched to form via holes in other film layers, and then electrically connected to the first active layer 31 at the bottom.
  • the conductor layer 45 can also be directly disposed in the first via hole and the second via hole.
  • the first conductor layer 451 is disposed in the first via hole 250
  • the second conductor layer 452 is disposed in the second via hole 251.
  • the first via hole 250 and the second via hole 251 can be arranged symmetrically with respect to the second channel region 323.
  • the first via hole 250 and the second via hole 251 are respectively arranged in the heavily doped region. At the middle position of 321.
  • the corresponding heavily doped area is divided into two parts.
  • the doping concentration corresponding to the first part 3211 and the doping concentration in the second part 3212 may be different.
  • the ion doping concentration in the outer second part 3212 is greater than the ion doping concentration in the first part 3211. concentration, thereby forming different concentration differences to further improve the mobility of carriers inside the device.
  • concentration difference can be formed between the first part 3211 and the lightly doped region, and the ion concentration in the first part 3211 is greater than the ion concentration in the lightly doped region to further improve the performance of the device.
  • concentration difference in different areas can be set according to the actual product, which will not be described in detail here.
  • the corresponding conductor layer can extend into the through hole and be electrically connected to the second active layer 32 through the through hole.
  • the material of the first conductor layer 451 and the second conductor layer 452 can be the same material, such as any one of Ti, Al, Mo, and Ti/Al composite materials, or other metal materials with good electrical properties.
  • the material of the conductor layer can also be the same as the material in the heavily doped region of the first active layer 31, when the material of the conductor layer is the same as the material in the heavily doped region of the first active layer 31.
  • the material of the conductor layer is N-type heavily doped material or P-type heavily doped material.
  • the via hole corresponding to the source/drain metal layer is directly etched from the interlayer insulating layer 105 to the corresponding position of the first active layer 31 .
  • the conductor layer is equivalent to a part of the source/drain metal layer, and the parallel structure of the first active layer 31 and the second active layer 32 is realized through the source/drain metal layer. This effectively simplifies the process of thin film transistors and improves the overall performance of the device.
  • the length of the first active layer 31 may be greater than or equal to the length of the second active layer 32 . That is, the length of the orthographic projection of the first active layer 31 on the substrate is greater than or equal to the length of the orthogonal projection of the second active layer 32 on the substrate.
  • the length of the first channel region 313 of the first active layer 31 can be is greater than the length of the channel region 323 of the second active layer 32 .
  • the length of the lightly doped region 312 of the first active layer 31 may be smaller than the length of the lightly doped region 322 of the second active layer 32 .
  • the length of the first channel region 313 of the first active layer 31 is set to 2.1um-3.1um, and the length of the second channel region 323 of the second active layer 32 is set to 1.5um-2.5um. , correspondingly, the length of the first channel region 313 of the first active layer 31 may be 0.4um-1.6um longer than the second channel region of the second active layer 32 .
  • the length of the channel region 313 of the first active layer 31 is 0.6 ⁇ m longer than the channel region of the second active layer 32 .
  • the length of the lightly doped region 322 on each side of the second active layer 32 is set to 1.0um-2.0um.
  • the length of the lightly doped region 322 on one side of the second active layer 32 is set to 1.5um.
  • the length of the lightly doped region 312 on each side of the first active layer 31 is set to 0.7um-1.7um.
  • the length of the lightly doped region 312 on one side of the first active layer 31 is Set to 1.2um.
  • the length of the lightly doped region 312 of the first active layer 31 is 0.3 ⁇ m shorter than the length of the lightly doped region 322 of the second active layer 32 .
  • the length of the heavily doped region on each side of the first active layer 31 and the second active layer 32 is set to between 2.5um and 3.2um, such as 3um.
  • the corresponding different functional areas in the first active layer 31 and the second active layer 32 are set to different parameters, thereby preventing the active layer of the upper layer from being damaged when preparing and forming different active layers.
  • the layer deviation affects the performance of the underlying active layer and effectively improves the performance of the thin film transistor.
  • the length of the gate electrode 222 is not less than the length of the channel region of the first active layer 31, and at the same time, the length of the gate electrode 222 is not less than the length of the second active layer 31.
  • Figure 3 is a schematic diagram of the film structure of the third array substrate provided by the embodiment of the present application.
  • the array substrate may further include a connecting metal layer 46 .
  • the connection metal layer 46 is provided at the corresponding film layer between the first active layer 31 and the second active layer 32 .
  • the connection metal layer 46 is disposed on the first gate insulating layer 103 , and the connection metal layer 46 and the gate electrode 222 are disposed on the same layer.
  • connection metal layer 46 is described by taking the first connection metal layer 461 and the second connection metal layer 462 as an example.
  • the first connection metal layer 461 and the second connection metal layer 462 are respectively disposed on heavily doped layers on both sides. at the corresponding location of the complex area.
  • the connection metal layer is equivalent to a transition connection film layer of the conductor layer.
  • the connection metal layer is provided to reduce the via depth of the first via hole and the second via hole, thereby improving the connection between the devices. connection stability and further improve the overall performance of thin film transistors.
  • a via structure is provided in the heavily doped region 321 of the second active layer 32.
  • the connecting metal layer is electrically connected.
  • the source electrode 201 is electrically connected to the second active layer 32 through the hole, and one end of the source electrode 201 is also electrically connected to the first connection metal layer 461 .
  • the drain electrode 202 is electrically connected to the second active layer 32 through another via hole. At the same time, one end of the drain electrode 202 is also electrically connected to the second connection metal layer 462 . Therefore, the parallel connection between the first active layer 31 and the second active layer 32 is achieved through the source/drain metal layer and the connection metal layer.
  • the first connection metal layer 461 and the second connection metal layer 462 each include an extension portion 4611 and a main body portion 4612.
  • the extension portion 4611 is disposed at an edge of the main body portion 4612, such as a planar structure.
  • the projection of the extension portion 4611 on the substrate is located within the orthographic projection of the heavily doped region 321 on the substrate. Thereby ensuring the performance of the thin film transistor.
  • the via hole corresponding to the connection metal layer can be provided corresponding to the first via hole and the second via hole.
  • the source/drain metal layer can be located in the same vertical plane as the connection metal layer to reduce the problem of The complexity of small process technology.
  • connection metal layer 46 may be the same as the material of the gate electrode 201 . And during preparation, the connection metal layer and the gate electrode are prepared in the same layer, thereby further simplifying the device preparation process. If metal Mo or other metal materials with excellent electrical properties are used, they will not be described in detail here.
  • FIG. 4 is a schematic diagram of the film structure of the fourth array substrate provided by the embodiment of the present application.
  • the first via hole 250 and the second via hole 251 are provided between the first active layer 31 and the second active layer 32 .
  • the heavily doped region 311 of the first active layer 31 is electrically connected to the heavily doped region 321 of the second active layer 32 through the first via hole and the second via hole.
  • the material in the first via hole 250 and the second via hole 251 can be the same as the material in the heavily doped region of the second active layer 32.
  • the material can correspond to N-type heavily doped impurity materials or P-type heavily doped materials.
  • the first via hole 250 and the second via hole are directly provided between the first active layer 31 and the second active layer.
  • Two via holes 251 are provided, thereby effectively reducing the depth of the via hole structure, simplifying the preparation process, and effectively improving the stability of the connection.
  • Figure 5 is a schematic diagram of the film structure of the fifth array substrate provided by an embodiment of the present application.
  • a third via hole 271 and a fourth via hole 272 are provided in the array substrate.
  • the third via hole 271 and the fourth via hole 272 are respectively provided at corresponding positions in the heavily doped region.
  • the third via hole 271 and the fourth via hole 272 penetrate the second active layer 32 and other film layers, and extend to the surface of the first active layer 31.
  • the third via hole 271 and the fourth via hole 271 pass through the second active layer 32 and other film layers.
  • the hole 272 can be obtained through one photomask process, thereby simplifying the manufacturing process.
  • the source electrode 201 is disposed in the third via hole 271
  • the drain electrode 202 is also disposed in the fourth via hole 272 .
  • the source electrode 201 is arranged in the via hole corresponding to the second active layer and extends to the surface of the first active layer 31.
  • the drain electrode 202 is arranged in the via hole corresponding to the second active layer and extends to the first active layer 31. surface of source layer 31 .
  • the source electrode 201 and the drain electrode 202 are directly disposed on the surface of the second active layer 32.
  • the source electrode 201 and the drain electrode 202 are respectively connected with the third via hole 271 and the fourth via hole 272.
  • the two active layers 32 and the first active layer 31 are electrically connected, thereby realizing a parallel structure of the first active layer 31 and the second active layer 32 .
  • the source electrode 201 and the drain electrode 202 are directly disposed on the surface of the second active layer 32. Therefore, there is surface contact between the source/drain metal layer and the active layer, and the contact area is large, and , the source/drain metal layer is directly disposed on the second active layer 32, thereby eliminating an interlayer dielectric layer. Therefore, the array substrate prepared in the embodiment of the present application can effectively improve the connection stability between the source/drain metal layer and the active layer and the overall performance of the device.
  • FIG. 6 is a schematic diagram of the film structure of the sixth array substrate provided by the embodiment of the present application. Combined with the film layer structure in the embodiment of FIG. 3, in the embodiment of the present application, when the source/drain metal layer and the connection metal layer 46 are provided, the source/drain metal layer is directly provided on the second active layer 31, and The source electrode 201 and the drain electrode 202 are respectively disposed in the third via hole 271 and the fourth via hole 272 .
  • the first connection metal layer 461, the second connection metal layer 462 and the gate electrode 222 can be prepared in the same layer, thereby simplifying the preparation process.
  • the material of the first connection metal layer 461 and the second connection metal layer 462 can be the same as the material of the gate electrode 222, and can be selected as metal Mo.
  • the fifth via hole 611 and the sixth via hole 612 penetrating the first gate insulating layer 103 are also provided on the first gate insulation layer 103 .
  • the fifth via hole 611 and the sixth via hole 611 are arranged corresponding to the third via hole 271 and the fourth via hole 272, and the first connection metal layer 461 is arranged in the fifth via hole 611 and is connected with the first via hole 611.
  • the active layer 31 is electrically connected
  • the second connection metal layer 462 is disposed in the sixth via hole 612 and is electrically connected to the first active layer 32 .
  • connection metal layer and a via hole are provided in the film layer between the first active layer 31 and the second active layer 32, thereby reducing the depth of the via hole, and
  • the preparation process is simplified, and at the same time, the performance of the internal via holes of the device and the stability of the connection between devices are effectively improved.
  • the corresponding source/drain metal layers and connection metal layers in the first gate insulating layer 103 and the second gate insulating layer 104 form a parallel structure between the first active layer and the second active layer.
  • the thickness of the first active layer 31 and the second active layer 32 is set to 400 ⁇ - 500 ⁇ .
  • the thickness of the first gate insulating layer 103 and the second gate insulating layer 104 is set to 1000 ⁇ -1500 ⁇ , and the corresponding materials may be insulating SiOx and other materials.
  • the thickness of the interlayer insulating layer 105 is set to 5000 ⁇ -7000 ⁇ , and the corresponding material may be at least one of SiOx and SiNx. Or set it according to the actual product specifications, which will not be described here.
  • embodiments of the present application also provide a method for preparing an array substrate.
  • the preparation process corresponding to the film layer structure provided in FIG. 1 is taken as an example for description.
  • Figures 7-13 are schematic diagrams of the film structure of the array substrate shown in Figure 1 during different preparation processes.
  • a substrate 101 is first provided, and a light-shielding layer 110 is prepared on the substrate 101 .
  • a buffer layer 102 is prepared on the light-shielding layer 110 .
  • a semiconductor layer is prepared on the buffer layer 102 .
  • the semiconductor layer is conductorized to form a heavily doped region 311, a lightly doped region 312, and a first channel region 313.
  • the first channel region 313 may correspond to an ion-doped polysilicon layer. And form the first active layer 31 in the embodiment of the present application.
  • a first gate insulating layer 103 is prepared on the first active layer 31.
  • a gate insulating layer 103 is prepared on the first gate insulating layer 103.
  • electrode 222 and prepare a second gate insulating layer 104 on the gate electrode 222.
  • the first gate insulating layer 103 completely covers the first active layer 31
  • the second gate insulating layer 104 completely covers the gate 222 .
  • a second active layer 31 is prepared on the second gate insulating layer 104 .
  • the light-shielding layer 110, the first active layer 31 and the second active layer 32, and the gate electrode 222 can be arranged correspondingly, that is, the above-mentioned film layers can be arranged in the same vertical plane, and the light-shielding layer
  • the length of 110 is greater than the total length of the first channel region 313 and the lightly doped region 312 of the first active layer 31 .
  • the material of the light shielding layer 110 can be the same as the material of the connecting metal layer, the conductor layer or the source/drain metal layer.
  • the second active layer 32 When forming the second active layer 32, a semiconductor layer is first prepared on the second gate insulating layer 104, and the semiconductor layer is ion doped, and finally forms the semiconductor layer in the embodiment of the present application.
  • the second active layer 32 also includes a heavily doped region 321 , a lightly doped region 322 and a second channel region 323 .
  • the ion concentration in the heavily doped region 321 and the lightly doped region 322 can be set according to the actual product.
  • a planarization layer 106 is prepared on the second active layer 32 .
  • the planarization layer 106 completely covers the second active layer 32 .
  • holes are opened at positions corresponding to the active layer of the thin film transistor.
  • first, third and fourth via holes 271 and 272 are provided at corresponding positions of the first active layer 31 and the second active layer 32 .
  • the third via hole 271 penetrates the heavily doped region 321 of the second active layer 32, and simultaneously penetrates the planarization layer 106, the first gate insulating layer 103 and the second gate insulating layer 104, and makes Part of the first active layer 31 is exposed.
  • the depths of the third via hole 271 and the fourth via hole 272 are relatively deep, they can be etched through a two-pass etching process.
  • the third via hole 271 is etched to the surface of the second gate insulating layer 104 , and then in the second process, the third via hole 271 is etched from the surface of the second gate insulating layer 104 to the first via hole 271 .
  • the surface of the source layer 31 finally forms the via structure provided in the embodiment of the present application.
  • the through hole in the second active layer 31 overlaps with the corresponding third via hole 271 or fourth via hole 272 .
  • the size of the through hole of the active layer 31 can be determined according to the specifications of the actual product, and during etching, the through hole can be located in the central area of the heavily doped region.
  • the source electrode 201 is prepared in the third via hole 271, and at the same time, the drain electrode 202 is prepared in the fourth via hole 272, and The source electrode 201 and the drain electrode 202 are electrically connected to the first active layer 31 and the second active layer 32 .
  • a planarization layer 106 is prepared on the interlayer insulating layer 105.
  • etching is performed and a via hole 725 is formed at the position corresponding to the planarization layer 106 and the drain electrode 202.
  • the surface of the drain electrode 202 is exposed through the via hole 725 .
  • a first electrode layer 107 is prepared on the planarization layer 106 .
  • a passivation layer 108 is prepared on the planarization layer 106.
  • the passivation layer 108 completely covers the first electrode layer 107.
  • the passivation layer 108 is etched at a position corresponding to the via hole 725 , and a via hole 726 is formed.
  • the via hole 726 is located in the via hole 725 , and its aperture is smaller than the via hole aperture of the via hole 725 .
  • a second electrode layer 109 is prepared on the passivation layer 108 , and the second electrode layer 109 fills the via hole 726 and is electrically connected to the drain electrode 202 .
  • a stack structure in which two-layer active layers are connected in parallel is formed through preparation.
  • the parallel structure can effectively increase the on-state current in the device, and at the same time, further improve the carrier migration efficiency of the device.
  • the first active layer and the second active layer are arranged in a double-layer vertical structure, thereby effectively reducing the layout area of the devices in the array substrate.
  • they can be prepared in the existing process technology and are compatible with the existing process technology.
  • the preparation method and process provided in this application are simpler. It can further improve the overall performance of the device.
  • embodiments of the present application also provide a display panel.
  • the display panel may include an array substrate and a pixel expression layer disposed on the array substrate.
  • the pixel expression layer may include functional film layers such as a liquid crystal layer, an organic light-emitting function, an electrophoretic layer, etc., and the pixel expression layer is used to realize or assist in realizing the luminescent display of the display panel.
  • the thin film transistor of the display panel provided in the embodiment of the present application adopts a double-layer parallel structure, thereby effectively improving the luminous efficiency and overall performance of the display panel.
  • the display panel can be any product or component with display function and touch function such as mobile phone, computer, electronic paper, monitor, notebook computer, digital photo frame, etc., and its specific type is not specifically limited.

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Abstract

本申请实施例提供一种阵列基板及显示面板。包括第一有源层、栅极、栅极绝缘层、第二有源层以及源/漏金属层，且第一有源层通过该导体层与第二有源层并联。通过两层并联的有源层结构，有效提高器件的开态电流和载流子迁移率，并提高器件的综合性能。

Description

阵列基板及显示面板 技术领域
本发明涉及显示面板的制造技术领域，尤其涉及一种阵列基板及显示面板。
 背景技术
随着显示面板制备技术的发展，人们对显示面板及显示装置的显示效果以及综合性能均提出了更高的要求。
显示面板中，低温多晶硅薄膜晶体管是液晶显示器（Liquid Crystal Display，LCD）和有机发光二极管（Organic Light Emitting Diode，OLED）等显示装置中有源驱动、周边电路中的关键部件。其中，为了提高薄膜晶体管的性能，现有技术中，通常通过在薄膜晶体管内部制备形成轻掺杂漏、抬升源漏等结构，通过轻掺杂漏、抬升源漏结构以达到提高薄膜晶体管器件的稳定性及可靠性。因此，由上述结构制备得到的器件，虽然能在一定程度上可对薄膜晶体管的性能进行提升。但是，上述结构还会额外引入新的串联电阻结构，该串联电阻结构容易导致薄膜晶体管内部的开态电流以及等效载流子的迁移率降低，进而影响薄膜晶体管的性能，不利于薄膜晶体管综合性能的进一步提高。
因此需要对现有技术中的问题提出解决方法。
 技术问题
综上所述，现有的显示面板中，显示面板内部的薄膜晶体管的开态电流以及等效载流子的迁移率较低，不利于显示面板综合性能的进一步提高。
 技术解决方案
为解决上述问题，本发明实施例提供一种阵列基板及显示面板。以有效的提高显示面板内部的薄膜晶体管的开态电流及载流子的迁移率，并提高器件的综合性能。
为解决上述技术问题，本发明提供一种阵列基板及显示面板。该阵列基板包括：
衬底；
第一有源层，设置于所述衬底之上，所述第一有源层包括第一沟道区以及设置在所述第一沟道区两侧的第一掺杂区；
栅极，设置于所述第一有源层之上；
栅极绝缘层，设置于所述第一有源层之上，并覆盖所述栅极；
第二有源层，设置于所述栅极绝缘层之上，所述第二有源层包括第二沟道区以及设置在所述第二沟道区两侧的第二掺杂区；以及，
源/漏金属层，设置于所述第二有源层之上；
其中，所述第一掺杂区与所述第二掺杂区对应设置，所述源/漏金属层与所述第二掺杂区内的所述第二有源层电性连接，且所述第一掺杂区内的所述第一有源层，对应的与所述第二掺杂区内的所述第二有源层电性连接；
其中，所述第一有源层的长度大于等于所述第二有源层的长度。
根据本发明一实施例，所述第二掺杂区在所述衬底上的正投影的长度，大于所述第一掺杂区在所述衬底上的正投影的长度。
根据本发明一实施例，所述第一掺杂区以及所述第二掺杂区均包括重掺杂区域与轻掺杂区，所述轻掺杂区与所述重掺杂区相邻，且所述重掺杂区域远离沟道区设置；
其中，所述第一有源层的所述重掺杂区与所述第二有源层的所述重掺杂区相对应，所述第一有源层的所述轻掺杂区与所述第二有源层的所述轻掺杂区相对应，且所述源/漏金属层与所述重掺杂区内对应的所述第二有源层电性连接。
根据本发明实施例的第二方面，还提供一种阵列基板，该阵列基板包括：
衬底；
第一有源层，设置于所述衬底之上，所述第一有源层包括第一沟道区以及设置在所述第一沟道区两侧的第一掺杂区；
栅极，设置于所述第一有源层之上；
栅极绝缘层，设置于所述第一有源层之上，并覆盖所述栅极；
第二有源层，设置于所述栅极绝缘层之上，所述第二有源层包括第二沟道区以及设置在所述第二沟道区两侧的第二掺杂区；以及，
源/漏金属层，设置于所述第二有源层之上；
其中，所述第一掺杂区与所述第二掺杂区对应设置，所述源/漏金属层与所述第二掺杂区内的所述第二有源层电性连接，且所述第一掺杂区内的所述第一有源层，对应的与所述第二掺杂区内的所述第二有源层电性连接。
根据本发明一实施例，所述第二掺杂区在所述衬底上的正投影的长度，大于所述第一掺杂区在所述衬底上的正投影的长度。
根据本发明一实施例，所述第一掺杂区以及所述第二掺杂区均包括重掺杂区域与轻掺杂区，所述轻掺杂区与所述重掺杂区相邻，且所述重掺杂区域远离沟道区设置；
其中，所述第一有源层的所述重掺杂区与所述第二有源层的所述重掺杂区相对应，所述第一有源层的所述轻掺杂区与所述第二有源层的所述轻掺杂区相对应，且所述源/漏金属层与所述重掺杂区内对应的所述第二有源层电性连接。
根据本发明一实施例，所述阵列基板还包括第一过孔与第二过孔，所述第一有源层的所述重掺杂区通过所述第一过孔以及所述第二过孔，与所述第二有源层的所述重掺杂区连接。
根据本发明一实施例，所述阵列基板还包括导体层，所述导体层设置在所述第一过孔与所述第二过孔内，且所述第一有源层通过所述导体层与所述第二有源层并联。
根据本发明一实施例，所述导体层的材料与所述重掺杂区内对应的所述第二有源层的材料相同。
根据本发明一实施例，所述阵列基板还包括第三过孔与第四过孔，所述源/漏金属层设置在所述第二有源层的所述重掺杂区的表面，且所述源/漏金属层通过所述第三过孔与所述第四过孔与所述第一有源层的重掺杂区电性连接。
根据本发明一实施例，所述第三过孔以及所述第四过孔贯穿所述第二有源层的所述重掺杂区。
根据本发明一实施例，所述源/漏金属层设置在所述第二有源层的重掺杂区域的上表面，所述源/漏金属层与所述第二有源层电性连接，并通过对应的过孔与所述第一有源层电性连接。
根据本发明一实施例，所述阵列基板还包括连接金属层，所述连接金属层设置在所述第一有源层与所述第二有源层之间对应的膜层内。
根据本发明一实施例，所述连接金属层与所述栅极同层设置，且所述连接金属层与所述源/漏金属层以及所述第一有源层的所述重掺杂区电性连接。
根据本发明一实施例，所述连接金属层与所述栅极的材料相同。
根据本发明一实施例，所述第一有源层的所述轻掺杂区的长度小于所述第二有源层的所述轻掺杂区的长度。
根据本发明一实施例，所述第一沟道区与所述第二沟道区与所述栅极对应设置。
根据本发明一实施例，所述第二沟道区在所述衬底上的正投影，位于所述第一沟道区在所述衬底上的正投影内。
根据本发明一实施例，所述阵列基板还包括遮光层，所述遮光层设置在所述衬底之上，且所述第一有源层设置在所述遮光层之上。
根据本发明一实施例，所述第一有源层的所述第一沟道区在所述衬底上的正投影，位于所述遮光层在所述衬底上的正投影内。
根据本发明实施例的第三方面，还提供一种显示面板，包括：
阵列基板；以及，
像素表述层，设置于所述阵列基板之上；
其中，所述阵列基板内至少设置两层有源层，所述有源层之间并联，且所述阵列基板为如本申请实施例中提供的所述的阵列基板。
 有益效果
综上所述，本发明实施例的有益效果为：
本申请实施例提供一种阵列基板及显示面板。阵列基板包括第一有源层、栅极、栅极绝缘层、第二有源层以及源/漏金属层，其中，该阵列基板还包括导体层，该导体层设置在第一有源层与第二有源层之间，且该第一有源层通过该导体层与第二有源层并联。本申请实施例中，通过设置两层并联的有源层结构，从而有效的提高薄膜晶体管的开态电流和载流子的迁移率。同时，本申请实施例中，该双层并联的有源层结构垂直布置，有效的减小了有源层的布局面积，进一步提高该阵列基板的综合性能。
 附图说明
图1为本申请实施例提供的第一种阵列基板的膜层结构示意图；
图2为本申请实施例提供的第二种阵列基板的膜层结构示意图；
图3为本申请实施例提供的第三种阵列基板的膜层结构示意图；
图4为本申请实施例提供的第四种阵列基板的膜层结构示意图；
图5为本申请实施例提供的第五种阵列基板的膜层结构示意图；
图6为本申请实施例提供的第六种阵列基板的膜层结构示意图；
图7-图13为图1所示阵列基板在不同制备工艺时对应的膜层结构示意图；
图14为图1中提供的阵列基板中的部分膜层对应的平面简化示意图；
图15为图1中提供的阵列基板的侧视图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本揭示可用以实施的特定实施例。
随着显示面板制备技术的不断发展，人们对显示面板及显示装置的性能以及显示效果均提出了更高的要求。
显示设备性能的好坏与其内部器件的性能密切相关。现有技术中，在制备形成显示面板内的薄膜晶体管器件时，通常得到的薄膜晶体管的性能不理想，如制备得到的薄膜晶体管的开态电流以及载流子的迁移率不理想，进而降低器件质量及效果，不利于显示设备综合性能的提高。
本申请实施例提供一种阵列基板及显示面板，以有效的提高显示面板的综合性能。
如图1所示，图1为本申请实施例提供的第一种阵列基板的膜层结构示意图。具体的，包括衬底101、遮光层110、缓冲层102、第一有源层31、第一栅极绝缘层103、栅极222、第二栅极绝缘层104、第二有源层32、层间绝缘层105、以及源极201和漏极202。
具体的，该遮光层110设置在衬底101上，同时，缓冲层102设置在衬底101上，并完全覆盖该遮光层110。第一有源层31设置在缓冲层102上，第一栅极绝缘层103设置在第一有源层31上，同时，该第一栅极绝缘层103完全覆盖该第一有源层31。
同时，该栅极222设置在第一栅极绝缘层103上，第二栅极绝缘层104设置在第一栅极绝缘层103上，且该第二栅极绝缘层104完全覆盖该栅极222，第二有源层32设置在第二栅极绝缘层104上，层间绝缘层105设置在第二栅极绝缘层104上，且该层间绝缘层105完全覆盖该第二有源层32。
本申请实施例中，该源极201和漏极202设置在层间绝缘层105上。本申请实施例中该源/漏金属层分别对应源极201与漏极202。具体的，源极201和漏极202对应设置在第一有源层31与第二有源层32相对应的位置处，且该源极201和漏极202至少通过对应的过孔与第二有源层32电性连接。
进一步的，该阵列基板还包括平坦化层106，平坦化层106设置在层间绝缘层105上，且该平坦化层106完全覆盖该源极201和漏极202。以及，设置在该平坦化层106之上的第一电极层107和钝化层108。该第一电极层107设置在平坦化层106上，且钝化层108完全覆盖该第一电极层107，其中，该第一电极层107可为第一像素电极。
同时，该阵列基板还包括第二电极层109，该第二电极层109设置在钝化层108上，且该第二电极层109通过对应的过孔与该漏极202电连接，其中，该第二电极层109可为第二像素电极。
本申请实施例中，在该阵列基板内，该第一有源层31、栅极222、第二有源层32、源极201、漏极202以及对应的各层间介质层形成一薄膜晶体管203。通过该薄膜晶体管203以向显示器件提供驱动及控制信号。同时，在该薄膜晶体管203内，包括第一有源层31和第二有源层32，且第一有源层32和第二有源层32为并联结构，从而有效提高该薄膜晶体管203的开态电流等性能。
以下具体实施例中，该薄膜晶体管203由至少两个有源层并联所形成，且该有源层以第一有源层31和第二有源层32为例进行说明。两层有源层在各膜层之间呈层叠结构进行设置，如各有源层在衬底上的正投影相互对应或者均位于同一区域内。
优选的，该第二有源层32在衬底上的正投影，位于该第一有源层31在衬底上的正投影对应的区域内。如两者的正投影完全重合。或者，该第二有源层的正投影位于该第一有源层的正投影区域内。当第一有源层31的投影与第二有源层32的正投影完全重合时，该第二有源层32设置在第一有源层31的正上方，从而有效的节省的阵列基板内不同有源层的布局空间，以提高器件的性能。
进一步的，本申请实施例中，该第一有源层31包括第一掺杂区316及第一沟道区313，第一掺杂区316对应设置在第一沟道区313的两侧位置处。第二有源层32包括第二掺杂区317及第二沟道区323，第二掺杂区317对应设置在第二沟道区323的两侧。其中，该第一掺杂区316与第二掺杂区317对应设置，第一沟道区313与第二沟道区323对应设置。优选的，该第二掺杂区317设置在第一掺杂区316的正上方位置处，第二沟道区323设置在第一沟道区313的正上方位置处。
其中，该第二掺杂区317在衬底上的正投影的投影长度大于第一掺杂区316在衬底上的正投影的投影长度。
本申请实施例中，第一有源层31的第一掺杂区316以及第二有源层32的第二掺杂区317可为有源层的掺杂区。以下实施例中，该第一掺杂区316和第二掺杂区317均以掺杂区为例进行说明。
具体的，在该第一有源层31中，第一掺杂区316包括第一有源层31的轻掺杂区312以及重掺杂区311。该轻掺杂区312与重掺杂区311相邻设置，且该轻掺杂区312设置在靠近第一沟道区313的一侧。优选的，第一有源层31的轻掺杂区312和重掺杂区311相对该第一沟道区313对称设置。
同时，在该第二有源层32中，第二掺杂区317包括第二有源层32的轻掺杂区322以及重掺杂区321。该轻掺杂区322与重掺杂区321相邻设置，且该轻掺杂区322设置在靠近第二沟道区323的一侧。优选的，轻掺杂区322和重掺杂区321相对该第二沟道区323对称设置。
本申请实施例中，该第一有源层31的轻掺杂区312与第二有源层32的轻掺杂区322对应设置。同时，第一有源层31的重掺杂区311与第二有源层32的重掺杂区321对应设置。优选的，均设置在对应区域的正上方位置处。
其中，该源/漏金属层设置在与第二掺杂区317对应位置处，并与第二有源层32电性连接。具体的，源极201设置在第二掺杂区317的重掺杂区321上方位置处，漏极202设置在另一侧第二掺杂区317的重掺杂区321的上方位置处。
具体的，该阵列基板还包括第一过孔250和第二过孔251。第一过孔250与第二过孔251设置在第一有源层31的掺杂区上方位置处，且该第一过孔250和第二过孔251贯穿第二有源层32，并在该第二有源层32的掺杂区321中形成一通孔结构。
本申请实施例中，该源漏金属层通过该第一过孔250和第二过孔251与第一有源层31以及第二有源层32电性连接。从而使得第一有源层31与第二有源层32形成并联结构。
进一步的，如图14及图15所示，图14为图1中提供的阵列基板中的部分膜层对应的平面简化示意图，图15为图1中提供的阵列基板的侧视图。详见图14，该薄膜晶体管内的栅极222设置在第一有源层之上。具体的，该第一有源层包括重掺杂区311、轻掺杂区312以及沟道区313。同时，该栅极222对应设置在该沟道区313上方。详见图15，在设置第一有源层31、第二有源层32以及遮光层110时，三种可位于同一竖直方向上。
具体的，如图2所示，图2为本申请实施例提供的第二种阵列基板的膜层结构示意图。
本申请实施例中，该阵列基板内还设置有导体层45。该导体层45设置在第一有源层31和第二有源层32之间对应的膜层中，且该第一有源层31通过该导体层45与第二有源层32进行连接，并使第一有源层31与第二有源层32形成并联结构。
具体的，本申请实施例中，该导体层45以第一导体层451和第二导体层452为例进行说明。该第一导体层451和第二导体层452分别对应设置在第一有源层31的重掺杂区311与第二有源层32的重掺杂区321之间的区域内。同时，该第一导体层451的一端对应的与第一有源层31的重掺杂区311电性连接，第一导体层451的另一端对应的与第二有源层32的重掺杂区321电性连接。且，该第二导体层452的两端对应的与另一侧的有源层的重掺杂区电性连接。
优选的，本申请实施例中，该导体层在与第二有源层32电性连接时，可通过直接接触式连接。即直接在第二有源层32的重掺杂区位置处设置该导体层，并在其他膜层中蚀刻形成过孔，再与底部的第一有源层31电性连接。
同时，该导体层45还可直接设置在第一过孔与第二过孔内。优选的，第一导体层451设置在第一过孔250内，第二导体层452设置在第二过孔251内，其中，在形成上述第一过孔250与第二过孔251时，可通过一次蚀刻形成，并可直接将该导体层填充在该过孔内，从而有效的简化了制备工艺，并提高器件的性能。
本申请实施例中，该第一过孔250和第二过孔251可相对第二沟道区323对称设置，优选的，第一过孔250和第二过孔251分别设置在重掺杂区321的中间位置处。
进一步的，本申请实施例中，第一过孔250和第二过孔251在贯穿第一有源层31时，将对应的重掺杂区分成两部分。如第一部分3211和另一侧的第二部分3212。本申请实施例中，该第一部分3211对应的掺杂浓度和第二部分3212内的掺杂浓度可不同，如外侧的第二部分3212内的离子掺杂浓度大于第一部分3211内的离子掺杂浓度，从而形成不同的浓度差，以进一步提高该器件内部载流子的迁移率。
优选的，该第一部分3211还可与轻掺杂区之间形成另一浓度差，且该第一部分3211的内的离子浓度大于轻掺杂区内的离子浓度，以进一步提高器件的性能，具体的，不同区域内的浓度差可根据实际产品进行设置，这里不详细赘述。
当该有源层32内设置有第一过孔250和第二过孔251时，其对应的导体层可延伸至该通孔内，并通过该通孔与第二有源层32电连接。
同时，该第一导体层451和第二导体层452的材料可为相同的材料，如Ti、Al、Mo以及Ti/Al复合材料中的任意一种，或者其他电性性能好的金属材料。进一步的，该导体层的材料还可与第一有源层31的重掺杂区域内的材料相同，当该导体层的材料与第一有源层31的重掺杂区域内的材料相同时，该导体层的材料为N型重掺杂材料或P型重掺杂材料。
具体的，如图1中，本申请实施例中，该源/漏金属层对应的过孔从层间绝缘层105处直接蚀刻至第一有源层31对应位置处。这样，该导体层相当于源/漏金属层的一部分，通过该源/漏金属层实现第一有源层31与第二有源层32的并联结构。从而有效的简化薄膜晶体管的工艺制程并提高器件的综合性能。
进一步的，本申请实施例中，在设置上述第一有源层31和第二有源层32时，该第一有源层31的长度可大于等于第二有源层32的长度。即第一有源层31在衬底上的正投影长度，大于等于第二有源层32在衬底上的正投影的长度。
同时，为了保证该薄膜晶体管的性能，本申请实施例中，在设置第一有源层31以及第二有源层32时，该第一有源层31的第一沟道区313的长度可大于第二有源层32的沟道区323的长度。同时，该第一有源层31的轻掺杂区312的长度可小于第二有源层32的轻掺杂区322的长度。
优选的，该第一有源层31的第一沟道区313的长度设置为2.1um-3.1um，该第二有源层32的第二沟道区323的长度设置为1.5um-2.5um，对应的，该第一有源层31的第一沟道区313的长度可比第二有源层32的第二沟道区长0.4um-1.6um。如第一有源层31的沟道区313的长度比第二有源层32的沟道区长0.6um。
同时，该第二有源层32的每一侧的轻掺杂区322的长度设置为1.0um-2.0um。优选的，该第二有源层32的单侧的该轻掺杂区322的长度设置为1.5um。且，该第一有源层31的每一侧的轻掺杂区312的长度设置为0.7um-1.7um，优选的，该第一有源层31的单侧的轻掺杂区312的长度设置为1.2um。此时，该第一有源层31的轻掺杂区312的长度比第二有源层32的轻掺杂区322的长度短0.3um。
进一步的，本申请实施例中，该第一有源层31与第二有源层32的每一侧的重掺杂区的长度设置为2.5um-3.2um之间，如设置为3um。本申请实施例中，通过将第一有源层31以及第二有源层32中对应的不同功能区设置为不同的参数，从而防止在制备形成不同的有源层时，防止上层的有源层出现偏移而影响下层有源层的性能，并有效的提高薄膜晶体管的性能。
本申请实施例中，在设置薄膜晶体管的栅极222时，该栅极222的长度不小于第一有源层31的沟道区的长度，同时，该栅极222的长度不小于第二有源层32的沟道区的长度。
进一步的，如图3所示，图3为本申请实施例提供的第三种阵列基板的膜层结构示意图。同时结合图1-图2中的膜层结构。本申请实施例中，该阵列基板还可包括一连接金属层46。连接金属层46设置在第一有源层31与第二有源层32之间对应的膜层处。其中，以下实施例中，该连接金属层46设置在第一栅极绝缘层103上，并且该连接金属层46与栅极222同层设置。
以下实施例中，该连接金属层46以第一连接金属层461和第二连接金属层462为例进行说明，第一连接金属层461和第二连接金属层462分别设置在两侧的重掺杂区域对应位置处。本申请实施例中，该连接金属层相当于该导体层的一过渡连接膜层，通过设置该连接金属层以减小第一过孔与第二过孔的过孔深度，从而提高器件之间连接的稳定性，并进一步提高薄膜晶体管的综合性能。
具体的，本申请实施例中，该第二有源层32的重掺杂区域321内分别设置有过孔结构，通过该过孔结构，薄膜晶体管的源极201与漏极202分别与对应的连接金属层电连接。其中，源极201通过孔与第二有源层32电连接，源极201的一端还与该第一连接金属层461电连接。漏极202通过另一过孔与第二有源层32电连接，同时，该漏极202的一端还与第二连接金属层462电连接。从而通过该源/漏金属层以及连接金属层，实现该第一有源层31和第二有源层32之间的并联。
优选的，该第一连接金属层461和第二连接金属层462均包括一延伸部4611和主体部4612，该延伸部4611设置在主体部4612的边缘位置处，如设置为一平面结构。且该延伸部4611在衬底上的投影位于该重掺杂区321在衬底上的正投影内。从而保证该薄膜晶体管的性能。
本申请实施例中，该连接金属层对应的过孔可与第一过孔与第二过孔对应设置，这样，该源/漏金属层可与连接金属层位于同一竖直面内，以减小制程工艺的复杂性。
本申请实施例中，该连接金属层46的材料可与栅极201的材料相同。且在进行制备时，该连接金属层与栅极同层制备，从而进一步简化器件的制备工艺。如均采用金属Mo，或者其他电性优良的金属材料，这里不再详细赘述。
如图4所示，图4为本申请实施例提供的第四种阵列基板的膜层结构示意图。本申请实施例中，该第一过孔250和第二过孔251设置在第一有源层31和第二有源层32之间。且第一有源层31的重掺杂区域311通过该第一过孔以及第二过孔，与第二有源层32的重掺杂区域321电性连接。
具体的，在进行连接时，该第一过孔250与第二过孔251内的材料可与第二有源层32的重掺杂区域的材料相同，如该材料可对应为N型重掺杂材料或P型重掺杂材料。
相较于图1中源/漏金属层对应的深过孔结构，本申请实施例中，通过直接在该第一有源层31与第二有源层之间设置第一过孔250与第二过孔251，从而有效的减小了该过孔结构的深度，并简化了制备工艺，有效的提高其连接的稳定性。
优选的，如图5所示，图5为本申请实施例提供的第五种阵列基板的膜层结构示意图。同时结合图1-图4中的膜层结构，本申请实施例中，该阵列基板内设置有第三过孔271和第四过孔272。第三过孔271和第四过孔272对应设置在重掺杂区域对应位置处。并且该第三过孔271和第四过孔272贯穿第二有源层32以及其他膜层，并延伸至第一有源层31的表面，此时，该第三过孔271和第四过孔272可通过一次光罩处理得到，从而简化制备工艺。
本申请实施例中，在该第三过孔271内设置有源极201，第四过孔272内还设置有漏极202。源极201设置在第二有源层对应的过孔内，并延伸至第一有源层31的表面，漏极202设置在第二有源层对应的过孔内，并延伸至第一有源层31的表面。
进一步的，本申请实施例中，源极201和漏极202直接设置在第二有源层32的表面，该源极201和漏极202分别第三过孔271和第四过孔272与第二有源层32以及第一有源层31电连接，从而实现第一有源层31与第二有源层32的并联结构。
本申请实施例中，该源极201和漏极202直接设置在第二有源层32的表面，因此，源/漏金属层与有源层之间为面接触，且接触面较大，并且，该源/漏金属层直接设置在第二有源层32上，从而可省去一层层间介质层。因此，本申请实施例中制备得到的该阵列基板，可有效的提高了源/漏金属层与有源层之间的连接稳定性以及器件的综合性能。
进一步的，如图6所示，图6为本申请实施例提供的第六种阵列基板的膜层结构示意图。结合图3实施例中的膜层结构，本申请实施例中，在设置该源/漏金属层以及连接金属层46时，该源/漏金属层直接设置在第二有源层31上，且该源极201和漏极202均对应设置在该第三过孔271和第四过孔272内。
本申请实施例中，该第一连接金属层461与第二连接金属层462与栅极222可同层制备，从而简化制备工艺。优选的，该第一连接金属层461与第二连接金属层462的材料可与该栅极222的材料相同，可选取为金属Mo。
进一步的，在设置对应位置处的过孔结构时，在第一栅极绝缘层103上还设置有贯穿该层的第五过孔611和第六过孔612。其中，该第五过孔611和第六过孔611与第三过孔271和第四过孔272对应设置，且该第一连接金属层461设置在第五过孔611内，并与第一有源层31电连接，该第二连接金属层462设置在第六过孔612内，并与第一有源层32电连接。
结合图1中的结构，本申请实施例中，通过在第一有源层31与第二有源层32之间的膜层内设置连接金属层以及过孔，从而减小过孔深度，并简化制备工艺，同时，还有效的提高了器件内部过孔的性能以及器件之间连接的稳定性。
此时，该第一栅极绝缘层103以及第二栅极绝缘层104内对应的源/漏极金属层以及连接金属层，使第一有源层与第二有源层形成并联结构。
进一步的，本申请实施例中，在设置上述各膜层结构时，为了达到尽可能降低形成的显示面板的厚度，该第一有源层31和第二有源层32的厚度设置为400Å-500Å。同时，该第一栅极绝缘层103和第二栅极绝缘层104的厚度设置为1000Å-1500Å，其对应的材料可为绝缘的SiOx等材料。以及该层间绝缘层105的厚度设置为5000Å-7000Å，其对应的材料可为SiOx、SiNx中的至少一种。或者根据实际产品的规格进行设定，这里不再赘述。
优选的，本申请实施例还提供一种阵列基板的制备方法。以下实施例中，以图1中提供的膜层结构对应的制备工艺为例进行说明。如图7-图13所示，图7-图13为图1所示阵列基板在不同制备工艺时对应的膜层结构示意图。
具体的，首先提供一衬底101，并在该衬底101上制备一遮光层110。同时，在该遮光层110上制备一缓冲层102。并在该缓冲层102上制备半导体层。
制备完成后，对该半导体层进行导体化处理，并使其形成重掺杂区311、轻掺杂区312、以及第一沟道区313。本申请实施例中，该第一沟道区313可对应为进行离子掺杂的多晶硅层。并形成本申请实施例中的第一有源层31。
详见图9，第一有源层31制备完成后，再在该第一有源层31上制备一第一栅极绝缘层103，同时，在该第一栅极绝缘层103上制备一栅极222，并在该栅极222上制备一第二栅极绝缘层104。本申请实施例中，该第一栅极绝缘层103完全覆盖第一有源层31，第二栅极绝缘层104完全覆盖栅极222。并在该第二栅极绝缘层104上制备第二有源层31。
本申请实施例中，该遮光层110、该第一有源层31以及第二有源层32、栅极222可对应设置，即上述膜层可设置在同一竖直平面内，且该遮光层110的长度大于该第一有源层31的第一沟道区313与轻掺杂区312的总长度。同时，该遮光层110的材料可与连接金属层、导体层或者源/漏金属层的材料相同。
详见图10，在形成该第二有源层32时，先在该第二栅极绝缘层104上制备一半导体层，并对该半导体层进行离子掺杂，并最终形成本申请实施例中的第二有源层32。其中，该第二有源层32也包括重掺杂区321、轻掺杂区322以及第二沟道区323。本申请实施例中，该重掺杂区321和轻掺杂区322内的离子浓度可根据实际产品进行设定。
详见图11所示，第二有源层32制备完成后，在该第二有源层32上制备一平坦化层106。本申请实施例中，该平坦化层106完全覆盖该第二有源层32。平坦化层106制备完成后，在该薄膜晶体管的有源层对应的位置处进行开孔。
具体的，在该第一有源层31以及第二有源层32对应的位置处设置第一第三过孔271和第四过孔272。此时，该第三过孔271贯穿该第二有源层32的重掺杂区321，并同时贯穿平坦化层106、第一栅极绝缘层103和第二栅极绝缘层104，并使部分第一有源层31暴露。
此时，由于该第三过孔271和第四过孔272的深度较深，可通过两道次的蚀刻工艺进行蚀刻。第一道蚀刻时，将该第三过孔271蚀刻至第二栅极绝缘层104的表面，然后在第二道次工艺中，从该第二栅极绝缘层104的表面蚀刻至第一有源层31的表面，并最终形成本申请实施例中提供的过孔结构。
本申请实施例中，该第二有源层31中的通孔与对应的第三过孔271或第四过孔272相重合。同时，该有源层31的通孔大小可根据实际产品的规格进行确定，并且在蚀刻时，使该通孔位于重掺杂区中心区域处。
详见图12所示，第三过孔271和第四过孔272蚀刻完成后，在第三过孔271内制备源极201，同时，在第四过孔272内制备漏极202，并使源极201和漏极202与第一有源层31和第二有源层32电性连接。
源/漏金属层制备完成后，在层间绝缘层105上制备一平坦化层106，同时，在平坦化层106与漏极202对应位置处，进行蚀刻并形成一过孔725。通过该过孔725使漏极202的表面暴露。同时，再在该平坦化层106上制备一第一电极层107。
详见图13，第一电极层107制备完成后，再在平坦化层106上制备一钝化层108，该钝化层108完全覆盖第一电极层107。
同时，在与过孔725对应的位置处，对该钝化层108蚀刻，并形成过孔726，该过孔726位于过孔725内，且其孔径小于过孔725的过孔孔径。
再在该钝化层108上制备第二电极层109，并使该第二电极层109填充过孔726，并与漏极202电性连接。
本申请实施例中，通过制备形成双层有源层并联的叠构。当阵列基板内的薄膜晶体管正常工作时，通过该并联的结构，可有效的提高器件内的开态电流，同时，可进一步提高器件的载流子迁移效率。
同时，本申请实施例中提供的阵列基板，该第一有源层与第二有源层为双层垂直结构设置，从而有效的减小了阵列基板内器件的布局占地面积。并且，在制备形成该阵列基板及对应的显示面板时，可在现有的制程工艺中进行制备，能与现有的制程工艺相兼容，同时，本申请中提供的制备方法及工艺更简单，能进一步提高器件的综合性能。
进一步的，本申请实施例还提供一种显示面板。该显示面板可包括阵列基板、以及设置在该阵列基板之上的像素表达层。本申请实施例中，该像素表达层可包括液晶层、有机发光功能、电泳层等功能膜层，通过该像素表达层以实现或者辅助实现显示面板的发光显示。本申请实施例中提供的显示面板的薄膜晶体管采用双层并联的结构，从而有效的提高了显示面板的发光效率及综合性能。
其中，该显示面板可为手机、电脑、电子纸、显示器、笔记本电脑、数码相框等任何具有显示功能以及触控功能的产品或部件，其具体类型不做具体限制。
综上所述，以上对本发明实施例所提供的一种阵列基板及显示面板进行了详细介绍，本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的技术方案及其核心思想；虽然本发明以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为基准。

Claims (20)

  1. 一种阵列基板，包括：
    衬底；
    第一有源层，设置于所述衬底之上，所述第一有源层包括第一沟道区以及设置在所述第一沟道区两侧的第一掺杂区；
    栅极，设置于所述第一有源层之上；
    栅极绝缘层，设置于所述第一有源层之上，并覆盖所述栅极；
    第二有源层，设置于所述栅极绝缘层之上，所述第二有源层包括第二沟道区以及设置在所述第二沟道区两侧的第二掺杂区；以及，
    源/漏金属层，设置于所述第二有源层之上；
    其中，所述第一掺杂区与所述第二掺杂区对应设置，所述源/漏金属层与所述第二掺杂区电性连接，且所述第一掺杂区内的所述第一有源层，对应的与所述第二掺杂区内的所述第二有源层电性连接；
    其中，所述第一有源层的长度大于等于所述第二有源层的长度。
  2. 根据权利要求1所述的阵列基板，其中所述第二掺杂区在所述衬底上的正投影的长度，大于所述第一掺杂区在所述衬底上的正投影的长度。
  3. 根据权利要求1所述的阵列基板，其中所述第一掺杂区以及所述第二掺杂区均包括重掺杂区与轻掺杂区，所述轻掺杂区与所述重掺杂区相邻，且所述重掺杂区远离沟道区设置；
    其中，所述第一有源层的所述重掺杂区与所述第二有源层的所述重掺杂区相对应，所述第一有源层的所述轻掺杂区与所述第二有源层的所述轻掺杂区相对应，且所述源/漏金属层与所述重掺杂区内对应的所述第二有源层电性连接。
  4. 一种阵列基板，包括：
    衬底；
    第一有源层，设置于所述衬底之上，所述第一有源层包括第一沟道区以及设置在所述第一沟道区两侧的第一掺杂区；
    栅极，设置于所述第一有源层之上；
    栅极绝缘层，设置于所述第一有源层之上，并覆盖所述栅极；
    第二有源层，设置于所述栅极绝缘层之上，所述第二有源层包括第二沟道区以及设置在所述第二沟道区两侧的第二掺杂区；以及，
    源/漏金属层，设置于所述第二有源层之上；
    其中，所述第一掺杂区与所述第二掺杂区对应设置，所述源/漏金属层与所述第二掺杂区电性连接，且所述第一掺杂区内的所述第一有源层，对应的与所述第二掺杂区内的所述第二有源层电性连接。
  5. 根据权利要求4所述的阵列基板，其中所述第二掺杂区在所述衬底上的正投影的长度，大于所述第一掺杂区在所述衬底上的正投影的长度。
  6. 根据权利要求4所述的阵列基板，其中所述第一掺杂区以及所述第二掺杂区均包括重掺杂区与轻掺杂区，所述轻掺杂区与所述重掺杂区相邻，且所述重掺杂区远离沟道区设置；
    其中，所述第一有源层的所述重掺杂区与所述第二有源层的所述重掺杂区相对应，所述第一有源层的所述轻掺杂区与所述第二有源层的所述轻掺杂区相对应，且所述源/漏金属层与所述重掺杂区内对应的所述第二有源层电性连接。
  7. 根据权利要求6所述的阵列基板，其中所述阵列基板还包括第一过孔与第二过孔，所述第一有源层的所述重掺杂区通过所述第一过孔以及所述第二过孔，与所述第二有源层的所述重掺杂区连接。
  8. 根据权利要求7所述的阵列基板，其中所述阵列基板还包括导体层，所述导体层设置在所述第一过孔与所述第二过孔内，且所述第一有源层通过所述导体层与所述第二有源层并联。
  9. 根据权利要求8所述的阵列基板，其中所述导体层的材料与所述重掺杂区内对应的所述第二有源层的材料相同。
  10. 根据权利要求6所述的阵列基板，其中所述阵列基板还包括第三过孔与第四过孔，所述源/漏金属层设置在所述第二有源层的所述重掺杂区的表面，且所述源/漏金属层通过所述第三过孔与所述第四过孔与所述第一有源层的重掺杂区电性连接。
  11. 根据权利要求10所述的阵列基板，其中所述第三过孔以及所述第四过孔贯穿所述第二有源层的所述重掺杂区。
  12. 根据权利要求6所述的阵列基板，其中所述源/漏金属层设置在所述第二有源层的重掺杂区域的上表面，所述源/漏金属层与所述第二有源层电性连接，并通过对应的过孔与所述第一有源层电性连接。
  13. 根据权利要求4所述的阵列基板，其中所述阵列基板还包括连接金属层，所述连接金属层设置在所述第一有源层与所述第二有源层之间对应的膜层内。
  14. 根据权利要求13所述的阵列基板，其中所述连接金属层与所述栅极同层设置，且所述连接金属层与所述源/漏金属层以及所述第一有源层的所述重掺杂区电性连接。
  15. 根据权利要求14所述的阵列基板，其中所述连接金属层与所述栅极的材料相同。
  16. 根据权利要求6所述的阵列基板，其中所述第一有源层的所述轻掺杂区的长度小于所述第二有源层的所述轻掺杂区的长度。
  17. 根据权利要求4所述的阵列基板，其中所述第一沟道区与所述第二沟道区与所述栅极对应设置。
  18. 根据权利要求17所述的阵列基板，其中所述第二沟道区在所述衬底上的正投影，位于所述第一沟道区在所述衬底上的正投影内。
  19. 根据权利要求4所述的阵列基板，其中所述阵列基板还包括遮光层，所述遮光层设置在所述衬底之上，且所述第一有源层设置在所述遮光层之上。
  20. 一种显示面板，包括：
    阵列基板；以及，
    像素表述层，设置于所述阵列基板之上；
    其中，所述阵列基板内至少设置两层有源层，所述有源层之间并联，且所述阵列基板包括：
    衬底；
    第一有源层，设置于所述衬底之上，所述第一有源层包括第一沟道区以及设置在所述第一沟道区两侧的第一掺杂区；
    栅极，设置于所述第一有源层之上；
    栅极绝缘层，设置于所述第一有源层之上，并覆盖所述栅极；
    第二有源层，设置于所述栅极绝缘层之上，所述第二有源层包括第二沟道区以及设置在所述第二沟道区两侧的第二掺杂区；以及，
    源/漏金属层，设置于所述第二有源层之上；
    其中，所述第一掺杂区与所述第二掺杂区对应设置，所述源/漏金属层与所述第二掺杂区电性连接，且所述第一掺杂区内的所述第一有源层，对应的与所述第二掺杂区内的所述第二有源层电性连接。
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