WO2022088365A1 - 显示面板及其制备方法 - Google Patents

显示面板及其制备方法 Download PDF

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Publication number
WO2022088365A1
WO2022088365A1 PCT/CN2020/132326 CN2020132326W WO2022088365A1 WO 2022088365 A1 WO2022088365 A1 WO 2022088365A1 CN 2020132326 W CN2020132326 W CN 2020132326W WO 2022088365 A1 WO2022088365 A1 WO 2022088365A1
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Prior art keywords
layer
interlayer dielectric
gate insulating
via hole
contact hole
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PCT/CN2020/132326
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English (en)
French (fr)
Inventor
赵慧慧
朴宇成
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武汉华星光电半导体显示技术有限公司
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Priority to US17/278,262 priority Critical patent/US20230387134A1/en
Publication of WO2022088365A1 publication Critical patent/WO2022088365A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning
    • H10K71/231—Changing the shape of the active layer in the devices, e.g. patterning by etching of existing layers

Definitions

  • the present invention relates to the field of display technology, and in particular, to a display panel and a manufacturing method thereof.
  • the preparation of LTPO display panels requires more layers. After the silicon transistors are prepared, metal oxide (IGZO) is deposited over the silicon transistors by sputtering to form oxide semiconductor transistors.
  • IGZO metal oxide
  • the fabrication process of the LTPO display panel requires at least 16 patterning processes. Due to the complex fabrication process, the yield is low and the manufacturing cost is high.
  • vias are used for connection between the source and drain of the silicon transistor and the active layer, and between the source and drain of the oxide semiconductor transistor and the active layer, and two patterning processes need to be used for digging separately. ;
  • the first via hole and the second via hole located in the non-display area also need to be dug separately by two patterning processes. Therefore, the current process only uses four patterning processes for hole excavation, and the process is complicated. The cost is high, and each process can lead to yield loss.
  • the display panel and the manufacturing method thereof provided by the present invention solve the technical problems of low yield and high manufacturing cost due to the complicated manufacturing process of the LTPO display panel in the prior art.
  • An embodiment of the present invention provides a method for manufacturing a display panel, the display panel includes a display area and a non-display area surrounding the display area, and the method for manufacturing the display panel includes the following steps:
  • S10 Provide a base substrate, the base substrate includes a first flexible layer, a second flexible layer, and an inorganic layer disposed between the first flexible layer and the second flexible layer;
  • S20 forming silicon transistors and oxide semiconductor transistors located in the display area, and a first via hole and a second via hole connected to each other located in the non-display area on the base substrate, wherein the silicon transistor The transistor is located in the first film layer group, and the oxide semiconductor transistor is located in the second film layer group;
  • step S20 includes the following steps:
  • S202 Form a first contact hole penetrating at least a part of the second film layer group and the first via hole penetrating the second film layer group through the same first patterning process.
  • the step S20 further includes the following steps:
  • S203 Form a second contact hole penetrating the first film layer group and at least a part of the second film layer group and the second via hole penetrating the second film layer group through the same second patterning process.
  • the step S201 includes the following steps:
  • a first active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer and a first interlayer dielectric of the silicon transistor are sequentially formed on the buffer layer layers, resulting in the first set of film layers;
  • a second active layer, a third gate insulating layer, a third gate layer and a second interlayer dielectric layer of the oxide semiconductor transistor are sequentially formed on the first interlayer dielectric layer to obtain the second interlayer dielectric layer.
  • the first contact hole and the first via hole formed by the same first patterning process penetrate through the second interlayer dielectric layer and the third gate insulating layer, and pass through the same second interlayer dielectric layer and the third gate insulating layer.
  • the second contact hole formed by the patterning process penetrates through the second interlayer dielectric layer, the third gate insulating layer, the first interlayer dielectric layer, the second gate insulating layer, and the third gate insulating layer.
  • a gate insulating layer and the buffer layer, the second via hole formed by the same second patterning process penetrates the first interlayer dielectric layer, the second gate insulating layer, the first a gate insulating layer, the buffer layer and the blocking layer.
  • forming the first contact hole and the first via hole through the same first patterning process includes the following steps:
  • the first photoresist layer is sequentially exposed, developed and etched to obtain the first contact hole and the first pass through the second interlayer dielectric layer and the third gate insulating layer. holes;
  • the remaining first photoresist layer is stripped.
  • forming the second contact hole and the second via hole through the same second patterning process includes the following steps:
  • the second photoresist layer is sequentially exposed, developed and etched, so as to obtain through the second interlayer dielectric layer, the third gate insulating layer, the first interlayer dielectric layer, and the first interlayer dielectric layer.
  • the remaining second photoresist layer is stripped.
  • the step S20 further includes:
  • a first source-drain metal layer is formed on the second interlayer dielectric layer, the first source-drain metal layer is connected to the second active layer through the first contact hole, and the first source The drain metal layer is connected to the first active layer through the second contact hole.
  • the preparation method of the display panel after the first source and drain metal layer is formed on the second interlayer dielectric layer, the preparation method further includes the following steps:
  • a passivation layer, a first flat layer and the second source and drain metal layer are sequentially formed on the first source and drain metal layer, and the first flat layer fills the first via hole and the second a via hole, a third contact hole is formed on the first flat layer, and the second source-drain metal layer is connected to the first source-drain metal layer through the third contact hole;
  • a second flat layer, an anode, a pixel defining layer, a light-emitting layer and a spacer are sequentially formed on the second source-drain metal layer, a fourth contact hole is formed on the second flat layer, and the anode passes through the The fourth contact hole is connected to the second source-drain metal layer.
  • An embodiment of the present invention provides a method for manufacturing a display panel, the display panel includes a display area and a non-display area surrounding the display area, and the method for manufacturing the display panel includes the following steps:
  • S20 forming silicon transistors and oxide semiconductor transistors located in the display area, and a first via hole and a second via hole connected to each other located in the non-display area on the base substrate, wherein the silicon transistor The transistor is located in the first film layer group, and the oxide semiconductor transistor is located in the second film layer group;
  • step S20 includes the following steps:
  • S202 Form a first contact hole penetrating at least a part of the second film layer group and the first via hole penetrating the second film layer group through the same first patterning process.
  • the step S20 further includes the following steps:
  • S203 Form a second contact hole penetrating the first film layer group and at least a part of the second film layer group and the second via hole penetrating the second film layer group through the same second patterning process.
  • the step S201 includes the following steps:
  • a first active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer and a first interlayer dielectric of the silicon transistor are sequentially formed on the buffer layer layers, resulting in the first set of film layers;
  • a second active layer, a third gate insulating layer, a third gate layer and a second interlayer dielectric layer of the oxide semiconductor transistor are sequentially formed on the first interlayer dielectric layer to obtain the second interlayer dielectric layer.
  • the first contact hole and the first via hole formed by the same first patterning process penetrate through the second interlayer dielectric layer and the third gate insulating layer, and pass through the same second interlayer dielectric layer and the third gate insulating layer.
  • the second contact hole formed by the patterning process penetrates through the second interlayer dielectric layer, the third gate insulating layer, the first interlayer dielectric layer, the second gate insulating layer, and the third gate insulating layer.
  • a gate insulating layer and the buffer layer, the second via hole formed by the same second patterning process penetrates the first interlayer dielectric layer, the second gate insulating layer, the first a gate insulating layer, the buffer layer and the blocking layer.
  • forming the first contact hole and the first via hole through the same first patterning process includes the following steps:
  • the first photoresist layer is sequentially exposed, developed and etched to obtain the first contact hole and the first pass through the second interlayer dielectric layer and the third gate insulating layer. holes;
  • the remaining first photoresist layer is stripped.
  • forming the second contact hole and the second via hole through the same second patterning process includes the following steps:
  • the second photoresist layer is sequentially exposed, developed and etched, so as to obtain through the second interlayer dielectric layer, the third gate insulating layer, the first interlayer dielectric layer, and the first interlayer dielectric layer.
  • the remaining second photoresist layer is stripped.
  • the step S20 further includes:
  • a first source-drain metal layer is formed on the second interlayer dielectric layer, the first source-drain metal layer is connected to the second active layer through the first contact hole, and the first source The drain metal layer is connected to the first active layer through the second contact hole.
  • the preparation method of the display panel after the first source and drain metal layer is formed on the second interlayer dielectric layer, the preparation method further includes the following steps:
  • a passivation layer, a first flat layer and the second source and drain metal layer are sequentially formed on the first source and drain metal layer, and the first flat layer fills the first via hole and the second a via hole, a third contact hole is formed on the first flat layer, and the second source-drain metal layer is connected to the first source-drain metal layer through the third contact hole;
  • a second flat layer, an anode, a pixel defining layer, a light-emitting layer and a spacer are sequentially formed on the second source-drain metal layer, a fourth contact hole is formed on the second flat layer, and the anode passes through the The fourth contact hole is connected to the second source-drain metal layer.
  • An embodiment of the present invention provides a display panel, including a display area and a non-display area surrounding the display area, the display panel includes:
  • the silicon transistor is located in the first film layer group
  • the oxide semiconductor transistor is located in the second film layer group
  • the first film layer group and the second film layer group are sequentially arranged on the base substrate
  • the oxide semiconductor transistor includes a first contact hole, the first contact hole penetrates at least the second film layer group, the first via hole penetrates the second film layer group, the first contact hole The depth is equal to the depth of the first via.
  • the silicon transistor and the oxide semiconductor transistor include a second contact hole, and the second contact hole penetrates the first film layer group and at least part of the second film layer group, the second via hole penetrates the second film layer group, and the depth of the second contact hole is equal to the depth of the second via hole.
  • the first film layer group includes a barrier layer, a buffer layer, a first active layer, a first gate insulating layer, and a first gate layer that are sequentially arranged on the base substrate a pole layer, a second gate insulating layer, a second gate layer and a first interlayer dielectric layer;
  • the second film layer group includes a second active layer, a third gate insulating layer, a third gate layer and a second interlayer dielectric layer that are sequentially arranged on the first interlayer dielectric layer;
  • the first contact hole and the first via hole penetrate through the second interlayer dielectric layer and the third gate insulating layer, and the second contact hole penetrates through the second interlayer dielectric layer, The third gate insulating layer, the first interlayer dielectric layer, the second gate insulating layer, the first gate insulating layer, the first active layer and the buffer layer, all The second via hole penetrates through the first interlayer dielectric layer, the second gate insulating layer, the first gate insulating layer, the buffer layer and the blocking layer.
  • a first source-drain metal layer is disposed on the second interlayer dielectric layer, and the display panel further includes a passivation disposed on the first source-drain metal layer layer, a first flat layer and a second source and drain metal layer.
  • the diameter of the first via hole is larger than that of the second via hole, and the diameter of the first via hole and the diameter of the second via hole are along the second The direction from the interlayer dielectric layer to the base substrate gradually decreases.
  • the base substrate includes a first flexible layer, a second flexible layer, and an inorganic layer disposed between the first flexible layer and the second flexible layer.
  • the display panel and the manufacturing method thereof provided by the present invention are used for connecting the source-drain metal layer of the oxide semiconductor transistor and the first contact hole of the second active layer, and the first contact hole is the same as that of the first via hole.
  • the sub-patterning process and the same mask are formed, and the second contact hole for connecting the source and drain metal layers of the silicon transistor and the first active layer is formed by the same patterning process and the same mask as the second via hole. Therefore, compared with the prior art, the manufacturing process of the display panel can save at least two patterning processes, thereby simplifying the manufacturing process of the display panel, reducing the production cost and improving the product yield.
  • FIG. 1 is a flowchart of a method for manufacturing a display panel according to an embodiment of the present invention
  • FIG. 2 is a flowchart of step S20 in a method for manufacturing a display panel provided by an embodiment of the present invention
  • 3A to 3G are schematic flow diagrams of a method for manufacturing a display panel according to an embodiment of the present invention.
  • FIG. 4 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional structure diagram of a display panel according to an embodiment of the present invention.
  • the present invention is directed to the prior art display panel and its manufacturing method. Due to the complicated manufacturing process of the LTPO display panel, the yield rate is low and the manufacturing cost is high. This embodiment can solve the defect.
  • a method for fabricating a display panel includes the following steps:
  • the base substrate 100 includes a display area A and a non-display area B surrounding the display area A. as well as
  • S20 forming a silicon transistor 200 and an oxide semiconductor transistor 300 in the display area A of the base substrate 100, and forming a first via hole 201 and a second via hole 202 in the non-display area B that are connected to each other,
  • the silicon transistor 200 is located in the first film layer group 1
  • the oxide semiconductor transistor 300 is located in the second film layer group 2 .
  • step S20 includes the following steps:
  • S202 Form a first contact hole 101 penetrating at least part of the second film layer group 2 and the first via hole 201 penetrating the second film layer group 2 through the same first patterning process.
  • the manufacturing process of the display panel can save one patterning process.
  • step S20 also includes the following steps:
  • the manufacturing process of the display panel can further save a patterning process.
  • step S201 includes the following steps:
  • a barrier layer 14 and a buffer layer 15 are sequentially formed on the base substrate 100 .
  • the blocking layer 14 is located on the base substrate 100
  • the buffer layer 15 is located on the blocking layer 14
  • the materials used for the blocking layer 14 include silicon oxide, nitride
  • silicon oxide, nitride One or more of silicon, silicon oxynitride and amorphous silicon are mainly used to block water and oxygen to prevent external water vapor or oxygen from eroding the display panel.
  • the material used for the buffer layer 15 includes one or both of silicon nitride and silicon oxide, which mainly play the role of buffering and protection.
  • the base substrate 100 includes a first flexible layer 11 , a second flexible layer 13 and an inorganic layer 12 disposed between the first flexible layer 11 and the second flexible layer 13 .
  • the layer 12 is used to block water and oxygen, and on the other hand, it is used to prevent damage to the first flexible layer 11 and the second flexible layer 13 caused by laser lift-off.
  • a first active layer 16 , a first gate insulating layer 17 , a first gate layer 18 , a second gate insulating layer 19 , and a second gate layer of the silicon transistor 200 are sequentially formed on the buffer layer 15 20 and the first interlayer dielectric layer 21 to obtain the first film layer group.
  • the first active layer 16 is patterned and formed on the side of the buffer layer 15 away from the base substrate 100 , and the material of the first active layer 16 is low temperature polysilicon .
  • the first gate insulating layer 17 covers the first active layer 16
  • the first gate layer 18 is patterned and formed on the side of the first gate insulating layer 17 away from the base substrate 100
  • the second gate insulating layer 19 covers the first gate layer 18
  • the second gate layer 20 is patterned on the second gate insulating layer 19
  • the first interlayer dielectric Layer 21 covers the second gate layer 20 .
  • the second active layer 22 , the third gate insulating layer 23 , the third gate layer 24 and the second interlayer dielectric layer 25 of the oxide semiconductor transistor 300 are sequentially formed on the first interlayer dielectric layer 21 , to obtain the second film layer group.
  • the second active layer 22 is patterned and formed on the side of the first interlayer dielectric layer 21 away from the base substrate 100 .
  • the material is a metal oxide.
  • the third gate insulating layer 23 covers the second active layer 22
  • the third gate insulating layer 24 is patterned and formed on the side of the third gate insulating layer 23 away from the base substrate 100
  • the second interlayer dielectric layer 25 covers the third gate layer 24 .
  • the first contact hole 101 and the first via hole 201 formed by the same first patterning process penetrate through the second interlayer dielectric layer 25 and the third gate insulating layer 23, and pass through the same first patterning process.
  • the second contact hole 102 formed by the second patterning process penetrates through the second interlayer dielectric layer 25 , the third gate insulating layer 23 , the first interlayer dielectric layer 21 , and the second interlayer dielectric layer 25 .
  • the gate insulating layer 19 and the first gate insulating layer 17, the second via hole 202 formed by the same second patterning process penetrates through the first interlayer dielectric layer 21 and the second gate The insulating layer 19 , the first gate insulating layer 17 , the buffer layer 15 and the blocking layer 14 .
  • Forming the first contact hole 101 and the first via hole 201 through the same first patterning process includes the following steps:
  • a first photoresist layer is formed on the second interlayer dielectric layer 25 .
  • the first photoresist layer is sequentially exposed, developed and etched to obtain the first contact hole 101 and the first contact hole 101 penetrating the second interlayer dielectric layer 25 and the third gate insulating layer 23 The first via hole 201 . as well as
  • the remaining first photoresist layer is stripped.
  • forming the first contact hole 101 and the first via hole 201 needs to etch the second interlayer dielectric layer 25 and the third gate insulating layer 23 successively.
  • the thickness of the second active layer 22 is very thin. Therefore, the thicknesses of the layers required to be etched to form the first contact hole 101 and the first via hole 201 are almost the same, which are equivalent to the second interlayer.
  • the first contact hole 101 and the first via hole 201 are prepared by different masks, which can reduce one patterning process, reduce production cost, and improve product yield.
  • the bottom of the first contact hole 101 is in contact with the side of the second active layer 22 that is far away from the base substrate 100 , and the bottom of the first via hole 201 is far away from the first interlayer dielectric layer 21
  • One side of the base substrate 100 is in contact, the angle formed by the side wall of the first contact hole 101 and the first direction is between 50° and 80°, and the first via hole 201 has an angle between 50° and 80°.
  • the angle formed by the side wall and the first direction ranges from 30° to 60°, wherein the first direction is a horizontal direction perpendicular to the thickness direction of the display panel.
  • forming the second contact hole 102 and the second via hole 202 through the same second patterning process includes the following steps:
  • a second photoresist layer is formed on the second interlayer dielectric layer 25 and the inner sidewall of the first via hole 201 .
  • the second photoresist layer is sequentially exposed, developed and etched to obtain the second interlayer dielectric layer 25, the third gate insulating layer 23, the first interlayer dielectric layer 21,
  • the remaining second photoresist layer is stripped.
  • forming the second via hole 202 requires successively etching the second interlayer dielectric layer 25 , the third gate insulating layer 23 , and the third gate insulating layer 23 .
  • the thickness of the film to be etched to form the second contact hole 102 is 1100 nm to 1350 nm, and the thickness of the film to be etched to form the second via hole 202 is also 1100nm-1350nm. Therefore, the second contact hole 102 can be formed by successively etching the second interlayer dielectric layer 25 , the third gate insulating layer 23 , the first interlayer dielectric layer 21 , and the second gate electrode The insulating layer 19 , the first gate insulating layer 17 , the first active layer 16 and the buffer layer 15 . Therefore, in the embodiment of the present invention, the second contact hole 102 and the second via hole 202 can be formed by the same patterning process.
  • the etching process in the patterning process is etched.
  • the blocking layer 14 is stopped, and the second via hole 202 is formed, the etching process in the patterning process is stopped when the second flexible layer 13 of the base substrate 100 is etched.
  • the second contact hole 102 and the second via hole 202 are prepared by different masks, which can reduce one patterning process, reduce production cost, and improve product yield.
  • the bottom of the second contact hole 102 is in contact with the side of the barrier layer 14 away from the base substrate 100 , and the bottom of the second via hole 202 and the barrier layer 14 are close to the substrate
  • the angle formed between the side wall of the second contact hole 102 and the first direction is between 50° and 80°
  • the side wall of the second via hole 202 is between 50° and 80°.
  • the value of the included angle formed with the first direction ranges from 25° to 55°.
  • the first via hole 201 and the second via hole 202 communicate with each other, which can be used to remove part of the inorganic insulating material of the display panel and improve the bending resistance of the display panel.
  • the diameter of the first via hole 201 is larger than that of the second via hole 202 , and the diameter of the first via hole 201 and the diameter of the second via hole 202 are along the second interlayer dielectric layer.
  • the direction from 25 to the base substrate 100 gradually decreases.
  • a stepped surface is formed between the first via hole 201 and the second via hole 202 , and the stepped surface is located on the side of the first interlayer dielectric layer 21 away from the base substrate 100 .
  • the edge of the step surface is relatively smooth, which not only facilitates the wiring of the first source-drain metal layer 26 prepared subsequently, but also the step surface can clearly distinguish the two etching processes in step S20 .
  • step S20 further includes:
  • a first source-drain metal layer 26 is formed on the second interlayer dielectric layer 25 , and the first source-drain metal layer 26 is connected to the second active layer 22 through the first contact hole 101 , the first source-drain metal layer 26 is connected to the first active layer 16 through the second contact hole 102 .
  • the first source-drain metal layer 26 is formed by patterning on the side of the second interlayer dielectric layer 25 away from the base substrate 100 , and the first source-drain metal layer 26 is formed.
  • the metal layer 26 includes a first source electrode and a first drain electrode of the silicon transistor 200, the number of the second contact holes 102 in each group is three, and the first source electrode passes through one of the second contact holes 102 is connected to the first active layer 16 , and the first drain is connected to the first active layer 16 through one of the second contact holes 102 .
  • the first source-drain metal layer 26 further includes a second source electrode and a second drain electrode of the oxide semiconductor transistor 300 , and the second source electrode is connected to the second source electrode through another second contact hole 102 .
  • the first active layer 16 is connected.
  • the number of the first contact holes 101 in each group is two, the second source electrode is connected to the second active layer 22 through one of the first contact holes 101 , and the second drain electrode is connected to the second active layer 22 through another One of the first contact holes 101 is connected to the second active layer 22 .
  • the first source electrode and the first drain electrode, and the second source electrode and the second drain electrode are located in the same metal layer and can be fabricated by the same process, which can simplify the Process.
  • the preparation method further includes the following steps:
  • the first passivation layer 27 , the first planarization layer 28 and the second source/drain metal layer 29 are sequentially formed on the first source/drain metal layer 26 , and the first planarization layer 28 fills the The first via hole 201 and the second via hole 202, a third contact hole 103 is formed on the first flat layer 28, and the second source-drain metal layer 29 is connected to the third contact hole 103 through the third contact hole 103.
  • the first source-drain metal layer 26 is connected.
  • a second flat layer 30 , an anode 31 , a pixel definition layer 32 , a light-emitting layer 33 and a spacer 34 are sequentially formed on the second source-drain metal layer 29 , and a fourth contact is formed on the second flat layer 30 hole 104 , the anode 31 is connected to the second source-drain metal layer 29 through the fourth contact hole 104 .
  • the second source-drain metal layer 29 is connected to the first drain through the third contact hole 103 .
  • the first flat layer 28 and the second flat layer 30 are made of flexible materials, and the first flat layer 28 is filled in the first via hole 201 and the second via hole 202 to prevent the The metal trace in the fold area is broken.
  • the orthographic projection of the second source-drain metal layer 29 on the base substrate 100 covers the orthographic projection of the second active layer 22 on the base substrate 100 , so that the second source-drain metal layer
  • the layer 29 plays the role of shielding light and shielding ions for the second active layer 22, so as to avoid the occurrence of bad situations.
  • the device characteristics of the second active layer 22 can also be ensured by improving the film forming process and annealing process of the second interlayer dielectric layer 25 .
  • the step of forming a passivation layer thereon can be removed, which can further reduce one patterning process.
  • the display panel provided by the embodiment of the present invention is prepared by the preparation method of the display panel provided by the above-mentioned embodiment.
  • the display panel includes a display area A and a non-display area B surrounding the display area A.
  • the non-display area B can be bent to the back of the display panel to reduce the lower frame of the display panel, which is beneficial to increase the screen ratio and facilitate the realization of full-screen display.
  • the display panel includes a base substrate 100 , a silicon transistor 200 , an oxide semiconductor transistor 300 , a first via hole 201 and a second via hole 202 .
  • the silicon transistor 200 and the oxide semiconductor transistor 300 are disposed on the base substrate 100, wherein the silicon transistor 200 and the oxide semiconductor transistor 300 are located in the display area A, and the first pass The hole 201 and the second via hole 202 are both located in the bending region B. Since the threshold voltage of the silicon transistor 200 does not drift, it can be used as a driving transistor; because the oxide semiconductor transistor 300 has good switching performance, it can be used as a driving transistor as a switching transistor.
  • the silicon transistor 200 is located in the first film layer group 1, the oxide semiconductor transistor 300 is located in the second film layer group 2, and the first film layer group 1 and the second film layer group 2 are sequentially arranged in On the base substrate 100, the oxide semiconductor transistor 300 includes a first contact hole 101, the first contact hole 101 penetrates at least the second film layer group 2, and the first via hole 201 penetrates the In the second film layer group 2 , the depth of the first contact hole 101 is equal to the depth of the first via hole 201 .
  • the silicon transistor 200 and the oxide semiconductor transistor 300 include a second contact hole 102 , and the second contact hole 102 penetrates through the first film layer group 1 and at least part of the second film layer group 2 , the second via hole 202 penetrates the second film layer group 2 , and the depth of the second contact hole 102 is equal to the depth of the second via hole 202 .
  • the first film layer group 1 includes a barrier layer 14, a buffer layer 15, a first active layer 16, a first gate insulating layer 17, a first gate layer 18, a Two gate insulating layers 19 , a second gate layer 20 and a first interlayer dielectric layer 21 ;
  • the second film layer group 2 includes a second active layer sequentially disposed on the first interlayer dielectric layer 21 22 , the third gate insulating layer 23 , the third gate layer 24 and the second interlayer dielectric layer 25 .
  • the first contact hole 101 and the first via hole 201 penetrate through the second interlayer dielectric layer 25 and the third gate insulating layer 23
  • the second contact hole 102 penetrates through the second interlayer dielectric layer 25 and the third gate insulating layer 23 .
  • the interlayer dielectric layer 25, the third gate insulating layer 23, the first interlayer dielectric layer 21, the second gate insulating layer 19, the first gate insulating layer 17, the first The active layer 16 and the buffer layer 15, the second via hole 202 penetrates through the first interlayer dielectric layer 21, the second gate insulating layer 19, the first gate insulating layer 17, the The buffer layer 15 and the barrier layer 14 are formed.
  • the silicon transistor 200 in the embodiment of the present invention adopts a double gate structure, including a first active layer 16 , a first gate insulating layer 17 , and a first gate layer sequentially disposed on the buffer layer 15 18 .
  • the oxide semiconductor transistor 300 includes a second active layer 22 , a third gate insulating layer 23 , a third gate layer 24 and a second interlayer dielectric layer that are sequentially disposed on the first interlayer dielectric layer 21 25.
  • a first source-drain metal layer 26 is disposed on the second interlayer dielectric layer 25, and the first source-drain metal layer 26 is connected to the second active layer 22 through the first contact hole 101 , the first source-drain metal layer 26 is connected to the first active layer 16 through the second contact hole 102 .
  • the first source-drain metal layer 26 includes a first source and a first drain of the silicon transistor 200 , the number of the second contact holes 102 in each group is three, and the first source The electrode is connected to the first active layer 16 through one of the second contact holes 102 , and the first drain is connected to the first active layer 16 through one of the second contact holes 102 .
  • the first source-drain metal layer 26 further includes a second source electrode and a second drain electrode of the oxide semiconductor transistor 300 , and the second source electrode is connected to the second source electrode through another second contact hole 102 . The first active layer 16 is connected.
  • the number of the first contact holes 101 in each group is two, the second source electrode is connected to the second active layer 22 through one of the first contact holes 101 , and the second drain electrode is connected to the second active layer 22 through another One of the first contact holes 101 is connected to the second active layer 22 .
  • the first via hole 201 and the second via hole 202 communicate with each other.
  • the first contact hole 101 and the first via hole 201 penetrate through the second interlayer dielectric layer 25 and the third gate insulating layer 23
  • the second contact hole 102 penetrates through the second interlayer
  • the dielectric layer 25, the third gate insulating layer 23, the first interlayer dielectric layer 21, the second gate insulating layer 19, the first gate insulating layer 17, the first active layer 16 and the buffer layer 15, the second via hole 202 penetrates through the first interlayer dielectric layer 21, the second gate insulating layer 19, the first gate insulating layer 17, and the buffer layer 15 and the barrier layer 14 .
  • the first contact hole 101 and the first via hole 201 can be formed by the same patterning process, and the second contact hole 102 and the second via hole 202 can be formed by the same patterning process, which is similar to the prior art. In comparison, two patterning processes can be reduced, production costs can be reduced, and product yields can be improved.
  • the bottom of the first contact hole 101 is in contact with the side of the second active layer 22 that is far away from the base substrate 100 , and the bottom of the second contact hole 102 is far away from the buffer layer 15 .
  • One side of the base substrate 100 is in contact.
  • the bottom of the first via hole 201 is in contact with the side of the first interlayer dielectric layer 21 away from the base substrate 100 , and the bottom of the second via hole 202 and the barrier layer 14 are close to the substrate One side of the base substrate 100 is in contact.
  • the diameter of the first via hole 201 is larger than that of the second via hole 202 .
  • the directions of the base substrate 100 are gradually reduced.
  • a stepped surface is formed between the first via hole 201 and the second via hole 202 , and the stepped surface is located on the side of the first interlayer dielectric layer 21 away from the base substrate 100 .
  • the display panel further includes a passivation layer 27 , a first flat layer 28 and a second source and drain metal layer 29 which are sequentially arranged on the first source and drain metal layer 26 , and the passivation layer 27 covers the The second interlayer dielectric layer 25 , the first source-drain metal layer 26 , and the first flat layer 28 are filled in the first via hole 201 and the second via hole 202 .
  • a second flat layer 30 , an anode 31 , a pixel definition layer 32 , a light-emitting layer 33 and a plurality of spacers 34 are sequentially disposed on the second source-drain metal layer 29 , and the pixel definition layer 32 covers the anode 31 , the pixel definition layer 32 is provided with a groove exposing the anode 31 , the light emitting layer 33 is arranged in the groove, and a plurality of the spacers 34 are arranged on the pixel definition layer 32 at intervals A side away from the base substrate 100 .
  • the second source-drain metal layer 29 is connected to the first source-drain metal layer 26 through the third contact hole 103 penetrating the first planar layer 28 , and the anode 31 penetrates the second planar layer
  • the fourth contact hole 104 of 30 is connected to the second source-drain metal layer 29 .
  • the difference between the display panel provided in FIG. 5 and the display panel provided in FIG. 4 is that the passivation layer 27 is omitted, thereby reducing the overall thickness of the display panel.
  • the device characteristics of the second active layer 22 can be ensured by improving the film forming process and the annealing process of the second interlayer dielectric layer 25 .
  • the beneficial effects are: the display panel and the preparation method thereof provided by the present invention are used for connecting the source-drain metal layer of the oxide semiconductor transistor and the first contact hole of the second active layer, and the same patterning process is adopted as the first via hole. Formed with the same mask, the second contact hole used to connect the source-drain metal layer of the silicon transistor and the first active layer is formed by the same patterning process and the same mask as the second via, so the phase Compared with the prior art, the manufacturing process of the display panel can save at least two patterning processes, thereby simplifying the manufacturing process of the display panel, reducing the production cost and improving the product yield.

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Abstract

一种显示面板及其制备方法，显示面板的制备方法包括：通过同一第一构图工艺形成贯穿至少部分第二膜层组（2）的第一接触孔（101）和贯穿第二膜层组（2）的第一过孔（201），通过同一第二构图工艺形成贯穿第一膜层组（1）和至少部分第二膜层组（2）的第二接触孔（102）以及贯穿第二膜层组（2）的第二过孔（202），至少可以节约两次构图工艺。

Description

显示面板及其制备方法 技术领域
本发明涉及显示技术领域，尤其涉及一种显示面板及其制备方法。
 背景技术
随着显示技术的不断发展，人们对显示产品的分辨率、功耗和画质的要求越来越高，低温多晶氧化物(Low Temperature Polycrystalline Oxide，LTPO)技术逐渐成为未来显示基板的主要发展方向。由于硅晶体管迁移率高，可以加快对像素电容的充电速度，金属氧化物半导体晶体管具有更低的泄漏电流，该技术将硅晶体管和金属氧化物半导体晶体管这两种晶体管的优势相结合，有助于高分辨率、低功耗、高画质的显示产品的开发。
与制备低温多晶硅显示面板相比，制备LTPO显示面板需要更多的膜层，制备完成硅晶体管之后，通过溅射将金属氧化物（IGZO）沉积在硅晶体管上方以形成氧化物半导体晶体管。LTPO显示面板的制备过程至少需要16次构图工艺，由于其制程复杂，导致良率偏低、制造成本较高。在该制备过程中，硅晶体管的源漏极与有源层之间、氧化物半导体晶体管的源漏极与有源层之间采用过孔连接，需要分别采用2次构图工艺单独进行挖孔处理；此外，位于非显示区的第一过孔和第二过孔也需要分别采用2次构图工艺单独进行挖孔处理，因此，当前工艺仅进行挖孔就采用了4次构图工艺，工艺复杂，成本高，且每一道制程都可能导致良率受损。
综上所述，需要提供一种新的显示面板及其制备方法，来解决上述技术问题。
 技术问题
本发明提供的显示面板及其制备方法，解决了现有技术中由于LTPO显示面板的制备过程复杂，导致良率偏低、制造成本较高的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种显示面板的制备方法，所述显示面板包括显示区和围绕所述显示区的非显示区，所述显示面板的制备方法包括以下步骤：
S10：提供衬底基板，所述衬底基板包括第一柔性层、第二柔性层以及设置于所述第一柔性层和所述第二柔性层之间的无机层；以及
S20：在所述衬底基板上形成位于所述显示区的硅晶体管和氧化物半导体晶体管，以及位于所述非显示区的相互连通的第一过孔和第二过孔，其中，所述硅晶体管位于第一膜层组，所述氧化物半导体晶体管位于第二膜层组；
其中，所述步骤S20包括以下步骤：
S201：在所述衬底基板依次形成所述第一膜层组和所述第二膜层组；以及
S202：通过同一第一构图工艺形成贯穿至少部分所述第二膜层组的第一接触孔和贯穿所述第二膜层组的所述第一过孔。
根据本发明实施例提供的显示面板的制备方法，所述步骤S20还包括以下步骤：
S203：通过同一第二构图工艺形成贯穿所述第一膜层组和至少部分所述第二膜层组的第二接触孔和贯穿所述第二膜层组的所述第二过孔。
根据本发明实施例提供的显示面板的制备方法，所述步骤S201包括以下步骤：
在所述衬底基板上依次形成阻隔层和缓冲层；
在所述缓冲层上依次形成所述硅晶体管的第一有源层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层以及第一层间介质层，得到所述第一膜层组；以及
在所述第一层间介质层上依次形成所述氧化物半导体晶体管的第二有源层、第三栅极绝缘层、第三栅极层以及第二层间介质层，得到所述第二膜层组；
其中，通过同一所述第一构图工艺形成的所述第一接触孔和所述第一过孔贯穿所述第二层间介质层和所述第三栅极绝缘层，通过同一所述第二构图工艺形成的所述第二接触孔贯穿所述第二层间介质层、所述第三栅极绝缘层、所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层以及所述缓冲层，通过同一所述第二构图工艺形成的所述第二过孔贯穿所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻隔层。
根据本发明实施例提供的显示面板的制备方法，通过同一所述第一构图工艺形成所述第一接触孔和所述第一过孔，包括以下步骤：
在所述第二层间介质层上形成第一光刻胶层；
对所述第一光刻胶层依次进行曝光、显影和刻蚀，得到贯穿所述第二层间介质层和所述第三栅极绝缘层的所述第一接触孔和所述第一过孔；以及
剥离剩余的所述第一光刻胶层。
根据本发明实施例提供的显示面板的制备方法，通过同一所述第二构图工艺形成所述第二接触孔和所述第二过孔，包括以下步骤：
在所述第二层间介质层和所述第一过孔的内侧壁上形成第二光刻胶层；
对所述第二光刻胶层依次进行曝光、显影和刻蚀，得到贯穿所述第二层间介质层、所述第三栅极绝缘层、所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层以及所述缓冲层的所述第二接触孔，以及贯穿所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻隔层的所述第二过孔；以及
剥离剩余的所述第二光刻胶层。
根据本发明实施例提供的显示面板的制备方法，在所述通过同一所述第二构图工艺形成所述第二接触孔和所述第二过孔之后，所述步骤S20还包括：
在所述第二层间介质层上形成第一源漏极金属层，所述第一源漏极金属层通过所述第一接触孔与所述第二有源层连接，所述第一源漏极金属层通过所述第二接触孔和与所述第一有源层连接。
根据本发明实施例提供的显示面板的制备方法，在所述第二层间介质层上形成第一源漏极金属层之后，所述制备方法还包括以下步骤：
在所述第一源漏极金属层上依次形成钝化层、第一平坦层以及所述第二源漏极金属层，所述第一平坦层填充所述第一过孔和所述第二过孔，所述第一平坦层上形成有第三接触孔，所述第二源漏极金属层通过所述第三接触孔与所述第一源漏极金属层连接；以及
在所述第二源漏极金属层上依次形成第二平坦层、阳极、像素界定层、发光层以及隔垫物，所述第二平坦层上形成有第四接触孔，所述阳极通过所述第四接触孔与所述第二源漏极金属层连接。
本发明实施例提供一种显示面板的制备方法，所述显示面板包括显示区和围绕所述显示区的非显示区，所述显示面板的制备方法包括以下步骤：
S10：提供衬底基板；以及
S20：在所述衬底基板上形成位于所述显示区的硅晶体管和氧化物半导体晶体管，以及位于所述非显示区的相互连通的第一过孔和第二过孔，其中，所述硅晶体管位于第一膜层组，所述氧化物半导体晶体管位于第二膜层组；
其中，所述步骤S20包括以下步骤：
S201：在所述衬底基板依次形成所述第一膜层组和所述第二膜层组；以及
S202：通过同一第一构图工艺形成贯穿至少部分所述第二膜层组的第一接触孔和贯穿所述第二膜层组的所述第一过孔。
根据本发明实施例提供的显示面板的制备方法，所述步骤S20还包括以下步骤：
S203：通过同一第二构图工艺形成贯穿所述第一膜层组和至少部分所述第二膜层组的第二接触孔和贯穿所述第二膜层组的所述第二过孔。
根据本发明实施例提供的显示面板的制备方法，所述步骤S201包括以下步骤：
在所述衬底基板上依次形成阻隔层和缓冲层；
在所述缓冲层上依次形成所述硅晶体管的第一有源层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层以及第一层间介质层，得到所述第一膜层组；以及
在所述第一层间介质层上依次形成所述氧化物半导体晶体管的第二有源层、第三栅极绝缘层、第三栅极层以及第二层间介质层，得到所述第二膜层组；
其中，通过同一所述第一构图工艺形成的所述第一接触孔和所述第一过孔贯穿所述第二层间介质层和所述第三栅极绝缘层，通过同一所述第二构图工艺形成的所述第二接触孔贯穿所述第二层间介质层、所述第三栅极绝缘层、所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层以及所述缓冲层，通过同一所述第二构图工艺形成的所述第二过孔贯穿所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻隔层。
根据本发明实施例提供的显示面板的制备方法，通过同一所述第一构图工艺形成所述第一接触孔和所述第一过孔，包括以下步骤：
在所述第二层间介质层上形成第一光刻胶层；
对所述第一光刻胶层依次进行曝光、显影和刻蚀，得到贯穿所述第二层间介质层和所述第三栅极绝缘层的所述第一接触孔和所述第一过孔；以及
剥离剩余的所述第一光刻胶层。
根据本发明实施例提供的显示面板的制备方法，通过同一所述第二构图工艺形成所述第二接触孔和所述第二过孔，包括以下步骤：
在所述第二层间介质层和所述第一过孔的内侧壁上形成第二光刻胶层；
对所述第二光刻胶层依次进行曝光、显影和刻蚀，得到贯穿所述第二层间介质层、所述第三栅极绝缘层、所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层以及所述缓冲层的所述第二接触孔，以及贯穿所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻隔层的所述第二过孔；以及
剥离剩余的所述第二光刻胶层。
根据本发明实施例提供的显示面板的制备方法，在所述通过同一所述第二构图工艺形成所述第二接触孔和所述第二过孔之后，所述步骤S20还包括：
在所述第二层间介质层上形成第一源漏极金属层，所述第一源漏极金属层通过所述第一接触孔与所述第二有源层连接，所述第一源漏极金属层通过所述第二接触孔和与所述第一有源层连接。
根据本发明实施例提供的显示面板的制备方法，在所述第二层间介质层上形成第一源漏极金属层之后，所述制备方法还包括以下步骤：
在所述第一源漏极金属层上依次形成钝化层、第一平坦层以及所述第二源漏极金属层，所述第一平坦层填充所述第一过孔和所述第二过孔，所述第一平坦层上形成有第三接触孔，所述第二源漏极金属层通过所述第三接触孔与所述第一源漏极金属层连接；以及
在所述第二源漏极金属层上依次形成第二平坦层、阳极、像素界定层、发光层以及隔垫物，所述第二平坦层上形成有第四接触孔，所述阳极通过所述第四接触孔与所述第二源漏极金属层连接。
本发明实施例提供一种显示面板，包括显示区和围绕所述显示区的非显示区，所述显示面板包括：
衬底基板；以及
位于所述衬底基板上的硅晶体管和氧化物半导体晶体管，以及相互连通的第一过孔和第二过孔，所述硅晶体管和所述氧化物半导体晶体管位于所述显示区，所述第一过孔和所述第二过孔位于所述非显示区；
其中，所述硅晶体管位于第一膜层组，所述氧化物半导体晶体管位于第二膜层组，所述第一膜层组和所述第二膜层组依次设置于所述衬底基板上，所述氧化物半导体晶体管包括第一接触孔，所述第一接触孔贯穿至少所述第二膜层组，所述第一过孔贯穿所述第二膜层组，所述第一接触孔的深度和所述第一过孔的深度相等。
根据本发明实施例提供的显示面板，所述硅晶体管和所述氧化物半导体晶体管包括第二接触孔，所述第二接触孔贯穿所述第一膜层组和至少部分所述第二膜层组，所述第二过孔贯穿所述第二膜层组，所述第二接触孔的深度和所述第二过孔的深度相等。
根据本发明实施例提供的显示面板，所述第一膜层组包括依次设置于所述衬底基板上的阻隔层、缓冲层、第一有源层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层以及第一层间介质层；
所述第二膜层组包括依次设置于所述第一层间介质层上的第二有源层、第三栅极绝缘层、第三栅极层以及第二层间介质层；
其中，所述第一接触孔和所述第一过孔贯穿所述第二层间介质层和所述第三栅极绝缘层，所述第二接触孔贯穿所述第二层间介质层、所述第三栅极绝缘层、所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述第一有源层以及所述缓冲层，所述第二过孔贯穿所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻隔层。
根据本发明实施例提供的显示面板，所述第二层间介质层上设置有第一源漏极金属层，所述显示面板还包括设置于所述第一源漏极金属层上的钝化层、第一平坦层以及第二源漏极金属层。
根据本发明实施例提供的显示面板，所述第一过孔的孔径大于所述第二过孔的孔径，所述第一过孔的孔径和所述第二过孔的孔径沿所述第二层间介质层至所述衬底基板的方向均逐渐减小。
根据本发明实施例提供的显示面板，所述衬底基板包括第一柔性层、第二柔性层以及设置于所述第一柔性层和所述第二柔性层之间的无机层。
 有益效果
本发明的有益效果为：本发明提供的显示面板及其制备方法，用于连接氧化物半导体晶体管的源漏极金属层和第二有源层的第一接触孔，与第一过孔采用同一次构图工艺和同一掩膜板形成，用于连接硅晶体管的源漏极金属层和第一有源层的第二接触孔，与第二过孔通过同一次构图工艺和同一掩膜板形成，因此，相比于现有技术，该显示面板的制造过程至少可以节约两次构图工艺，从而简化了显示面板的制程，降低了生产成本，提升了产品良率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的一种显示面板的制备方法的流程图；
图2为本发明实施例提供的一种显示面板的制备方法中的步骤S20的流程图；
图3A~图3G为本发明实施例提供的一种显示面板的制备方法的流程结构示意图；
图4为本发明实施例提供的一种显示面板的截面结构示意图；
图5为本发明实施例提供的一种显示面板的截面结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
本发明针对现有技术的显示面板及其制备方法，由于LTPO显示面板的制备过程复杂，导致良率偏低、制造成本较高，本实施例能够解决该缺陷。
请参阅图1，本发明实施例提供的显示面板的制备方法，包括以下步骤：
S10：提供衬底基板100，所述衬底基板100包括显示区A和围绕所述显示区A的非显示区B。以及
S20：在所述衬底基板100的所述显示区A形成硅晶体管200和氧化物半导体晶体管300，以及在所述非显示区B形成相互连通的第一过孔201和第二过孔202，其中，所述硅晶体管200位于第一膜层组1，所述氧化物半导体晶体管300位于第二膜层组2。
其中，如图2所示，所述步骤S20包括以下步骤：
S201：在所述衬底基板100依次形成所述第一膜层组1和所述第二膜层组2；以及
S202：通过同一第一构图工艺形成贯穿至少部分所述第二膜层组2的第一接触孔101和贯穿所述第二膜层组2的所述第一过孔201。
由于所述第一接触孔101和所述第一过孔201均开设于所述第二膜层组2内，两者深度接近，故所述第一接触孔101和所述第一过孔201采用同一次构图工艺和同一掩膜板形成，相比于现有技术，该显示面板的制造过程可以节约一次构图工艺。
进一步地，所述步骤S20还包括以下步骤：
S203：通过同一第二构图工艺形成贯穿所述第一膜层组1和至少部分所述第二膜层组2的第二接触孔102和贯穿所述第二膜层组2的所述第二过孔202。
由于所述第二接触孔102和所述第二过孔202的深度接近，故所述第二接触孔102和所述第二过孔202采用同一次构图工艺和同一掩膜板形成，相比于现有技术，该显示面板的制造过程可以进一步节约一次构图工艺。
具体地，所述步骤S201包括以下步骤：
在所述衬底基板100上依次形成阻隔层14和缓冲层15。
具体地，如图3A所示，所述阻隔层14位于所述衬底基板100上，所述缓冲层15位于所述阻隔层14上，所述阻隔层14所用的材料包括氧化硅、氮化硅、氮氧化硅和非晶硅中的一种或几种，主要用于阻隔水氧，防止外部的水汽或者氧气侵蚀所述显示面板。所述缓冲层15所用的材料包括氮化硅和氧化硅中的一种或两种，主要起到缓冲和保护的作用。
可选地，所述衬底基板100包括第一柔性层11、第二柔性层13以及设置于所述第一柔性层11和所述第二柔性层13之间的无机层12，所述无机层12一方面用于阻隔水氧，另一方面用于防止激光剥离对所述第一柔性层11和所述第二柔性层13造成损伤。
在所述缓冲层15上依次形成所述硅晶体管200的第一有源层16、第一栅极绝缘层17、第一栅极层18、第二栅极绝缘层19、第二栅极层20以及第一层间介质层21，得到所述第一膜层组。
具体地，如图3B所示，所述第一有源层16图案化形成于所述缓冲层15远离所述衬底基板100的一侧，所述第一有源层16的材料为低温多晶硅。所述第一栅极绝缘层17覆盖所述第一有源层16，所述第一栅极层18图案化形成于所述第一栅极绝缘层17远离所述衬底基板100的一侧，所述第二栅极绝缘层19覆盖所述第一栅极层18，所述第二栅极层20图案化形成于所述第二栅极绝缘层19上，所述第一层间介质层21覆盖所述第二栅极层20。
在所述第一层间介质层21上依次形成所述氧化物半导体晶体管300的第二有源层22、第三栅极绝缘层23、第三栅极层24以及第二层间介质层25，得到所述第二膜层组。
具体地，如图3C所示，所述第二有源层22图案化形成于所述第一层间介质层21远离所述衬底基板100的一侧，所述第二有源层22的材料为金属氧化物。所述第三栅极绝缘层23覆盖所述第二有源层22，所述第三栅极层24图案化形成于所述第三栅极绝缘层23远离所述衬底基板100的一侧，所述第二层间介质层25覆盖所述第三栅极层24。
其中，通过同一所述第一构图工艺形成的所述第一接触孔101和所述第一过孔201贯穿所述第二层间介质层25和所述第三栅极绝缘层23，通过同一所述第二构图工艺形成的所述第二接触孔102贯穿所述第二层间介质层25、所述第三栅极绝缘层23、所述第一层间介质层21、所述第二栅极绝缘层19以及所述第一栅极绝缘层17，通过同一所述第二构图工艺形成的所述第二过孔202贯穿所述第一层间介质层21、所述第二栅极绝缘层19、所述第一栅极绝缘层17、所述缓冲层15以及所述阻隔层14。
通过同一所述第一构图工艺形成所述第一接触孔101和所述第一过孔201，包括以下步骤：
在所述第二层间介质层25上形成第一光刻胶层。
对所述第一光刻胶层依次进行曝光、显影和刻蚀，得到贯穿所述第二层间介质层25和所述第三栅极绝缘层23的所述第一接触孔101和所述第一过孔201。以及
剥离剩余的所述第一光刻胶层。
具体地，如图3D所示，形成所述第一接触孔101和所述第一过孔201需要先后蚀刻所述第二层间介质层25和所述第三栅极绝缘层23，由于所述第二有源层22的厚度很薄，因此，形成所述第一接触孔101和所述第一过孔201所需刻蚀的膜层厚度近乎相同，均相当于所述第二层间介质层25和所述第三栅极绝缘层23的厚度之和，故在本发明实施例中，所述第一接触孔101和所述第一过孔201可以采用同一次构图工艺形成，因所述第二有源层22具有刻蚀阻挡的作用，因此该构图工艺中的蚀刻过程在蚀刻至所述第二有源层22时停止，而所述第三栅极绝缘层23不具有刻蚀阻挡的作用，因此该构图工艺中的蚀刻过程在蚀刻至所述第二层间介质层25时停止。
此步骤相比现有技术中，所述第一接触孔101和所述第一过孔201由不同的掩膜板制备，能够减少一次构图工艺，降低生产成本，提升产品良率。
所述第一接触孔101的底部与所述第二有源层22远离所述衬底基板100的一侧接触，所述第一过孔201的底部与所述第一层间介质层21远离所述衬底基板100的一侧接触，所述第一接触孔101的侧壁与第一方向形成的夹角的取值介于50°至80°之间，所述第一过孔201的侧壁与第一方向形成的夹角的取值介于30°至60°之间，其中第一方向为与所述显示面板厚度方向垂直的水平方向。
进一步地，通过同一所述第二构图工艺形成所述第二接触孔102和所述第二过孔202，包括以下步骤：
在所述第二层间介质层25和所述第一过孔201的内侧壁上形成第二光刻胶层。
对所述第二光刻胶层依次进行曝光、显影和刻蚀，得到贯穿所述第二层间介质层25、所述第三栅极绝缘层23、所述第一层间介质层21、所述第二栅极绝缘层19、所述第一栅极绝缘层17以及所述缓冲层15的所述第二接触孔102，以及贯穿所述第一层间介质层21、所述第二栅极绝缘层19、所述第一栅极绝缘层17、所述缓冲层15以及所述阻隔层14的所述第二过孔202，以及
剥离剩余的所述第二光刻胶层。
具体地，如图3E所示，和步骤S203的原理相似，形成所述第二过孔202需要先后蚀刻所述第二层间介质层25、所述第三栅极绝缘层23、所述第一层间介质层21、所述第二栅极绝缘层19、所述第一栅极绝缘层17、所述缓冲层15以及所述阻隔层14。由于所述阻隔层14的厚度与所述第二层间介质层25及所述第三栅极绝缘层23的厚度相等，而形成所述第二接触孔102和所述第二过孔202所需刻蚀的膜层厚度近乎相同，具体地，形成所述第二接触孔102所需蚀刻的膜层厚度为1100nm~1350nm，形成所述第二过孔202所需蚀刻的膜层厚度也为1100nm-1350nm。因此，形成所述第二接触孔102可以通过先后蚀刻所述第二层间介质层25、所述第三栅极绝缘层23、所述第一层间介质层21、所述第二栅极绝缘层19、所述第一栅极绝缘层17、所述第一有源层16以及所述缓冲层15。故在本发明实施例中，所述第二接触孔102和所述第二过孔202可以采用同一次构图工艺形成，形成所述第二接触孔102时，该构图工艺中的蚀刻过程在蚀刻至所述阻隔层14时停止，形成所述第二过孔202时，该构图工艺中的蚀刻过程在蚀刻至所述衬底基板100的所述第二柔性层13时停止。
同理，此步骤相比现有技术中，所述第二接触孔102和所述第二过孔202由不同的掩膜板制备，能够减少一次构图工艺，降低生产成本，提升产品良率。
具体地，所述第二接触孔102的底部与所述阻隔层14远离所述衬底基板100的一侧接触，所述第二过孔202的底部与所述阻隔层14靠近所述衬底基板100的一侧接触，所述第二接触孔102的侧壁与所述第一方向形成的夹角的取值介于50°至80°之间，所述第二过孔202的侧壁与所述第一方向形成的夹角的取值介于25°至55°之间。
本发明实施例中，所述第一过孔201和所述第二过孔202之间相互连通，可用于去除所述显示面板的部分无机绝缘材料，提高所述显示面板的抗弯折性能。其中，所述第一过孔201的孔径大于所述第二过孔202的孔径，所述第一过孔201的孔径和所述第二过孔202的孔径沿所述第二层间介质层25至所述衬底基板100的方向均逐渐减小。所述第一过孔201和所述第二过孔202之间形成一台阶面，所述台阶面位于所述第一层间介质层21远离所述衬底基板100的一侧，由于所述台阶面边缘较为圆滑，不仅方便后续制备而成的第一源漏极金属层26进行布线，而且所述台阶面能够将步骤S20中的两次刻蚀过程明显区分开来。
在所述通过同一所述第二构图工艺形成所述第二接触孔和所述第二过孔之后，所述步骤S20还包括：
在所述第二层间介质层25上形成第一源漏极金属层26，所述第一源漏极金属层26通过所述第一接触孔101和与所述第二有源层22连接，所述第一源漏极金属层26通过所述第二接触孔102和与所述第一有源层16连接。
具体地，如图3F所示，在所述第二层间介质层25远离所述衬底基板100的一侧图案化形成所述第一源漏极金属层26，所述第一源漏极金属层26包括所述硅晶体管200的第一源极和第一漏极，每组所述第二接触孔102的数量为三个，所述第一源极通过其中一个所述第二接触孔102与所述第一有源层16连接，所述第一漏极通过其中一个所述第二接触孔102与所述第一有源层16连接。同样地，所述第一源漏极金属层26还包括所述氧化物半导体晶体管300的第二源极和第二漏极，所述第二源极通过另外一个所述第二接触孔102与所述第一有源层16连接。每组所述第一接触孔101的数量为两个，所述第二源极通过其中一个所述第一接触孔101与所述第二有源层22连接，所述第二漏极通过另外一个所述第一接触孔101与所述第二有源层22连接。
在本发明实施例中，所述第一源极和所述第一漏极，以及所述第二源极和所述第二漏极位于同一金属层，可采用同一工艺制备而成，能够简化制程。
进一步地，如图3G所示，在所述第二层间介质层25上形成第一源漏极金属层26之后，所述制备方法还包括以下步骤：
在所述第一源漏极金属层26上依次形成所述第一钝化层27、第一平坦层28以及所述第二源漏极金属层29，所述第一平坦层28填充所述第一过孔201和所述第二过孔202，所述第一平坦层28上形成有第三接触孔103，所述第二源漏极金属层29通过所述第三接触孔103与所述第一源漏极金属层26连接。
在所述第二源漏极金属层29上依次形成第二平坦层30、阳极31、像素定义层32、发光层33以及隔垫物34，所述第二平坦层30上形成有第四接触孔104，所述阳极31通过所述第四接触孔104与所述第二源漏极金属层29连接。
具体地，所述第二源漏极金属层29通过所述第三接触孔103与所述第一漏极连接。所述第一平坦层28和所述第二平坦层30采用柔性材料，所述第一平坦层28填充于所述第一过孔201和所述第二过孔202，以防止位于所述弯折区内的金属走线发生断裂。所述第二源漏极金属层29在所述衬底基板100的正投影覆盖所述第二有源层22在所述衬底基板100的正投影，以使所述第二源漏极金属层29对于所述第二有源层22起到遮光和屏蔽离子的作用，避免不良情况产生。
此外，还可以通过改善所述第二层间介质层25的成膜工艺及退火工艺来确保所述第二有源层22的器件特性，由此上述在所述第一源漏极金属层26上形成钝化层的步骤可以去除，可进一步减少一次构图工艺。
请参阅图4，本发明实施例提供的显示面板，采用上述实施例提供的显示面板的制备方法制备而成，所述显示面板包括显示区A和围绕所述显示区A的非显示区B，所述非显示区B可弯折至所述显示面板背面，以减小所述显示面板的下边框，有利于提高屏占比，便于实现全面屏显示。
所述显示面板包括衬底基板100、硅晶体管200、氧化物半导体晶体管300、第一过孔201以及第二过孔202。
所述硅晶体管200和所述氧化物半导体晶体管300设置于所述衬底基板100上，其中，所述硅晶体管200和所述氧化物半导体晶体管300位于所述显示区A，所述第一过孔201和所述第二过孔202均位于所述弯折区B，由于所述硅晶体管200阈值电压不漂移，可用作驱动晶体管；由于所述氧化物半导体晶体管300开关性能好，可用作开关晶体管。
其中，所述硅晶体管200位于第一膜层组1，所述氧化物半导体晶体管300位于第二膜层组2，所述第一膜层组1和所述第二膜层组2依次设置于所述衬底基板100上，所述氧化物半导体晶体管300包括第一接触孔101，所述第一接触孔101贯穿至少所述第二膜层组2，所述第一过孔201贯穿所述第二膜层组2，所述第一接触孔101的深度和所述第一过孔201的深度相等。
进一步地，所述硅晶体管200和所述氧化物半导体晶体管300包括第二接触孔102，所述第二接触孔102贯穿所述第一膜层组1和至少部分所述第二膜层组2，所述第二过孔202贯穿所述第二膜层组2，所述第二接触孔102的深度和所述第二过孔202的深度相等。
所述第一膜层组1包括依次设置于所述衬底基板上的阻隔层14、缓冲层15、第一有源层16、第一栅极绝缘层17、第一栅极层18、第二栅极绝缘层19、第二栅极层20以及第一层间介质层21；所述第二膜层组2包括依次设置于所述第一层间介质层21上的第二有源层22、第三栅极绝缘层23、第三栅极层24以及第二层间介质层25。
其中，所述第一接触孔101和所述第一过孔201贯穿所述第二层间介质层25和所述第三栅极绝缘层23，所述第二接触孔102贯穿所述第二层间介质层25、所述第三栅极绝缘层23、所述第一层间介质层21、所述第二栅极绝缘层19、所述第一栅极绝缘层17、所述第一有源层16以及所述缓冲层15，所述第二过孔202贯穿所述第一层间介质层21、所述第二栅极绝缘层19、所述第一栅极绝缘层17、所述缓冲层15以及所述阻隔层14。
其中，本发明实施例中的所述硅晶体管200采用双栅极结构，包括依次设置于所述缓冲层15上的第一有源层16、第一栅极绝缘层17、第一栅极层18、第二栅极绝缘层19、第二栅极层20以及第一层间介质层21。所述氧化物半导体晶体管300包括依次设置于所述第一层间介质层21上的第二有源层22、第三栅极绝缘层23、第三栅极层24以及第二层间介质层25，所述第二层间介质层25上设置有第一源漏极金属层26，所述第一源漏极金属层26通过第一接触孔101和与所述第二有源层22连接，所述第一源漏极金属层26通过第二接触孔102和与所述第一有源层16连接。
具体地，所述第一源漏极金属层26包括所述硅晶体管200的第一源极和第一漏极，每组所述第二接触孔102的数量为三个，所述第一源极通过其中一个所述第二接触孔102与所述第一有源层16连接，所述第一漏极通过其中一个所述第二接触孔102与所述第一有源层16连接。同样地，所述第一源漏极金属层26还包括所述氧化物半导体晶体管300的第二源极和第二漏极，所述第二源极通过另外一个所述第二接触孔102与所述第一有源层16连接。每组所述第一接触孔101的数量为两个，所述第二源极通过其中一个所述第一接触孔101与所述第二有源层22连接，所述第二漏极通过另外一个所述第一接触孔101与所述第二有源层22连接。
所述第一过孔201和所述第二过孔202之间相互连通。所述第一接触孔101和所述第一过孔201贯穿所述第二层间介质层25和所述第三栅极绝缘层23，所述第二接触孔102贯穿所述第二层间介质层25、所述第三栅极绝缘层23、所述第一层间介质层21、所述第二栅极绝缘层19、所述第一栅极绝缘层17、所述第一有源层16以及所述缓冲层15，所述第二过孔202贯穿所述第一层间介质层21、所述第二栅极绝缘层19、所述第一栅极绝缘层17、所述缓冲层15以及所述阻隔层14。所述第一接触孔101和所述第一过孔201可以采用同一次构图工艺形成，所述第二接触孔102和所述第二过孔202可以采用同一次构图工艺形成，与现有技术相比，能够减少两次构图工艺，降低生产成本，提升产品良率。
具体地，所述第一接触孔101的底部与所述第二有源层22远离所述衬底基板100的一侧接触，所述第二接触孔102的底部与所述缓冲层15远离所述衬底基板100的一侧接触。所述第一过孔201的底部与所述第一层间介质层21远离所述衬底基板100的一侧接触，所述第二过孔202的底部与所述阻隔层14靠近所述衬底基板100的一侧接触。
所述第一过孔201的孔径大于所述第二过孔202的孔径，所述第一过孔201的孔径和所述第二过孔202的孔径沿所述第二层间介质层25至所述衬底基板100的方向均逐渐减小。所述第一过孔201和所述第二过孔202之间形成一台阶面，所述台阶面位于所述第一层间介质层21远离所述衬底基板100的一侧。
所述显示面板还包括依次设置于所述第一源漏极金属层26上的钝化层27、第一平坦层28以及第二源漏极金属层29，所述钝化层27覆盖所述第二层间介质层25和所述第一源漏极金属层26，所述第一平坦层28填充于所述第一过孔201和所述第二过孔202。所述第二源漏极金属层29上依次设置有第二平坦层30、阳极31、像素定义层32、发光层33以及多个隔垫物34，所述像素定义层32覆盖所述阳极31，所述像素定义层32上设置有暴露出所述阳极31的凹槽，所述发光层33设置于所述凹槽内，多个所述隔垫物34间隔设置于所述像素定义层32远离所述衬底基板100的一侧。所述第二源漏极金属层29通过贯穿所述第一平坦层28的第三接触孔103与所述第一源漏极金属层26连接，所述阳极31通过贯穿所述第二平坦层30的第四接触孔104与所述第二源漏极金属层29连接。
进一步地，如图5所示，图5提供的显示面板与图4提供的显示面板的不同之处在于，省去了所述钝化层27，减少了所述显示面板的整体厚度。具体可以通过改善所述第二层间介质层25的成膜工艺及退火工艺来确保所述第二有源层22的器件特性。
有益效果为：本发明提供的显示面板及其制备方法，用于连接氧化物半导体晶体管的源漏极金属层和第二有源层的第一接触孔，与第一过孔采用同一次构图工艺和同一掩膜板形成，用于连接硅晶体管的源漏极金属层和第一有源层的第二接触孔，与第二过孔通过同一次构图工艺和同一掩膜板形成，因此，相比于现有技术，该显示面板的制造过程至少可以节约两次构图工艺，从而简化了显示面板的制程，降低了生产成本，提升了产品良率。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种显示面板的制备方法，所述显示面板包括显示区和围绕所述显示区的非显示区，所述显示面板的制备方法包括以下步骤：
    S10：提供衬底基板,所述衬底基板包括第一柔性层、第二柔性层以及设置于所述第一柔性层和所述第二柔性层之间的无机层；以及
    S20：在所述衬底基板上形成位于所述显示区的硅晶体管和氧化物半导体晶体管，以及位于所述非显示区的相互连通的第一过孔和第二过孔，其中，所述硅晶体管位于第一膜层组，所述氧化物半导体晶体管位于第二膜层组；
    其中，所述步骤S20包括以下步骤：
    S201：在所述衬底基板依次形成所述第一膜层组和所述第二膜层组；以及
    S202：通过同一第一构图工艺形成贯穿至少部分所述第二膜层组的第一接触孔和贯穿所述第二膜层组的所述第一过孔。
  2. 根据权利要求1所述的显示面板的制备方法，其中所述步骤S20还包括以下步骤：
    S203：通过同一第二构图工艺形成贯穿所述第一膜层组和至少部分所述第二膜层组的第二接触孔和贯穿所述第二膜层组的所述第二过孔。
  3. 根据权利要求2所述的显示面板的制备方法，其中所述步骤S201包括以下步骤：
    在所述衬底基板上依次形成阻隔层和缓冲层；
    在所述缓冲层上依次形成所述硅晶体管的第一有源层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层以及第一层间介质层，得到所述第一膜层组；以及
    在所述第一层间介质层上依次形成所述氧化物半导体晶体管的第二有源层、第三栅极绝缘层、第三栅极层以及第二层间介质层，得到所述第二膜层组；
    其中，通过同一所述第一构图工艺形成的所述第一接触孔和所述第一过孔贯穿所述第二层间介质层和所述第三栅极绝缘层，通过同一所述第二构图工艺形成的所述第二接触孔贯穿所述第二层间介质层、所述第三栅极绝缘层、所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层以及所述缓冲层，通过同一所述第二构图工艺形成的所述第二过孔贯穿所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻隔层。
  4. 根据权利要求3所述的显示面板的制备方法，其中通过同一所述第一构图工艺形成所述第一接触孔和所述第一过孔，包括以下步骤：
    在所述第二层间介质层上形成第一光刻胶层；
    对所述第一光刻胶层依次进行曝光、显影和刻蚀，得到贯穿所述第二层间介质层和所述第三栅极绝缘层的所述第一接触孔和所述第一过孔；以及
    剥离剩余的所述第一光刻胶层。
  5. 根据权利要求3所述的显示面板的制备方法，其中通过同一所述第二构图工艺形成所述第二接触孔和所述第二过孔，包括以下步骤：
    在所述第二层间介质层和所述第一过孔的内侧壁上形成第二光刻胶层；
    对所述第二光刻胶层依次进行曝光、显影和刻蚀，得到贯穿所述第二层间介质层、所述第三栅极绝缘层、所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层以及所述缓冲层的所述第二接触孔，以及贯穿所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻隔层的所述第二过孔；以及
    剥离剩余的所述第二光刻胶层。
  6. 根据权利要求3所述的显示面板的制备方法，其中在所述通过同一所述第二构图工艺形成所述第二接触孔和所述第二过孔之后，所述步骤S20还包括：
    在所述第二层间介质层上形成第一源漏极金属层，所述第一源漏极金属层通过所述第一接触孔与所述第二有源层连接，所述第一源漏极金属层通过所述第二接触孔和与所述第一有源层连接。
  7. 根据权利要求6所述的显示面板的制备方法，其中在所述第二层间介质层上形成第一源漏极金属层之后，所述制备方法还包括以下步骤：
    在所述第一源漏极金属层上依次形成钝化层、第一平坦层以及所述第二源漏极金属层，所述第一平坦层填充所述第一过孔和所述第二过孔，所述第一平坦层上形成有第三接触孔，所述第二源漏极金属层通过所述第三接触孔与所述第一源漏极金属层连接；以及
    在所述第二源漏极金属层上依次形成第二平坦层、阳极、像素界定层、发光层以及隔垫物，所述第二平坦层上形成有第四接触孔，所述阳极通过所述第四接触孔与所述第二源漏极金属层连接。
  8. 一种显示面板的制备方法，所述显示面板包括显示区和围绕所述显示区的非显示区，所述显示面板的制备方法包括以下步骤：
    S10：提供衬底基板；以及
    S20：在所述衬底基板上形成位于所述显示区的硅晶体管和氧化物半导体晶体管，以及位于所述非显示区的相互连通的第一过孔和第二过孔，其中，所述硅晶体管位于第一膜层组，所述氧化物半导体晶体管位于第二膜层组；
    其中，所述步骤S20包括以下步骤：
    S201：在所述衬底基板依次形成所述第一膜层组和所述第二膜层组；以及
    S202：通过同一第一构图工艺形成贯穿至少部分所述第二膜层组的第一接触孔和贯穿所述第二膜层组的所述第一过孔。
  9. 根据权利要求8所述的显示面板的制备方法，其中所述步骤S20还包括以下步骤：
    S203：通过同一第二构图工艺形成贯穿所述第一膜层组和至少部分所述第二膜层组的第二接触孔和贯穿所述第二膜层组的所述第二过孔。
  10. 根据权利要求9所述的显示面板的制备方法，其中所述步骤S201包括以下步骤：
    在所述衬底基板上依次形成阻隔层和缓冲层；
    在所述缓冲层上依次形成所述硅晶体管的第一有源层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层以及第一层间介质层，得到所述第一膜层组；以及
    在所述第一层间介质层上依次形成所述氧化物半导体晶体管的第二有源层、第三栅极绝缘层、第三栅极层以及第二层间介质层，得到所述第二膜层组；
    其中，通过同一所述第一构图工艺形成的所述第一接触孔和所述第一过孔贯穿所述第二层间介质层和所述第三栅极绝缘层，通过同一所述第二构图工艺形成的所述第二接触孔贯穿所述第二层间介质层、所述第三栅极绝缘层、所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层以及所述缓冲层，通过同一所述第二构图工艺形成的所述第二过孔贯穿所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻隔层。
  11. 根据权利要求10所述的显示面板的制备方法，其中通过同一所述第一构图工艺形成所述第一接触孔和所述第一过孔，包括以下步骤：
    在所述第二层间介质层上形成第一光刻胶层；
    对所述第一光刻胶层依次进行曝光、显影和刻蚀，得到贯穿所述第二层间介质层和所述第三栅极绝缘层的所述第一接触孔和所述第一过孔；以及
    剥离剩余的所述第一光刻胶层。
  12. 根据权利要求10所述的显示面板的制备方法，其中通过同一所述第二构图工艺形成所述第二接触孔和所述第二过孔，包括以下步骤：
    在所述第二层间介质层和所述第一过孔的内侧壁上形成第二光刻胶层；
    对所述第二光刻胶层依次进行曝光、显影和刻蚀，得到贯穿所述第二层间介质层、所述第三栅极绝缘层、所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层以及所述缓冲层的所述第二接触孔，以及贯穿所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻隔层的所述第二过孔；以及
    剥离剩余的所述第二光刻胶层。
  13. 根据权利要求10所述的显示面板的制备方法，其中在所述通过同一所述第二构图工艺形成所述第二接触孔和所述第二过孔之后，所述步骤S20还包括：
    在所述第二层间介质层上形成第一源漏极金属层，所述第一源漏极金属层通过所述第一接触孔与所述第二有源层连接，所述第一源漏极金属层通过所述第二接触孔和与所述第一有源层连接。
  14. 根据权利要求13所述的显示面板的制备方法，其中在所述第二层间介质层上形成第一源漏极金属层之后，所述制备方法还包括以下步骤：
    在所述第一源漏极金属层上依次形成钝化层、第一平坦层以及所述第二源漏极金属层，所述第一平坦层填充所述第一过孔和所述第二过孔，所述第一平坦层上形成有第三接触孔，所述第二源漏极金属层通过所述第三接触孔与所述第一源漏极金属层连接；以及
    在所述第二源漏极金属层上依次形成第二平坦层、阳极、像素界定层、发光层以及隔垫物，所述第二平坦层上形成有第四接触孔，所述阳极通过所述第四接触孔与所述第二源漏极金属层连接。
  15. 一种显示面板，包括显示区和围绕所述显示区的非显示区，所述显示面板包括：
    衬底基板；以及
    位于所述衬底基板上的硅晶体管和氧化物半导体晶体管，以及相互连通的第一过孔和第二过孔，所述硅晶体管和所述氧化物半导体晶体管位于所述显示区，所述第一过孔和所述第二过孔位于所述非显示区；
    其中，所述硅晶体管位于第一膜层组，所述氧化物半导体晶体管位于第二膜层组，所述第一膜层组和所述第二膜层组依次设置于所述衬底基板上，所述氧化物半导体晶体管包括第一接触孔，所述第一接触孔贯穿至少所述第二膜层组，所述第一过孔贯穿所述第二膜层组，所述第一接触孔的深度和所述第一过孔的深度相等。
  16. 根据权利要求15所述的显示面板，其中所述硅晶体管和所述氧化物半导体晶体管包括第二接触孔，所述第二接触孔贯穿所述第一膜层组和至少部分所述第二膜层组，所述第二过孔贯穿所述第二膜层组，所述第二接触孔的深度和所述第二过孔的深度相等。
  17. 根据权利要求16所述的显示面板，其中所述第一膜层组包括依次设置于所述衬底基板上的阻隔层、缓冲层、第一有源层、第一栅极绝缘层、第一栅极层、第二栅极绝缘层、第二栅极层以及第一层间介质层；
    所述第二膜层组包括依次设置于所述第一层间介质层上的第二有源层、第三栅极绝缘层、第三栅极层以及第二层间介质层；
    其中，所述第一接触孔和所述第一过孔贯穿所述第二层间介质层和所述第三栅极绝缘层，所述第二接触孔贯穿所述第二层间介质层、所述第三栅极绝缘层、所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述第一有源层以及所述缓冲层，所述第二过孔贯穿所述第一层间介质层、所述第二栅极绝缘层、所述第一栅极绝缘层、所述缓冲层以及所述阻隔层。
  18. 根据权利要求17所述的显示面板，其中所述第二层间介质层上设置有第一源漏极金属层，所述显示面板还包括设置于所述第一源漏极金属层上的钝化层、第一平坦层以及第二源漏极金属层。
  19. 根据权利要求17所述的显示面板，其中所述第一过孔的孔径大于所述第二过孔的孔径，所述第一过孔的孔径和所述第二过孔的孔径沿所述第二层间介质层至所述衬底基板的方向均逐渐减小。
  20. 根据权利要求15所述的显示面板，其中所述衬底基板包括第一柔性层、第二柔性层以及设置于所述第一柔性层和所述第二柔性层之间的无机层。
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