WO2019029009A1 - 薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板 - Google Patents

薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板 Download PDF

Info

Publication number
WO2019029009A1
WO2019029009A1 PCT/CN2017/106975 CN2017106975W WO2019029009A1 WO 2019029009 A1 WO2019029009 A1 WO 2019029009A1 CN 2017106975 W CN2017106975 W CN 2017106975W WO 2019029009 A1 WO2019029009 A1 WO 2019029009A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
conductor
source
semiconductor layer
drain
Prior art date
Application number
PCT/CN2017/106975
Other languages
English (en)
French (fr)
Inventor
李松杉
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US15/737,305 priority Critical patent/US10510899B2/en
Publication of WO2019029009A1 publication Critical patent/WO2019029009A1/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78609—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device for preventing leakage current

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a method of manufacturing a thin film transistor and a thin film transistor, and a liquid crystal display panel.
  • Thin Film Transistor is widely used in liquid crystal display devices (Liquid) Crystal Display (abbreviated as LCD) and active matrix driven organic electroluminescent display device (Active Matrix Organic Light-Emitting) Diode, referred to as AMOLED), therefore, thin film transistors affect the development of the display industry.
  • LCD Liquid
  • AMOLED Active Matrix Organic Light-Emitting
  • thin film transistors affect the development of the display industry.
  • the formed thin film transistor has a problem that the leakage current is excessively large, and the characteristics of the thin film transistor are affected.
  • Embodiments of the present invention provide a method for fabricating a thin film transistor and a thin film transistor, and a liquid crystal display panel to solve the problem of excessive leakage current of the thin film transistor.
  • a technical solution adopted by the embodiment of the present invention is to provide a thin film transistor including a substrate, a gate layer disposed on the substrate, an insulating layer covering the gate layer, and a semiconductor layer.
  • the conductor layer is disposed on the semiconductor layer;
  • the source and drain layers are disposed on the conductor layer and the insulating layer, and a conductor layer or a conductive spacer is disposed between the source and drain layers and the semiconductor layer;
  • the layer is disposed on the insulating layer, the source and drain layers, and the semiconductor layer.
  • another technical solution adopted by the embodiment of the present invention is to provide a method for manufacturing a thin film transistor, the manufacturing method comprising: a substrate; a gate layer and an insulating layer are sequentially formed on the substrate, and the insulating layer covers the gate a semiconductor layer and a conductor layer are sequentially formed on the insulating layer; a source/drain layer is formed on the conductor layer and the insulating layer, wherein a conductor layer or a conductive spacer is disposed between the source and drain layers and the semiconductor layer; A conductive spacer is disposed between the electrode layer and the semiconductor layer, and a conductive spacer is disposed on the insulating layer before the source and drain layers are formed; and a passivation layer is disposed on the insulating layer, the source/drain layer, and the semiconductor layer.
  • a liquid crystal display panel including a thin film transistor including a substrate, a gate layer disposed on the substrate, and an insulating layer. Covering the gate layer; the semiconductor layer is disposed on the insulating layer; the conductor layer is disposed on the semiconductor layer; the semiconductor layer has a channel region, the channel region divides the semiconductor layer into left and right portions, and the conductor layer is formed on the semiconductor layer a left and right portion to form a two-island structure; a source-drain layer disposed on the conductor layer and the insulating layer, a conductor layer or a conductive spacer disposed between the source-drain layer and the semiconductor layer; and a passivation layer disposed on The insulating layer, the source and drain layers, and the semiconductor layer; the gate layer and the source and drain layers are metal materials; the insulating layer, the insulating spacer layer, and the passivation layer are all insulating materials.
  • the invention sequentially forms a gate layer and an insulating layer on the substrate, the insulating layer covers the gate layer; the semiconductor layer and the conductor layer are sequentially formed on the insulating layer; the source and drain layers are formed on the conductor layer and the insulating layer, wherein the source and drain are formed a conductive layer or a conductive spacer is disposed between the pole layer and the semiconductor layer; if a conductive spacer is disposed between the source drain layer and the semiconductor layer, a conductive spacer is disposed on the insulating layer before the source drain layer is formed; Providing a passivation layer on the insulating layer, the source/drain layer, and the semiconductor layer, and by providing a conductor layer or a conductive spacer between the source/drain layer and the semiconductor layer, direct contact between the source/drain layer and the semiconductor layer can be prevented, thereby There is an effect of reducing leakage current and improving the characteristics of the thin film transistor.
  • FIG. 1 is a schematic structural view of an embodiment of a thin film transistor of the present invention.
  • FIG. 2 is a schematic structural view of another embodiment of a thin film transistor of the present invention.
  • FIG. 3 is a schematic flow chart of an embodiment of a method for fabricating a thin film transistor of the present invention
  • FIG. 4 is a schematic structural view of a substrate after step S13 in the method of manufacturing the thin film transistor shown in FIG. 3;
  • FIG. 5 is a schematic flow chart of another embodiment of a method of manufacturing a thin film transistor of the present invention.
  • FIG. 6 is a schematic structural view of a substrate after step S232 in the method of manufacturing the thin film transistor shown in FIG. 5;
  • FIG. 7 is a schematic structural view of a substrate after step S234 in the method of manufacturing the thin film transistor shown in FIG. 5;
  • FIG. 8 is a schematic structural view of a substrate after step S25 in the method of manufacturing the thin film transistor shown in FIG. 5;
  • FIG. 9 is a schematic flow chart showing still another embodiment of a method of manufacturing a thin film transistor of the present invention.
  • FIG. 10 is a schematic view showing the mask etching in step S334 of the manufacturing method of the thin film transistor shown in FIG. 9; FIG.
  • FIG. 11 is a schematic structural view of an embodiment of a liquid crystal display panel of the present invention.
  • a plurality is at least two, such as two, three, etc., unless specifically defined otherwise.
  • the terms “comprises” and “comprising” and “comprising” are intended to cover a non-exclusive inclusion.
  • a process, method, system, product, or device that comprises a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units not listed, or, optionally, Other steps or units inherent to these processes, methods, products or equipment.
  • references to "an embodiment” herein mean that a particular feature, structure, or characteristic described in connection with the embodiments can be included in at least one embodiment of the invention.
  • the appearances of the phrases in various places in the specification are not necessarily referring to the same embodiments, and are not exclusive or alternative embodiments that are mutually exclusive. Those skilled in the art will understand and implicitly understand that the embodiments described herein can be combined with other embodiments.
  • FIG. 1 is a schematic structural view of an embodiment of a thin film transistor of the present invention
  • FIG. 2 is a schematic structural view of another embodiment of the thin film transistor of the present invention.
  • both embodiments of FIGS. 1 and 2 are given the same reference numerals.
  • the thin film transistor 100 includes a substrate 110, a gate layer 120, an insulating layer 130, a semiconductor layer 140, a conductor layer 150, a source and drain layer 170, and a passivation layer 180, and in one embodiment further includes a conductive spacer 160.
  • the thin film transistor 100 has a laminated structure, and each of the above layers is sequentially formed on the substrate 110, and the substrate 110 may be a glass substrate.
  • the gate layer 120 is formed on the substrate 110, and the insulating layer 130 covers the gate layer 120.
  • the thin film transistor 100 is a bottom gate structure.
  • the semiconductor layer 140 is formed as an active layer of the thin film transistor 100 on the insulating layer 130; the conductive layer 150 is formed on the semiconductor layer 140 for connecting the semiconductor layer 140 and the source and drain layers 170, and the source and drain layers 170 pass between After the conductor layer 150 is formed with a current through the semiconductor layer 140, the semiconductor layer 140 is directly connected to the source and drain layer 170. In this embodiment, the conductor layer 150 has a small resistance, and the source and drain layers 170 and the semiconductor layer 140 can be reduced. Leakage current condition.
  • a conductive layer 150 or a conductive spacer 160 is further formed on the insulating layer 130 in this embodiment, that is, the conductive layer 150 or the conductive spacer 160 is disposed in the same layer as the semiconductor layer 140; the source and drain layer 170 is formed on the conductive layer 150. And a conductive spacer 160; the conductive spacer 160 is located between the semiconductor layer 140 and the source and drain layers 170.
  • the conductive layer 150 or the conductive spacers 160 are disposed between the semiconductor layer 140 and the source and drain layers 170, that is, there is no direct contact connection between the semiconductor layer 140 and the source and drain layers 170, so that the semiconductor layer 140 can be effectively reduced. Leakage current between the source and drain layers 170.
  • the semiconductor layer 140 has a channel region 141 which divides the semiconductor layer 140 into left and right portions, and a conductor layer 150 is formed on the left and right portions of the semiconductor layer 140 to form a two-island structure.
  • the source and drain layers 170 formed on the two island structures of the conductor layer 150 are also distinguished as a source and a drain.
  • the passivation layer 180 is formed on the source and drain layers 170 and the semiconductor layer 140, specifically formed on the channel region 141 of the semiconductor 140, and formed between the two island structures of the conductor layer 150.
  • the insulating layer 130 and the passivation layer 180 are both made of an insulating material, and may be silicon oxide or silicon nitride.
  • the gate layer 120 and the source/drain layer 170 are made of a metal material, and may be a metal material such as molybdenum or aluminum, or a metal material of a combination of molybdenum-aluminum-molybdenum.
  • the semiconductor layer 140 may be polysilicon, and the conductor layer 150 and the conductive spacers 160 may be P+ conductor layers formed of polysilicon doped with B ions.
  • a conductor layer 150 or a conductive spacer 160 may be disposed between the semiconductor layer 140 and the source and drain layers 170 in this embodiment, such as the two modes shown in FIGS. 1 and 2.
  • a conductive spacer 160 is formed on a side of the semiconductor layer 140 such that the conductive spacer 160 is disposed between the source and drain layers 170 and the semiconductor layer 140.
  • the conductor layer 150 covers the semiconductor layer 140 such that the conductor layer 150 is disposed between the source and drain layers 170 and the semiconductor layer 140, and is also formed on the side of the semiconductor layer 140 on the insulating layer 130.
  • the conductive spacer or the conductor layer is located between the source and drain layers and the semiconductor layer, which can block the direct contact between the source and drain layers and the semiconductor layer, thereby reducing the problem of leakage current, thereby improving the performance of the thin film transistor.
  • the thin film transistor of the present embodiment includes the substrate including a substrate; a gate layer disposed on the substrate; an insulating layer covering the gate layer; a semiconductor layer disposed on the insulating layer; a conductor layer disposed on the semiconductor layer; and a source and drain a pole layer disposed on the conductor layer and the insulating layer, a conductor layer or a conductive spacer disposed between the source and drain layers and the semiconductor layer; and a passivation layer disposed on the insulating layer, the source/drain layer, and the semiconductor layer A conductor layer or a conductive spacer is provided between the source/drain layer and the semiconductor layer, thereby reducing the path of leakage, and has the effect of reducing leakage current.
  • FIG. 3 is a schematic flow chart of an embodiment of a method for fabricating a thin film transistor of the present invention.
  • the method of manufacturing the thin film transistor may include the following steps:
  • a substrate for manufacturing a thin film transistor which may be a glass substrate, is prepared.
  • S12 sequentially forming a gate layer and an insulating layer on the substrate, and the insulating layer covers the gate layer.
  • a metal layer is deposited on the glass substrate prepared in the above step S11 to form a gate layer.
  • the metal material forming the gate layer in this embodiment is molybdenum, of course, in other embodiments. It may also be other metal materials; and an insulating layer is disposed on the gate layer that has been disposed, wherein the insulating layer is overlaid on the gate layer, that is, the gate layer is formed between the substrate and the insulating layer,
  • the material of the insulating layer in the embodiment is silicon oxide, and in other embodiments, it may be silicon nitride or other material capable of achieving the purpose of insulation.
  • the glass substrate formed in this step is used in the following step S13.
  • the semiconductor layer and the conductor layer are continuously disposed on the glass substrate obtained in the above step S12. Specifically, a layer of amorphous silicon is deposited on the upper surface of the insulating layer, patterned by the process, and a layer is deposited.
  • the conductor material is crystallized by a process to form a semiconductor layer and a conductor layer, the semiconductor layer is formed on a side close to the insulating layer, and the conductor layer is formed on a side away from the insulating layer, that is, the insulating layer is in the semiconductor layer and the gate layer
  • the semiconductor layer is intermediate between the insulating layer and the conductor layer.
  • FIG. 4 is a schematic structural view of the substrate after step S13 in the method of manufacturing the thin film transistor shown in FIG. 4, a glass substrate 110, a gate layer 120, and an insulating layer 130 are formed.
  • the gate layer 120 is formed on the substrate 110
  • the insulating layer 130 covers the gate layer 120
  • the semiconductor layer 140 is formed on the insulating layer 130.
  • 150 is formed on the semiconductor layer 140.
  • S14 forming a source/drain layer on the conductor layer and the insulating layer, and providing a conductor layer or a conductive spacer between the source and drain layers and the semiconductor layer.
  • a conductor layer or a conductive spacer may be disposed between the source/drain layer and the semiconductor layer.
  • the conductor layer formed in step S13 covers the semiconductor layer, so that the source/drain layer and the semiconductor layer formed in this step S14 are separated by a conductor layer. interval.
  • a conductive spacer is provided on the insulating layer before this step S14. That is, the conductive spacer is disposed in the same layer as the semiconductor layer such that the source/drain layer and the semiconductor layer formed in this step S14 are separated by a conductive spacer.
  • S15 providing a passivation layer on the insulating layer, the source/drain layer, and the semiconductor layer.
  • step S14 Due to the occurrence of the conductor layer or the conductive spacer in step S14, two different shapes of thin film transistors are formed after step S15.
  • the conductor layer is patterned to form a channel, and the conductor layer is a two-separated island structure.
  • the passivation layer formed in this step S15 is formed on the semiconductor layer, that is, in the channel.
  • the thin film transistor of the embodiment includes preparing a substrate; sequentially forming a gate layer and an insulating layer on the substrate, the insulating layer covering the gate layer; sequentially forming a semiconductor layer and a conductor layer on the insulating layer; and providing a conductor layer at both ends of the semiconductor layer Or a conductive spacer, a source/drain layer is formed on the conductor layer and the insulating layer; a passivation layer is disposed on the insulating layer, the source/drain layer and the semiconductor layer, and the source and drain layers are not contacted by the conductive layer or the conductive spacer
  • the semiconductor layer can have the effect of reducing leakage current and improving the characteristics of the thin film transistor.
  • FIG. 5 is a schematic flow chart of a method for fabricating a thin film transistor according to still another embodiment of the present invention.
  • the method for manufacturing a thin film transistor may include the following steps.
  • S22 sequentially forming a gate layer and an insulating layer on the substrate, and the insulating layer covers the gate layer.
  • Steps S21-S22 are similar to steps S11-S12.
  • a gate layer and an insulating layer are provided on the glass substrate, specifically, PVD (Physical) is used on the glass substrate.
  • Vapor Deposition physical vapor deposition technique deposits a layer of metal and is patterned to form a gate layer.
  • the metal material forming the gate layer in this embodiment is molybdenum, although other metal materials may be used in other embodiments;
  • Reuse PECVD Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition method deposits an insulating material to form an insulating layer, and the insulating layer covers the gate layer, that is, the gate layer is formed between the glass substrate and the insulating layer, in this embodiment
  • the material of the insulating layer is silicon oxide, and in other embodiments it may be silicon nitride or other material capable of achieving the purpose of insulation.
  • S23 a semiconductor layer and a conductor layer are sequentially formed on the insulating layer, and a photoresist material is disposed on the conductor layer.
  • step S23 the semiconductor layer and the conductor layer are continuously provided on the glass substrate obtained in the above step S22, and specifically, the following steps are included.
  • amorphous silicon material is deposited on the insulating layer by PECVD, and then amorphous silicon is patterned by exposure etching to obtain an amorphous silicon layer.
  • a layer of conductor layer material is deposited on the patterned amorphous silicon by PECVD technology.
  • a small amount of diborane is added to the film forming gas in the PECVD technology.
  • the amount of diborane can be added according to the actual operation, such as 0.5 ml, 1
  • the milliliter, 5 ml, 10 ml, etc. may be used in the present embodiment in an amount of 10 ml, so that the deposited conductor material contains boron ions.
  • S233 The amorphous silicon layer is subjected to crystallization treatment to obtain a polycrystalline silicon layer as a semiconductor layer.
  • the lower layer can be crystallized, that is, amorphous silicon is formed into polycrystalline silicon.
  • the heating temperature and time can be set according to actual conditions.
  • the amorphous silicon is crystallized by heating at a temperature of 650 ° C for 15 min by a rapid heating technique. Since the upper surface contains more boron ions, the temperature and time of crystallization are lowered, so the crystal orientation is From the top down, a conductor material away from the insulating layer and a semiconductor layer close to the insulating layer are formed.
  • step S24 After the conductor material is patterned, the photoresist material on the conductor layer is not removed, and the process proceeds directly to step S24.
  • FIG. 6 is a schematic structural view of the substrate after step S232 in the method for fabricating the thin film transistor shown in FIG. 5, and FIG. 7 is a substrate after step S234 in the method for fabricating the thin film transistor shown in FIG. Schematic.
  • FIG. 6 shows a glass substrate 110, a gate layer 120, and an insulating layer 130.
  • the gate layer 120 is formed on the substrate 110, the insulating layer 130 covers the gate layer 120, and the amorphous silicon layer 140 is formed on the insulating layer 130.
  • Conductor layer material 150 is deposited on amorphous silicon layer 140.
  • a semiconductor layer 140 is formed on the insulating layer 130, a conductor layer 150 is formed on the semiconductor layer 140, and a photoresist material 190 is disposed on the conductor layer 150, and other reference numerals are the same as those described in FIG.
  • S24 Doping the semiconductor layer to provide a conductive spacer on the insulating layer and on the side of the semiconductor layer.
  • the ion implantation technique is used to implant a certain amount of boron ions into the semiconductor layer, and the implantation dose of boron ions can be set according to actual needs, for example, implanting 0.1 ml, 0.5. In the present embodiment, the implantation dose of boron ions is 1 ml.
  • the activation treatment is performed by a rapid heating technique, and the heating temperature is 550 ° C to 590 ° C.
  • the heating time is 1 to 2 minutes, wherein the heating temperature and the heating time can be set according to actual conditions, for example, the heating temperature can be 550 ° C, 560 ° C, 570 ° C, 580 ° C, 590 ° C, and the heating time can be 1 minute. 1 minute 15 seconds, 1 minute 30 seconds, 1 minute 45 seconds, 2 minutes.
  • the heating temperature is 550 ° C
  • the heating time is 2 minutes, at which time the conductor layer material is also formed on the sidewall of the semiconductor layer. , that is, the conductive spacer.
  • the photoresist material is removed.
  • a metal material superposed by three layers of molybdenum, aluminum and molybdenum is deposited on the conductor layer by physical vapor deposition technique, and patterned to form a source and drain layer, and the source and drain layers are disposed on the conductor layer and the insulating layer.
  • the source/drain layer is blocked by the conductive spacer and is not in contact with the semiconductor layer.
  • FIG. 8 is a schematic structural view of the substrate after step S25 in the method of manufacturing the thin film transistor shown in FIG. 5.
  • the conductive spacers 160 are disposed on the sidewalls of the semiconductor layer 140, and are also disposed between the conductor layer 150 and the insulating layer 130, and other reference portions are the same as those described in FIG.
  • S27 providing a passivation layer on the insulating layer, the source/drain layer, and the semiconductor layer.
  • the conductive layer is processed to form a channel, the conductor layer on the upper surface of the channel is removed, and the semiconductor layer in the lower portion of the channel is left.
  • a passivation layer is further provided to protect The channel, specifically, the formed source/drain layer is a metal electrode, which is used as a mask to etch the conductor layer to form a channel, and the conductor layer on the upper surface of the channel is removed, leaving the lower portion Channel semiconductor layer, thereby obtaining a thin film transistor.
  • a passivation material is deposited by PECVD, patterned to form a passivation layer, and the passivation material may be silicon oxide or other materials.
  • the passivation material is oxidized. silicon.
  • the passivation layer is disposed on the insulating layer, the source and drain layers, and the semiconductor layer to complete the fabrication of the thin film transistor.
  • the resulting thin film transistor can be referred to the case shown in FIG.
  • FIG. 9 is a schematic flow chart of a method for fabricating a thin film transistor according to still another embodiment of the present invention.
  • the method for manufacturing a thin film transistor may include the following steps.
  • S32 sequentially forming a gate layer and an insulating layer on the substrate, and the insulating layer covers the gate layer.
  • S34 forming a source/drain layer on the conductor layer and the insulating layer, wherein a conductor layer is disposed between the source and drain layers and the semiconductor layer.
  • S35 providing a passivation layer on the insulating layer, the source/drain layer, and the semiconductor layer.
  • step S33 in this embodiment specifically includes the following steps.
  • S331 forming an amorphous silicon layer on the insulating layer.
  • S332 depositing a conductor material on the amorphous silicon layer.
  • S333 The amorphous silicon layer is subjected to crystallization treatment to obtain a polycrystalline silicon layer as a semiconductor layer.
  • FIG. 10 is a schematic diagram of mask etching in step S334 of the method for manufacturing the thin film transistor shown in FIG.
  • the reticle In the process of etching by the reticle, the reticle is large in size, and in the process of patterning the conductor material, the region of the conductor layer is defined by the reticle, so that the pattern of the conductor layer is slightly larger than the pattern of the semiconductor layer, that is, The conductor layer is overlaid on the semiconductor layer, and the conductor layer is also disposed over the insulating layer.
  • step S34 a metal material superposed by three layers of molybdenum, aluminum, and molybdenum is deposited on the conductor layer by physical vapor deposition, and the pattern is processed to form a source and drain layer, and the source and drain layers are disposed at On the conductor layer and the insulating layer, since the semiconductor layer is covered by the conductor layer, the source/drain layer is blocked by the conductor layer and is not in contact with the semiconductor layer.
  • step S35 after the source and drain layers are formed, the conductive layer is processed to form a channel, the conductor layer on the upper surface of the channel is removed, and the semiconductor layer in the lower portion of the channel is left.
  • a blunt layer is continuously formed.
  • the layer is formed to protect the channel.
  • the source and drain layers are formed as metal electrodes, and the photo-mask is used as a mask to etch the conductor layer to form a channel, and the conductor layer on the upper surface of the channel is removed.
  • the lower channel semiconductor layer is left to obtain a thin film transistor.
  • a passivation material is deposited by PECVD, patterned to form a passivation layer, and the passivation material may be silicon oxide or other materials, which is blunt in this embodiment.
  • the material is silicon oxide.
  • the passivation layer is disposed on the insulating layer, the source and drain layers, and the semiconductor layer to complete the fabrication of the thin film transistor.
  • the resulting thin film transistor can be referred to the case shown in FIG. 2.
  • the thin film transistor of the embodiment includes preparing a substrate; sequentially forming a gate layer and an insulating layer on the substrate, the insulating layer covering the gate layer; sequentially forming a semiconductor layer and a conductor layer on the insulating layer; and providing a conductor layer at both ends of the semiconductor layer Or a conductive spacer, a source/drain layer is formed on the conductor layer and the insulating layer; a passivation layer is disposed on the insulating layer, the source/drain layer, and the semiconductor layer, and a conductive layer or a conductive layer is formed between the source and drain layers and the semiconductor layer
  • the spacer is blocked to prevent direct contact between the source and drain layers and the semiconductor layer, and the effect of reducing leakage current can be improved to improve the characteristics of the thin film transistor.
  • FIG. 11 is a schematic structural view of an embodiment of a liquid crystal display panel of the present invention.
  • the liquid crystal display panel 200 of the present embodiment includes a thin film transistor 21 similar to the above-described thin film transistor 100, and details are not described herein.
  • the thin film transistor 21 constitutes a layer, and in order to realize display, the liquid crystal display panel 200 further includes a liquid crystal layer 22.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Nonlinear Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种薄膜晶体管、薄膜晶体管的制造方法及液晶显示面板，其中薄膜晶体管（100）包括：基板（110）；栅极层（120），设置在基板上；绝缘层（130），覆盖于栅极层；半导体层（140），设置在绝缘层上；导体层（150），设置在半导体层上；源漏极层（170），设置在导体层和绝缘层上，在源漏极层和半导体层之间设置有导体层或者导电间隔部（160）；钝化层（180），设置在绝缘层、源漏极层和半导体层上。该薄膜晶体管中漏电流较小，薄膜晶体管质量较高。

Description

薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板
【技术领域】
本发明涉及显示技术领域，特别是涉及一种薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板。
【背景技术】
薄膜晶体管(Thin Film Transistor，简称TFT)广泛应用于液晶显示装置(Liquid Crystal Display，简称LCD)和有源矩阵驱动式有机电致发光显示装置(Active Matrix Organic Light-Emitting Diode，简称AMOLED)中，因此，薄膜晶体管影响到显示行业的发展。然而当前薄膜晶体管的制造方法中，形成的薄膜晶体管存在漏电流过大的问题，导致薄膜晶体管的特性受到影响。
【发明内容】
本发明实施例提供一种薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板，以解决薄膜晶体管存在漏电流过大的问题。
为解决上述技术问题，本发明实施例采用的一个技术方案是：提供一种薄膜晶体管，该薄膜晶体管包括基板；栅极层，设置在基板上；绝缘层，覆盖于栅极层；半导体层，设置在绝缘层上；导体层，设置在半导体层上；源漏极层，设置在导体层和绝缘层上，在源漏极层和半导体层之间设置有导体层或者导电间隔部；钝化层，设置在绝缘层、源漏极层和半导体层上。
为解决上述技术问题，本发明实施例采用的另一个技术方案是：提供一种薄膜晶体管的制造方法，该制造方法包括基板；在基板上依次形成栅极层及绝缘层，绝缘层覆盖于栅极层；在绝缘层上依次形成半导体层和导体层；在导体层和绝缘层上形成源漏极层，其中源漏极层和半导体层之间设置有导体层或者导电间隔部；若源漏极层和半导体层之间设置有导电间隔部，则在形成源漏极层之前，在绝缘层上设置导电间隔部；在绝缘层、源漏极层和半导体层上设置钝化层。
为解决上述技术问题，本发明实施例采用的又一个技术方案是：提供一种液晶显示面板，该液晶显示面板包括薄膜晶体管，薄膜晶体管包括基板；栅极层，设置在基板上；绝缘层，覆盖于栅极层；半导体层，设置在绝缘层上；导体层，设置在半导体层上；半导体层具有一沟道区，沟道区将半导体层分为左右部分，导体层形成于半导体层的左右部分上，以形成两岛体结构；源漏极层，设置在导体层和绝缘层上，在源漏极层和半导体层之间设置有导体层或者导电间隔部；钝化层，设置在绝缘层、源漏极层和半导体层上；栅极层和源漏极层为金属材料；绝缘层、绝缘间隔层以及钝化层均为绝缘材料。
本发明在基板上依次形成栅极层及绝缘层，绝缘层覆盖于栅极层；在绝缘层上依次形成半导体层和导体层；在导体层和绝缘层上形成源漏极层，其中源漏极层和半导体层之间设置有导体层或者导电间隔部；若源漏极层和半导体层之间设置有导电间隔部，则在形成源漏极层之前，在绝缘层上设置导电间隔部；在绝缘层、源漏极层和半导体层上设置钝化层，通过在源漏极层和半导体层之间设置导体层或者导电间隔部，能够阻止源漏极层和半导体层的直接接触，从而有可以减小漏电流的效果，改善薄膜晶体管的特性。
【附图说明】
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明薄膜晶体管一实施例的结构示意图；
图2是本发明薄膜晶体管另一实施例的结构示意图；
图3是本发明薄膜晶体管的制造方法一实施例的流程示意图；
图4是图3所示薄膜晶体管的制造方法中步骤S13之后基板的结构示意图；
图5是本发明薄膜晶体管的制造方法另一实施例的流程示意图；
图6是图5所示薄膜晶体管的制造方法中步骤S232后基板的结构示意图；
图7是图5所示薄膜晶体管的制造方法中步骤S234后基板的结构示意图；
图8是图5所示薄膜晶体管的制造方法中步骤S25后基板的结构示意图；
图9是本发明薄膜晶体管的制造方法又一实施例的流程示意图；
图10是图9所示薄膜晶体管的制造方法步骤S334中光罩蚀刻的示意图；
图11是本发明液晶显示面板一实施例的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本发明的一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本发明的描述中，“多个”的含义是至少两个，例如两个，三个等，除非另有明确具体的限定。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本发明的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
请参阅图1和图2，图1是本发明薄膜晶体管一实施例的结构示意图，图2是本发明薄膜晶体管另一实施例的结构示意图。
在图1和图2两实施例中，薄膜晶体管的区别仅仅在于导体层形状的不同以及是否存在导电间隔部，因此图1和图2的两实施例均采用相同标号。
薄膜晶体管100包括基板110、栅极层120、绝缘层130、半导体层140、导体层150、源漏极层170以及钝化层180，在一实施例中还包括导电间隔部160。
薄膜晶体管100为层叠结构，上述各层依次形成在基板110上，基板110可以为玻璃基板。其中，栅极层120形成于基板110上，绝缘层130覆盖于栅极层120，本实施例中薄膜晶体管100为底栅结构。
半导体层140作为薄膜晶体管100的有源层，形成于绝缘层130上；导体层150形成于半导体层140上，用于连接半导体层140和源漏极层170，源漏极层170之间通过导体层150后经由半导体层140形成电流，相较于源漏极层170直接连接半导体层140，本实施例中导体层150电阻较小，能够减少源漏极层170与半导体层140之间的漏电流情况。
在本实施例中的绝缘层130上还形成有导体层150或导电间隔部160，即导体层150或导电间隔部160与半导体层140同层设置；源漏极层170则形成在导体层150和导电间隔部160上；导电间隔部160位于半导体层140和源漏极层170之间。
在实施例中半导体层140和源漏极层170之间设置有导体层150或导电间隔部160，即半导体层140与源漏极层170之间没有直接接触连接，因而能够有效减少半导体层140与源漏极层170之间的漏电流。
半导体层140具有一沟道区141，沟道区141将半导体层140分为左右部分，导体层150形成在半导体层140的左右部分上，形成两岛体结构。形成在导体层150两岛体结构上的源漏极层170也被区分为源极和漏极。
钝化层180形成于源漏极层170和半导体层140上，具体形成于半导体140的沟道区141上，且形成于导体层150的两岛体结构之间。
对于上述结构的薄膜晶体管100，其中绝缘层130以及钝化层180均为绝缘材料构，可以为氧化硅或氮化硅。栅极层120和源漏极层170则为金属材料，可以为钼、铝的等金属材料，还可为钼-铝-钼三层组合的金属材料。半导体层140可以为多晶硅，导体层150和导电间隔部160则可以为掺杂B离子的多晶硅所形成的P+导体层。
此外，本实施例中半导体层140和源漏极层170之间可设置导体层150或导电间隔部160，例如图1和图2所示的两种方式。
图1中，导电间隔部160形成在半导体层140的侧面，以使源漏极层170和半导体层140之间设置该导电间隔部160。图2中，导体层150则覆盖半导体层140，以使源漏极层170和半导体层140之间设置该导体层150，还形成于半导体层140侧面，位于绝缘层130上。
上述实施例中导电间隔部或导体层位于源漏极层和半导体层之间，能够阻隔源漏极层和半导体层的直接接触，减少漏电流的问题，从而提高薄膜晶体管的性能。
本实施例薄膜晶体管包括该薄膜晶体管包括基板；栅极层，设置在基板上；绝缘层，覆盖于栅极层；半导体层，设置在绝缘层上；导体层，设置在半导体层上；源漏极层，设置在导体层和绝缘层上，在源漏极层和半导体层之间设置有导体层或者导电间隔部；钝化层，设置在绝缘层、源漏极层和半导体层上，通过在源漏极层和半导体层之间设置导体层或者导电间隔部，从而减少漏电的路径，有减小漏电流的效果。
为制得上述薄膜晶体管，本发明还提出一种薄膜晶体管的制造方法，请参阅图3，图3是本发明薄膜晶体管的制造方法一实施例的流程示意图。在本实施例中，薄膜晶体管的制造方法可以包括以下步骤：
S11：准备基板。
准备制造薄膜晶体管的基板，该基板可以是玻璃基板。
S12：在基板上依次形成栅极层及绝缘层，绝缘层覆盖于栅极层。
在本步骤S12中，在上述步骤S11中准备的玻璃基板上沉积一层金属使之图形化形成栅极层，在本实施例中形成栅极层的金属材料是钼，当然在其他实施例中也可以是其他的金属材料；再在已经设置完成的栅极层上设置一层绝缘层，其中绝缘层是覆盖在栅极层上的，即栅极层形成在基板和绝缘层中间，在本实施例中绝缘层的材料是氧化硅，在其他实施例中也可以是氮化硅或其他能够达到绝缘目的的材料，在本步骤中形成的玻璃基板用于下述步骤S13中使用。
S13：在绝缘层上依次形成半导体层和导体层。
在本步骤S13中，在上述步骤S12中得到的玻璃基板上继续设置半导体层和导体层，具体来说，在绝缘层上表面沉积一层非晶硅，通过工艺使其图案化，沉积一层导体材料，通过工艺使其结晶，从而形成半导体层和导体层，半导体层形成于靠近绝缘层的一侧，导体层形成于远离绝缘层的一侧，即绝缘层在半导体层和栅极层之间，半导体层在绝缘层和导体层中间。
可结合图4理解上述步骤，图4是图3所示薄膜晶体管的制造方法中步骤S13之后基板的结构示意图。图4中示出玻璃基板110、栅极层120及绝缘层130，栅极层120形成于基板110上，绝缘层130覆盖于栅极层120，半导体层140形成于绝缘层130上，导体层150形成于半导体层140上。
S14：在导体层和绝缘层上形成源漏极层，源漏极层和半导体层之间设置有导体层或导电间隔部。
在本步骤S14中，源漏极层和半导体层之间可能设置有导体层或导电间隔部。
对于源漏极层和半导体层之间设置导体层的情况，即步骤S13中所形成的导体层覆盖于半导体层，使得本步骤S14中所形成的源漏极层与半导体层之间由导体层间隔。
对于源漏极层和半导体层之间设置导电间隔部的情况，在本步骤S14之前，会在绝缘层上设置导电间隔部。即该导电间隔部与半导体层同层设置，使得本步骤S14中形成的源漏极层与半导体层之间由导电间隔部间隔。
S15：在绝缘层、源漏极层和半导体层上设置钝化层。
由于步骤S14中出现导体层或者导电间隔部两种情况，导致步骤S15后形成两种不同形状的薄膜晶体管，对于两种不同形状的薄膜晶体管，可参阅图1和图2，图1即对应导电间隔部的情况，图2对应导体层的情况。
在步骤S14中形成源漏极层后，对导体层进行图案处理，形成沟道，导体层为两分离岛体结构。在本步骤S15中所形成的钝化层会形成于半导体层上，即位于沟道中。
本实施例薄膜晶体管包括准备基板；在基板上依次形成栅极层及绝缘层，绝缘层覆盖于栅极层；在绝缘层上依次形成半导体层和导体层；：在半导体层两端设置导体层或者导电间隔部，在导体层和绝缘层上形成源漏极层；在绝缘层、源漏极层和半导体层上设置钝化层，由于源漏极层被导体层或导电间隔部阻挡不能接触半导体层，可以有减小漏电流的效果，改善薄膜晶体管的特性。
请参阅图5，图5是本发明又一实施例薄膜晶体管的制造方法的流程示意图，在本实施例中，薄膜晶体管的制造方法可以包括以下步骤。
S21：准备基板。
S22：在基板上依次形成栅极层及绝缘层，绝缘层覆盖于栅极层。
步骤S21-S22与步骤S11-S12类似。此外，本步骤S22中在玻璃基板上设置栅极层和绝缘层，具体来说，在玻璃基板上利用PVD（Physical Vapor Deposition，物理气相沉积）技术沉积一层金属，并且图形化以形成栅极层，在本实施例中形成栅极层的金属材料是钼，当然在其他实施例中也可以是其他金属材料；接着再利用PECVD（Plasma Enhanced Chemical Vapor Deposition，等离子体增强化学的气相沉积法）技术沉积一层绝缘物质形成绝缘层，绝缘层是覆盖在栅极层上的，即栅极层形成在玻璃基板和绝缘层中间，在本实施例中绝缘层的材料是氧化硅，在其他实施例中也可以是氮化硅或其他能够达到绝缘目的的材料。
S23：在绝缘层上依次形成半导体层和导体层，导体层上设置有光阻材料。
本步骤S23中，在上述步骤S22中得到的玻璃基板上继续设置半导体层和导体层，具体来说，包括以下步骤。
S231：在绝缘层上形成非晶硅层。
在绝缘层上利用PECVD技术沉积一层非晶硅材料，然后通过曝光刻蚀使非晶硅图形化，得到非晶硅层。
S232：在非晶硅层上沉积导体材料。
在已经图形化的非晶硅上利用PECVD技术沉积一层导体层材料，PECVD技术中的成膜气体里加入少量的乙硼烷，乙硼烷的用量可以根据实际操作添加，如0.5毫升，1毫升，5毫升，10毫升等，在本实施例中用量可以是10毫升，因此沉积的导体材料中包含硼离子。
S233：对非晶硅层进行结晶处理，得到作为半导体层的多晶硅层。
利用快速加热技术在650℃（±50℃）的温度下加热15min（±1min）就可以结晶使下层形成半导体层，即非晶硅形成为多晶硅，加热的温度和时间可以根据实际情况进行设定，在本实施例中，利用快速加热技术在650℃的温度下加热15min使非晶硅进行结晶，由于上表面中含有较多的硼离子，结晶的温度和时间会被降低，所以结晶方向是从上向下进行的，形成远离绝缘层的导体材料和接近绝缘层的半导体层。
S234：对导体材料进行图案化处理，得到导体层。
在对导体材料图案化处理后，不去除导体层上的光阻材料，直接进入步骤S24。
可结合图6和图7理解上述步骤，图6是图5所示薄膜晶体管的制造方法中步骤S232后基板的结构示意图，图7是图5所示薄膜晶体管的制造方法中步骤S234后基板的结构示意图。
图6中示出玻璃基板110、栅极层120及绝缘层130，栅极层120形成于基板110上，绝缘层130覆盖于栅极层120，非晶硅层140形成于绝缘层130上，导体层材料150沉积于非晶硅层140上。
图7中示出半导体层140形成于绝缘层130上，导体层150形成于半导体层140上，光阻材料190设置于导体层150上，其他标号部分与图6中描述相同。
S24：对半导体层进行掺杂处理，以在绝缘层上及半导体层的侧面设置导电间隔部。
利用离子注入技术对半导体层植入一定量的硼离子，硼离子的植入剂量可以根据实际需求进行设定，例如植入0.1毫升、0.5 毫升、1毫升、3毫升等等，本实施例中硼离子的植入剂量为1毫升，除去导体层上的光阻材料后，利用快速加热技术进行活化处理，加热温度为550℃~590℃，加热时间为1~2分钟，其中加热温度和加热时间可根据实际情况进行设定，例如加热温度可以是550℃、560℃、570℃、580℃、590℃，加热时间可以是1分钟、1分15秒、1分30秒、1分45秒、2分钟，在本实施例中，加热温度为550℃，加热时间为2分钟，此时会在半导体层的侧壁也形成导体层材料，即导电间隔部。
S25：去除光阻材料。
形成导电间隔部后，去除光阻材料。
S26：在导体层和绝缘层上形成源漏极层。
利用物理气相沉积技术在导体层上沉积一层由钼、铝、钼三层叠加的金属材料，将近其图案化处理以形成源漏极层，此时源漏极层设置于导体层和绝缘层上，由于半导体层侧壁有导电间隔部，所以源漏极层被导电间隔部阻挡，不与半导体层接触。
可结合图8理解上述步骤，图8是图5所示薄膜晶体管的制造方法中步骤S25后基板的结构示意图。
图8中示出，导电间隔部160设置于半导体层140的侧壁，还设置于导体层150与绝缘层130之间，其他标号部分与图7中描述相同。
S27：在绝缘层、源漏极层和半导体层上设置钝化层。
形成源漏极层之后，对导电层进行处理，从而形成沟道，去掉沟道上表面的导体层，留下沟道下部的半导体层，形成沟道之后，会继续设置一层钝化层来保护沟道，具体来说，以形成的源漏极层为金属电极，将其做为光罩进行对导体层进行刻蚀以形成沟道，将沟道上表面的导体层去除掉，留下下部的沟道半导体层，从而得到薄膜晶体管，此时再利用PECVD沉积一层钝化材料，图案化以形成钝化层，钝化材料可以是氧化硅或其他材料，本实施例中钝化材料为氧化硅。钝化层设置在绝缘层、源漏极层和半导体层上，完成薄膜晶体管的制作。最终得到的薄膜晶体管即可参考图1所示的情况。
请参阅图9，图9是本发明又一实施例薄膜晶体管的制造方法的流程示意图，在本实施例中，薄膜晶体管的制造方法可以包括以下步骤。
S31：准备基板。
S32：在基板上依次形成栅极层及绝缘层，绝缘层覆盖于栅极层。
S33：在绝缘层上依次形成半导体层和导体层。
S34：在导体层和绝缘层上形成源漏极层，其中源漏极层和半导体层之间设置有导体层。
S35：在绝缘层、源漏极层和半导体层上设置钝化层。
本实施例中的上述步骤S31-S35与上述实施例的相应步骤类似，相同部分不再赘述。
不同之处在于，本实施例步骤S33中，具体包括以下步骤。
S331：在绝缘层上形成非晶硅层。
S332：在非晶硅层上沉积导体材料。
S333：对非晶硅层进行结晶处理，得到作为半导体层的多晶硅层。
S334：对导体材料进行图案化处理，得到导体层。
其中，在步骤S334对导体材料进行图案化处理时，得到覆盖半导体层的导体层，具体结合图10进行理解，图10是图9所示薄膜晶体管的制造方法步骤S334中光罩蚀刻的示意图。在利用光罩进行蚀刻的过程中，光罩尺寸较大，在对导体材料进行图案化过程中，通过光罩来定义导体层区域，使导体层的图形比半导体层的图形稍大一点，即导体层覆盖在半导体层上，导体层还设置在绝缘层之上。
在步骤S34中，利用物理气相沉积技术在导体层上沉积一层由钼、铝、钼三层叠加的金属材料，将近其图案化处理以形成源漏极层，此时源漏极层设置于导体层和绝缘层上，由于半导体层被导体层覆盖，所以源漏极层被导体层阻挡，不与半导体层接触。
步骤S35中，形成源漏极层之后，对导电层进行处理，从而形成沟道，去掉沟道上表面的导体层，留下沟道下部的半导体层，形成沟道之后，会继续设置一层钝化层来保护沟道，具体来说，以形成的源漏极层为金属电极，将其做为光罩进行对导体层进行刻蚀以形成沟道，将沟道上表面的导体层去除掉，留下下部的沟道半导体层，从而得到薄膜晶体管，此时再利用PECVD沉积一层钝化材料，图案化以形成钝化层，钝化材料可以是氧化硅或其他材料，本实施例中钝化材料为氧化硅。钝化层设置在绝缘层、源漏极层和半导体层上，完成薄膜晶体管的制作。最终得到的薄膜晶体管即可参考图2所示的情况。
本实施例薄膜晶体管包括准备基板；在基板上依次形成栅极层及绝缘层，绝缘层覆盖于栅极层；在绝缘层上依次形成半导体层和导体层；：在半导体层两端设置导体层或者导电间隔部，在导体层和绝缘层上形成源漏极层；在绝缘层、源漏极层和半导体层上设置钝化层，由于源漏极层与半导体层之间有导体层或导电间隔部阻挡，从而阻止源漏极层与半导体层直接接触，可以有减小漏电流的效果，改善薄膜晶体管的特性。
请参阅图11，图11是本发明液晶显示面板一实施例的结构示意图。本实施例液晶显示面板200包括薄膜晶体管21，薄膜晶体管21与上述薄膜晶体管100类似，具体不再赘述。
此外，薄膜晶体管21构成一层，为实现显示，液晶显示面板200中还包括液晶层22。
本实施例中，液晶显示面板中薄膜晶体管源漏极层和半导体层之间没有直接接触，减少了二者之间漏电流的问题，从而提高薄膜晶体管的性能，继而提高液晶显示面板的显示性能。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种液晶显示面板，所述液晶显示面板包括薄膜晶体管，其中，所述薄膜晶体管包括：
    基板；
    栅极层，设置在所述基板上；
    绝缘层，覆盖于所述栅极层；
    半导体层，设置在所述绝缘层上；
    导体层，设置在所述半导体层上；
    所述半导体层具有一沟道区，所述沟道区将所述半导体层分为左右部分，所述导体层形成于所述半导体层的左右部分上，以形成两岛体结构；
    源漏极层，设置在所述导体层和所述绝缘层上，在所述源漏极层和所述半导体层之间设置有所述导体层或者导电间隔部；
    钝化层，设置在所述绝缘层、源漏极层和所述半导体层上；
    所述栅极层和所述源漏极层为金属材料；
    所述绝缘层、所述绝缘间隔层以及所述钝化层均为绝缘材料。
  2. 根据权利要求1所述的液晶显示面板，其中，所述导体层覆盖所述半导体层，以使所述源漏极层和所述半导体层之间设置有所述导体层。
  3. 根据权利要求1所述的液晶显示面板，其中，在所述半导体层的侧面设置所述导电间隔部，以使所述源漏极层和所述半导体层之间设置有所述导电间隔部。
  4. 根据权利要求3所述的液晶显示面板，其中，所述导电间隔部的材料与所述导体层的材料相同。
  5. 根据权利要求1所述的液晶显示面板，其中，所述半导体层包括多晶硅层，所述导体层包括P型导体层或N型导体层，所述源漏极层包括钼、铝、钼三层金属依次叠加的组合层。
  6. 一种薄膜晶体管，其中，所述薄膜晶体管包括：
    基板；
    栅极层，设置在所述基板上；
    绝缘层，覆盖于所述栅极层；
    半导体层，设置在所述绝缘层上；
    导体层，设置在所述半导体层上；
    源漏极层，设置在所述导体层和所述绝缘层上，在所述源漏极层和所述半导体层之间设置有所述导体层或者导电间隔部；
    钝化层，设置在所述绝缘层、源漏极层和所述半导体层上。
  7. 根据权利要求6所述的薄膜晶体管，其中，所述导体层覆盖所述半导体层，以使所述源漏极层和所述半导体层之间设置有所述导体层。
  8. 根据权利要求6所述的薄膜晶体管，其中，在所述半导体层的侧面设置所述导电间隔部，以使所述源漏极层和所述半导体层之间设置有所述导电间隔部。
  9. 根据权利要求8所述的薄膜晶体管，其中，所述导电间隔部的材料与所述导体层的材料相同。
  10. 根据权利要求6所述的薄膜晶体管，其中，所述半导体层包括多晶硅层，所述导体层包括P型导体层或N型导体层，所述源漏极层包括钼、铝、钼三层金属依次叠加的组合层。
  11. 一种薄膜晶体管的制造方法，其中，所述制造方法包括：
    基板；
    在所述基板上依次形成栅极层及绝缘层，所述绝缘层覆盖于所述栅极层；
    在所述绝缘层上依次形成半导体层和导体层；
    在所述导体层和所述绝缘层上形成源漏极层，其中所述源漏极层和所述半导体层之间设置有所述导体层或者导电间隔部；
    若所述源漏极层和所述半导体层之间设置有所述导电间隔部，则在形成源漏极层之前，在所述绝缘层上设置所述导电间隔部；
    在所述绝缘层、源漏极层和所述半导体层上设置钝化层。
  12. 根据权利要求11所述的制造方法，其中，所述制造方法进一步包括：
    在所述绝缘层上依次形成半导体层和导体层，所述导体层上设置有光阻材料；
    对所述半导体层进行掺杂处理，以在所述绝缘层上及所述半导体层的侧面设置所述导电间隔部；
    在所述导体层和所述绝缘层上形成源漏极层，其中所述源漏极层和所述半导体层之间设置有所述导电间隔部。
  13. 根据权利要求11所述的制造方法，其中，所述在所述绝缘层上依次形成半导体层和导体层包括：
    在所述绝缘层上形成半导体层和导体材料；
    对所述导体材料进行图案化处理，得到覆盖所述半导体层的导体层；
    在所述导体层和所述绝缘层上形成源漏极层，其中所述源漏极层和所述半导体层之间设置有所述导体层。
  14. 根据权利要求12所述的制造方法，其中，所述在所述绝缘层上依次形成半导体层和导体层包括：
    在所述绝缘层上形成非晶硅层；
    在所述非晶硅层上沉积导体材料；
    对所述非晶硅层进行结晶处理，得到作为所述半导体层的多晶硅层；
    对所述导体材料进行图案化处理，得到导体层。
  15. 根据权利要求13所述的制造方法，其中，所述在所述绝缘层上依次形成半导体层和导体层包括：
    在所述绝缘层上形成非晶硅层；
    在所述非晶硅层上沉积导体材料；
    对所述非晶硅层进行结晶处理，得到作为所述半导体层的多晶硅层；
    对所述导体材料进行图案化处理，得到导体层。
PCT/CN2017/106975 2017-08-07 2017-10-20 薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板 WO2019029009A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/737,305 US10510899B2 (en) 2017-08-07 2017-10-20 Thin film transistor, thin film transistor manufacturing method and liquid crystal display panel

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710669995.4A CN107369718A (zh) 2017-08-07 2017-08-07 薄膜晶体管及其制造方法、液晶显示面板
CN201710669995.4 2017-08-07

Publications (1)

Publication Number Publication Date
WO2019029009A1 true WO2019029009A1 (zh) 2019-02-14

Family

ID=60309050

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/106975 WO2019029009A1 (zh) 2017-08-07 2017-10-20 薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板

Country Status (2)

Country Link
CN (1) CN107369718A (zh)
WO (1) WO2019029009A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110581177A (zh) * 2019-08-13 2019-12-17 武汉华星光电半导体显示技术有限公司 阵列基板及其制备方法
CN113113475B (zh) * 2021-04-08 2023-06-02 合肥京东方显示技术有限公司 薄膜晶体管及制备方法、阵列基板及制备方法、显示装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101320181A (zh) * 2007-06-05 2008-12-10 株式会社日立显示器 显示装置及其制造方法
CN101339923A (zh) * 2007-10-17 2009-01-07 友达光电股份有限公司 形成薄膜晶体管阵列面板的方法及薄膜晶体管阵列面板
CN101409308A (zh) * 2007-10-10 2009-04-15 中华映管股份有限公司 薄膜晶体管、像素结构及其制造方法
CN101800248A (zh) * 2009-02-09 2010-08-11 索尼公司 薄膜晶体管和显示器件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101320181A (zh) * 2007-06-05 2008-12-10 株式会社日立显示器 显示装置及其制造方法
CN101409308A (zh) * 2007-10-10 2009-04-15 中华映管股份有限公司 薄膜晶体管、像素结构及其制造方法
CN101339923A (zh) * 2007-10-17 2009-01-07 友达光电股份有限公司 形成薄膜晶体管阵列面板的方法及薄膜晶体管阵列面板
CN101800248A (zh) * 2009-02-09 2010-08-11 索尼公司 薄膜晶体管和显示器件

Also Published As

Publication number Publication date
CN107369718A (zh) 2017-11-21

Similar Documents

Publication Publication Date Title
WO2012097564A1 (zh) 一种自对准薄膜晶体管的制作方法
WO2016119280A1 (zh) 氧化物薄膜晶体管及其制作方法
WO2017054191A1 (zh) 一种tft阵列基板及其制作方法
WO2017054250A1 (zh) 一种tft阵列基板及其制作方法
WO2019000493A1 (zh) 薄膜晶体管阵列基板及其制备方法、oled显示装置
WO2017035851A1 (zh) Tft、阵列基板及tft的制备方法
WO2012097563A1 (zh) 一种薄膜晶体管的制作方法
WO2018176566A1 (zh) 一种阵列基板的制作方法及阵列基板
WO2017054258A1 (zh) Tft阵列基板的制备方法、tft阵列基板及显示装置
WO2017219432A1 (zh) 一种薄膜晶体管阵列基板及液晶面板
WO2018120309A1 (zh) Oled显示装置的阵列基板及其制作方法
WO2020134965A1 (zh) 阵列基板的制造方法、装置及阵列基板
WO2017054259A1 (zh) 液晶显示面板、阵列基板及其制造方法
WO2019029008A1 (zh) 薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板
WO2019000651A1 (zh) 一种柔性背板的制作方法、液晶显示面板以及oled显示面板
WO2012092752A1 (zh) 一种finfet晶体管的制作方法
WO2019024195A1 (zh) 一种低温多晶硅阵列基板的制程方法以及低温多晶硅薄膜晶体管的制程方法
WO2018107554A1 (zh) Oled显示面板以及oled显示装置
WO2017024573A1 (zh) 一种阵列基板及其制作方法
WO2017067062A1 (zh) 一种双栅极薄膜晶体管及其制作方法、以及阵列基板
WO2020135052A1 (zh) 阵列基板结构的制备方法、阵列基板及显示面板
WO2017140015A1 (zh) 双栅极tft阵列基板及制作方法
WO2019029009A1 (zh) 薄膜晶体管及薄膜晶体管的制造方法、液晶显示面板
WO2016090690A1 (zh) 一种ltps像素单元及其制造方法
WO2017206269A1 (zh) 阵列基板及其制备方法

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17921025

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17921025

Country of ref document: EP

Kind code of ref document: A1