WO2017219432A1 - 一种薄膜晶体管阵列基板及液晶面板 - Google Patents

一种薄膜晶体管阵列基板及液晶面板 Download PDF

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Publication number
WO2017219432A1
WO2017219432A1 PCT/CN2016/090886 CN2016090886W WO2017219432A1 WO 2017219432 A1 WO2017219432 A1 WO 2017219432A1 CN 2016090886 W CN2016090886 W CN 2016090886W WO 2017219432 A1 WO2017219432 A1 WO 2017219432A1
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Prior art keywords
layer
gate
film transistor
thin film
drain
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PCT/CN2016/090886
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English (en)
French (fr)
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梁博
王选芸
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武汉华星光电技术有限公司
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Priority to US15/118,870 priority Critical patent/US10170503B2/en
Publication of WO2017219432A1 publication Critical patent/WO2017219432A1/zh

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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
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    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a thin film transistor array substrate and a liquid crystal panel.
  • Organic light-emitting diode (organic light-emitting diode, OLED) display is an emerging flat panel display with self-illumination, high contrast, thin thickness, wide viewing angle, fast response, and excellent characteristics for flexible display panels, so it has a very good development prospect.
  • OLED as a self-luminous display
  • LTPS low temperature polysilicon
  • the semiconductor layers of the PMOS region and the NMOS region in the CMOS circuit are separately fabricated to drive the OELD display.
  • LTPS technology is due to polysilicon (poly The carrier mobility of Si) is large, resulting in a large off-state current (Ioff), resulting in easy formation of afterimages (image) Sticking).
  • the larger off-state current requires a smaller W/L value, so the gate length value (L value) is larger in the thin film transistor (TFT) design, and the gate width value (W value) is smaller. More, causing an increase in the TFT area of the active region (AA region), resulting in a decrease in aperture ratio.
  • the technical problem to be solved by the present invention is to provide a thin film transistor array substrate and a liquid crystal panel, which can manufacture a thin film transistor array substrate for driving an OLED display with a relatively high aperture ratio in a relatively simple process.
  • a technical solution adopted by the present invention is to provide a thin film transistor array substrate including: a substrate, and a silicon thin film transistor, a semiconductor oxide transistor, and a capacitor formed on the substrate; and a silicon film
  • the transistor and the semiconductor oxide transistor have a top gate structure; the capacitor and the silicon thin film transistor or the capacitor and the semiconductor oxide transistor are overlapped;
  • the thin film transistor array substrate comprises: a polysilicon layer and a semiconductor oxide layer which are disposed on the substrate; and a polysilicon layer And a gate insulating layer of the semiconductor oxide layer; a first gate, a first metal layer, and a second gate disposed on the gate insulating layer, wherein the first gate is above the polysilicon layer, and the second gate Located above the semiconductor oxide layer; an etch barrier covering the first gate, the first metal layer and the second gate, the etch barrier layer comprises a first insulating layer and a second insulating layer disposed in a stack; and is disposed on the etch barrier layer a
  • the thin film transistor array substrate includes a second metal layer formed by a portion of the first drain; wherein the first metal layer is above the polysilicon layer; wherein the first metal layer, the etch barrier layer, and the second The metal layer forms a capacitor.
  • a thin film transistor array substrate including: a substrate, and a silicon thin film transistor, a semiconductor oxide transistor, and a capacitor formed on the substrate; silicon
  • the thin film transistor and the semiconductor oxide transistor have a top gate structure; the capacitor and the silicon thin film transistor or the capacitor and the semiconductor oxide transistor are overlapped.
  • the thin film transistor array substrate includes: a polysilicon layer and a semiconductor oxide layer spaced apart on the substrate; a gate insulating layer covering the polysilicon layer and the semiconductor oxide layer; a first gate spaced apart from the gate insulating layer, the first a metal layer, a second gate, wherein the first gate is above the polysilicon layer, the second gate is above the semiconductor oxide layer; and the etch barrier covering the first gate, the first metal layer and the second gate
  • the etch barrier layer includes a first insulating layer and a second insulating layer which are stackedly disposed; a source/drain metal layer disposed on the etch barrier layer, the source/drain metal layer includes a first source, a first drain, and a first interval a second source and a second drain, wherein the first source and the first drain are respectively in contact with the polysilicon layer, and the second source and the second drain are respectively in contact with the semiconductor oxide layer; wherein the polysilicon layer and the gate are respectively a very insulating layer,
  • the silicon thin film transistor further includes a floating gate; wherein the floating gate is disposed between the first insulating layer and the second insulating layer, wherein the floating gate is located above the first gate.
  • the thin film transistor array substrate includes a second metal layer formed by a portion of the first drain; wherein the first metal layer is above the polysilicon layer; wherein the first metal layer, the etch barrier layer, and the second The metal layer forms a capacitor.
  • the thin film transistor array substrate includes a third metal layer disposed between the first insulating layer and the second insulating layer and located above the second gate; wherein, the second gate and the first insulating layer A capacitance is formed with the third metal layer.
  • the first metal layer is between the polysilicon layer and the semiconductor oxide layer, and the first metal layer is in contact with the first drain.
  • the floating gate and the third metal layer are formed by the same mask process.
  • first gate and the second gate are formed by the same mask process.
  • the thin film transistor array substrate further includes a buffer layer; wherein the buffer layer is disposed on the substrate; wherein the polysilicon layer and the semiconductor oxide layer are disposed on the buffer layer.
  • a liquid crystal panel including a thin film transistor array substrate;
  • the thin film transistor array substrate includes: a substrate, and a silicon thin film transistor, a semiconductor oxide transistor, and a capacitor formed on the substrate;
  • the silicon thin film transistor and the semiconductor oxide transistor have Top gate structure; capacitors and silicon thin film transistors or capacitors and semiconductor oxide transistors are overlapped.
  • the thin film transistor array substrate includes: a polysilicon layer and a semiconductor oxide layer spaced apart on the substrate; a gate insulating layer covering the polysilicon layer and the semiconductor oxide layer; a first gate spaced apart from the gate insulating layer, the first a metal layer, a second gate, wherein the first gate is above the polysilicon layer, the second gate is above the semiconductor oxide layer; and the etch barrier covering the first gate, the first metal layer and the second gate
  • the etch barrier layer includes a first insulating layer and a second insulating layer which are stackedly disposed; a source/drain metal layer disposed on the etch barrier layer, the source/drain metal layer includes a first source, a first drain, and a first interval a second source and a second drain, wherein the first source and the first drain are respectively in contact with the polysilicon layer, and the second source and the second drain are respectively in contact with the semiconductor oxide layer; wherein the polysilicon layer and the gate are respectively a very insulating layer,
  • the silicon thin film transistor further includes a floating gate; wherein the floating gate is disposed between the first insulating layer and the second insulating layer, wherein the floating gate is located above the first gate.
  • the thin film transistor array substrate includes a second metal layer formed by a portion of the first drain; wherein the first metal layer is above the polysilicon layer; wherein the first metal layer, the etch barrier layer, and the second The metal layer forms a capacitor.
  • the thin film transistor array substrate includes a third metal layer disposed between the first insulating layer and the second insulating layer and located above the second gate; wherein, the second gate and the first insulating layer A capacitance is formed with the third metal layer.
  • the first metal layer is between the polysilicon layer and the semiconductor oxide layer, and the first metal layer is in contact with the first drain.
  • the floating gate and the third metal layer are formed by the same mask process.
  • first gate and the second gate are formed by the same mask process.
  • the thin film transistor array substrate further includes a buffer layer; wherein the buffer layer is disposed on the substrate; wherein the polysilicon layer and the semiconductor oxide layer are disposed on the buffer layer.
  • the invention has the beneficial effects that the secret transistor array substrate and the liquid crystal panel of the present invention comprise a substrate, and a silicon thin film transistor, a semiconductor oxide transistor and a capacitor formed on the substrate, which are different from the prior art.
  • the silicon thin film transistor and the semiconductor oxide transistor have the same top gate structure, thereby being compatible with the silicon thin film transistor and the semiconductor oxide transistor process, reducing the number of times of using the photoresist mask, thereby reducing the production cost of the thin film transistor array substrate.
  • the capacitance is overlapped with the silicon thin film transistor or the capacitor and the semiconductor oxide transistor, so that the aperture ratio of the bottom-emitting OLED can be greatly increased.
  • FIG. 1 is a schematic structural view of a thin film transistor array substrate according to a first embodiment of the present invention
  • FIG. 2 is a schematic structural view of a thin film transistor array substrate according to a second embodiment of the present invention.
  • FIG 3 is a schematic structural view of a liquid crystal panel according to an embodiment of the present invention.
  • the thin film transistor array substrate 10 includes a substrate 11, and a silicon thin film transistor 101, a semiconductor oxide transistor 102, and a capacitor 103 formed on the substrate 11.
  • the silicon thin film transistor 101 and the semiconductor oxide transistor 102 have the same top gate structure, and the silicon thin film transistor 101 and the capacitor 103 are overlapped.
  • the silicon thin film transistor 101 may be an LTPS transistor, and the semiconductor oxide transistor 102 may be an IGZO transistor.
  • the silicon thin film transistor 101 is a P-channel device (ie, a PMOS transistor), the semiconductor oxide transistor 102 is an N-channel device (ie, an NMOS transistor), and the silicon thin film transistor 101 and the semiconductor oxide transistor 102 are in phase.
  • the CMOS circuit is combined to drive the OLED display.
  • the silicon thin film transistor 101 serves as a driving transistor
  • the semiconductor oxide transistor 102 functions as a switching transistor.
  • the thin film transistor array substrate 10 includes a substrate 11, a buffer layer 12, a polysilicon layer 13, a semiconductor oxide layer 14, a gate insulating layer 15, a gate metal layer 16, an etch barrier layer 17, and a source/drain metal layer 18 in this order.
  • the buffer layer 12 is disposed on the substrate 11.
  • the polysilicon layer 13 and the semiconductor oxide layer 14 are spaced apart from each other on the buffer layer 12.
  • the material of the polysilicon layer 13 is polysilicon (poly Si)
  • the material of the semiconductor oxide layer is indium gallium zinc oxide (IGZO).
  • the thin film transistor array substrate 10 may not include the buffer layer 12. At this time, the polysilicon layer 13 and the semiconductor oxide layer 14 are disposed on the substrate 11 at intervals.
  • the gate insulating layer 15 covers the polysilicon layer 13 and the semiconductor oxide layer 14.
  • the gate metal layer 16 is disposed on the gate insulating layer 15.
  • the gate metal layer 16 includes a first gate 161, a first metal layer 162, and a second gate 163 on the gate insulating layer.
  • the first gate 161 is located above the polysilicon layer 13 and the second gate 163 is located above the semiconductor oxide layer 14.
  • the first gate 161, the first metal layer 162 and the second gate 163 are processed by the same mask.
  • the material of the gate metal layer 16 is germanium (GE).
  • the etch barrier layer 17 covers the first gate electrode 161, the first metal layer 162, and the second gate electrode 163.
  • the etch barrier layer 17 includes a stacked first insulating layer 171 and a second insulating layer 172 .
  • the material of the first insulating layer 171 is silicon nitride (SiN), and the material of the second insulating layer 172 is silicon oxide (SiO).
  • the source and drain metal layers 18 are disposed on the etch barrier layer 17.
  • the source and drain metal layers include a first source 181, a first drain 182, a second source 183, and a second drain 184 that are spaced apart.
  • the first source 181 and the first drain 182 are respectively in contact with the polysilicon layer 13, and the second source 183 and the second drain 184 are respectively in contact with the semiconductor oxide layer 14.
  • the polysilicon layer 13, the gate insulating layer 15, the first gate 161, the etch barrier layer 17, the first source 181, and the first drain 182 form a silicon thin film transistor 101; the semiconductor oxide layer 14, the gate insulating layer 15
  • the second gate 163, the etch stop layer 17, the second source 183, and the second drain 184 form a semiconductor oxide transistor 102.
  • the silicon thin film transistor 101 further includes a floating gate 164 disposed between the first insulating layer 171 and the second insulating layer 172, and the floating gate 164 is located Above the first gate 161.
  • the introduction of the floating gate 164 increases the gate control capability of the silicon thin film transistor 101, thereby enabling the silicon thin film transistor 101 to cope with a higher driving voltage.
  • the thin film transistor array substrate 10 further includes a second metal layer 19 formed by a portion of the first drain electrode 182.
  • the second metal layer 19, the etch stop layer 17, and the first metal layer 162 form a capacitor 103.
  • the first metal layer 162 is located above the polysilicon layer 13 and the second metal layer 19 is disposed opposite the first metal layer 162.
  • the second metal layer 19 can also be formed by a portion of the first source 181. At this time, the position of the first metal layer 19 is located at the first gate 161 away from the second.
  • the side of the gate 163 and the second metal layer 19 and the first metal layer 162 are disposed opposite each other.
  • the capacitor 103 and the silicon thin film transistor 101 are overlapped to be Bottom-emission.
  • the OLED increases the aperture ratio. Since the first metal layer 162 as the lower substrate of the capacitor 103 and the first gate 161 and the second gate 163 are the same mask, the second metal layer 19 as the upper substrate of the capacitor 103 and the first drain 182 are the same. The reticle thus makes the process of the capacitor 103 in the thin film transistor array substrate 10 simpler, thereby reducing the production cost.
  • the silicon thin film transistor 101 and the semiconductor oxide transistor 102 have the same top gate structure, thereby being compatible with the processes of the silicon thin film transistor 101 and the semiconductor oxide transistor 102, reducing the number of times of using the photoresist mask, thereby simplifying the thin film transistor array.
  • the thin film transistor array substrate 20 includes a substrate 21, and a silicon thin film transistor 201, a semiconductor oxide transistor 202, and a capacitor 203 formed on the substrate 21.
  • the silicon thin film transistor 201 and the semiconductor oxide transistor 202 have a top gate structure, and the semiconductor oxide transistor 202 and the capacitor 203 are overlapped.
  • the thin film transistor array substrate 20 sequentially includes a substrate 21, a buffer layer 22, a polysilicon layer 23, a semiconductor oxide layer 24, a gate insulating layer 25, a gate metal layer 26, an etch barrier layer 27, and a source/drain metal layer 28.
  • the buffer layer 22 is disposed on the substrate 21.
  • the polysilicon layer 23 and the semiconductor oxide layer 24 are spaced apart from each other on the buffer layer 22.
  • the gate insulating layer 25 covers the polysilicon layer 23 and the semiconductor oxide layer 24.
  • a gate metal layer 26 is disposed on the gate insulating layer 25.
  • the gate metal layer 26 includes a first gate 261, a first metal layer 262, and a second gate 263 disposed on the gate insulating layer 25, and the first gate 261, the first metal layer 262, and the second gate.
  • the pole 263 is formed by the same reticle process.
  • the first gate 261 is located above the polysilicon layer 23 and the second gate 263 is located above the semiconductor oxide layer 24.
  • the etch barrier layer 27 covers the first gate 261, the first metal layer 262, and the second gate 263.
  • the etch barrier layer 27 includes a stacked first insulating layer 271 and a second insulating layer 272 .
  • the source and drain metal layers 28 are disposed on the etch barrier layer 27.
  • the source and drain metal layer 28 includes a first source 281, a first drain 282, a second source 283, and a second drain 284 that are spaced apart.
  • the first source 281 and the first drain 282 are respectively in contact with the polysilicon layer 23, and the second source 283 and the second drain 284 are respectively in contact with the semiconductor oxide layer 24.
  • the polysilicon layer 23, the gate insulating layer 25, the first gate 261, the etch stop layer 27, the first source 281, and the first drain 282 form a silicon thin film transistor 201;
  • the pole insulating layer 25, the second gate 263, the etch stop layer 27, the second source 283, and the second drain 284 form a semiconductor oxide transistor 202.
  • the first metal layer 262 is located between the polysilicon layer 23 and the semiconductor oxide layer 24, and the first metal layer 262 is in contact with the first drain electrode 282.
  • the silicon thin film transistor 201 further includes a floating gate 264 disposed between the first insulating layer 271 and the second insulating layer 272, and the floating gate 264 is located Above the first gate 261.
  • the introduction of the floating gate 264 increases the gate control capability of the silicon thin film transistor 201, so that the silicon thin film transistor 201 can cope with a higher driving voltage.
  • the thin film transistor array substrate 20 further includes a third metal layer 29.
  • the third metal layer 29 is disposed between the first insulating layer 271 and the second insulating layer 272, and the third metal layer 29 is located above the second gate 263.
  • the second gate 263, the first insulating layer 271, and the third metal layer 29 form a capacitor 203.
  • the capacitor 203 and the semiconductor oxide transistor 202 are disposed to overlap each other, thereby increasing the aperture ratio for the bottom-emitting OLED. Since the second substrate 263 is used as the lower substrate of the capacitor 203, the third metal layer 29 as the upper substrate of the capacitor 203 and the floating gate 264 of the silicon thin film transistor 201 are in the same mask, thereby making the thin film transistor array substrate 20 The manufacturing process of the capacitor 203 is simpler, thereby reducing the production cost. In addition, the introduction of the third metal layer 29 increases the gate control capability of the semiconductor oxide transistor 202, thereby allowing the semiconductor oxide transistor 202 to cope with higher drive voltages.
  • the liquid crystal panel 1 includes the above-described thin film transistor array substrate 10 or thin film transistor array substrate 20.
  • the invention has the beneficial effects that the thin film transistor array substrate and the liquid crystal panel of the present invention comprise a substrate, and a silicon thin film transistor, a semiconductor oxide transistor and a capacitor formed on the substrate, which are different from the prior art.
  • the silicon thin film transistor and the semiconductor oxide transistor have the same top gate structure, thereby being compatible with the silicon thin film transistor and the semiconductor oxide transistor process, reducing the number of times of using the photoresist mask, thereby reducing the production cost of the thin film transistor array substrate.
  • the capacitance is overlapped with the silicon thin film transistor or the semiconductor oxide transistor, so that the aperture ratio of the bottom-emitting OLED can be greatly increased.

Abstract

一种薄膜晶体管阵列基板（10）及液晶面板。薄膜晶体管阵列基板包括：基板（11），以及形成于基板上的硅薄膜晶体管（101）、半导体氧化物晶体管（102）和电容（103）。其中，硅薄膜晶体管和半导体氧化物晶体管具有相同的顶栅结构，从而可以兼容硅薄膜晶体管和半导体氧化物晶体管制程，减少光刻胶掩膜板的使用次数，进而减少薄膜晶体管阵列基板的生产成本。另外，电容和硅薄膜晶体管或半导体氧化物晶体管重叠设置，从而可以大大增加底发射的OLED的开口率。

Description

一种薄膜晶体管阵列基板及液晶面板
【技术领域】
本发明涉及液晶显示领域，特别是涉及一种薄膜晶体管阵列基板及液晶面板。
【背景技术】
有机电致发光二极管（organic light-emitting diode, OLED）显示器是一种新兴的平板显示器，其具备自发光，对比度高，厚度薄，视角广，反应速度快，可用于柔性显示面板等优异的特性，因此具有非常好的发展前景。
OLED作为一种自发光显示，目前，较为成熟的技术是采用低温多晶硅（LTPS，low temperature poly silicon）分别制备CMOS电路中PMOS区域和NMOS区域的半导体层来驱动OELD显示。其中，在利用LTPS工艺制备CMOS电路的过程中，需要使用至少9次以上的光刻胶掩膜板和至少4次以上的掺杂工艺（p型离子掺杂，n型离子掺杂，LDD掺杂及Ch掺杂），制作流程复杂，生产成本较高。
同时，LTPS技术由于多晶硅（poly Si）的载流子迁移率很大，从而造成关态电流（Ioff）较大，导致容易形成残像（image sticking）。同时，关态电流较大则需要W/L值更小，因此在薄膜晶体管（TFT）设计中栅极长度值（L值）偏大，栅极宽度值（W值）偏小，目前S型较多，造成有源区（AA区）的TFT面积增大，导致开口率降低。
因此，如何实现一种制程简单、开口率高的薄膜晶体管阵列基板以驱动OELD显示是一个亟待解决的问题。
【发明内容】
本发明主要解决的技术问题是提供一种薄膜晶体管阵列基板及液晶面板，能够以相对简单的制程制造开口率较高的用于驱动OLED显示的薄膜晶体管阵列基板。
为解决上述问题，本发明采用的一个技术方案是：提供一种薄膜晶体管阵列基板，该薄膜晶体管阵列基板包括：基板，以及形成于基板上的硅薄膜晶体管、半导体氧化物晶体管和电容；硅薄膜晶体管和半导体氧化物晶体管具有顶栅结构；电容和硅薄膜晶体管或电容和半导体氧化物晶体管重叠设置；其中，薄膜晶体管阵列基板包括：间隔设置于基板上的多晶硅层和半导体氧化层；覆盖多晶硅层和半导体氧化层的栅极绝缘层；间隔设置于栅极绝缘层上的第一栅极、第一金属层、第二栅极，其中，第一栅极位于多晶硅层的上方，第二栅极位于半导体氧化层的上方；覆盖第一栅极、第一金属层和第二栅极的蚀刻阻挡层，蚀刻阻挡层包括层迭设置的第一绝缘层和第二绝缘层；设置于蚀刻阻挡层上的源漏金属层，源漏金属层包括间隔设置的第一源极、第一漏极、第二源极和第二漏极，其中，第一源极和第一漏极分别与多晶硅层相接触，第二源极和第二漏极分别与半导体氧化层相接触；其中，多晶硅层、栅极绝缘层、第一栅极、蚀刻阻挡层、第一源极和第一漏极形成硅薄膜晶体管；半导体氧化层、栅极绝缘层、第二栅极、蚀刻阻挡层、第二源极和第二漏极形成半导体氧化物晶体管；其中，硅薄膜晶体管进一步包括浮动栅极；其中，浮动栅极设置于第一绝缘层和第二绝缘层之间，其中，浮动栅极位于第一栅极的上方；其中，第一栅极和第二栅极采用同一道光罩制程形成。
其中，薄膜晶体管阵列基板包括第二金属层，第二金属层由第一漏极的一部分形成；其中，第一金属层位于多晶硅层的上方；其中，第一金属层、蚀刻阻挡层和第二金属层形成电容。
为解决上述问题，本发明采用的另一个技术方案是：提供一种薄膜晶体管阵列基板，该薄膜晶体管阵列基板包括：基板，以及形成于基板上的硅薄膜晶体管、半导体氧化物晶体管和电容；硅薄膜晶体管和半导体氧化物晶体管具有顶栅结构；电容和硅薄膜晶体管或电容和半导体氧化物晶体管重叠设置。
其中，薄膜晶体管阵列基板包括：间隔设置于基板上的多晶硅层和半导体氧化层；覆盖多晶硅层和半导体氧化层的栅极绝缘层；间隔设置于栅极绝缘层上的第一栅极、第一金属层、第二栅极，其中，第一栅极位于多晶硅层的上方，第二栅极位于半导体氧化层的上方；覆盖第一栅极、第一金属层和第二栅极的蚀刻阻挡层，蚀刻阻挡层包括层迭设置的第一绝缘层和第二绝缘层；设置于蚀刻阻挡层上的源漏金属层，源漏金属层包括间隔设置的第一源极、第一漏极、第二源极和第二漏极，其中，第一源极和第一漏极分别与多晶硅层相接触，第二源极和第二漏极分别与半导体氧化层相接触；其中，多晶硅层、栅极绝缘层、第一栅极、蚀刻阻挡层、第一源极和第一漏极形成硅薄膜晶体管；半导体氧化层、栅极绝缘层、第二栅极、蚀刻阻挡层、第二源极和第二漏极形成半导体氧化物晶体管。
其中，硅薄膜晶体管进一步包括浮动栅极；其中，浮动栅极设置于第一绝缘层和第二绝缘层之间，其中，浮动栅极位于第一栅极的上方。
其中，薄膜晶体管阵列基板包括第二金属层，第二金属层由第一漏极的一部分形成；其中，第一金属层位于多晶硅层的上方；其中，第一金属层、蚀刻阻挡层和第二金属层形成电容。
其中，薄膜晶体管阵列基板包括第三金属层，第三金属层设置于第一绝缘层和第二绝缘层之间，且位于第二栅极的上方；其中，第二栅极、第一绝缘层和第三金属层形成电容。
其中，第一金属层位于多晶硅层和半导体氧化层之间，第一金属层与第一漏极相接触。
其中，浮动栅极和第三金属层采用同一道光罩制程形成。
其中，第一栅极和第二栅极采用同一道光罩制程形成。
其中，薄膜晶体管阵列基板进一步包括缓冲层；其中，缓冲层设置于基板上；其中，多晶硅层和半导体氧化层间隔设置于缓冲层上。
为解决上述技术问题，本发明采用的再一个技术方案是： 提供一种液晶面板，该液晶面板包括薄膜晶体管阵列基板；该薄膜晶体管阵列基板包括：基板，以及形成于基板上的硅薄膜晶体管、半导体氧化物晶体管和电容；硅薄膜晶体管和半导体氧化物晶体管具有顶栅结构；电容和硅薄膜晶体管或电容和半导体氧化物晶体管重叠设置。
其中，薄膜晶体管阵列基板包括：间隔设置于基板上的多晶硅层和半导体氧化层；覆盖多晶硅层和半导体氧化层的栅极绝缘层；间隔设置于栅极绝缘层上的第一栅极、第一金属层、第二栅极，其中，第一栅极位于多晶硅层的上方，第二栅极位于半导体氧化层的上方；覆盖第一栅极、第一金属层和第二栅极的蚀刻阻挡层，蚀刻阻挡层包括层迭设置的第一绝缘层和第二绝缘层；设置于蚀刻阻挡层上的源漏金属层，源漏金属层包括间隔设置的第一源极、第一漏极、第二源极和第二漏极，其中，第一源极和第一漏极分别与多晶硅层相接触，第二源极和第二漏极分别与半导体氧化层相接触；其中，多晶硅层、栅极绝缘层、第一栅极、蚀刻阻挡层、第一源极和第一漏极形成硅薄膜晶体管；半导体氧化层、栅极绝缘层、第二栅极、蚀刻阻挡层、第二源极和第二漏极形成半导体氧化物晶体管。
其中，硅薄膜晶体管进一步包括浮动栅极；其中，浮动栅极设置于第一绝缘层和第二绝缘层之间，其中，浮动栅极位于第一栅极的上方。
其中，薄膜晶体管阵列基板包括第二金属层，第二金属层由第一漏极的一部分形成；其中，第一金属层位于多晶硅层的上方；其中，第一金属层、蚀刻阻挡层和第二金属层形成电容。
其中，薄膜晶体管阵列基板包括第三金属层，第三金属层设置于第一绝缘层和第二绝缘层之间，且位于第二栅极的上方；其中，第二栅极、第一绝缘层和第三金属层形成电容。
其中，第一金属层位于多晶硅层和半导体氧化层之间，第一金属层与第一漏极相接触。
其中，浮动栅极和第三金属层采用同一道光罩制程形成。
其中，第一栅极和第二栅极采用同一道光罩制程形成。
其中，薄膜晶体管阵列基板进一步包括缓冲层；其中，缓冲层设置于基板上；其中，多晶硅层和半导体氧化层间隔设置于缓冲层上。
本发明的有益效果是：区别于现有技术的情况，本发明的保密晶体管阵列基板及液晶面板包括基板，以及形成于基板上的硅薄膜晶体管、半导体氧化物晶体管和电容。其中，硅薄膜晶体管和半导体氧化物晶体管具有相同的顶栅结构，从而可以兼容硅薄膜晶体管和半导体氧化物晶体管制程，减少光刻胶掩膜板的使用次数，进而减少薄膜晶体管阵列基板的生产成本。另外，电容和硅薄膜晶体管或电容和半导体氧化物晶体管重叠设置，从而可以大大增加底发射的OLED的开口率。
【附图说明】
图1是本发明第一实施例的薄膜晶体管阵列基板的结构示意图；
图2是本发明第二实施例的薄膜晶体管阵列基板的结构示意图；
图3是本发明实施例的液晶面板的结构示意图。
【具体实施方式】
下面结合附图和实施方式对本发明进行详细说明。
图1是本发明第一实施例的薄膜晶体管阵列基板的结构示意图。如图1所示，薄膜晶体管阵列基板10包括基板11、以及形成于基板11上的硅薄膜晶体管101、半导体氧化物晶体管102和电容103。
其中，硅薄膜晶体管101和半导体氧化物晶体管102具有相同的顶栅结构，硅薄膜晶体管101和电容103重叠设置。
其中，硅薄膜晶体管101可以为LTPS晶体管，半导体氧化物晶体管102可以为IGZO晶体管。在本实施例中，硅薄膜晶体管101是P沟道设备（也即PMOS晶体管），半导体氧化物晶体管102是N沟道设备（也即NMOS晶体管），硅薄膜晶体管101和半导体氧化物晶体管102相结合来制备CMOS电路从而驱动OLED显示。其中，硅薄膜晶体管101作为驱动晶体管，半导体氧化物晶体管102作为开关晶体管。
具体来说，薄膜晶体管阵列基板10依次包括基板11、缓冲层12、多晶硅层13、半导体氧化层14、栅极绝缘层15、栅极金属层16、蚀刻阻挡层17和源漏金属层18。
缓冲层12设置于基板11上。多晶硅层13和半导体氧化层14间隔设置在缓冲层12上。优选地，多晶硅层13的材料为多晶硅（poly Si），半导体氧化层的材料为铟镓锌氧化物（IGZO）。在其它实施例中，薄膜晶体管阵列基板10也可以不包括缓冲层12，此时，多晶硅层13和半导体氧化层14间隔设置在基板11上。
栅极绝缘层15覆盖多晶硅层13和半导体氧化层14。
栅极金属层16设置在栅极绝缘层15上。其中，栅极金属层16包括间隔设置栅极绝缘层上的第一栅极161、第一金属层162和第二栅极163。其中，第一栅极161位于多晶硅层13的上方，第二栅极163位于半导体氧化层14的上方。优选地，第一栅极161、第一金属层162和第二栅极163采用同一道光罩制程。优选地，栅极金属层16的材料为锗（GE）。
蚀刻阻挡层17覆盖第一栅极161、第一金属层162和第二栅极163。其中，蚀刻阻挡层17包括层迭的第一绝缘层171和第二绝缘层172 。优选地，第一绝缘层171的材料为氮化硅（SiN），第二绝缘层172的材料为氧化硅（SiO）。
源漏极金属层18设置在蚀刻阻挡层17上。源漏极金属层包括间隔设置的第一源极181、第一漏极182、第二源极183和第二漏极184。其中，第一源极181和第一漏极182分别与多晶硅层13相接触，第二源极183和第二漏极184分别与半导体氧化层14相接触。
其中，多晶硅层13、栅极绝缘层15、第一栅极161、蚀刻阻挡层17、第一源极181和第一漏极182形成硅薄膜晶体管101；半导体氧化层14、栅极绝缘层15、第二栅极163、蚀刻阻挡层17、第二源极183和第二漏极184形成半导体氧化物晶体管102。
优选地，为了提高硅薄膜晶体管101的栅控制力，硅薄膜晶体管101进一步包括浮动栅极164，浮动栅极164设置于第一绝缘层171和第二绝缘层172之间，浮动栅极164位于第一栅极161的上方。其中，浮动栅极164的引入，增大了硅薄膜晶体管101的栅控能力，进而使得硅薄膜晶体管101可以应对更高的驱动电压。
在本实施例中，薄膜晶体管阵列基板10进一步包括第二金属层19,第二金属层19由第一漏极182的一部分形成。第二金属层19、蚀刻阻挡层17和第一金属层162形成电容103。优选地，第一金属层162位于多晶硅层13的上方，第二金属层19与第一金属层162相对设置。本领域的技术人员可以理解，在其它实施例中，第二金属层19也可以由第一源极181的一部分形成，此时，第一金属层19的位置位于第一栅极161远离第二栅极163的侧边，且第二金属层19和第一金属层162相对设置。
在本实施例中，电容103和硅薄膜晶体管101重叠设置，从而为底发射（Bottom-emission） 的OLED增大了开口率。由于作为电容103的下基板的第一金属层162和第一栅极161以及第二栅极163采用同一道光罩，作为电容103的上基板的第二金属层19和第一漏极182采用同一道光罩，从而使得薄膜晶体管阵列基板10中电容103的制程更加简单，进而降低了生产成本。
本领域的技术人员可以理解，在本实施例中使用两种不同类型的晶体管也即硅薄膜晶体管101和半导体氧化物晶体管102来驱动OLED显示，与现有技术相比，由于半导体氧化物晶体管102中氧化物的载流子迁移率值不高，从而使得关态电流较小，进而使得W/L的设计条件更宽泛，可以在较小的栅极长度值（L值）下也即较小尺寸的薄膜晶体管，达到为底发射的OLED增大开口率的效果。进一步，硅薄膜晶体管101和半导体氧化物晶体管102具有相同的顶栅结构，从而可以兼容硅薄膜晶体管101和半导体氧化物晶体管102制程，减少光刻胶掩膜板的使用次数，进而简化薄膜晶体管阵列基板10的生产制程。
图2是本发明第二实施例的薄膜晶体管阵列基板的结构示意图。如图2所示，薄膜晶体管阵列基板20包括基板21、以及形成于基板21上的硅薄膜晶体管201、半导体氧化物晶体管202和电容203。
其中，硅薄膜晶体管201和半导体氧化物晶体管202具有顶栅结构，半导体氧化物晶体管202和电容203重叠设置。
具体来说，薄膜晶体管阵列基板20依次包括基板21、缓冲层22、多晶硅层23、半导体氧化层24、栅极绝缘层25、栅极金属层26、蚀刻阻挡层27和源漏金属层28。
缓冲层22设置于基板21上。多晶硅层23和半导体氧化层24间隔设置在缓冲层22上。栅极绝缘层25覆盖多晶硅层23和半导体氧化层24。
栅极金属层26设置在栅极绝缘层25上。其中，栅极金属层26包括间隔设置栅极绝缘层25上的第一栅极261、第一金属层262和第二栅极263，第一栅极261、第一金属层262和第二栅极263采用同一道光罩制程形成。其中，第一栅极261位于多晶硅层23的上方，第二栅极263位于半导体氧化层24的上方。
蚀刻阻挡层27覆盖第一栅极261、第一金属层262和第二栅极263。其中，蚀刻阻挡层27包括层迭的第一绝缘层271和第二绝缘层272 。源漏极金属层28设置在蚀刻阻挡层27上。源漏极金属层28包括间隔设置的第一源极281、第一漏极282、第二源极283和第二漏极284。其中，第一源极281和第一漏极282分别与多晶硅层23相接触，第二源极283和第二漏极284分别与半导体氧化层24相接触。
在本实施例中，多晶硅层23、栅极绝缘层25、第一栅极261、蚀刻阻挡层27、第一源极281和第一漏极282形成硅薄膜晶体管201；半导体氧化层24、栅极绝缘层25、第二栅极263、蚀刻阻挡层27、第二源极283和第二漏极284形成半导体氧化物晶体管202。
在本实施例中，优选地，第一金属层262位于多晶硅层23和半导体氧化层24之间，第一金属层262与第一漏极282相接触。
优选地，为了提高硅薄膜晶体管201的栅控制力，硅薄膜晶体管201进一步包括浮动栅极264，浮动栅极264设置于第一绝缘层271和第二绝缘层272之间，浮动栅极264位于第一栅极261的上方。其中，浮动栅极264的引入，增大了硅薄膜晶体管201的栅控能力，进而使得硅薄膜晶体管201可以应对更高的驱动电压。
在本实施例中，薄膜晶体管阵列基板20进一步包括第三金属层29。在本实施例中，第三金属层29设置于第一绝缘层271和第二绝缘层272之间，第三金属层29位于第二栅极263的上方。第二栅极263、第一绝缘层271和第三金属层29形成电容203。
在本实施例中，电容203和半导体氧化物晶体管202重叠设置，从而为底发射的OLED增大了开口率。由于作为电容203的下基板采用第二栅极263，作为电容203的上基板的第三金属层29与硅薄膜晶体管201中浮动栅极264采用同一道光罩，从而使得的薄膜晶体管阵列基板20中的电容203的制程更加简单，进而降低了生产成本。另外，第三金属层29的引入，增大了半导体氧化物晶体管202的栅控能力，进而使得半导体氧化物晶体管202可以应对更高的驱动电压。
图3是本发明实施例的液晶面板的结构示意图。如图3所示，液晶面板1包括了上述的薄膜晶体管阵列基板10或薄膜晶体管阵列基板20。
本发明的有益效果是：区别于现有技术的情况，本发明的薄膜晶体管阵列基板及液晶面板包括基板，以及形成于基板上的硅薄膜晶体管、半导体氧化物晶体管和电容。其中，硅薄膜晶体管和半导体氧化物晶体管具有相同的顶栅结构，从而可以兼容硅薄膜晶体管和半导体氧化物晶体管制程，减少光刻胶掩膜板的使用次数，进而减少薄膜晶体管阵列基板的生产成本。另外，电容和硅薄膜晶体管或半导体氧化物晶体管重叠设置，从而可以大大增加底发射的OLED的开口率。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：基板，以及形成于所述基板上的硅薄膜晶体管、半导体氧化物晶体管和电容；
    所述硅薄膜晶体管和所述半导体氧化物晶体管具有顶栅结构；
    所述电容和所述硅薄膜晶体管或所述电容和所述半导体氧化物晶体管重叠设置；
    其中，所述薄膜晶体管阵列基板包括：
    间隔设置于所述基板上的多晶硅层和半导体氧化层；
    覆盖所述多晶硅层和半导体氧化层的栅极绝缘层；
    间隔设置于所述栅极绝缘层上的第一栅极、第一金属层、第二栅极，其中，所述第一栅极位于所述多晶硅层的上方，所述第二栅极位于所述半导体氧化层的上方；
    覆盖所述第一栅极、第一金属层和第二栅极的蚀刻阻挡层，所述蚀刻阻挡层包括层迭设置的第一绝缘层和第二绝缘层；
    设置于所述蚀刻阻挡层上的源漏金属层，所述源漏金属层包括间隔设置的第一源极、第一漏极、第二源极和第二漏极，其中，所述第一源极和第一漏极分别与所述多晶硅层相接触，所述第二源极和所述第二漏极分别与所述半导体氧化层相接触；
    其中，所述多晶硅层、所述栅极绝缘层、所述第一栅极、所述蚀刻阻挡层、所述第一源极和所述第一漏极形成所述硅薄膜晶体管；所述半导体氧化层、所述栅极绝缘层、所述第二栅极、所述蚀刻阻挡层、所述第二源极和所述第二漏极形成所述半导体氧化物晶体管；
    所述硅薄膜晶体管进一步包括浮动栅极；
    其中，所述浮动栅极设置于所述第一绝缘层和所述第二绝缘层之间，其中，所述浮动栅极位于所述第一栅极的上方；
    所述第一栅极和所述第二栅极采用同一道光罩制程形成。
  2. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括第二金属层，所述第二金属层由所述第一漏极的一部分形成；
    其中，所述第一金属层位于所述多晶硅层的上方；
    其中，所述第一金属层、所述蚀刻阻挡层和所述第二金属层形成所述电容。
  3. 一种薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：基板，以及形成于所述基板上的硅薄膜晶体管、半导体氧化物晶体管和电容；
    所述硅薄膜晶体管和所述半导体氧化物晶体管具有顶栅结构；
    所述电容和所述硅薄膜晶体管或所述电容和所述半导体氧化物晶体管重叠设置。
  4. 根据权利要求3所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括：
    间隔设置于所述基板上的多晶硅层和半导体氧化层；
    覆盖所述多晶硅层和半导体氧化层的栅极绝缘层；
    间隔设置于所述栅极绝缘层上的第一栅极、第一金属层、第二栅极，其中，所述第一栅极位于所述多晶硅层的上方，所述第二栅极位于所述半导体氧化层的上方；
    覆盖所述第一栅极、第一金属层和第二栅极的蚀刻阻挡层，所述蚀刻阻挡层包括层迭设置的第一绝缘层和第二绝缘层；
    设置于所述蚀刻阻挡层上的源漏金属层，所述源漏金属层包括间隔设置的第一源极、第一漏极、第二源极和第二漏极，其中，所述第一源极和第一漏极分别与所述多晶硅层相接触，所述第二源极和所述第二漏极分别与所述半导体氧化层相接触；
    其中，所述多晶硅层、所述栅极绝缘层、所述第一栅极、所述蚀刻阻挡层、所述第一源极和所述第一漏极形成所述硅薄膜晶体管；所述半导体氧化层、所述栅极绝缘层、所述第二栅极、所述蚀刻阻挡层、所述第二源极和所述第二漏极形成所述半导体氧化物晶体管。
  5. 根据权利要求4所述的薄膜晶体管阵列基板，其中，所述硅薄膜晶体管进一步包括浮动栅极；
    其中，所述浮动栅极设置于所述第一绝缘层和所述第二绝缘层之间，其中，所述浮动栅极位于所述第一栅极的上方。
  6. 根据权利要求5所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括第二金属层，所述第二金属层由所述第一漏极的一部分形成；
    其中，所述第一金属层位于所述多晶硅层的上方；
    其中，所述第一金属层、所述蚀刻阻挡层和所述第二金属层形成所述电容。
  7. 根据权利要求5所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括第三金属层，所述第三金属层设置于所述第一绝缘层和所述第二绝缘层之间，且位于所述第二栅极的上方；
    其中，所述第二栅极、所述第一绝缘层和所述第三金属层形成所述电容。
  8. 根据权利要求7所述的薄膜晶体管阵列基板，其中，所述第一金属层位于所述多晶硅层和所述半导体氧化层之间，所述第一金属层与所述第一 漏极相接触。
  9. 根据权利要求7所述的薄膜晶体管阵列基板，其中，所述浮动栅极和所述第三金属层采用同一道光罩制程形成。
  10. 根据权利要求4所述的薄膜晶体管阵列基板，其中，所述第一栅极和所述第二栅极采用同一道光罩制程形成。
  11. 根据权利要求4所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板进一步包括缓冲层；
    其中，所述缓冲层设置于所述基板上；
    其中，所述多晶硅层和所述半导体氧化层间隔设置于所述缓冲层上。
  12. 一种液晶面板，其中，包括薄膜晶体管阵列基板； 所述薄膜晶体管阵列基板包括：基板，以及形成于所述基板上的硅薄膜晶体管、半导体氧化物晶体管和电容；
    所述硅薄膜晶体管和所述半导体氧化物晶体管具有顶栅结构；
    所述电容和所述硅薄膜晶体管或所述电容和所述半导体氧化物晶体管重叠设置。
  13. 根据权利要求12所述的液晶面板，其中，所述薄膜晶体管阵列基板包括：
    间隔设置于所述基板上的多晶硅层和半导体氧化层；
    覆盖所述多晶硅层和半导体氧化层的栅极绝缘层；
    间隔设置于所述栅极绝缘层上的第一栅极、第一金属层、第二栅极，其中，所述第一栅极位于所述多晶硅层的上方，所述第二栅极位于所述半导体氧化层的上方；
    覆盖所述第一栅极、第一金属层和第二栅极的蚀刻阻挡层，所述蚀刻阻挡层包括层迭设置的第一绝缘层和第二绝缘层；
    设置于所述蚀刻阻挡层上的源漏金属层，所述源漏金属层包括间隔设置的第一源极、第一漏极、第二源极和第二漏极，其中，所述第一源极和第一漏极分别与所述多晶硅层相接触，所述第二源极和所述第二漏极分别与所述半导体氧化层相接触；
    其中，所述多晶硅层、所述栅极绝缘层、所述第一栅极、所述蚀刻阻挡层、所述第一源极和所述第一漏极形成所述硅薄膜晶体管；所述半导体氧化层、所述栅极绝缘层、所述第二栅极、所述蚀刻阻挡层、所述第二源极和所述第二漏极形成所述半导体氧化物晶体管。
  14. 根据权利要求13所述的液晶面板，其中，所述硅薄膜晶体管进一步包括浮动栅极；
    其中，所述浮动栅极设置于所述第一绝缘层和所述第二绝缘层之间，其中，所述浮动栅极位于所述第一栅极的上方。
  15. 根据权利要求14所述的液晶面板，其中，所述薄膜晶体管阵列基板包括第二金属层，所述第二金属层由所述第一漏极的一部分形成；
    其中，所述第一金属层位于所述多晶硅层的上方；
    其中，所述第一金属层、所述蚀刻阻挡层和所述第二金属层形成所述电容。
  16. 根据权利要求14所述的液晶面板，其中，所述薄膜晶体管阵列基板包括第三金属层，所述第三金属层设置于所述第一绝缘层和所述第二绝缘层之间，且位于所述第二栅极的上方；
    其中，所述第二栅极、所述第一绝缘层和所述第三金属层形成所述电容。
  17. 根据权利要求16所述的液晶面板，其中，所述第一金属层位于所述多晶硅层和所述半导体氧化层之间，所述第一金属层与所述第一 漏极相接触。
  18. 根据权利要求16所述的液晶面板，其中，所述浮动栅极和所述第三金属层采用同一道光罩制程形成。
  19. 根据权利要求13所述的液晶面板，其中，所述第一栅极和所述第二栅极采用同一道光罩制程形成。
  20. 根据权利要求13所述的液晶面板，其中，所述薄膜晶体管阵列基板进一步包括缓冲层；
    其中，所述缓冲层设置于所述基板上；
    其中，所述多晶硅层和所述半导体氧化层间隔设置于所述缓冲层上。
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