WO2020019728A1 - 薄膜晶体管及其制备方法、阵列基板 - Google Patents

薄膜晶体管及其制备方法、阵列基板 Download PDF

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WO2020019728A1
WO2020019728A1 PCT/CN2019/077873 CN2019077873W WO2020019728A1 WO 2020019728 A1 WO2020019728 A1 WO 2020019728A1 CN 2019077873 W CN2019077873 W CN 2019077873W WO 2020019728 A1 WO2020019728 A1 WO 2020019728A1
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layer
metal oxide
semiconductor layer
metal
drain
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PCT/CN2019/077873
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English (en)
French (fr)
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谢华飞
陈书志
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深圳市华星光电半导体显示技术有限公司
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Publication of WO2020019728A1 publication Critical patent/WO2020019728A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors

Definitions

  • the present invention relates to the technical field of array substrate manufacturing, and in particular, to a thin film transistor, a method for manufacturing the same, and an array substrate.
  • Some metal oxide semiconductors have the characteristics of high mobility, low leakage current, and good uniformity, and are suitable for applications such as large size, flexible and transparent, and can prepare thin film transistor devices with smaller sizes.
  • Using the metal oxide semiconductor as the active layer of a thin film transistor device can improve the display transmittance, so that the metal oxide semiconductor has received great attention and research in the display field.
  • Oxide TFTs metal oxide thin film transistors
  • NTIS Oxide Bias stability
  • PBTIS Oxide Bias stability
  • stability to the environment water, oxygen
  • the etching solution reacts with or remains in the active metal oxide layer, causing damage to the active metal oxide layer, thereby deteriorating the stability of the device.
  • the present invention provides a thin film transistor, a method for manufacturing the same, and an array substrate, which can prevent damage to an active layer and improve the stability of the device.
  • the specific technical solution proposed by the present invention is: providing a method for preparing a thin film transistor, the method comprising the steps:
  • a gate and a gate insulating layer are formed on the substrate by a patterning process, the gate insulating layer includes a source region, a back channel region, and a drain region, and the back channel region is located in the source region and the drain region between;
  • a third semiconductor layer is formed in the back channel region through a patterning process, and the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer constitute an active layer.
  • a first metal oxide layer and a first metal layer are deposited on the gate insulating layer, and the first metal oxide layer and the first metal layer are etched.
  • the steps of forming the first semiconductor layer and the source electrode in the source region, and the second semiconductor layer and the drain electrode in the drain region specifically include:
  • the first metal layer and the patterned metal oxide layer are etched to form a first semiconductor layer and a source electrode in a source region, a second semiconductor layer and a drain electrode in a drain region.
  • a first metal oxide layer and a first metal layer are deposited on the gate insulating layer, and the first metal oxide layer and the first metal layer are etched.
  • the steps of forming the first semiconductor layer and the source electrode in the source region, and the second semiconductor layer and the drain electrode in the drain region specifically include:
  • the photoresist is removed to form a first semiconductor layer and a source located in a source region, and a second semiconductor layer and a drain located in a drain region.
  • the step of forming a third semiconductor layer in the back channel region through a patterning process specifically includes:
  • the step of forming a gate and a gate insulating layer on the substrate through a patterning process specifically includes:
  • An insulating material layer is deposited on the substrate to form a gate insulating layer.
  • the method further includes:
  • a passivation material layer is deposited on the source and drain electrodes to form a passivation layer.
  • a material of the first metal oxide layer is indium gallium zinc oxide, aluminum doped zinc oxide, or indium oxide.
  • the invention also provides a thin film transistor, which is prepared by the method described in any one of the above.
  • the invention also provides an array substrate including the thin film transistor described above.
  • the array substrate further includes a pixel electrode layer, and the pixel electrode layer is connected to the drain electrode through a via.
  • the method for preparing a thin film transistor provided by the present invention, when the first metal layer is etched to obtain a source electrode and a drain electrode, a part of the first metal oxide layer located in the back channel region is also etched, and then passed through The patterning process forms a third semiconductor layer in the back channel region, so that the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer constitute the active layer of the thin film transistor, thereby avoiding the formation of the acid etching solution used for the source and drain electrodes. Damage to the active layer improves the stability of the thin film transistor.
  • Embodiment 1 is a schematic structural diagram of an array substrate in Embodiment 1;
  • 3a to 3j are flowcharts of a method for manufacturing a thin film transistor in Embodiment 2.
  • the array substrate in this embodiment includes a plurality of thin film transistors 1 arranged in an array.
  • Each thin film transistor 1 includes a substrate 11, a gate 12, a gate insulating layer 13, an active layer 14, a source 15, and a drain. Pole 16.
  • the structure of the thin film transistor 1 is a bottom-gate structure.
  • the gate 12 is disposed on the substrate 11.
  • the gate insulating layer 13 covers the substrate 11 and the gate 12.
  • the gate insulating layer 13 includes a source region 10, a back channel region 20, The drain region 30 and the back channel region are located between the source region 10 and the drain region 30.
  • the source region 10, the back channel region 20, and the drain region 30 are disposed opposite to the gate 12.
  • the active layer 14 includes a first semiconductor layer 14a, a second semiconductor layer 14b, and a third semiconductor layer 14c.
  • the first semiconductor layer 14a and the source electrode 15 are sequentially stacked in the source region 10 in a direction away from the gate insulating layer 13, That is, the source electrode 15 is located on the first semiconductor layer 14a, and the second semiconductor layer 14b and the drain electrode 16 are sequentially stacked in the drain region 30 in a direction away from the gate insulating layer 13. That is, the drain electrode 16 is located on the second semiconductor layer 14b.
  • the third semiconductor layer 14c is located in the back channel region 20 and is connected to the first semiconductor layer 14a and the second semiconductor layer 14b.
  • the thin film transistor 1 further includes a passivation layer 17, which is disposed on the source electrode 15 and the drain electrode 16 and covers the source electrode 15 and the drain electrode 16.
  • the passivation layer 17 protects the source electrode 15 and the drain electrode 16.
  • the array substrate in this embodiment further includes a pixel electrode 2, which is disposed on the passivation layer 17 and connected to the drain electrode 16 through a via hole 40.
  • the method for manufacturing the thin film transistor 1 in this embodiment is described in detail below.
  • the method includes the following steps:
  • a substrate 11 is provided, as shown in FIG. 2a.
  • a gate 12 and a gate insulating layer 13 are formed on the substrate 11 through a patterning process.
  • the gate insulating layer 13 includes a source region 10, a back channel region 20, and a drain region 30.
  • the back channel region 20 is located in the source region 10 and the drain. Between the regions 30, as shown in Figs. 2b to 2d.
  • a third semiconductor layer 14c is formed in the back channel region 20 through a patterning process.
  • the first semiconductor layer 14a, the second semiconductor layer 14b, and the third semiconductor layer 14c constitute an active layer 14, as shown in FIGS. 2i to 2j.
  • step S2 includes:
  • a second metal layer 23 is deposited on the substrate 11, as shown in FIG. 2b.
  • the second metal layer 23 is imaged, and a gate electrode 12 is formed on the substrate 11.
  • the image is formed by a wet etching process, as shown in FIG. 2c.
  • step S3 includes:
  • a first metal oxide layer 21 is deposited on the gate insulating layer 13, as shown in FIG. 2e.
  • a first metal layer 22 is deposited on the patterned metal oxide layer 24, as shown in FIG. 2g.
  • step S4 includes:
  • a second metal oxide layer 25 is deposited on the source electrode 15 and the drain electrode 16, as shown in FIG. 2i.
  • the second metal oxide layer 25 is patterned, and a third semiconductor layer 14c is formed in the back channel region, as shown in FIG. 2j.
  • the thin film transistor 1 in this embodiment further includes a passivation layer 17, and after step S4, the preparation method further includes steps:
  • a passivation material layer is deposited on the source electrode 15 and the drain electrode 16 to form a passivation layer 17, as shown in FIG. 2k.
  • the materials of the first metal oxide layer 21 and the second metal oxide layer 25 in this embodiment are all indium gallium zinc oxide (IGZO), aluminum doped zinc oxide (AZO), and indium oxide (In2O3), that is, the whole
  • the material of the active layer 14 is IGZO, AZO, and In2O3.
  • the first metal layer 22 is etched to obtain the source electrode 15 and the drain electrode 16
  • a portion of the first metal oxide layer 21 located in the back channel region 20 is also etched.
  • a third semiconductor layer 14c in the back channel region 20 through a patterning process, so that the first semiconductor layer 14a, the second semiconductor layer 14b, and the third semiconductor layer 14c constitute the active layer 14 of the thin film transistor, thereby avoiding formation
  • the acid etching solution used for the source electrode 15 and the drain electrode 16 causes damage to the active layer 14 and improves the stability of the thin film transistor.
  • the structure of the array substrate in this embodiment is the same as that in Embodiment 1, and is not repeated here.
  • the difference between this embodiment and Embodiment 1 is a method for manufacturing a thin film transistor. Referring to FIGS. 3a to 3j, the method for manufacturing the thin film transistor 1 in this embodiment is described in detail below.
  • the manufacturing method includes steps:
  • a substrate 11 is provided, as shown in FIG. 3a.
  • a gate 12 and a gate insulating layer 13 are formed on the substrate 11 through a patterning process.
  • the gate insulating layer 13 includes a source region 10, a back channel region 20, and a drain region 30.
  • the back channel region 20 is located in the source region 10 and the drain. Between the regions 30, as shown in Figs. 3b to 3d.
  • a third semiconductor layer 14c is formed in the back channel region 20 through a patterning process.
  • the first semiconductor layer 14a, the second semiconductor layer 14b, and the third semiconductor layer 14c constitute an active layer 14, as shown in FIGS. 3h to 3i.
  • step S2 includes:
  • a second metal layer 23 is deposited on the substrate 11, as shown in FIG. 3b.
  • the second metal layer 23 is imaged, and a gate electrode 12 is formed on the substrate 11.
  • the image is formed by a wet etching process, as shown in FIG. 3c.
  • An insulating material layer is deposited on the substrate 11 to form a gate insulating layer 13, as shown in FIG. 3d.
  • step S3 includes:
  • a first metal oxide layer 21, a first metal layer 22, and a photoresist 26 are sequentially deposited on the gate insulating layer 13, as shown in FIG. 3e.
  • the patterning process here includes exposure, development, and etching processes, wherein the etching process is a wet method The etching process is shown in FIG. 3f.
  • the photoresist is removed to form a first semiconductor layer 14a and a source electrode 15 located in the source region 10, a second semiconductor layer 14b and a drain electrode 16 located in the drain region 30, as shown in FIG. 3g.
  • step S4 includes:
  • a second metal oxide layer 25 is deposited on the source electrode 15 and the drain electrode 16, as shown in FIG. 3h.
  • the second metal oxide layer 25 is patterned, and a third semiconductor layer 14c is formed in the back channel region, as shown in FIG. 3i.
  • the thin film transistor 1 in this embodiment further includes a passivation layer 17, and after step S4, the preparation method further includes steps:
  • a passivation material layer is deposited on the source electrode 15 and the drain electrode 16 to form a passivation layer 17, as shown in FIG. 3j.
  • the manufacturing method of the thin film transistor proposed in this embodiment reduces the number of patterning treatments. Therefore, the manufacturing method in this embodiment avoids the acid etching used to form the source electrode 15 and the drain electrode 16 The liquid causes damage to the active layer 14 and improves the stability of the thin film transistor while simplifying the manufacturing process and reducing the cost.

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

本发明提供一种薄膜晶体管及其制备方法、阵列基板，制备方法包括以下步骤：在衬底上形成栅极和栅绝缘层；在栅绝缘层上沉积第一金属氧化物层、第一金属层，刻蚀第一金属氧化物层、第一金属层，以形成第一半导体层和源极、第二半导体层和漏极；在第一半导体层和第二半导体层之间形成第三半导体层。

Description

薄膜晶体管及其制备方法、阵列基板 技术领域
本发明涉及阵列基板制造技术领域，尤其涉及一种薄膜晶体管及其制备方法、阵列基板。
 背景技术
有金属氧化物半导体因具有迁移率高、漏电流低、均一性好的特点，适用于大尺寸、柔性透明等应用领域中，并可制备出尺寸较小的薄膜晶体管器件。将金属氧化物半导体作为薄膜晶体管器件的有源层，能够提高显示透过率，从而使得金属氧化物半导体在显示领域中得到了高度的重视和研究。
目前，金属氧化物薄膜晶体管（Oxide TFT）的难点与问题点主要集中在Oxide TFT的高温光照下的偏压稳定性（NBTIS、PBTIS）和对环境（水、氧）的稳定性，而从工艺角度考虑，这主要是由于器件制备工艺过程中，金属层刻蚀时的酸蚀刻液与金属氧化物有源层反应或出现残留，造成对金属氧化物有源层的损坏，从而使器件稳定性变差。
 技术问题
为了解决上述问题，本发明提供一种薄膜晶体管及其制备方法、阵列基板，能够避免对有源层造成损坏，提升器件的稳定性。
 技术解决方案
本发明提出的具体技术方案为：提供一种薄膜晶体管的制备方法，所述制备方法包括步骤：
提供一衬底；
通过构图工艺在所述衬底上形成栅极和栅绝缘层，所述栅绝缘层包括源区、背沟道区、漏区，所述背沟道区位于所述源区和所述漏区之间；
在所述栅绝缘层上沉积第一金属氧化物层、第一金属层，刻蚀所述第一金属氧化物层、第一金属层，以形成位于源区的第一半导体层和源极、位于漏区的第二半导体层和漏极；
通过构图工艺在所述背沟道区形成第三半导体层，所述第一半导体层、第二半导体层、第三半导体层构成有源层。
在本申请实施例所提供的薄膜晶体管的制备方法中，在所述栅绝缘层上沉积第一金属氧化物层、第一金属层，刻蚀所述第一金属氧化物层、第一金属层，以形成位于源区的第一半导体层和源极、位于漏区的第二半导体层和漏极步骤具体包括：
在所述栅绝缘层上沉积第一金属氧化物层；
图案化所述第一金属氧化物层，以获得图案化的金属氧化物层；
在所述图案化的金属氧化物层上沉积第一金属层；
刻蚀所述第一金属层、图案化的金属氧化物层，形成位于源区的第一半导体层和源极、位于漏区的第二半导体层和漏极。
在本申请实施例所提供的薄膜晶体管的制备方法中，在所述栅绝缘层上沉积第一金属氧化物层、第一金属层，刻蚀所述第一金属氧化物层、第一金属层，以形成位于源区的第一半导体层和源极、位于漏区的第二半导体层和漏极步骤具体包括：
在所述栅绝缘层上依次沉积第一金属氧化物层、第一金属层、光刻胶；
图案化所述第一金属氧化物层、第一金属层、光刻胶；
去除光刻胶，形成位于源区的第一半导体层和源极、位于漏区的第二半导体层和漏极。
在本申请实施例所提供的薄膜晶体管的制备方法中，通过构图工艺在所述背沟道区形成第三半导体层步骤具体包括：
在所述源极、漏极上沉积第二金属氧化物层；
图形化所述第二金属氧化物层，在所述背沟道区形成第三半导体层。
在本申请实施例所提供的薄膜晶体管的制备方法中，通过构图工艺在所述衬底上形成栅极和栅绝缘层步骤具体包括：
在所述衬底上沉积第二金属层；
图像化所述第二金属层，在所述衬底上形成栅极；
在所述衬底上沉积一绝缘材料层，形成栅绝缘层。
在本申请实施例所提供的薄膜晶体管的制备方法中，在通过构图工艺在所述背沟道区形成第三半导体层步骤之后，所述制备方法还包括：
在所述源极、漏极上沉积钝化材料层，形成钝化层。
在本申请实施例所提供的薄膜晶体管的制备方法中，所述第一金属氧化物层的材质为铟镓锌氧化物、铝掺杂氧化锌、氧化铟。
本发明还提供一种薄膜晶体管，采用如上任一项所述的方法制备而成。
本发明还提供了一种阵列基板，所述阵列基板包括如上所述的薄膜晶体管。
在本申请实施例所提供的薄膜晶体管的制备方法中，所述阵列基板还包括像素电极层，所述像素电极层通过过孔与所述漏极连接。
 有益效果
本发明提出的薄膜晶体管的制备方法，在对所述第一金属层进行刻蚀得到源极、漏极时将第一金属氧化物层位于背沟道区中的部分也刻蚀掉，然后通过构图工艺在背沟道区形成第三半导体层，使得第一半导体层、第二半导体层、第三半导体层构成薄膜晶体管的有源层，从而避免了形成源极、漏极采用的酸蚀刻液对有源层造成损坏，提升了薄膜晶体管的稳定性。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为实施例1中阵列基板的结构示意图；
图2a～2k为实施例1中薄膜晶体管的制备方法流程图；
图3a～3j为实施例2中薄膜晶体管的制备方法流程图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是用以相同标号表示。
参照图1，本实施例中的阵列基板包括阵列设置的多个薄膜晶体管1，每个薄膜晶体管1包括衬底11、栅极12、栅绝缘层13、有源层14、源极15、漏极16。其中，薄膜晶体管1的结构为底栅结构，栅极12设置于衬底11上，栅绝缘层13覆盖衬底11和栅极12，栅绝缘层13包括源区10、背沟道区20、漏区30，背沟道区位于源区10和漏区30之间，源区10、背沟道区20、漏区30与栅极12相对设置。有源层14包括第一半导体层14a、第二半导体层14b、第三半导体层14c，第一半导体层14a、源极15沿着远离栅绝缘层13的方向依次堆叠设于源区10中，即源极15位于第一半导体层14a上，第二半导体层14b、漏极16沿着远离栅绝缘层13的方向依次堆叠设于漏区30中，即漏极16位于第二半导体层14b上，第三半导体层14c位于背沟道区20中并与第一半导体层14a、第二半导体层14b连接。
薄膜晶体管1还包括钝化层17，钝化层17设于源极15、漏极16上并覆盖源极15、漏极16。钝化层17起到保护源极15、漏极16的作用。
本实施例中的阵列基板还包括像素电极2，像素电极2设于钝化层17上并通过过孔40与漏极16连接。
参照图2a～2k，下面详细描述本实施例中薄膜晶体管1的制备方法，所述制备方法包括步骤：
S1、提供一衬底11，如图2a所示。
S2、通过构图工艺在衬底11上形成栅极12和栅绝缘层13，栅绝缘层13包括源区10、背沟道区20、漏区30，背沟道区20位于源区10和漏区30之间，如图2b～2d所示。
S3、在栅绝缘层13上沉积第一金属氧化物层21、第一金属层22，刻蚀第一金属氧化物层21、第一金属层22，以形成位于源区10的第一半导体层14a和源极15、位于漏区30的第二半导体层14b和漏极16，如图2e～2h所示。
S4、通过构图工艺在背沟道区20形成第三半导体层14c，第一半导体层14a、第二半导体层14b、第三半导体层14c构成有源层14，如图2i～2j所示。
具体地，步骤S2包括：
S21、在衬底11上沉积第二金属层23，如图2b所示。
S22、图像化第二金属层23，在衬底11上形成栅极12，其中，图像化采用的是湿法刻蚀工艺，如图2c所示。
S23、在衬底11上沉积一绝缘材料层，形成栅绝缘层13，如图2d所示。
具体地，步骤S3包括：
S31、在栅绝缘层13上沉积第一金属氧化物层21，如图2e所示。
S32、图案化第一金属氧化物层21，以获得图案化的金属氧化物层24，如图2f所示。
S33、在图案化的金属氧化物层24上沉积第一金属层22，如图2g所示。
S34、刻蚀第一金属层22、图案化的金属氧化物层24，形成位于源区10的第一半导体层14a和源极15、位于漏区30的第二半导体层14b和漏极16，这里的刻蚀方法为湿法刻蚀，如图2h所示。
具体地，步骤S4包括：
S41、在源极15、漏极16上沉积第二金属氧化物层25，如图2i所示。
S42、图形化第二金属氧化物层25，在背沟道区形成第三半导体层14c，如图2j所示。
本实施例中的薄膜晶体管1还包括钝化层17，在步骤S4之后，所述制备方法还包括步骤：
S5、在源极15、漏极16上沉积钝化材料层，形成钝化层17，如图2k所示。
本实施例中的第一金属氧化物层21、第二金属氧化物层25的材质均为铟镓锌氧化物（IGZO）、铝掺杂氧化锌（AZO）、氧化铟（In2O3），即整个有源层14的材质为IGZO、AZO、In2O3。
本实施例提出的薄膜晶体管的制备方法，在对第一金属层22进行刻蚀得到源极15、漏极16时将第一金属氧化物层21位于背沟道区20中的部分也刻蚀掉，然后通过构图工艺在背沟道区20形成第三半导体层14c，使得第一半导体层14a、第二半导体层14b、第三半导体层14c构成薄膜晶体管的有源层14，从而避免了形成源极15、漏极16采用的酸蚀刻液对有源层14造成损坏，提升了薄膜晶体管的稳定性。
实施例2
本实施例中阵列基板的结构与实施例1中相同，这里不再赘述。本实施例与实施例1的不同之处为薄膜晶体管的制备方法，参照图3a～3j，下面详细描述本实施例中薄膜晶体管1的制备方法，所述制备方法包括步骤：
S1、提供一衬底11，如图3a所示。
S2、通过构图工艺在衬底11上形成栅极12和栅绝缘层13，栅绝缘层13包括源区10、背沟道区20、漏区30，背沟道区20位于源区10和漏区30之间，如图3b～3d所示。
S3、在栅绝缘层13上沉积第一金属氧化物层21、第一金属层22，刻蚀第一金属氧化物层21、第一金属层22，以形成位于源区10的第一半导体层14a和源极15、位于漏区30的第二半导体层14b和漏极16，如图3e～3g所示。
S4、通过构图工艺在背沟道区20形成第三半导体层14c，第一半导体层14a、第二半导体层14b、第三半导体层14c构成有源层14，如图3h～3i所示。
具体地，步骤S2包括：
S21、在衬底11上沉积第二金属层23，如图3b所示。
S22、图像化第二金属层23，在衬底11上形成栅极12，其中，图像化采用的是湿法刻蚀工艺，如图3c所示。
S23、在衬底11上沉积一绝缘材料层，形成栅绝缘层13，如图3d所示。
具体地，步骤S3包括：
S31、在栅绝缘层13上依次沉积第一金属氧化物层21、第一金属层22、光刻胶26，如图3e所示。
S32、图案化第一金属氧化物层21、第一金属层22、光刻胶26，如图3f所示，这里的图案化工艺包括曝光、显影、刻蚀工艺，其中刻蚀工艺为湿法刻蚀工艺，如图3f所示。
S33、去除光刻胶，形成位于源区10的第一半导体层14a和源极15、位于漏区30的第二半导体层14b和漏极16，如图3g所示。
具体地，步骤S4包括：
S41、在源极15、漏极16上沉积第二金属氧化物层25，如图3h所示。
S42、图形化第二金属氧化物层25，在背沟道区形成第三半导体层14c，如图3i所示。
本实施例中的薄膜晶体管1还包括钝化层17，在步骤S4之后，所述制备方法还包括步骤：
S5、在源极15、漏极16上沉积钝化材料层，形成钝化层17，如图3j所示。
本实施例提出的薄膜晶体管的制备方法相对于实施例1中的制备方法减少了图案化处理的次数，因此，本实施例中的制备方法在避免形成源极15、漏极16采用的酸蚀刻液对有源层14造成损坏、提升薄膜晶体管的稳定性的同时简化了制备工艺、降低了成本。
以上所述仅是本申请的具体实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本申请原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本申请的保护范围。

Claims (10)

  1. 一种薄膜晶体管的制备方法，其中，所述制备方法包括步骤：
    提供一衬底；
    通过构图工艺在所述衬底上形成栅极和栅绝缘层，所述栅绝缘层包括源区、背沟道区、漏区，所述背沟道区位于所述源区和所述漏区之间；
    在所述栅绝缘层上沉积第一金属氧化物层、第一金属层，刻蚀所述第一金属氧化物层、第一金属层，以形成位于源区的第一半导体层和源极、位于漏区的第二半导体层和漏极；
    通过构图工艺在所述背沟道区形成第三半导体层，所述第一半导体层、第二半导体层、第三半导体层构成有源层。
  2. 根据权利要求1所述的制备方法，其中，在所述栅绝缘层上沉积第一金属氧化物层、第一金属层，刻蚀所述第一金属氧化物层、第一金属层，以形成位于源区的第一半导体层和源极、位于漏区的第二半导体层和漏极步骤具体包括：
    在所述栅绝缘层上沉积第一金属氧化物层；
    图案化所述第一金属氧化物层，以获得图案化的金属氧化物层；
    在所述图案化的金属氧化物层上沉积第一金属层；
    刻蚀所述第一金属层、图案化的金属氧化物层，形成位于源区的第一半导体层和源极、位于漏区的第二半导体层和漏极。
  3. 根据权利要求1所述的制备方法，其中，在所述栅绝缘层上沉积第一金属氧化物层、第一金属层，刻蚀所述第一金属氧化物层、第一金属层，以形成位于源区的第一半导体层和源极、位于漏区的第二半导体层和漏极步骤具体包括：
    在所述栅绝缘层上依次沉积第一金属氧化物层、第一金属层、光刻胶；
    图案化所述第一金属氧化物层、第一金属层、光刻胶；
    去除光刻胶，形成位于源区的第一半导体层和源极、位于漏区的第二半导体层和漏极。
  4. 根据权利要求1所述的制备方法，其中，通过构图工艺在所述背沟道区形成第三半导体层步骤具体包括：
    在所述源极、漏极上沉积第二金属氧化物层；
    图形化所述第二金属氧化物层，在所述背沟道区形成第三半导体层。
  5. 根据权利要求4所述的制备方法，其中，通过构图工艺在所述衬底上形成栅极和栅绝缘层步骤具体包括：
    在所述衬底上沉积第二金属层；
    图像化所述第二金属层，在所述衬底上形成栅极；
    在所述衬底上沉积一绝缘材料层，形成栅绝缘层。
  6. 根据权利要求1所述的制备方法，其中，通过构图工艺在所述背沟道区形成第三半导体层步骤之后，所述制备方法还包括：
    在所述源极、漏极上沉积钝化材料层，形成钝化层。
  7. 根据权利要求1所述的制备方法，其中，所述第一金属氧化物层的材质为铟镓锌氧化物、铝掺杂氧化锌、氧化铟。
  8. 一种薄膜晶体管，其采用如权利要求 1所述的方法制备而成。
  9. 一种阵列基板，其包括如权利要求8所述的薄膜晶体管。
  10. 根据权利要求9所述的阵列基板，其中，所述阵列基板还包括像素电极层，所述像素电极层通过过孔与所述漏极连接。
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