JP2004040108A - Ldd構造を有する薄膜トランジスタとその製造方法 - Google Patents
Ldd構造を有する薄膜トランジスタとその製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 51
- 239000010409 thin film Substances 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- 239000000463 material Substances 0.000 claims abstract description 34
- 150000002500 ions Chemical class 0.000 claims description 45
- 238000000034 method Methods 0.000 claims description 13
- 125000006850 spacer group Chemical group 0.000 claims description 12
- 208000022010 Lhermitte-Duclos disease Diseases 0.000 claims description 5
- 239000002784 hot electron Substances 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 118
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 38
- 229920005591 polysilicon Polymers 0.000 description 31
- 238000005468 ion implantation Methods 0.000 description 16
- 239000002019 doping agent Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 239000011521 glass Substances 0.000 description 9
- 238000005224 laser annealing Methods 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 239000000758 substrate Substances 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 230000008025 crystallization Effects 0.000 description 4
- 238000005499 laser crystallization Methods 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VRAIHTAYLFXSJJ-UHFFFAOYSA-N alumane Chemical compound [AlH3].[AlH3] VRAIHTAYLFXSJJ-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000006356 dehydrogenation reaction Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
Abstract
【解決手段】 単一LDD構造を有する薄膜トランジスタが提供される。単一LDD構造224がソース/ドレイン構造2211,2221の間に配置される。その単一LDD224構造は、ソース/ドレイン構造の第1の構造に隣接した第1の側面と、そのソース/ドレイン構造の第2の構造に対して本質的に半導体物質223で隔てられた第2の側面とを有する。他の薄膜トランジスタとして、第1のLDD構造と第2のLDD構造を有し、第2のLDD構造が第1のLDD構造に隣接したものが提供される。このような薄膜トランジスタの製造工程が開示される。
【選択図】 図2(f)
Description
25,33,45,53 絶縁層
26,34,46 ゲート構造
35,55 スペーサ構造
221,222,321,322,421,422,521,522 ソース/ドレイン構造
223,323,423,523 チャンネル領域
224,324 単一LDD構造
425,426,427,428,525,526,527,528 LDD構造
Claims (14)
- 薄膜トランジスタであって、
半導体物質で形成された半導体層と、
前記半導体層において互いに離れて形成されたソース構造及びドレイン構造からなるソース/ドレイン構造と、
前記ソース/ドレイン構造の間に配置され、そのソース/ドレイン構造の第1の構造に隣接した側面と、そのソース/ドレイン構造の第2の構造に対して本質的に前記半導体物質で隔てられた側面とを有する単一LDD構造と、
前記半導体層の上方に形成されたゲート構造と、
前記半導体層とゲート構造の間に配置されゲート構造を前記ソース/ドレイン構造及びLDD構造から絶縁する絶縁層と、を備えていることを特徴とする薄膜トランジスタ。 - 前記単一LDD構造が、ゲートとドレインが重なりを有するLDD(GO−LDD)である請求項1に記載の薄膜トランジスタ。
- 前記ソース/ドレイン構造の第1の構造がドレイン構造であり、前記ソース/ドレイン構造の第2の構造がソース構造である請求項1に記載の薄膜トランジスタ。
- 前記薄膜トランジスタがN型であり、前記LDD構造がPイオン、Asイオン、PHxイオン、AsHxイオン、及びこれらの組合せの中から選択されたドーピング物質を含んでいる請求項1に記載の薄膜トランジスタ。
- 薄膜トランジスタであって、
半導体物質で形成された半導体層と、
前記半導体層において互いに離れて形成されたソース構造及びドレイン構造からなるソース/ドレイン構造と、
前記ソース/ドレイン構造の間に配置され、そのソース/ドレイン構造の第1の構造に隣接した第1の側面と、その第1の側面の反対側に第2の側面を有する第1のLDD構造と、
前記第1のLDD構造の前記第2の側面に隣接した第3の側面と、前記ソース/ドレイン構造の第2の構造に対して本質的に前記半導体物質で隔てられた第4の側面とを有する第2のLDD構造と、
前記半導体層の上方に形成されたゲート構造と、
前記半導体層とゲート構造の間に配置されゲート構造を前記ソース/ドレイン構造及びLDD構造から絶縁する絶縁層と、を備えていることを特徴とする薄膜トランジスタ。 - 前記第1及び第2のLDD構造が、ゲートとドレインが重なりを有するLDD(GO−LDD)である請求項5に記載の薄膜トランジスタ。
- 前記薄膜トランジスタがN型であり、前記第1のLDD構造がPイオン、Asイオン、PHxイオン、AsHxイオン、及びこれらの組合せの中から選択されたドーピング物質を含んでおり、前記第2のLDD構造がBイオン、BHxイオン、B2Hxイオン、及びこれらの組合せの中から選択されたドーピング物質を含んでいる請求項5に記載の薄膜トランジスタ。
- 前記ソース/ドレイン構造の間に配置され、そのソース/ドレイン構造の第2の構造に隣接した第5の側面と、その第5の側面の反対側に第6の側面を有する第3のLDD構造と、
前記第3のLDD構造の前記第6の側面に隣接した第7の側面と、前記ソース/ドレイン構造の第2の構造に対して本質的に前記半導体物質で隔てられた第8の側面とを有する第4のLDD構造と、をさらに備えた請求項5に記載の薄膜トランジスタ。 - 少なくとも前記第1及び第3のLDD構造の一部が、前記第2及び第4のLDD構造及び前記ソース/ドレイン構造によって覆われていない請求項8に記載の薄膜トランジスタ。
- 前記第1のLDD構造が前記第2のLDD構造及び前記ソース/ドレイン構造の第1の構造によって囲まれており、前記第3のLDD構造が前記第4のLDD構造及び前記ソース/ドレイン構造の第2の構造によって囲まれている請求項8に記載の薄膜トランジスタ。
- 薄膜トランジスタの製造方法であって、
半導体層を形成する工程と、
前記半導体層の上にゲート絶縁層を形成する工程と、
前記ゲート絶縁層の上にゲート構造を形成する工程と、
前記半導体層にチャネル領域で互いに隔てられたソース/ドレイン構造を形成する工程と、
第1のLDD構造を形成するために、前記半導体層の表面から第1の角度の第1の方向で前記チャネル領域の第1の端部に第1のドーピング物質を注入する工程と、
前記第1のLDD構造に接触している第2のLDD構造を形成するために、前記半導体層の前記表面から第2の角度の第2の方向で前記チャネル領域の前記第1の端部に第2のドーピング物質を注入する工程と、を備えていることを特徴とする薄膜トランジスタの製造方法。 - 前記第1のドーピング物質を注入する前記工程が、前記ゲート構造をマスクとして用いて前記チャネル領域に対して行われ、
第3のLDD構造が、前記第1のLDD構造が形成される時、前記チャネル領域における第1の端部の反対側の第2の端部に同時に形成される請求項11に記載の薄膜トランジスタの製造方法。 - 前記第3のLDD構造に接触している第4のLDD構造を形成するために、前記半導体層の前記表面から第3の角度の第3の方向で前記チャネル領域の前記第2の端部に第3のドーピング物質を注入する工程をさらに備えている請求項12に記載の薄膜トランジスタの製造方法。
- 前記ゲート構造が、ゲート電極とその電極のそばのスペーサ構造を含み、
前記第1のドーピング物質を注入する前記工程が、前記スペーサ構造が除去された後に行われる請求項11に記載の薄膜トランジスタの製造方法。
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TW091115101A TW544941B (en) | 2002-07-08 | 2002-07-08 | Manufacturing process and structure of thin film transistor |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006287205A (ja) * | 2005-03-07 | 2006-10-19 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7176095B1 (en) * | 2004-03-01 | 2007-02-13 | Advanced Micro Devices, Inc. | Bi-modal halo implantation |
US7745293B2 (en) * | 2004-06-14 | 2010-06-29 | Semiconductor Energy Laboratory Co., Ltd | Method for manufacturing a thin film transistor including forming impurity regions by diagonal doping |
US7504327B2 (en) * | 2004-06-14 | 2009-03-17 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing thin film semiconductor device |
US7144782B1 (en) | 2004-07-02 | 2006-12-05 | Advanced Micro Devices, Inc. | Simplified masking for asymmetric halo |
US7211489B1 (en) * | 2004-09-07 | 2007-05-01 | Advanced Micro Devices, Inc. | Localized halo implant region formed using tilt pre-amorphization implant and laser thermal anneal |
US7210499B2 (en) * | 2005-01-18 | 2007-05-01 | Dale Carpenter | Methods and apparatus for a direct connect on-off controller |
TW200627643A (en) * | 2005-01-19 | 2006-08-01 | Quanta Display Inc | A method for manufacturing a thin film transistor |
US20060197088A1 (en) * | 2005-03-07 | 2006-09-07 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method of the same |
KR101239889B1 (ko) * | 2005-08-13 | 2013-03-06 | 삼성디스플레이 주식회사 | 박막 트랜지스터 기판 및 그 제조 방법 |
US7495258B2 (en) * | 2006-05-17 | 2009-02-24 | Tpo Displays Corp. | N-channel TFT and OLED display apparatus and electronic device using the same |
CN103050410B (zh) * | 2012-10-30 | 2015-09-16 | 昆山工研院新型平板显示技术中心有限公司 | 低温多晶硅薄膜晶体管的制造方法、低温多晶硅薄膜晶体管 |
CN104779167A (zh) * | 2015-04-09 | 2015-07-15 | 京东方科技集团股份有限公司 | 多晶硅薄膜晶体管及其制备方法、阵列基板、显示面板 |
TWI759751B (zh) * | 2020-05-29 | 2022-04-01 | 逢甲大學 | 短通道複晶矽薄膜電晶體及其方法 |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58204570A (ja) * | 1982-05-24 | 1983-11-29 | Seiko Epson Corp | 半導体集積回路装置の製造方法 |
JPH0414262A (ja) * | 1990-05-07 | 1992-01-20 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JPH05307189A (ja) * | 1992-01-31 | 1993-11-19 | Canon Inc | 半導体装置及び液晶表示装置 |
JPH06232160A (ja) * | 1993-02-01 | 1994-08-19 | Fuji Xerox Co Ltd | 薄膜トランジスタの製造方法 |
JPH104198A (ja) * | 1996-03-13 | 1998-01-06 | Texas Instr Inc <Ti> | ハロー注入を有するシリコン上半導体トランジスタ |
JP2000196091A (ja) * | 1998-12-24 | 2000-07-14 | Hitachi Ltd | 半導体集積回路装置 |
JP2001085692A (ja) * | 1999-08-12 | 2001-03-30 | Internatl Business Mach Corp <Ibm> | 半導体デバイスおよびその製造方法 |
JP2001308337A (ja) * | 2000-04-24 | 2001-11-02 | Matsushita Electric Ind Co Ltd | 低温ポリシリコンtftの製造方法 |
JP2002076361A (ja) * | 2000-09-05 | 2002-03-15 | Sharp Corp | 半導体装置およびその製造方法および画像表示装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52156576A (en) * | 1976-06-23 | 1977-12-27 | Hitachi Ltd | Production of mis semiconductor device |
JPS61191070A (ja) * | 1985-02-20 | 1986-08-25 | Toshiba Corp | 半導体装置の製造方法 |
US4949136A (en) * | 1988-06-09 | 1990-08-14 | University Of Connecticut | Submicron lightly doped field effect transistors |
KR940004446B1 (ko) * | 1990-11-05 | 1994-05-25 | 미쓰비시뎅끼 가부시끼가이샤 | 반도체장치의 제조방법 |
JP3370806B2 (ja) | 1994-11-25 | 2003-01-27 | 株式会社半導体エネルギー研究所 | Mis型半導体装置の作製方法 |
US6165876A (en) | 1995-01-30 | 2000-12-26 | Yamazaki; Shunpei | Method of doping crystalline silicon film |
US5917199A (en) | 1998-05-15 | 1999-06-29 | Ois Optical Imaging Systems, Inc. | Solid state imager including TFTS with variably doped contact layer system for reducing TFT leakage current and increasing mobility and method of making same |
US6071762A (en) | 1998-11-16 | 2000-06-06 | Industrial Technology Research Institute | Process to manufacture LDD TFT |
US6281552B1 (en) | 1999-03-23 | 2001-08-28 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistors having ldd regions |
-
2002
- 2002-07-08 TW TW091115101A patent/TW544941B/zh not_active IP Right Cessation
- 2002-10-02 US US10/263,077 patent/US6747325B2/en not_active Expired - Lifetime
-
2003
- 2003-07-03 JP JP2003270766A patent/JP2004040108A/ja active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58204570A (ja) * | 1982-05-24 | 1983-11-29 | Seiko Epson Corp | 半導体集積回路装置の製造方法 |
JPH0414262A (ja) * | 1990-05-07 | 1992-01-20 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JPH05307189A (ja) * | 1992-01-31 | 1993-11-19 | Canon Inc | 半導体装置及び液晶表示装置 |
JPH06232160A (ja) * | 1993-02-01 | 1994-08-19 | Fuji Xerox Co Ltd | 薄膜トランジスタの製造方法 |
JPH104198A (ja) * | 1996-03-13 | 1998-01-06 | Texas Instr Inc <Ti> | ハロー注入を有するシリコン上半導体トランジスタ |
JP2000196091A (ja) * | 1998-12-24 | 2000-07-14 | Hitachi Ltd | 半導体集積回路装置 |
JP2001085692A (ja) * | 1999-08-12 | 2001-03-30 | Internatl Business Mach Corp <Ibm> | 半導体デバイスおよびその製造方法 |
JP2001308337A (ja) * | 2000-04-24 | 2001-11-02 | Matsushita Electric Ind Co Ltd | 低温ポリシリコンtftの製造方法 |
JP2002076361A (ja) * | 2000-09-05 | 2002-03-15 | Sharp Corp | 半導体装置およびその製造方法および画像表示装置 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006287205A (ja) * | 2005-03-07 | 2006-10-19 | Semiconductor Energy Lab Co Ltd | 半導体装置及びその作製方法 |
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TW544941B (en) | 2003-08-01 |
US6747325B2 (en) | 2004-06-08 |
US20040065924A1 (en) | 2004-04-08 |
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