WO2017197678A1 - 一种阵列基板及其制备方法 - Google Patents

一种阵列基板及其制备方法 Download PDF

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Publication number
WO2017197678A1
WO2017197678A1 PCT/CN2016/085468 CN2016085468W WO2017197678A1 WO 2017197678 A1 WO2017197678 A1 WO 2017197678A1 CN 2016085468 W CN2016085468 W CN 2016085468W WO 2017197678 A1 WO2017197678 A1 WO 2017197678A1
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Prior art keywords
layer
photoresist
source
pattern
substrate
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PCT/CN2016/085468
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English (en)
French (fr)
Inventor
徐洪远
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深圳市华星光电技术有限公司
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Priority to US15/111,442 priority Critical patent/US10020301B2/en
Publication of WO2017197678A1 publication Critical patent/WO2017197678A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a method for fabricating the same.
  • Liquid crystal display panel (Liquid crystal Display, LCDs) is a widely used flat panel display, which mainly uses the liquid crystal switch to modulate the intensity of the backlight light field to realize the screen display.
  • the process of the LCDs includes the process of the array substrate.
  • the process of the conventional array substrate generally adopts five mask technologies or four mask technologies.
  • the five mask technologies are the gate electrode, the semiconductor layer, the source and drain, the passivation layer and the transparent electrode layer. They are prepared by a photomask.
  • the four-mask technology is to simultaneously form the semiconductor layer and the source drain with a halftone mask or a multi-gray mask.
  • An object of the present invention is to provide an array substrate and a preparation method thereof, which aim to solve the problem that the number of masks in the array substrate is too large, resulting in high process cost, long operation time, and low production efficiency.
  • the present invention provides a method for preparing an array substrate, the method comprising:
  • the ITO conductive layer was patterned using a third mask process to form an ITO pixel electrode.
  • the present invention provides a method for preparing an array substrate, the method comprising:
  • An ITO pixel electrode is formed on the contact hole pattern and the passivation layer.
  • a gate insulating layer, a semiconductor layer, a source/drain metal layer and a passivation layer are deposited on the gate electrode and the substrate, and the semiconductor layer, the source/drain metal layer and the passivation layer are patterned by a mask process to form a semiconductor
  • the pattern, the source drain pattern and the contact hole pattern include:
  • the semiconductor layer, the source/drain metal layer, and the first photoresist are patterned by a photomask to form a semiconductor pattern, a source and drain pattern, and a remaining second photoresist, and the remaining second photoresist is located in the source/drain metal layer. on;
  • the passivation layer on the second photoresist and the second photoresist is removed to form a contact hole pattern.
  • the patterning process of the semiconductor layer, the source/drain metal layer, and the first photoresist by using a photomask to form the semiconductor pattern, the source and drain patterns, and the remaining second photoresist includes:
  • the second area photoresist and the third area photoresist are ashed to form a source drain pattern, and the third area photoresist is left with a second photoresist.
  • the reticle is a multi-gray reticle, and the multi-gray reticle has four different transmittances.
  • the light transmittance of the first portion of the photoresist corresponding to the first region of the multi-gray mask is smaller than the transmittance of the second portion of the photoresist corresponding to the second region of the multi-gray mask, and the multi-gray mask corresponds to the second region.
  • the light transmissivity of the second portion of the photoresist is less than the transmittance of the third portion of the photoresist of the third region corresponding to the third region, and the multi-gray mask removes the remaining portions of the first portion, the second portion, and the third portion It is impervious to the membrane.
  • the method comprises:
  • the second photoresist is illuminated with a laser.
  • the removing the passivation layer on the second photoresist and the second photoresist to form the contact hole pattern includes:
  • the passivation layer on the second photoresist and the second photoresist is removed by the lithography process to form a contact hole pattern.
  • the sequentially depositing a gate insulating layer, a semiconductor layer, and a source/drain metal layer on the gate electrode and the substrate includes:
  • a source/drain metal layer is deposited on the semiconductor layer by physical vapor deposition.
  • depositing a semiconductor layer on the gate electrode and the substrate by using a chemical vapor deposition technique includes:
  • the amorphous silicon layer is doped to form a doped amorphous silicon layer.
  • the doped amorphous silicon layer is an N+ doped amorphous silicon layer.
  • forming the ITO pixel electrode on the contact hole pattern and the passivation layer comprises:
  • the ITO conductive layer was patterned using a third mask process to form an ITO pixel electrode.
  • depositing the ITO conductive layer on the passivation layer comprises:
  • ITO conductive layer is deposited on the passivation layer by physical vapor deposition.
  • the third mask process is a yellow light process, including development, wet etching and dry etching.
  • forming the gate electrode on a substrate comprises:
  • the gate metal layer is patterned using a first mask process to form a gate electrode.
  • the material of the gate metal layer is gold, silver, copper or iron.
  • the first mask process is a yellow light process, including development, wet etching and dry etching.
  • an array substrate comprising:
  • a gate insulating layer a semiconductor layer, a source/drain metal layer, a passivation layer formed on the gate electrode and the substrate, and a semiconductor pattern, a source drain pattern, and a contact hole pattern formed by a mask process;
  • An ITO pixel electrode formed on the contact hole pattern and the passivation layer.
  • the gate electrode is formed in a process of patterning the gate metal layer on the substrate by using the first mask process.
  • the ITO pixel electrode is formed in a process of patterning the contact hole pattern and the ITO conductive layer on the passivation layer by a third mask process.
  • the present invention forms a gate electrode on a substrate; deposits a gate insulating layer, a semiconductor layer, a source/drain metal layer and a passivation layer on the gate electrode and the substrate,
  • the semiconductor layer, the source/drain metal layer and the passivation layer are patterned by a mask process to form a semiconductor pattern, a source drain pattern and a contact hole pattern; and an ITO pixel electrode is formed on the contact hole pattern and the passivation layer.
  • the present invention utilizes a mask process to form a semiconductor pattern, a source drain pattern, and a contact hole pattern, so that the process of the array substrate is reduced to three masks, thereby reducing process cost, reducing operation time, and improving production efficiency.
  • FIG. 1 is a schematic flow chart of a first embodiment of a method for preparing an array substrate of the present invention
  • FIG. 2 is a schematic diagram of a specific process of step S1 in FIG. 1;
  • 3a-3b are schematic cross-sectional views of the array substrate in each step of FIG. 2;
  • step S2 in FIG. 1 is a schematic diagram of a specific process of step S2 in FIG. 1;
  • 5a-5d are schematic cross-sectional views of the array substrate in each step of FIG. 4;
  • FIG. 6 is a schematic diagram of a specific process of step S3 in FIG. 1;
  • FIG. 7a-7b are schematic cross-sectional views of the array substrate in each step of FIG. 6;
  • FIG. 8 is a schematic flow chart of a second embodiment of a method for preparing an array substrate of the present invention.
  • 9a-9j are schematic cross-sectional views of the array substrate in each step of FIG. 8;
  • Figure 10 is a schematic cross-sectional view showing a first embodiment of the array substrate of the present invention.
  • FIG. 1 it is a flowchart of a first embodiment of a method for fabricating an array substrate of the present invention.
  • the method for preparing the array substrate specifically includes the following steps:
  • the substrate 101 may be PEN (Polyethylene naphthalene, polyethylene naphthalate) Or PET (Polyethylene terephthalate) or PI (Polyimide, polyimide) or glass.
  • PEN Polyethylene naphthalene, polyethylene naphthalate
  • PET Polyethylene terephthalate
  • PI Polyimide, polyimide
  • the step may specifically include:
  • the material of the gate metal layer 102 includes but is not limited to materials such as gold, silver, copper or iron, please refer to FIG. 3a;
  • the gate metal layer 102 is patterned by using a first mask process to form the gate electrode 1021.
  • the gate metal layer 102 may be patterned by a yellow mask process (such as development, wet etching, dry etching, etc.). At this time, the processed gate metal layer 102 may serve as the gate electrode 1021.
  • the gate electrode 1021 is a bottom gate electrode 1021 and may be located in the middle of the upper surface of the substrate 101, see FIG. 3b.
  • the pattern of the top view of the bottom gate electrode 1021 includes, but is not limited to, a pattern of a straight line pattern, a curved pattern, a polygonal pattern, a circular pattern, an elliptical pattern, or a star pattern. It can be understood that the specific pattern shape can be determined according to actual use. The embodiment of the present invention is not specifically limited herein.
  • S2 depositing a gate insulating layer 103, a semiconductor layer 104, a source/drain metal layer 105, and a passivation layer 107 on the gate electrode 1021 and the substrate 101, and bonding the semiconductor layer 104, the source/drain metal layer 105, and the passivation through a mask process
  • the layer 107 is patterned to form a semiconductor pattern 1041, a source drain pattern 1051, and a contact hole pattern 108;
  • the step may include:
  • S103 sequentially depositing a gate insulating layer 103, a semiconductor layer 104, and a source/drain metal layer 105 on the gate electrode 1021 and the substrate 101, and covering the first photoresist 106;
  • a gate insulating layer 103 is first deposited on the gate electrode 1021 and the substrate 101 by chemical vapor deposition.
  • the gate insulating layer 103 covers the gate electrode 1021, and the gate insulating layer 103 is away from the gate electrode 1021.
  • the surface can be selected as a flat surface;
  • a semiconductor layer 104 is deposited on the gate insulating layer 103, and a first layer of amorphous silicon (a-Si) semiconductor material (not shown) is first deposited on the gate insulating layer 103, in amorphous silicon.
  • a-Si amorphous silicon
  • Source/drain metal layer 105 Forming a source/drain metal layer 105 on the amorphous silicon semiconductor layer 104 by means of physical vapor deposition or the like, and the source/drain metal layer 105 includes, but not limited to, metals such as aluminum, copper, cobalt, and titanium;
  • the first photoresist 106 is covered on the source/drain metal layer 105.
  • the photoresist is a photosensitive material, and the portion left after exposure and development protects the underlayer, and then is etched and stripped to obtain a desired pattern. .
  • S104 patterning the semiconductor layer 104, the source/drain metal layer 105, and the first photoresist 106 by using a photomask to form the semiconductor pattern 1041, the source/drain pattern 1051, and the remaining second photoresist 1061, and remaining the second The photoresist 1061 is located above the source and drain metal layer 105;
  • step S104 referring to FIG. 5b, the semiconductor pattern 1041 can be formed by using a mask.
  • the source drain pattern 1051, and the second photoresist 1061 remaining after the first photoresist 106 is exposed and developed can prepare for the subsequent formation of the contact hole pattern 108, which greatly reduces the process flow and reduces the process cost.
  • the reticle can be selected with a multi-gray reticle, and the multi-gray reticle has different transmittances of 3 or more.
  • different photoresist thicknesses can be formed, which are the semiconductor layer 104, the source and drain metal layers.
  • the patterning process of 105 and the first photoresist 106 is prepared.
  • the semiconductor pattern 1041 includes a channel 1043, a doping region 1042, and a storage capacitor portion (not shown).
  • the source drain pattern 1051 includes a source electrode 1052, a drain electrode 1053, and a data line (not shown).
  • the second photoresist 1061 is located on the drain 1053 of the source/drain pattern 1051.
  • S105 depositing a passivation layer 107 on the substrate 101, the passivation layer 107 covering the gate insulating layer 103, the semiconductor pattern 1041, the source and drain pattern 1051 and the second photoresist 1061;
  • a passivation layer 107 is deposited on the substrate 101 by chemical vapor deposition.
  • the passivation layer 107 covers the gate insulating layer 103 exposed at both ends, the source/drain pattern 1051, the channel 1043 in the semiconductor pattern 1041, And a second photoresist 1061.
  • the passivation layer 107 on the second photoresist 1061 and the second photoresist 1061 is removed by a lift-off process.
  • the lift-off process is to pass the passivation layer 107 through the raised photoresist pattern.
  • a protrusion is formed at a position where the contact hole pattern 108 is formed, and the second photoresist 1061 is partially pulled up, that is, removed, and the passivation layer 107 on the second photoresist 1061 is also removed.
  • a recess is formed at the location where the photoresist 1061 is located, thereby forming the desired contact hole pattern 108, see Figure 5d.
  • the second photoresist 1061 may be irradiated with laser light before the second photoresist 1061 is removed, so that the second photoresist 1061 is more easily removed.
  • the contact hole pattern 108 is formed by the lift-off process, even if the formed contact hole pattern 108 is irregular, the display effect of the array substrate is not affected, mainly because the contact hole pattern 108 mainly serves as a connection.
  • the effect of the source drain and the pixel electrode does not affect the display effect; and the size of all the contact hole patterns 108 formed by this method is close to each other, and there is no problem that the uniformity is poor when the photoresist is removed.
  • An ITO pixel electrode 110 is formed on the contact hole pattern 108 and the passivation layer 107.
  • the step may include:
  • An ITO conductive layer 109 is deposited on the passivation layer 107 by physical vapor deposition as shown in FIG. 7a.
  • the ITO conductive layer 109 is patterned by a third mask process to form the ITO pixel electrode 110.
  • the third mask process may be a yellow light process, including development, wet etching, dry etching, etc., and the ITO conductive layer 109 is patterned by the third mask, and the processed ITO conductive layer 109 may serve as the pixel electrode 110. Use, as shown in Figure 7b.
  • the third mask process adopts a conventional yellow light process, and the formed ITO pixel electrode 110 can obtain the same display effect as that of the conventional five-mask or four-mask technology, and there is no use in the prior art.
  • the lift-off process when the ITO pixel electrode is fabricated, the edges of the pattern are not neat, the line width is difficult to control, and the display is uneven.
  • the gate electrode 1021 is formed on a substrate 101; the gate insulating layer 103, the semiconductor layer 104, the source/drain metal layer 105 are deposited on the gate electrode 1021 and the substrate 101, and The passivation layer 107 is patterned by a mask process to form the semiconductor layer 104, the source/drain metal layer 105, and the passivation layer 107 to form the semiconductor pattern 1041, the source/drain pattern 1051, and the contact hole pattern 108; An ITO pixel electrode 110 is formed on the 108 and the passivation layer 107.
  • the present invention utilizes a mask process to form the semiconductor pattern 1041, the source-drain pattern 1051, and the contact hole pattern 108, so that the process of the array substrate is reduced to three masks, thereby reducing process cost, reducing operation time, and improving Productivity.
  • FIG. 8 it is a second embodiment of the method for fabricating the array substrate of the present invention.
  • FIGS. 9 a - 9 j are schematic cross-sectional views of the steps in the embodiment. Referring to FIG. 8 and FIG. 9 , the method for preparing the array substrate is as follows. Including the following steps:
  • the substrate 201 may be PEN (Polyethylene) Naphthalene, polyethylene naphthalate) or PET (Polyethylene) Made of terephthalate, polyethylene terephthalate or PI (Polyimide, polyimide).
  • PEN Polyethylene
  • PET Polyethylene
  • PI Polyimide, polyimide
  • a gate metal layer (shown in the drawing) on the upper surface of the substrate 201 by sputtering or the like, and the material of the gate metal layer includes, but not limited to, materials such as gold, silver, copper or iron; using the first mask The process patterning the gate metal layer to form the gate electrode 202, as shown in Figure 9a.
  • S202 sequentially depositing a gate insulating layer 203, a semiconductor layer 204, and a source/drain metal layer 205 on the gate electrode 202 and the substrate 201, and covering the first photoresist 206;
  • a gate insulating layer 203 is first deposited on the gate electrode 202 and the substrate 201 by chemical vapor deposition.
  • the gate insulating layer 203 covers the gate electrode 202, and the gate insulating layer 203 is away from the gate electrode 202.
  • the surface can be selected as a flat surface;
  • a semiconductor layer 204 is deposited on the gate insulating layer 203.
  • a first layer of amorphous silicon (a-Si) semiconductor material (shown in the drawing) is first deposited on the gate insulating layer 203, and then amorphous.
  • a layer of highly doped silicon, such as an N+ layer is first deposited on the silicon layer to form an amorphous silicon semiconductor layer 204;
  • the source/drain metal layer 205 includes, but is not limited to, metals such as aluminum, copper, cobalt, and titanium;
  • the first photoresist 206 is covered on the source/drain metal layer 205.
  • the photoresist is a photosensitive material, and the portion left after exposure and development protects the underlayer, and then is etched and removed to obtain a desired pattern. .
  • S203 exposing the first photoresist 206 by using a mask 30, exposing the source/drain metal layer 205 at both ends of the substrate 201, and forming the first photoresist 206 into three different thicknesses, wherein the three different thicknesses are respectively
  • the first photoresist 206 corresponds to the thickness of the first region photoresist 2061 of the semiconductor pattern 2041
  • the first photoresist 206 corresponds to the thickness of the second region photoresist 2062 of the source/drain pattern 2051
  • the first photoresist 206 corresponds to the second photoresist.
  • the mask 30 is a multi-gray mask 30.
  • the multi-gray mask 30 has four different transmittances.
  • the ends of the multi-gray mask 30 are impermeable to the film 31.
  • the intermediate portion of the multi-gray mask 31 includes three materials 32/33/34 of different transmittances, so that the first photoresist 206 is exposed to form three.
  • a different thickness wherein the thickness of the first region photoresist 2061 is the smallest, the thickness of the third region photoresist 2063 is the largest, and the thickness of the second region photoresist 2062 is between the two.
  • the thickness of the first region photoresist 2061 is 0.5 ⁇ m
  • the thickness of the second region photoresist 2062 is 1 ⁇ m
  • the thickness of the third region photoresist 2063 is 2.5 ⁇ m.
  • the exposed source/drain metal layer 205 at both ends is removed by wet etching, and the semiconductor layer 204 under the source and drain metal layers 205 at both ends is removed by dry etching to expose the gate insulating layer 203 at both ends.
  • the first photoresist 206 having three different film thicknesses is subjected to ashing treatment by using an oxygen-burning photoresist, and the first region photoresist 2061 is removed, and the thickness of the removed region is 0.5 ⁇ m, so the second region after the cleaning is performed.
  • the remaining thickness of the photoresist 2062 is 0.5 ⁇ m
  • the remaining thickness of the third region photoresist 2063 is 2 ⁇ m.
  • the source/drain metal layer 205 under the original first region photoresist 2061 is removed by one dry etching and one wet etching, and the layer of highly doped silicon under the source and drain metal layers is removed.
  • the channel 2043 and the doping region 2042 are exposed to form a semiconductor pattern 2041.
  • the semiconductor pattern 2041 includes a channel 2043, a doping region 2042, and a storage capacitor portion (not shown).
  • the second region photoresist 2062 and the third region photoresist 2063 are ashed by an oxy-storage photoresist to form a source-drain pattern 2051.
  • the source-drain pattern 2051 includes a source electrode 2052 and a drain electrode 2053. Data line (not shown).
  • the thickness of the removed second region photoresist 2062 is 0.5 ⁇ m, so the remaining thickness of the third region photoresist 2063 is 1.5 ⁇ m, and the remaining third region photoresist 2063 is referred to as a second photoresist 2064, and the second photoresist 2064 is located.
  • the source drain pattern 2051 is on the drain 2053.
  • S208 depositing a passivation layer 207 on the substrate 201, the passivation layer 207 covers the gate insulating layer 203, the semiconductor pattern 2041, the source and drain patterns 2051 and the second photoresist 2064;
  • a passivation layer 207 is deposited on the substrate 201 by chemical vapor deposition.
  • the passivation layer 207 covers the gate insulating layer 203 exposed at both ends, the source/drain pattern 2051, the channel 2043 in the semiconductor pattern 2041, And a second photoresist 2064.
  • the passivation layer 207 on the second photoresist 2064 and the second photoresist 2064 is removed by a lift-off process, and the lift-off process is blunt by the raised photoresist pattern.
  • the layer 207 has a protrusion at a position where the contact hole pattern 208 needs to be formed, and then the second photoresist 2064 is partially pulled up, that is, removed, by photoresist removal, and the passivation layer 207 on the second photoresist 2064 is also After being removed, a recess is formed at the location where the second photoresist 2064 is located, thereby forming the desired contact hole pattern 208.
  • the second photoresist 2064 may be irradiated with laser light before the second photoresist 2064 is removed, so that the second photoresist 2064 is more easily removed.
  • the contact hole pattern 208 is formed by the lift-off process, even if the formed contact hole pattern 208 is not aligned, the display effect of the array substrate is not affected, mainly because the contact hole pattern 208 mainly serves as a connection.
  • the action of the source drain and the pixel electrode does not affect the display effect; and the size of all the contact hole patterns 208 formed by this method is close to each other, and there is no problem that the uniformity is poor when the photoresist is removed.
  • An ITO pixel electrode 209 is formed on the contact hole pattern 208 and the passivation layer 207.
  • an ITO conductive layer (not shown) may be deposited on the passivation layer 207 by physical vapor deposition.
  • the ITO conductive layer is patterned by a third mask process to form an ITO pixel electrode 209.
  • the third mask process can be selected from a yellow light process, including development, wet etching, dry etching, etc., and the ITO conductive layer is patterned by the third mask, and the processed ITO conductive layer can be used as the ITO pixel electrode 209. .
  • the gate electrode 202 is formed on a substrate 201 by the first mask process, and the semiconductor layer 204, the gate source metal layer and the passivation layer 207 are patterned by the second mask process.
  • the ITO pixel electrode 209 is formed by the third mask process to form the semiconductor pattern 2041, the gate source 2052 pattern and the contact hole pattern 208, and finally the preparation of the array substrate is completed. In this way, the process of the array substrate is reduced to three masks, thereby reducing process cost, reducing operation time, and improving production efficiency.
  • the first embodiment of the array substrate of the present invention includes:
  • the ITO pixel electrode 408 is formed on the contact hole pattern 407 and the passivation layer 406.
  • a second embodiment of the array substrate of the present invention provides a display panel comprising the array substrate of any of the above embodiments.

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Abstract

一种阵列基板及其制备方法。所述制备方法包括：步骤S1，在一基板（101）上形成栅电极（1021）；步骤S2，在栅电极（1021）和基板（101）上沉积栅极绝缘层（103）、半导体层（104）、源漏金属层（105）及钝化层（107），通过一道光罩制程对半导体层（104）、源漏金属层（105）及钝化层（107）进行图案化处理以形成半导体图案（1041）、源漏极图案（1051）及接触孔图案（108）；步骤S3，在接触孔图案（108）及钝化层（107）上形成ITO像素电极（110）。通过这种方式，利用一道光罩制程形成半导体图案（1041）、源漏极图案（1051）及接触孔图案（108），使得阵列基板的制程缩减到三道光罩，从而降低制程成本、减小作业时间，提高生产效率。

Description

一种阵列基板及其制备方法
【技术领域】
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制备方法。
【背景技术】
液晶显示面板（Liquid crystal displays，LCDs）是一种被广泛应用的平板显示器，主要是通过液晶开关调制背光源光场强度来实现画面显示。LCDs的制程中包含阵列基板的制程，传统阵列基板的制程一般采用五道光罩技术或四道光罩技术，五道光罩技术是将栅电极、半导体层、源漏极、钝化层及透明电极层分别通过一道光罩进行制备；四道光罩技术是将半导体层和源漏极用一道半色调光罩或多灰阶光罩同时形成。
在阵列基板的制程中，采用的光罩次数越多，制程成本越高，相应的作业时间也越长，生产效率越低。
【发明内容】
本发明的目的在于提供一种阵列基板及其制备方法，旨在解决阵列基板中光罩次数过多而导致制程成本高、作业时间长、生产效率低的问题。
为实现上述目的，本发明提供一种阵列基板的制备方法，该方法包括：
在一基板上形成栅金属层；
利用第一道光罩制程对栅金属层进行图案化处理以形成栅电极；
在栅电极和基板上沉积栅极绝缘层、半导体层、源漏金属层及钝化层，通过第二道光罩制程对半导体层、源漏金属层及钝化层进行图案化处理以形成半导体图案、源漏极图案及接触孔图案；
在钝化层上沉积ITO导电层；
利用第三道光罩制程对ITO导电层进行图案化处理以形成ITO像素电极。
为实现上述目的，本发明提供一种阵列基板的制备方法，该方法包括：
在一基板上形成栅电极；
在栅电极和基板上沉积栅极绝缘层、半导体层、源漏金属层及钝化层，通过一道光罩制程对半导体层、源漏金属层及钝化层进行图案化处理以形成半导体图案、源漏极图案及接触孔图案；
在接触孔图案及钝化层上形成ITO像素电极。
其中，在栅电极和基板上沉积栅极绝缘层、半导体层、源漏金属层及钝化层，通过一道光罩制程对半导体层、源漏金属层及钝化层进行图案化处理以形成半导体图案、源漏极图案及接触孔图案包括：
在栅电极和基板上依次沉积栅极绝缘层、半导体层及源漏金属层，并覆盖第一光阻；
利用一光罩对半导体层、源漏金属层、第一光阻进行图案化处理以形成半导体图案、源漏极图案及剩余的第二光阻，剩余的第二光阻位于源漏金属层之上；
在基板上沉积钝化层，钝化层覆盖栅极绝缘层、半导体图案、源漏极图案及第二光阻；
清除第二光阻及第二光阻上的钝化层以形成接触孔图案。
其中，利用一光罩对半导体层、源漏金属层、第一光阻进行图案化处理以形成半导体图案、源漏极图案及剩余的第二光阻包括：
利用一光罩对第一光阻进行曝光，暴露出基板两端的源漏金属层，且使第一光阻形成三种不同的厚度，其中三种不同的厚度分别为第一光阻对应半导体图案的第一区域光阻的厚度、第一光阻对应源漏极图案的第二区域光阻的厚度及第一光阻对应第二光阻的第三区域光阻的厚度；
利用干刻和湿刻清除暴露的源漏金属层及对应的半导体层；
对第一光阻进行灰化处理以清除对应半导体图案的第一区域光阻；
利用干刻和湿刻清除对应半导体图案上的源漏金属层以形成半导体图案；
对第二区域光阻及第三区域光阻进行灰化处理以形成源漏极图案，第三区域光阻剩余第二光阻。
其中，光罩为多灰阶光罩，多灰阶光罩具有四种不同的透光率。
其中，多灰阶光罩对应第一区域光阻的第一部分的透光性小于多灰阶光罩对应第二区域光阻的第二部分的透光性，多灰阶光罩对应第二区域光阻的第二部分的透光性小于多灰阶光罩对应第三区域光阻的第三部分的透光性，多灰阶光罩除去第一部分、第二部分及第三部分的其余部分为不透膜。
其中，清除第二光阻及第二光阻上的钝化层以形成接触孔图案之前包括：
利用激光照射第二光阻。
其中，清除第二光阻及第二光阻上的钝化层以形成接触孔图案包括：
利用拔起微影制程对第二光阻及第二光阻上的钝化层进行清除，形成接触孔图案。
其中，在栅电极和基板上依次沉积栅极绝缘层、半导体层及源漏金属层包括：
利用化学气相沉积技术在栅电极和基板上依次沉积栅极绝缘层及半导体层；
利用物理气相沉淀技术在半导体层上沉积源漏金属层。
其中，利用化学气相沉积技术在栅电极和基板上沉积半导体层包括：
利用化学气相沉积技术在栅电极和基板上沉积非晶硅层；
对非晶硅层进行掺杂形成掺杂非晶硅层。
其中，掺杂非晶硅层为N+掺杂非晶硅层。
其中，在接触孔图案及钝化层上形成ITO像素电极包括：
在钝化层上沉积ITO导电层；
利用第三道光罩制程对ITO导电层进行图案化处理以形成ITO像素电极。
其中，在钝化层上沉积ITO导电层包括：
利用物理气相沉积法在钝化层上沉积ITO导电层。
其中，第三道光罩制程为黄光制程，包括显影、湿刻及干刻。
其中，在一基板上形成栅电极包括：
在基板上形成栅金属层；
利用第一道光罩制程对栅金属层进行图案化处理以形成栅电极。
其中，栅金属层的材料为金、银、铜或铁。
其中，第一道光罩制程为黄光制程，包括显影、湿刻及干刻。
为实现上述目的，本发明提供一种阵列基板，包括：
基板及在基板上形成的栅电极；
形成于栅电极和基板上的栅极绝缘层、半导体层、源漏金属层、钝化层，及通过一道光罩制程形成的半导体图案、源漏极图案、接触孔图案；
形成于接触孔图案与钝化层上的ITO像素电极。
其中，栅电极形成于利用第一道光罩制程对基板上的栅金属层进行图案化处理的过程中。
其中，ITO像素电极形成于利用第三道光罩制程对接触孔图案与钝化层上的ITO导电层进行图案化处理的过程中。
本发明的有益效果是：区别于现有技术的情况，本发明通过在一基板上形成栅电极；在栅电极和基板上沉积栅极绝缘层、半导体层、源漏金属层及钝化层，通过一道光罩制程对半导体层、源漏金属层及钝化层进行图案化处理以形成半导体图案、源漏极图案及接触孔图案；在接触孔图案及钝化层上形成ITO像素电极。通过这种方式，本发明利用一道光罩制程形成半导体图案、源漏极图案及接触孔图案，使得阵列基板的制程缩减到三道光罩，从而降低制程成本、减小作业时间，提高生产效率。
【附图说明】
图1是本发明阵列基板的制备方法第一实施方式的流程示意图；
图2是图1中步骤S1的具体流程示意图；
图3a-图3b是图2各步骤中阵列基板的截面示意图；
图4是图1中步骤S2的具体流程示意图；
图5a-图5d是图4各步骤中阵列基板的截面示意图；
图6是图1中步骤S3的具体流程示意图；
图7a-图7b是图6各步骤中阵列基板的截面示意图；
图8是本发明阵列基板的制备方法第二实施方式的流程示意图；
图9a-图9j是图8各步骤中阵列基板的截面示意图；
图10是本发明阵列基板第一实施方式的截面示意图。
【具体实施方式】
为使本领域的技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明所提供的一种阵列基板及其制备方法做进一步详细描述。
如图1所示，是本发明阵列基板的制备方法第一实施方式的流程图，该阵列基板的制备方法具体包括如下步骤：
S1：在一基板101上形成栅电极1021；
具体地，基板101可以是PEN(Polyethylene naphthalene，聚萘二甲酸乙二醇酯 ) 或PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯 ) 或PI(Polyimide，聚酰亚胺 ) 或玻璃制成的。
如图2所示，该步骤可具体包括：
S101：通过溅镀等方式在该基板101的上表面形成一栅金属层102，该栅金属层102的材料包含但不限于金、银、铜或铁等材料，请参阅图3a；
S102：利用第一道光罩制程对栅金属层102进行图案化处理以形成栅电极1021。
可以采用黄光制程（如显影、湿刻、干刻等）通过第一光罩对栅金属层102进行图形化处理，此时，处理后的栅金属层102可以作为栅电极1021。该栅电极1021是底栅电极1021，可以位于基板101上表面的中部，请参阅图3b。
底栅电极1021的俯视图的图案包括但不限于：直线图案、曲线图案、多边形图案、圆形图案、椭圆形图案或星形图案等图案，可以理解，具体的图案形状可根据实际使用来确定，本发明的实施方案在此不作具体限定。
S2：在栅电极1021和基板101上沉积栅极绝缘层103、半导体层104、源漏金属层105及钝化层107，通过一道光罩制程对半导体层104、源漏金属层105及钝化层107进行图案化处理以形成半导体图案1041、源漏极图案1051及接触孔图案108；
具体地，如图4所示，该步骤可包括：
S103：在栅电极1021和基板101上依次沉积栅极绝缘层103、半导体层104及源漏金属层105，并覆盖第一光阻106；
请查阅图5a，可选利用化学气相沉积法在栅电极1021和基板101上首先沉积栅极绝缘层103，栅极绝缘层103包覆栅电极1021，栅极绝缘层103远离栅电极1021的上表面可选为一平整面；
然后在栅极绝缘层103上沉积半导体层104，可选在栅极绝缘层103上首先沉积第一层的非晶硅（a-Si）半导体材料（图中未示出），在非晶硅层上沉积高掺杂的硅的层，例如N+层，形成非晶硅半导体层104；
再通过物理气相沉积法等方式在非晶硅半导体层104上形成源漏金属层105，源漏金属层105包括但不限于：铝、铜、钴、钛等金属；
在源漏金属层105上覆盖第一光阻106，光阻是一种光敏性物质，经曝光、显影后留下的部分对底层起保护作用，然后进行蚀刻脱膜并最终可获得需要的图案。
S104：利用一光罩对半导体层104、源漏金属层105、第一光阻106进行图案化处理以形成半导体图案1041、源漏极图案1051及剩余的第二光阻1061，剩余的第二光阻1061位于源漏金属层105之上；
在传统制程中，形成半导体图案1041、源漏极图案1051、接触孔图案108中需要用到三道光罩，而在步骤S104中，请参阅图5b，利用一道光罩即可形成半导体图案1041、源漏极图案1051，而第一光阻106曝光显影后剩余的第二光阻1061可为后续形成接触孔图案108做准备，大大缩减了制程流程，降低制程成本。
这里光罩可选多灰阶光罩，多灰阶光罩具有3中以上不同的透光率，对光阻进行曝光显影后可以形成不同的光阻厚度，为半导体层104、源漏金属层105及第一光阻106的图案化处理做准备。
其中，半导体图案1041包括沟道1043、掺杂区1042及存储电容部分（图中未示出），源漏极图案1051包括源极1052、漏极1053和数据线（图中未示出），第二光阻1061位于源漏极图案1051的漏极1053上。
S105：在基板101上沉积钝化层107，钝化层107覆盖栅极绝缘层103、半导体图案1041、源漏极图案1051及第二光阻1061；
请参阅图5c，利用化学气相沉积法在基板101上沉积钝化层107，钝化层107覆盖两端暴露的栅极绝缘层103、源漏极图案1051、半导体图案1041中的沟道1043、及第二光阻1061。
S106：清除第二光阻1061及第二光阻1061上的钝化层107以形成接触孔图案108。
利用拔起微影（lift-off）制程对第二光阻1061及第二光阻1061上的钝化层107进行清除，lift-off制程是通过突起的光阻图形使钝化层107在需要形成接触孔图案108的位置上有突起，再用去光阻的方式将第二光阻1061部分拔起，也就是清除，同时第二光阻1061上的钝化层107也被清除，第二光阻1061所在的位置上形成凹陷，也就形成需要的接触孔图案108，请参阅图5d。
利用lift-off制程形成接触孔图案108的过程中，为了提高效率，可在第二光阻1061被清除前，利用激光照射第二光阻1061，从而使得第二光阻1061更容易被清除。
另外，在利用lift-off制程形成接触孔图案108时，即使形成的接触孔图案108出现不整齐的现象，也不会影响阵列基板的显示效果，这主要是由于接触孔图案108主要起到连接源漏极与像素电极的作用，并不对显示效果造成影响；而且利用这种方式形成的所有接触孔图案108的尺寸接近，也就不存在去光阻时均匀性差的问题。
S3：在接触孔图案108及钝化层107上形成ITO像素电极110。
具体地，如图6所示，该步骤可包括：
S107：在钝化层107上沉积ITO导电层109；
利用物理气相沉积法在钝化层107上沉积ITO导电层109，如图7a所示。
S108：利用第三道光罩制程对ITO导电层109进行图案化处理以形成ITO像素电极110。
第三道光罩制程可选采用黄光制程，包括显影、湿刻、干刻等工艺，通过第三光罩对ITO导电层109进行图案化处理，处理后的ITO导电层109可以作为像素电极110使用，如图7b所示。
在对ITO导电层109进行图案化处理时，需要使得处理后的图案边缘整齐，并且ITO像素电极110控制在一定的宽度，从而使得组合后的显示面板的亮度均匀，不会产生各种痕迹，本实施方式中，第三道光罩制程采用传统的黄光制程，可使形成的ITO像素电极110获得与传统的五道光罩或四道光罩技术中相同的显示效果，不存在现有技术中利用lift-off制程制作ITO像素电极时出现的图案边缘不整齐、线宽不易控制及显示不均的问题。
可以看出，本发明阵列基板101第一实施方式，通过在一基板101上形成栅电极1021；在栅电极1021和基板101上沉积栅极绝缘层103、半导体层104、源漏金属层105及钝化层107，通过一道光罩制程对半导体层104、源漏金属层105及钝化层107进行图案化处理以形成半导体图案1041、源漏极图案1051及接触孔图案108；在接触孔图案108及钝化层107上形成ITO像素电极110。通过这种方式，本发明利用一道光罩制程形成半导体图案1041、源漏极图案1051及接触孔图案108，使得阵列基板的制程缩减到三道光罩，从而降低制程成本、减小作业时间，提高生产效率。
如图8所示，是本发明阵列基板的制备方法第二实施方式，图9a-图9j是本实施方式中各步骤的截面示意图，请参阅图8和图9，该阵列基板的制备方法具体包括如下步骤：
S201：在一基板201上形成栅电极202；
具体地，基板201可以是PEN(Polyethylene naphthalene，聚萘二甲酸乙二醇酯)或PET(Polyethylene terephthalate，聚对苯二甲酸乙二醇酯)或PI(Polyimide，聚酰亚胺)制成的。
通过溅镀等方式在该基板201的上表面形成一栅金属层(图中为示出)，栅金属层的材料包含但不限于金、银、铜或铁等材料；利用第一道光罩制程对栅金属层进行图案化处理以形成栅电极202，如图9a所示。
S202：在栅电极202和基板201上依次沉积栅极绝缘层203、半导体层204及源漏金属层205，并覆盖第一光阻206；
请查阅图9b，可选利用化学气相沉积法在栅电极202和基板201上首先沉积栅极绝缘层203，栅极绝缘层203包覆栅电极202，栅极绝缘层203远离栅电极202的上表面可选为一平整面；
然后在栅极绝缘层203上沉积半导体层204，可选在栅极绝缘层203上首先沉积第一层的非晶硅（a-Si）半导体材料（图中为示出），然后在非晶硅层上沉积高掺杂的硅的层，例如N+层，形成非晶硅半导体层204；
再通过物理气相沉积法等方式在非晶硅半导体层204上形成源漏金属层205，源漏金属层205包括但不限于：铝、铜、钴、钛等金属；
在源漏金属层205上覆盖第一光阻206，光阻是一种光敏性物质，经曝光、显影后留下的部分对底层起保护作用，然后进行蚀刻脱膜并最终可获得需要的图案。
S203：利用一光罩30对第一光阻206进行曝光，暴露出基板201两端的源漏金属层205，且使第一光阻206形成三种不同的厚度，其中三种不同的厚度分别为第一光阻206对应半导体图案2041的第一区域光阻2061的厚度、第一光阻206对应源漏极图案2051的第二区域光阻2062的厚度及第一光阻206对应第二光阻2064的第三区域光阻2063的厚度；
请参阅图9c，光罩30选用多灰阶光罩30，多灰阶光罩30具有四种不同的透光率，多灰阶光罩30的两端为不透膜31，对第一光阻206进行曝光后使得不透膜31对应的区域被清除，多灰阶光罩31的中间区域包含三种不同透光率的材料32/33/34，使第一光阻206曝光后形成三种不同的厚度，其中第一区域光阻2061的厚度最小、第三区域光阻2063的厚度最大，第二区域光阻2062的厚度位于这两者之间。
为了便于说明问题，以具体数字进行举例，并不表示任何限定。比如，令第一区域光阻2061的厚度为0.5μm，第二区域光阻2062的厚度为1μm，第三区域光阻2063的厚度为2.5μm。
S204：利用干刻和湿刻清除暴露的源漏金属层205及对应的半导体层204；
请参阅图9d，利用一次湿刻清除两端的暴露的源漏金属层205，再利用一次干刻清除两端源漏金属层205下方的半导体层204，使得位于两端的栅极绝缘层203暴露。
S205：对第一光阻206进行灰化处理以清除对应半导体图案2041的第一区域光阻2061；
请参阅图9e，利用氧烧光阻对具有三种不同膜厚的第一光阻206进行灰化处理，清除对第一区域光阻2061，清除的厚度为0.5μm，因此清除后第二区域光阻2062的剩余厚度为0.5μm，第三区域光阻2063的剩余厚度为2μm。
S206：利用干刻和湿刻清除对应半导体图案2041上的源漏金属层205以形成半导体图案2041；
请参阅图9f，利用一次干刻和一次湿刻清除掉位于原第一区域光阻2061下方的源漏金属层205，同时清除掉位于源漏极金属层下方的高掺杂的硅的层，暴露出沟道2043和掺杂区2042，形成半导体图案2041，半导体图案2041包括沟道2043、掺杂区2042及存储电容部分（图中未示出）。
S207：对第二区域光阻2062及第三区域光阻2063进行灰化处理以形成源漏极图案2051，第三区域光阻2063剩余第二光阻2064；
请参阅图9g，利用氧烧光阻对第二区域光阻2062及第三区域光阻2063进行灰化处理，形成源漏极图案2051，源漏极图案2051包括源极2052、漏极2053和数据线（图中未示出）。
清除的第二区域光阻2062的厚度为0.5μm，因此第三区域光阻2063的剩余厚度为1.5μm，剩余的第三区域光阻2063称为第二光阻2064，第二光阻2064位于源漏极图案2051的漏极2053上。
S208：在基板201上沉积钝化层207，钝化层207覆盖栅极绝缘层203、半导体图案2041、源漏极图案2051及第二光阻2064；
请参阅图9h，利用化学气相沉积法在基板201上沉积钝化层207，钝化层207覆盖两端暴露的栅极绝缘层203、源漏极图案2051、半导体图案2041中的沟道2043、及第二光阻2064。
S209：清除第二光阻2064及第二光阻2064上的钝化层207以形成接触孔图案208；
请参阅图9i，利用拔起微影（lift-off）制程对第二光阻2064及第二光阻2064上的钝化层207进行清除，lift-off制程是通过突起的光阻图形使钝化层207在需要形成接触孔图案208的位置上有突起，再用去光阻的方式将第二光阻2064部分拔起，也就是清除，同时第二光阻2064上的钝化层207也被清除，第二光阻2064所在的位置上形成凹陷，也就形成需要的接触孔图案208。
利用lift-off制程形成接触孔图案208的过程中，为了提高效率，可在第二光阻2064被清除前，利用激光照射第二光阻2064，从而使得第二光阻2064更容易被清除。
另外，在利用lift-off制程形成接触孔图案208时，即使形成的接触孔图案208出现不整齐的现象，也不会影响阵列基板的显示效果，这主要是由于接触孔图案208主要起到连接源漏极与像素电极的作用，并不对显示效果造成影响；而且利用这种方式形成的所有接触孔图案208的尺寸接近，也就不存在光阻去除时均匀性差的问题。
S210：在接触孔图案208及钝化层207上形成ITO像素电极209。
请参阅图9j，可选利用物理气相沉积法在钝化层207上沉积ITO导电层（图中未示出）， 利用第三道光罩制程对ITO导电层进行图案化处理以形成ITO像素电极209。
第三道光罩制程可选采用黄光制程，包括显影、湿刻、干刻等工艺，通过第三光罩对ITO导电层进行图案化处理，处理后的ITO导电层可以作为ITO像素电极209使用。
可以看出，本实施方式中，通过第一道光罩制程在一基板201上形成栅电极202，通过第二光罩制程对半导体层204、栅源金属层及钝化层207进行图案化处理以形成半导体图案2041、栅源极2052图案及接触孔图案208，通过第三道光罩制程形成ITO像素电极209，最终完成阵列基板的制备。通过这种方式，阵列基板的制程缩减到三道光罩，从而降低制程成本、减小作业时间，提高生产效率。
如图10所示，本发明阵列基板第一实施方式，包括：
基板401及在基板上形成的栅电极402；
形成于栅电极402和基板401上的栅极绝缘层403、半导体层404、源漏金属层405、钝化层406，及通过一道光罩制程形成的半导体图案404、源漏极图案405、接触孔图案407；
形成于接触孔图案407与钝化层406上的ITO像素电极408。
本发明阵列基板第二实施方式，提供一显示面板，包括上述任一实施方式中的阵列基板。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围。

Claims (20)

  1. 一种阵列基板的制备方法，其中，所述方法包括：
    在一基板上形成栅金属层；
    利用第一道光罩制程对所述栅金属层进行图案化处理以形成所述栅电极；
    在所述栅电极和所述基板上沉积栅极绝缘层、半导体层、源漏金属层及钝化层，通过第二道光罩制程对所述半导体层、源漏金属层及钝化层进行图案化处理以形成半导体图案、源漏极图案及接触孔图案；
    在所述钝化层上沉积ITO导电层；
    利用第三道光罩制程对所述ITO导电层进行图案化处理以形成所述ITO像素电极。
  2. 一种阵列基板的制备方法，其中，所述方法包括：
    在一基板上形成栅电极；
    在所述栅电极和所述基板上沉积栅极绝缘层、半导体层、源漏金属层及钝化层，通过一道光罩制程对所述半导体层、源漏金属层及钝化层进行图案化处理以形成半导体图案、源漏极图案及接触孔图案；
    在所述接触孔图案及所述钝化层上形成ITO像素电极。
  3. 根据权利要求2所述的方法，其中，所述在所述栅电极和所述基板上沉积栅极绝缘层、半导体层、源漏金属层及钝化层，通过一道光罩制程对所述半导体层、源漏金属层及钝化层进行图案化处理以形成半导体图案、源漏极图案及接触孔图案包括：
    在所述栅电极和所述基板上依次沉积所述栅极绝缘层、所述半导体层及所述源漏金属层，并覆盖第一光阻；
    利用一光罩对所述半导体层、所述源漏金属层、所述第一光阻进行图案化处理以形成所述半导体图案、所述源漏极图案及剩余的第二光阻，所述剩余的第二光阻位于所述源漏金属层之上；
    在所述基板上沉积钝化层，所述钝化层覆盖所述栅极绝缘层、所述半导体图案、所述源漏极图案及所述第二光阻；
    清除所述第二光阻及所述第二光阻上的钝化层以形成所述接触孔图案。
  4. 根据权利要求3所述的方法，其中，所述利用一光罩对所述半导体层、所述源漏金属层、所述第一光阻进行图案化处理以形成所述半导体图案、所述源漏极图案及剩余的第二光阻包括：
    利用一光罩对所述第一光阻进行曝光，暴露出所述基板两端的所述源漏金属层，且使所述第一光阻形成三种不同的厚度，其中所述三种不同的厚度分别为所述第一光阻对应所述半导体图案的第一区域光阻的厚度、所述第一光阻对应所述源漏极图案的第二区域光阻的厚度及所述第一光阻对应所述第二光阻的第三区域光阻的厚度；
    利用干刻和湿刻清除暴露的源漏金属层及对应的所述半导体层；
    对所述第一光阻进行灰化处理以清除对应所述半导体图案的第一区域光阻；
    利用干刻和湿刻清除对应所述半导体图案上的所述源漏金属层以形成所述半导体图案；
    对所述第二区域光阻及所述第三区域光阻进行灰化处理以形成所述源漏极图案，所述第三区域光阻剩余所述第二光阻。
  5. 根据权利要求4所述的方法，其中，
    所述光罩为多灰阶光罩，所述多灰阶光罩具有四种不同的透光率。
  6. 根据权利要求5所述的方法，其中，
    所述多灰阶光罩对应所述第一区域光阻的第一部分的透光性小于所述多灰阶光罩对应所述第二区域光阻的第二部分的透光性，所述多灰阶光罩对应所述第二区域光阻的第二部分的透光性小于所述多灰阶光罩对应所述第三区域光阻的第三部分的透光性，所述多灰阶光罩除去所述第一部分、所述第二部分及所述第三部分的其余部分为不透膜。
  7. 根据权利要求3所述的方法，其中，所述清除所述第二光阻及所述第二光阻上的钝化层以形成所述接触孔图案之前包括：
    利用激光照射所述第二光阻。
  8. 根据权利要求3所述的方法，其中，所述清除所述第二光阻及所述第二光阻上的钝化层以形成所述接触孔图案包括：
    利用拔起微影制程对所述第二光阻及所述第二光阻上的钝化层进行清除，形成所述接触孔图案。
  9. 根据权利要求3所述的方法，其中，所述在所述栅电极和所述基板上依次沉积所述栅极绝缘层、所述半导体层及所述源漏金属层包括：
    利用化学气相沉积技术在所述栅电极和所述基板上依次沉积所述栅极绝缘层及所述半导体层；
    利用物理气相沉淀技术在所述半导体层上沉积所述源漏金属层。
  10. 根据权利要求9所述的方法，其中，所述利用化学气相沉积技术在所述栅电极和所述基板上沉积所述半导体层包括：
    利用化学气相沉积技术在所述栅电极和所述基板上沉积非晶硅层；
    对所述非晶硅层进行掺杂形成掺杂非晶硅层。
  11. 根据权利要求10所述的方法，其中，
    所述掺杂非晶硅层为N+掺杂非晶硅层
  12. 根据权利要求2所述的方法，其中，所述在所述接触孔图案及所述钝化层上形成ITO像素电极包括：
    在所述钝化层上沉积ITO导电层；
    利用第三道光罩制程对所述ITO导电层进行图案化处理以形成所述ITO像素电极。
  13. 根据权利要求12所述的方法，其中，所述在所述钝化层上沉积ITO导电层包括：
    利用物理气相沉积法在所述钝化层上沉积ITO导电层。
  14. 根据权利要求12所述的方法，其中，
    所述第三道光罩制程为黄光制程，包括显影、湿刻及干刻。
  15. 根据权利要求2所述的方法，其中，所述在一基板上形成栅电极包括：
    在所述基板上形成栅金属层；
    利用第一道光罩制程对所述栅金属层进行图案化处理以形成所述栅电极。
  16. 根据权利要求15所述的方法，其中，
    所述栅金属层的材料为金、银、铜或铁。
  17. 根据权利要求15所述的方法，其中，
    所述第一道光罩制程为黄光制程，包括显影、湿刻及干刻。
  18. 一种阵列基板，其中，包括：
    基板及在基板上形成的栅电极；
    形成于所述栅电极和所述基板上的栅极绝缘层、半导体层、源漏金属层、钝化层，及通过一道光罩制程形成的半导体图案、源漏极图案、接触孔图案；
    形成于所述接触孔图案与所述钝化层上的ITO像素电极。
  19. 根据权利要求18所述的阵列基板，其中，
    所述栅电极形成于利用第一道光罩制程对所述基板上的栅金属层进行图案化处理的过程中。
  20. 根据权利要求18所述的阵列基板，其中，
    所述ITO像素电极形成于利用第三道光罩制程对所述接触孔图案与所述钝化层上的ITO导电层进行图案化处理的过程中。
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