WO2015043008A1 - 薄膜晶体管阵列基板的制造方法 - Google Patents

薄膜晶体管阵列基板的制造方法 Download PDF

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Publication number
WO2015043008A1
WO2015043008A1 PCT/CN2013/085364 CN2013085364W WO2015043008A1 WO 2015043008 A1 WO2015043008 A1 WO 2015043008A1 CN 2013085364 W CN2013085364 W CN 2013085364W WO 2015043008 A1 WO2015043008 A1 WO 2015043008A1
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Prior art keywords
photoresist pattern
thin film
film transistor
layer
array substrate
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PCT/CN2013/085364
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English (en)
French (fr)
Inventor
王俊
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/124,717 priority Critical patent/US9142653B2/en
Priority to JP2016543288A priority patent/JP6261747B2/ja
Priority to KR1020167006845A priority patent/KR101788488B1/ko
Priority to GB1600109.1A priority patent/GB2530223B/en
Publication of WO2015043008A1 publication Critical patent/WO2015043008A1/zh

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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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    • H01L27/1259—Multistep manufacturing methods
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    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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Definitions

  • the field of liquid crystal display manufacturing in particular, relates to a method for manufacturing a thin film tube array substrate using a three-time mask ( background;
  • the liquid crystal display has many advantages such as power saving and no radiation, and has been widely used.
  • Most of the liquid crystal displays on the market are backlight type liquid crystal displays, which include a liquid crystal panel and a backlight module.
  • the working principle of the liquid crystal panel is to place liquid crystal molecules in two parallel glass substrates, and apply driving voltages on the two glass substrates to control the rotation direction of the liquid crystal molecules to refract the light of the backlight module to generate a picture. Since the liquid crystal surface light source normally displays images, therefore, the back
  • the two parallel glass substrates in the liquid crystal panel are a thin film transistor array substrate and a color filter substrate, respectively.
  • the thin film transistor array substrate includes: a substrate; a gate line, a gate, a gate insulating layer, a semiconductor active layer, a data line, a source, a drain, and a source formed on the substrate, and a source formed on the substrate a protective layer on the drain, the drain, and a pixel electrode formed on the protective layer, wherein the gate, the source, the drain, and the semiconductor active layer constitute a thin film transistor (TFT).
  • TFT thin film transistor
  • the thin film transistor is an amorphous silicon thin film transistor or a low temperature polysilicon thin film transistor.
  • the amorphous silicon thin film transistor display matrix only needs 3-5 photolithographic masks, and the cost is low and the competition is strong.
  • the low temperature polysilicon thin film transistor display matrix usually requires 8-9 photolithographic masks, which is relatively high in cost.
  • Oxide semiconductor IGZO Indium Gallium Zinc Oxide
  • IGZO has a carrier mobility of 20 to 30 times that of amorphous silicon, which can greatly increase the charge and discharge rate of the thin film transistor to the pixel electrode and improve the response speed of the pixel. , achieving faster refresh rate, and faster response also greatly increases the pixel scan rate, making ultra-high resolution in Thin Film Transistor TFT-LCD
  • IGZO liquid crystal displays have higher energy efficiency levels and higher efficiency due to the reduction in the number of thin film transistors and the improvement of the transmittance of each pixel.
  • ZnO semiconductor IGZO can be produced using existing amorphous silicon production lines. It needs a little modification, so it is more competitive in terms of cost than low-temperature polysilicon.
  • thin film transistors fabricated by the oxide semiconductor IGZO are mainly manufactured by a 6-time mask process, which has a lower production efficiency and a higher production cost.
  • An object of the present invention is to provide a method for fabricating a thin film transistor array substrate by manufacturing a thin film transistor array substrate through three masks, which can significantly reduce the number of processing steps, shorten the processing time, and effectively reduce the production cost.
  • the production capacity is increased, and the thin film transistor array substrate is made of indium gallium zinc oxide, which can greatly increase the charging rate of the thin film transistor to the pixel electrode, improve the response speed of the pixel, and achieve a faster refresh rate.
  • the present invention provides a method of fabricating a thin film transistor array substrate using a top gate structure, and the method of fabricating the thin film transistor array substrate includes the following steps:
  • Step 1 providing a substrate
  • Step 2 sequentially depositing a buffer layer, an oxide semiconductor film and a first metal layer on the substrate;
  • Step 3 forming a first photoresist layer on the first metal layer, patterning the first photoresist layer to form a first photoresist pattern at a predetermined position, including a channel region corresponding to the oxide semiconductor film a first portion, and a second portion, the thickness of the first photoresist pattern in the second portion is thicker than the thickness of the first portion;
  • Step 4 etching away the first metal layer and the oxide semiconductor film without the region covered by the first photoresist pattern, removing the first portion of the first photoresist pattern to expose the first metal layer, and the second photoresist pattern Part of the mask is etched away from the first metal layer to expose the oxide semiconductor film, and the first photoresist pattern is stripped to form a source and a drain in the first metal layer;
  • Step 5 sequentially deposit an insulating layer and a second metal layer on the substrate, and pattern the second metal layer to form a gate.
  • the manufacturing method of the thin film transistor array substrate further includes:
  • step 6 after step 5, a protective layer is deposited on the substrate, a second photoresist layer is formed on the protective layer, and the second photoresist layer is patterned to form a second photoresist pattern at a predetermined position, a third portion over the drain side and a portion of the drain, and a fourth portion over the other side of the drain and a portion of the drain, forming a third portion and a fourth portion of the second photoresist pattern - a recess;
  • step 7 etching the protective layer not covered by the second photoresist pattern and the insulating layer corresponding to the portion of the protective layer to expose the drain, thereby forming a contact hole, and removing the third portion of the second photoresist pattern;
  • step 8 after step 7, a transparent conductive layer is deposited on the substrate, and the fourth portion of the second photoresist pattern and the transparent conductive layer thereon are peeled off by photoresist stripping.
  • the method for fabricating the thin film transistor array substrate further includes the step of annealing the substrate in step 9 after the step 8, to complete the fabrication of the thin film transistor array substrate.
  • the substrate is a glass substrate; the buffer layer is formed by deposition of silicon dioxide; and the oxide semiconductor film is an indium gallium zinc oxide film.
  • the first photoresist pattern in the step 3 is formed by gray scale, mask, exposure, and development.
  • the first metal layer is etched away by using the second portion of the first photoresist pattern as a mask; and the stripping the first photoresist pattern in the step 4 is the first photoresist pattern. The second part is stripped off
  • the insulating layer in the step 5 is formed by deposition of silicon dioxide; and the second metal layer in the step 5 forms a bridge by exposure, development, etching and photoresist stripping processes.
  • the etching is a wet etching.
  • the protective layer in the step 6 is formed by deposition of silicon dioxide or a silicon nitride compound; and the second photoresist pattern passes through a gray scale. Formed by masking, exposure, and development.
  • the protective layer not covered by the second photoresist pattern and the insulating layer corresponding to the partial protective layer are etched away by a thousand etching method to form a contact hole.
  • the present invention also provides a method of fabricating a thin film transistor array substrate using a top gate structure, and the method of fabricating the thin film transistor array substrate includes the following steps:
  • Step 1 providing a substrate
  • Step 2 Forming a buffer layer, an oxide semiconductor film, and a first metal layer sequentially on the substrate;
  • Step 3 forming a first photoresist layer on the first metal layer, patterning the first photoresist layer to form a first photoresist pattern at a predetermined position, including a channel region corresponding to the oxide semiconductor film a first portion, and a second portion, the thickness of the first photoresist pattern in the second portion is thicker than the thickness of the first portion;
  • Step 4 etching away the first metal layer and the oxide semiconductor film without the region covered by the first photoresist pattern, removing the first portion of the first photoresist pattern to expose the first metal layer, and the second photoresist pattern Part of the mask is used to etch away the first metal layer to expose the oxide semiconductor film, and stripping Deviating from the first photoresist pattern to form a source and a drain in the first metal layer;
  • Step 5 sequentially depositing an insulating layer and a second metal layer on the substrate, and patterning the second metal layer to form a 4-layer electrode;
  • step 6 after step 5, a protective layer is deposited on the substrate, a second photoresist layer is formed on the protective layer, and the second photoresist layer is patterned to form a second photoresist pattern at a predetermined position,
  • the third portion is disposed on the drain side and the portion of the drain, and the fourth portion is located on the other side of the drain and the portion of the drain.
  • the third portion and the fourth portion of the second photoresist pattern form a Concave
  • step 7 etching the protective layer not covered by the second photoresist pattern and the insulating layer corresponding to the portion of the protective layer to expose the drain, thereby forming a contact hole, and removing the third portion of the second photoresist pattern;
  • Step 8 after step 7, depositing a transparent conductive layer on the substrate, and peeling off the fourth portion of the second photoresist pattern and the transparent conductive layer thereon by photoresist stripping;
  • step 9 after the step 8 is performed to anneal the substrate to complete the fabrication of the thin film transistor array substrate
  • the substrate is a glass substrate;
  • the buffer layer is formed by depositing silicon dioxide; and the oxide semiconductor film is an indium gallium zinc oxide film;
  • the first photoresist pattern in the step 3 is shaped by gray scale, mask, exposure, and development;
  • the first metal layer is etched away by using the second portion of the first photoresist pattern as a mask; and the first photoresist is removed from the first photoresist pattern in the step 4 The second part of the pattern is peeled off.
  • the insulating layer in the step 5 is formed by deposition of silicon dioxide; the second metal layer in the step 5 is exposed. Development, etching, and photoresist stripping processes are formed.
  • the etch is a wet etch.
  • the protective layer in the step 6 is formed by depositing silicon dioxide or a silicon nitride compound; and the second photoresist pattern is formed by gray scale, masking, exposure, and development.
  • the protective layer not covered by the second photoresist pattern and the insulating layer corresponding to the portion of the protective layer are etched away by a thousand etching method to form a contact hole.
  • the thin film transistor array substrate employs a top gate structure, and the method of manufacturing the thin film transistor array substrate is
  • the TFT array substrate is fabricated by three masks, wherein the thin film transistor in the thin film transistor array substrate is fabricated by using indium gallium zinc oxide, which can greatly increase the charging speed of the thin film transistor to the pixel electrode. Rate, improve the response speed of the pixel, achieve faster refresh rate, and faster response also greatly improve the line scan rate of the pixel, making ultra-high resolution possible in the thin film transistor liquid crystal display; meanwhile, the manufacturing method is only Using 3 mask processes, it can significantly reduce process steps, shorten process time, effectively reduce production costs, increase production efficiency, and increase production capacity.
  • FIG. 1 is a flow chart showing a method of fabricating a thin film transistor array substrate of the present invention
  • FIG. 2 is a schematic structural view showing a buffer layer, an indium gallium zinc oxide film, and a first metal layer formed on a substrate in the present invention
  • FIG. 3 is a schematic structural view of a first photoresist layer formed on a substrate in the present invention.
  • FIG. 4 is a schematic structural view of etching an indium gallium zinc oxide film and a first metal layer without a first photoresist layer after exposure of the substrate in the present invention
  • FIG. 5 is a schematic view showing the structure of a first photoresist layer in which a substrate is ashed in a first gray-scale exposure region according to the present invention
  • FIG. 6 is a schematic view showing the structure of a first metal layer in which a substrate is completely etched away from a first gray-scale exposure region;
  • FIG. 7 is a schematic structural view of a substrate in which a first photoresist layer is peeled off according to the present invention.
  • FIG. 8 is a schematic diagram showing the structure of a node layer and a second metal layer deposited on a substrate in the present invention. i3 ⁇ 4J
  • FIG. 9 is a schematic structural view of forming a gate on a substrate in the present invention.
  • FIG. 10 is a schematic structural view of a protective layer formed on a substrate in the present invention.
  • FIG. 1 is a schematic structural view of a second light blocking layer formed on a substrate according to the present invention
  • FIG. 12 is a schematic structural view of a substrate forming a contact hole in the present invention.
  • FIG. 13 is a schematic view showing the structure of a second photoresist layer in which a substrate is ashed in a second gray-scale exposure region according to the present invention
  • FIG. 14 is a schematic structural view of a transparent conductive layer formed on a substrate in the present invention.
  • FIG. 5 is a schematic structural view of the second photoresist layer of the second normal exposure region and the transparent conductive layer on the second photoresist layer in the present invention. detailed description
  • the present invention provides a method for fabricating a thin film transistor array substrate.
  • the thin film transistor array substrate adopts a top gate structure, and the method only uses three mask processes to effectively reduce production cost and improve production. Efficiency, increase production capacity.
  • the manufacturing method of the thin film transistor array substrate specifically includes the following steps:
  • Step 1 Provide a substrate 21.
  • the substrate 21 is preferably a glass substrate.
  • the substrate is not limited thereto, and a substrate of another material such as plastic or the like may be used.
  • Step 2 A buffer layer 22, an oxide semiconductor film 23, and a first metal layer 24 are sequentially deposited on the substrate 21.
  • the buffer layer 22 is formed by depositing silicon oxide, and the oxide semiconductor film 23 is an indium gallium zinc oxide film.
  • Step 3 forming a first photoresist layer on the first metal layer 24, and patterning the first photoresist layer to form a first photoresist pattern 25 at a predetermined position, which includes a trench corresponding to the oxide semiconductor film 23.
  • the first portion 26 of the track region and the second portion 27 have a thickness of the first photoresist pattern 25 at the second portion 27 that is thicker than the thickness of the first portion 26.
  • the first photoresist pattern 25 in the step 3 is formed by gray scale, mask, exposure, development, and the first portion 26 of the first photoresist pattern 25 is formed by gray scale exposure.
  • the first masking process of the three mask processes in the present invention is carried out.
  • Step 4 etching away the first metal layer 24 and the oxide semiconductor film 23 in the region not covered by the first photoresist pattern 25, removing the first portion 26 of the first photoresist pattern 25 to expose the first metal layer 24, first The second portion 27 of the photoresist pattern 25 etches away the first metal layer 24 to expose the oxide semiconductor film 23, and peels off the first photoresist pattern 25 to form the source 27 and the drain 28 in the first metal layer 24.
  • the first metal layer 24 is etched away by using the second portion 27 of the first photoresist pattern 25 as a mask by a thousand etching method, as shown in FIG. 6, and the first photoresist pattern 25 is peeled off.
  • the second portion 27 of the first photoresist pattern 25 is peeled off.
  • Step 5 Deposit an insulating layer 3! and a second metal layer 32 on the substrate, and pattern the second metal layer 32 to form the cabinet 33.
  • the insulating layer 31 is preferably formed by deposition of silicon dioxide.
  • the second metal layer 32 is exposed, developed, etched and The photoresist stripping process forms the drain 33 0.
  • the exposure of the second metal layer 32 in this step is a common exposure, which is simple in operation, convenient and quick, and is advantageous for improving productivity; the etching of the second metal layer 32 is wet in this step. Etching.
  • the second mask process of the three mask processes in the present invention is carried out.
  • Step 6 depositing a protective layer 34 on the substrate, forming a second photoresist layer on the protective layer 34, and patterning the second photoresist layer to form a second photoresist pattern 35 at a predetermined position, which includes a drain portion 28 - a third portion 36 above the side and portion of the drain 28, and a fourth portion 37 above the other side of the drain 28 and a portion of the drain 28, and a third portion 36 of the second photoresist pattern 35 A recess is formed between the four portions 37, as shown in FIGS. 10 and 11.
  • the protective layer 34 is formed by deposition of silicon dioxide or a silicon nitride compound (SiN x ).
  • the second photoresist pattern 35 is formed by gray scale, mask, exposure, development, and the third portion 36 of the second photoresist pattern 35 is formed by gray scale exposure.
  • the second photoresist pattern 35 forms a recess with respect to the drain electrode 28, and the recess is used for etching to form the contact hole 41.
  • the third masking process of the three mask processes in the present invention is carried out.
  • Step 7 etching away the protective layer 34 not covered by the second photoresist pattern 35 and the insulating layer 3 corresponding to the portion of the protective layer 34 to expose the drain electrode 28, thereby forming the contact hole 41, and removing the second photoresist pattern 35 Three parts 36, as shown in Figures 12 and 13.
  • the protective layer 34 not covered by the second photoresist pattern 35 and the insulating layer 31 corresponding to the portion of the protective layer 34 are etched away by a thousand etching method, thereby forming a contact hole 41, and the contact hole 41 is located in the second light.
  • the third portion 36 and the fourth portion 37 of the resist pattern 35 are used to connect the drain of the thin film transistor.
  • Step 8 Depositing a transparent conductive layer 42 on the substrate, and peeling off the fourth portion 37 of the second photoresist pattern 35 and the transparent conductive layer 42 thereon by photoresist stripping, as shown in FIG. 14 and FIG. Show.
  • the transparent conductive layer 42 is configured to be coupled to a drain of the thin film transistor for use as an electrode of a storage capacitor in the array substrate.
  • Step 9 Annealing the substrate to complete the fabrication of the thin film transistor array substrate.
  • the thin film transistor array substrate adopts a top gate structure
  • the method of manufacturing the thin film transistor array substrate is to fabricate a TFT array substrate by using three masks, wherein indium gallium is used.
  • Zinc oxide to fabricate a thin film transistor array substrate The thin film transistor can greatly increase the charging rate of the thin film transistor to the pixel electrode, improve the response speed of the pixel, achieve a faster refresh rate, and at the same time, the faster response also greatly increases the pixel scanning rate, so that the ultra-high resolution is It is possible to use a thin film transistor liquid crystal display.
  • the manufacturing method uses only three masking processes, which can significantly reduce the processing steps, shorten the processing time, effectively reduce the production cost, increase the production efficiency, and increase the production capacity.

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Abstract

提供一种薄膜晶体管阵列基板的制造方法，该薄膜晶体管阵列基板采用顶栅结构，该薄膜晶体管阵列基板的制造方法通过三次掩模来制造TFT阵列基板，其中以铟镓锌氧化物来制造薄膜晶体管阵列基板中的薄膜晶体管，可以大大提高薄膜晶体管对像素电极的充电速率，提高像素的响应速度，实现更快的刷新率，同时更快的响应也提高了像素的行扫描速率，使得超高分辨率在薄膜晶体管液晶显示器中成为可能；同时，该制造方法仅采用了三次掩模工艺，能显著的减少制程步骤，缩短制程时间，有效地降低生产成本，提高生产效率，增加产能。

Description

液晶显示器制造领域， 尤其涉及一种釆用 3 次掩模的薄膜 体管阵列基板的制造方法 ( 背景;
现今科技蓬勃发展， 信息商品种类推陈出新， 满足了大众不同的需 （ Cathode Ray Tube, CRT )显示器， 由
Figure imgf000003_0001
耗电量大， 而且所产生的辐射对于长时间使用显示器的使 用者而言， 有危害身体的问题。 因此， 现今市面上的显示器渐渐将由液晶 显示器 ( Liquid Crystal Display , LCD )取代 i日有的 CRT显示器。
液晶显示' 省电、 无辐射等众多优点， 得到了广泛的应 用。 现有市场上的液晶显示器大部分为背光型液晶显示器， 其包括液晶面 板及背光模组 ( backlight module ) 。 液晶面板的工作原理是在两片平行的 玻璃基板当中放置液晶分子， 并在两片玻璃基板上施加驱动电压来控制液 晶分子的旋转方向， 以将背光模组的光线折射出来产生画面。 由于液晶面 光源来正常显示影像， 因此， 背
Figure imgf000003_0002
其中， 液晶面板中两片平行的玻璃基板分别为薄膜晶体管阵列基板与 彩色滤光片基板。 该薄膜晶体管阵列基板包括： 基板； 形成于所述基板上 的柵极线、 栅极、 柵绝缘层， 半导体有源层、 数据线、 源极、 漏极， 及形 成于所述数据线、 源极、 漏极上的保护层， 和形成于所述保护层上的像素 电极， 其中， 所述柵极、 源极、 漏极和半导体有源层构成薄膜晶体管 ( TFT ) 。 在现有技术中， 该薄膜晶体管为非晶硅薄膜晶体管或低温多晶 硅薄膜晶体管， 通常非晶硅薄膜晶体管显示矩阵只需 3— 5 次光刻掩模 板， 其成本较低， 竟争力强， 而低温多晶硅薄膜晶体管显示矩阵通常需要 8— 9次光刻掩模板， 相对成本较高。
氧化物半导体 IGZO ( Indium Gallium Zinc Oxide, 铟镓锌氧化物） 由 于其载流子迁移率是非晶硅的 20〜30倍， 可以大大提高薄膜晶体管对像素 电极的充放电速率， 提高像素的响应速度， 实现更快的刷新率， 同时更快 的响应也大大提高了像素的行扫描速率， 使得超高分辨率在薄膜晶体管液 显示器 ( Thin Film Transistor TFT-LCD ) 中成,为 可能 另外， 由于薄膜晶体管数量减少和提高了每个像素的透光率， IGZO 液晶显示器具有更高的能效水平， 而且效率更高„ 氧化物半导体 IGZO 可 以利用现有的非晶硅生产线生产， 只需稍加改动， 因此在成本方面比低温 多晶硅更有竟争力。
但， 目前， 以氧化物半导体 IGZO制造的薄膜晶体管主要是采用 6次 掩模 ( 6inasks )工艺制造， 生产效率较底， 生产成本较高。
' 本发明的目的在于提供一种薄膜晶体管阵列基板的制造方法， 通过 3 次掩模（3 masks )来制造薄膜晶体管阵列基板， 能显著的减少制程步骤， 缩短制程时间， 有效地降低生产成本， 增加产能， 且， 该薄膜晶体管阵列 基板采用铟镓锌氧化物制造而成， 可以大大提高薄膜晶体管对像素电极的 充电速率， 提高像素的响应速度， 实现更快的刷新率
为实现上述目的， 本发明提供一种薄膜晶体管阵列基板的制造方法， 该薄膜晶体管阵列基板采用顶栅结构， 所述薄膜晶体管阵列基板的制造方 法包括以下步骤：
步骤 1、 提供一基板；
步骤 2、 在所述.基板上依次沉积形成緩冲层、 氧化物半导体薄膜及第 一金属层；
步骤 3、 在所述第一金属层上形成第一光阻层， 图案化该第一光阻层 以在預定位置形成第一光阻图案， 其包括对应氧化物半导体薄膜的一沟道 区的第一部分、 及第二部分， 该第一光阻图案在第二部分的厚度厚于第一 部分的厚度；
步骤 4、 蚀刻掉没有第一光阻图案覆盖的区域的第一金属层及氧化物 半导体薄膜， 去掉第一光阻图案的第一部分以露出第一金属层， 以第一光 阻图案的第二部分为掩模蚀刻掉第一金属层以露出氧化物半导体薄膜， 剥 离第一光阻图案， 以在第一金属层形成源极及漏极；
步骤 5、 在基板上依次沉积绝缘层及第二金属层， 图案化第二金属层 以形成柵极。
所述薄膜晶体管阵列基板的制造方法还包括：
在步骤 5之后的步骤 6, 在所述基板上沉积保护层， 在所述保护层上 形成第二光阻层， 图案化该第二光阻层以在预定位置形成第二光阻图案， 其包括位于漏极一侧及部分漏极上方的第三部分、 以及位于漏极另一侧及 部分漏极上方的第四部分， 第二光阻图案的第三部分与第四部分之间形成 —凹部；
在步骤 6之后的步骤 7 , 蚀刻掉没有第二光阻图案覆盖的保护层及该 部分保护层对应的绝缘层以露出漏极， 进而形成接触孔， 去掉第二光阻图 案的第三部分；
在步骤 7之后的步骤 8， 在所述基板上沉积一透明导电层， 通过光阻 剥离将第二光阻图案的第四部分及其上的透明导电层剥离掉。
所述薄膜晶体管阵列基板的制造方法还包括在步骤 8之后的步骤 9， 对所述基板进行退火处理， 完成薄膜晶体管阵列基板的制造。
所述基板为玻璃基板； 所述緩冲层采用二氧化硅沉积而形成； 所述氧 化物半导体薄膜为铟镓锌氧化物薄膜。
所述步骤 3中的第一光阻图案通过灰阶、 掩模、 曝光、 显影而形成。 所述步骤 4 中采用千法蚀刻方式以第一光阻图案的第二部分为掩模蚀 刻掉第一金属层； 所述步骤 4 中的剥离第一光阻图案为将第一光阻图案的 第二部分剥离掉
所述步骤 5 中的绝缘层采用二氧化硅沉积而形成； 所述步骤 5中的第 二金属层通过曝光、 显影、 蚀刻及光阻剥离制程形成橋极。
所述蚀刻为湿法蚀刻。
所述步骤 6 中的保护层采用二氧化硅或硅氮化合物沉积而形成； 所述 第二光阻图案通过灰阶。 掩模、 曝光、 显影而形成。
所述步骤 7 中采用千法蚀刻方式蚀刻掉没有第二光阻图案覆盖的保护 层及该部分保护层对应的绝缘层， 进而形成接触孔。
本发明还提供一种薄膜晶体管阵列基板的制造方法， 该薄膜晶体管阵 列基板采用顶柵结构， 所述薄膜晶体管阵列基板的制造方法包括以下步 骤：
步骤 1、 提供一基板；
步骤 2。 在所述基板上依次沉积形成缓冲层、 氧化物半导体薄膜及第 一金属层；
步骤 3、 在所述第一金属层上形成第一光阻层， 图案化该第一光阻层 以在预定位置形成第一光阻图案， 其包括对应氧化物半导体薄膜的一沟道 区的第一部分、 及第二部分， 该第一光阻图案在第二部分的厚度厚于第一 部分的厚度；
步骤 4、 蚀刻掉没有第一光阻图案覆盖的区域的第一金属层及氧化物 半导体薄膜， 去掉第一光阻图案的第一部分以露出第一金属层， 以第一光 阻图案的第二部分为掩模蚀刻掉第一金属层以露出氧化物半导体薄膜， 剥 离第一光阻图案， 以在第一金属层形成源极及漏极；
步骤 5、 在基板上依次沉积绝缘层及第二金属层， 图案化第二金属层 以形成 4册极；
还包括：
在步骤 5 之后的步骤 6， 在所述基板上沉积保护层， 在所述保护层上 形成第二光阻层， 图案化该第二光阻层以在预定位置形成第二光阻图案， 其包括位于漏极一侧及部分漏极上方的第三部分, 以及位于漏极另一侧及 部分漏极上方的第四部分， 第二光阻图案的第三部分与第四部分之间形成 一凹部；
在步骤 6之后的步骤 7， 蚀刻掉没有第二光阻图案覆盖的保护层及该 部分保护层对应的绝缘层以露出漏极， 进而形成接触孔， 去掉第二光阻图 案的第三部分；
在步骤 7之后的步骤 8 , 在所述.基板上沉积一透明导电层， 通过光阻 剥离将第二光阻图案的第四部分及其上的透明导电层剥离掉；
还包括在步骤 8之后的步驟 9， 对所述基^!进行退火处理， 完成薄膜 晶体管阵列基板的制造；
其中， 所述基板为玻璃基板； 所述緩冲层采用二氧化硅沉积而形成； 所述氧化物半导体薄膜为铟镓锌氧化物薄膜；
其中， 所述步驟 3 中的第一光阻图案通过灰阶、 掩模、 曝光、 显影而 形 / ；
其中， 所述步骤 4 中采用千法蚀刻方式以第一光阻图案的第二部分为 掩模蚀刻掉第一金属层； 所述步骤 4 中的剥离第一光阻图案为将第一光阻 图案的第二部分剥离掉。
所述步骤 5中的绝缘层采用二氧化硅沉积而形成； 所述步骤 5中的第 二金属层通过曝光。 显影、 蚀刻及光阻剥离制程形成 *极。
所述独刻为湿法蚀刻。
所述步骤 6 中的保护层采用二氧化硅或硅氮化合物沉积而形成； 所述 第二光阻图案通过灰阶、 掩^ I、 曝光、 显影而形成。
所述步骤 7 中采用千法饯刻方式蚀刻掉没有第二光阻图案覆盖的保护 层及该部分保护层对应的绝缘层， 进而形成接触孔。
本发明的有益效杲： 本发明的薄膜晶体管阵列基板的制造方法， 该薄 膜晶体管阵列基板采用顶柵结构， 该薄膜晶体管阵列基板的制造方法通过
3次掩模来制造 TFT阵列基板， 其中以铟镓锌氧化物来制造薄膜晶体管阵 列基板中的薄膜晶体管， 可以大大提高薄膜晶体管对像素电极的充电速 率， 提高像素的响应速度， 实现更快的刷新率， 同时更快的响应也大大提 高了像素的行扫描速率， 使得超高分辨率在薄膜晶体管液晶显示器中成为 可能； 同时， 该制造方法仅采用了 3 次掩模工艺， 能显著的减少制程步 骤， 缩短制程时间， 有效地降低生产成本， 提高生产效率， 增加产能。
为了能更进一步了解本发明的特征以及技术内容， 请参阅以下有关本 发明的详细说明与 †图， 然而附图仅提供参考与说明用， 并非用来对本发 明加以限制。 附图说明
下面结合附图， 通过对本发明的具体实施方式详细描述， 将使本发明 的技术方案及其它有益效果显而易见。
附图中，
图 1为本发明薄膜晶体管阵列基板的制造方法的流程图；
图 2 为本发明中缓冲层、 铟镓锌氧化物薄膜及第一金属层形成于基板 上的结构示意图；
图 3为本发明中第一光阻层形成于基板上的结构示意图；
图 4 为本发明中基板曝光后蚀刻掉没有第一光阻层覆盖的铟镓锌氧化 物薄膜及第一金属层的结构示意图；
图 5 为本发明中基板灰化掉第一灰阶曝光区域的第一光阻层的结构示 意图；
图 6为本发明中基板独刻掉第一灰阶曝光区域的第一金属层的结构示 意图；
图 7为本发明中基板剥离掉第一光阻层的结构示意图；
图 8 为本发明中节点层及第二金属层沉积形成于基板上的结构示意 i¾J
图 9为本发明中基板上形成栅极的结构示意图；
图 10为本发明中保护层形成于基板上的结构示意图；
图 l i为本发明中第二阻光层形成于基板上的结构示意图；
图 12为本发明中基板形成接触孔的结构示意图；
图 13 为本发明中基板灰化掉第二灰阶曝光区域的第二光阻层的结构 示意图；
图 14为本发明中透明导电层形成于基板上的结构示意图；
图 〗5 为本发明中基本剥离掉第二正常曝光区域的第二光阻层及该部 分第二光阻层上的透明导电层后的结构示意图。 具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果， 以下结合本发明 的优选实施例及其附图进行详细描述。
请参阅图 1 至图 15 , 本发明提供一种薄膜晶体管阵列基板的制造方 法， 该薄膜晶体管阵列基板采用顶柵结构， 该方法仅采用了 3 次掩模工 艺， 有效地降低生产成本， 提高生产效率， 增加产能。
该薄膜晶体管阵列基板的制造方法具体包括以下步骤：
步骤 1、 提供一基板 21。
在本实施例中， 所述基板 21 优选采用玻璃基板， 然不限于此， 也可 以釆用其它材质的基板， 如塑料等。
步骤 2、 在所述基板 21 上依次沉积形成缓冲层 22、 氧化物半导体薄 膜 23及第一金属层 24。
如图 2 所示， 在本实施例中， 所述緩冲层 22采用二氧化硅沉积而形 成， 所述氧化物半导体薄膜 23为铟镓锌氧化物薄膜。
步骤 3、 在所述第一金属层 24上形成第一光阻层， 图案化该第一光阻 层以在预定位置形成第一光阻图案 25 , 其包括对应氧化物半导体薄膜 23 的一沟道区的第一部分 26、 及第二部分 27， 该第一光阻图案 25在第二部 分 27的厚度厚于第一部分 26的厚度。
如图 3所示， 所述步骤 3 中的第一光阻图案 25通过灰阶、 掩模、 曝 光、 显影, ¾形成， 且采用灰阶曝光形成第一光阻图案 25 的第一部分 26。 在该步骤中进行本发明中 3次掩模工艺的第 1次掩模工艺。
步骤 4、 蚀刻掉没有第一光阻图案 25覆盖的区域的第一金属层 24及 氧化物半导体薄膜 23， 去掉第一光阻图案 25的第一部分 26以露出第一金 属层 24， 以第一光阻图案 25的第二部分 27为掩模蚀刻掉第一金属层 24 以露出氧化物半导体薄膜 23， 剥离第一光阻图案 25 , 以在第一金属层 24 形成源极 27及漏极 28。
在该步骤中， 采用千法蝕刻方式以第一光阻图案 25的第二部分 27为 掩模蚀刻掉第一金属层 24， 如图 6 所示， 且， 所述剥离第一光阻图案 25 为将第一光阻图案 25的第二部分 27剥离掉， 如图 7所示。
步骤 5、 在基板上依次沉积绝缘层 3 ! 及第二金属层 32， 图案化第二 金属层 32以形成櫥极 33。
在本实施例中， 所述绝缘层 31优选采用二氧化硅沉积而形成。
请参阅图 8及图 9， 该步骤中第二金属层 32通过曝光、 显影， 蚀刻及 光阻剥离制程形成槲极 330 该步骤中对第二金属层 32 的曝光为一次普通 的曝光， 操作简单， 方便快捷， 有利于提高产能； 该步骤中对第二金属层 32的蚀刻为湿法蚀刻。 在该步骤中进行本发明中 3次掩模工艺的第 2次掩 模工艺。
步骤 6、 在所述基板上沉积保护层 34， 在所述保护层 34上形成第二 光阻层， 图案化该第二光阻层以在预定位置形成第二光阻图案 35 , 其包括 位于漏极 28 —側及部分漏极 28上方的第三部分 36、 以及位于漏极 28另 一侧及部分漏极 28上方的第四部分 37， 第二光阻图案 35 的第三部分 36 与第四部分 37之间形成一凹部， 如图 10及图 1 1所示。
在本实施例中， 所述保护层 34采用二氧化硅或硅氮化合物 （SiNx )沉 积而形成。 所述第二光阻图案 35 通过灰阶、 掩模、 曝光、 显影而形成， 且采用灰阶曝光形成第二光阻图案 35 的第三部分 36。 所述第二光阻图案 35相对漏极 28形成一凹部， 该凹部用于进行蚀刻， 从而形成接触孔 41。 在该步骤中进行本发明中 3次掩模工艺的第 3次掩模工艺。
步骤 7、 蚀刻掉没有第二光阻图案 35覆盖的保护层 34及该部分保护 层 34对应的绝缘层 3】 以露出漏极 28， 进而形成接触孔 41， 去掉第二光 阻图案 35的第三部分 36, 如图 12及图 13所示。
该步骤中釆用千法蚀刻方式蚀刻掉没有第二光阻图案 35 覆盖的保护 层 34及该部分保护层 34对应的绝缘层 31， 进而形成接触孔 41， 所述接 触孔 41位于第二光阻图案 35的第三部分 36与第四部分 37之间， 用于连 接薄膜晶体管的漏极。
步糠 8、 在所述基板上沉积一透明导电层 42 , 通过光阻剥离将第二光 阻图案 35的第四部分 37及其上的透明导电层 42剥离掉， 如图 14及图 15 所示。
所述透明导电层 42 用于耦接至所述薄膜晶体管的漏极， 用来作为阵 列基板中的存储电容的一电极。
步骤 9、 对所述基板进行退火处理， 完成薄膜晶体管阵列基板的制 造。
值得说明的是， 本发明的技术方案不仅仅适用于 TFT液晶显示器阵列 基板的制作， 同时也适用于其他涉及光学薄膜、 电子薄膜等沉积的相关领
" 综上所述， 本发明的薄膜晶体管阵列基板的制造方法， 该薄膜晶体管 阵列基板采用顶柵结构， 该薄膜晶体管阵列基板的制造方法通过 3 次掩模 来制造 TFT阵列基板， 其中以铟镓锌氧化物来制造薄膜晶体管阵列基板中 的薄膜晶体管， 可以大大提高薄膜晶体管对像素电极的充电速率， 提高像 素的响应速度， 实现更快的刷新率， 同时更快的响应也大大提高了像素的 行扫描速率， 使得超高分辨率在薄膜晶体管液晶显示器中成为可能； 同 时， 该制造方法仅釆用了 3 次掩^ 工艺， 能显著的减少制程步骤， 缩短制 程时间， 有效地降低生产成本， 提高生产效率， 增加产能。
以上所述， 对于本领域的普通技术人员来说， 可以根据本发明的技术 方案和技术构思作出其他各种相应的改变和变形， 而所有这些改变和变形 都应属于本发明权利要求的保护范围„

Claims

权 利 要 求
】、 一种薄膜晶体管阵列基板的制造方法， 该薄膜晶体管阵列基板采 用顶柵结构， 所述薄膜晶体管阵列基板的制造方法包括以下步骤：
步骤 1、 提供一基板；
步骤 2、 在所述基板上依次沉积形成缓冲层， 氧化物半导体薄膜及第 —金属层；
步骤 3。 在所述第一金属层上形成第一光阻层， 图案化该第一光阻层 以在预定位置形成第一光阻图案， 其包括对应氧化物半导体薄膜的一沟道 区的第一部分、 及第二部分， 该第一光阻图案在第二部分的厚度厚于第一 部分的厚度；
步骤 4、 蚀刻掉没有第一光阻图案覆盖的区域的第一金属层及氧化物 半导体薄膜， 去掉第一光阻图案的第一部分以露出第一金属层， 以第一光 阻图案的第二部分为掩模蚀刻掉第一金属层以露出氧化物半导体薄膜， 剥 离第一光阻图案， 以在第一金属层形成源极及漏极；
步骤 5、 在基板上依次沉积绝缘层及第二金属层， 图案化第二金属层 以形成 4册极。
2、 如权利要求 1所述的薄膜晶体管阵列基板的制造方法， 还包括： 在步骤 5之后的步骤 6， 在所述基板上沉积保护层， 在所述保护层上 形成第二光阻层， 图案化该第二光阻层以在预定位置形成第二光阻图案， 其包括位于漏极一侧及部分漏极上方的第三部分 以及位于漏极另一侧及 部分漏极上方的第四部分， 第二光阻图案的第三部分与第四部分之间形成 一凹部；
在步骤 6之后的步骤 7， 蚀刻掉没有第二光阻图案覆盖的保护层及该 部分保护层对应的绝缘层以露出漏极， 进而形成接触孔， 去掉第二光阻图 案的第三部分；
在步骤 7之后的步骤 8 , 在所述基板上沉积一透明导电层， 通过光阻 剥离将第二光阻图案的第四部分及其上的透明导电层剥离掉。
3、 如权利要求 2 所述的薄膜晶体管阵列基板的制造方法， 还包括在 步驟 8之后的步骤 9 , 对所述基板进行退火处理， 完成薄膜晶体管阵列基 板的制造。
4、 如权利要求 1 所述的薄膜晶体管阵列基板的制造方法， 其中， 所 述基板为玻璃基板； 所述緩冲层采用二氧化硅沉积而形成； 所述氧化物半
9 导体薄膜为铟镓锌氧化物薄膜。
5、 如权利要求 1 所述的薄膜晶体管阵列基板的制造方法， 其中， 所 述步骤 3中的第一光阻图案通过灰阶、 掩模、 曝光。 显影而形成。
6、 如权利要求 1 所述的薄膜晶体管阵列基板的制造方法， 其中， 所 述步骤 4 中采用千法独刻方式以第一光阻图案的第二部分为掩模蚀刻掉第 一金属层； 所述步骤 4 中的剥离第一光阻图案为将第一光阻图案的第二部 分剥离掉。
7、 如权利要求 1 所述的薄膜晶体管阵列基板的制造方法， 其中， 所 述步骤 5中的绝缘层釆用二氧化硅沉积而形成； 所述步驟 5中的第二金属 层通过曝光、 显影、 蚀刻及光阻剥离制程形成柵极。
8、 如权利要求 7 所述的薄膜晶体管阵列基板的制造方法， 其中， 所 述 ί:虫刻为湿法蚀刻。
9、 如权利要求 2 所述的薄膜晶体管阵列基板的制造方法， 其中， 所 述步骤 6 中的保护层采用二氧化硅或硅氮化合物沉积而形成； 所述第二光 阻图案通过灰阶、 掩模、 曝光、 显影而形成。
】0、 如权利要求 2所述的薄膜晶体管阵列基板的制造方法， 其中， 所 述步骤 7 中采用千法蚀刻方式蚀刻掉没有第二光阻图案覆盖的保护层及该 部分保护层对应的绝缘层， 进而形成接触孔。
1 1 . 一种薄膜晶体管阵列基板的制造方法， 该薄膜晶体管阵列基板釆 用顶 *结构， 所述薄膜晶体管阵列基板的制造方法包括以下步驟：
步骤 1、 提供一基板；
步骤 2、 在所述基板上依次沉积形成緩冲层 氧化物半导体薄膜及第 一金属层；
步骤 3、 在所述第一金属层上形成第一光阻层， 图案化该第一光阻层 以在预定位置形成第一光阻图案， 其包括对应氧化物半导体薄膜的一沟道 区的第一部分、 及第二部分， 该第一光阻图案在第二部分的厚度厚于第一 部分的厚度；
步骤 4、 蚀刻掉没有第一光阻图案覆盖的区域的第一金属层及氧化物 半导体薄膜， 去掉第一光阻图案的第一部分以露出第一金属层， 以第一光 阻图案的第二部分为掩模蚀刻掉第一金属层以露出氧化物半导体薄膜， 剥 离第一光阻图案， 以在第一金属层形成源极及漏极；
步骤 5、 在基板上依次沉积绝缘层及第二金属层， 图案化第二金属层 以形成楣-极；
还包括：
10 在步骤 5之后的步骤 6 , 在所述基板上沉积保护层， 在所述保护层上 形成第二光阻层， 图案化该第二光阻层以在预定位置形成第二光阻图案， 其包括位于漏极一侧及部分漏极上方的第三部分、 以及位于漏极另一侧及 部分漏极上方的第四部分， 第二光阻图案的第三部分与第四部分之间形成 一凹部；
在步骤 6之后的步骤 Ί , 蚀刻掉没有第二光阻图案覆盖的保护层及该 部分保护层对应的绝缘层以露出漏极， 进而形成接触孔， 去掉第二光阻图 案的第三部分；
在步骤 7之后的步骤 8 , 在所述基板上沉积一透明导电层， 通过光阻 剥离将第二光阻图案的第四部分及其上的透明导电层剥离掉；
还包括在步骤 8之后的步骤 9， 对所述基板进行退火处理， 完成薄膜 晶体管阵列基板的制造；
其中， 所述.基板为玻璃基板； 所述缓冲层采用二氧化硅沉积而形成； ' 其中: 所 步骤 中的 光阻图案通过灰阶、 掩模、 爆光、 显影而 其中， 所述步骤 4 中采用千法蚀刻方式以第一光阻图案的第二部分为 掩模蚀刻掉第一金属层； 所述步骤 4 中的剥离第一光阻图案为将第一光阻 图案的第二部分剥离掉。
12、 如权利要求 1 1 所述的薄膜晶体管阵列基板的制造方法， 其中， 所述步骤 5 中的绝缘层釆用二氧化硅沉积而形成； 所述步骤 5中的第二金 属层通过曝光、 显影、 蚀刻及光阻剥离制程形成柵极。
13、 如权利要求 12 所述的薄膜晶体管阵列基板的制造方法， 其中， 所述蚀刻为湿法蚀刻。
14、 如权利要求 11 所述的薄膜晶体管阵列基板的制造方法， 其中， 光阻 案通过灰阶、 掩模、 '曝 显影而 成。 ' i
15 , 如权利要求 11 所述的薄膜晶体管阵列基板的制造方法， 其中， 所述步骤 7 中采用千法蚀刻方式蚀刻掉没有第二光阻图案覆盖的保护层及 该部分保护层对应的绝缘层， 进而形成接触孔。
11
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