WO2019223208A1 - 非晶硅tft基板的制作方法 - Google Patents

非晶硅tft基板的制作方法 Download PDF

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WO2019223208A1
WO2019223208A1 PCT/CN2018/108074 CN2018108074W WO2019223208A1 WO 2019223208 A1 WO2019223208 A1 WO 2019223208A1 CN 2018108074 W CN2018108074 W CN 2018108074W WO 2019223208 A1 WO2019223208 A1 WO 2019223208A1
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layer
photoresist
amorphous silicon
photoresist pattern
source
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PCT/CN2018/108074
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English (en)
French (fr)
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刘广辉
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武汉华星光电技术有限公司
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Priority to US16/313,045 priority Critical patent/US20190355836A1/en
Publication of WO2019223208A1 publication Critical patent/WO2019223208A1/zh

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    • H01L27/1288—
    • H01L29/66757—

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  • the present invention relates to the field of display technology, and in particular, to a method for manufacturing an amorphous silicon TFT substrate.
  • LCDs liquid crystal displays
  • AMOLED active matrix-driven organic light-emitting diodes
  • Thin film transistor (TFT) array substrates are the main components of current LCD devices and AMOLED devices, which are directly related to the development direction of high-performance flat panel display devices. They are used to provide driving circuits for displays.
  • Grid scan lines and data lines, the grid scan lines and data lines define a plurality of pixel units, and each pixel unit is provided with a thin film transistor and a pixel electrode.
  • the gate scanning lines are connected. When the voltage on the gate scanning line reaches the turn-on voltage, the source and drain of the thin film transistor are turned on, thereby inputting the data voltage on the data line to the pixel electrode, and then controlling the corresponding pixel area. display.
  • the current TFT is mainly divided into an amorphous silicon (A-Si) TFT and a low temperature poly-silicon (LTPS) TFT.
  • amorphous silicon TFT technology has low resolution and high power consumption, but its short production cycle, low cost, and easy large-area manufacturing process, so it is a very popular product in the market and is currently used in the semiconductor industry. It is also the most extensive.
  • the exposure (Photo) equipment is the most core and most expensive equipment. Therefore, the production capacity of the mass production line is based on the exposure equipment. Therefore, in the development of the semiconductor industry, save on use
  • the exposure process carried out by Masks to increase production capacity and reduce costs has become a major requirement to promote technological development.
  • a 6mask process is usually used. Recently, through optimization design, a transition to a 5mask or even a 4mask process has been gradually implemented, but this still cannot meet the increasing production capacity requirements of the TFT array substrate.
  • An object of the present invention is to provide a method for manufacturing an amorphous silicon TFT substrate.
  • the present invention provides a method for manufacturing an amorphous silicon TFT substrate, including the following steps:
  • Step S1 providing a base substrate, and sequentially depositing and forming an amorphous silicon layer, an N-type doped amorphous silicon layer, a first transparent conductive layer, and a source / drain metal layer on the base substrate;
  • Step S2 coating a photoresist material on the source and drain metal layers and performing a first photomask process to form a first photoresist layer, and the first photoresist layer has a first photoresist pattern with an increasing thickness sequentially.
  • Step S3 Perform the first etching process using the first photoresist layer as a shielding layer to remove the amorphous silicon layer, the N-type doped amorphous silicon layer, the first transparent conductive layer, and the source and drain metal layers.
  • the portion not covered by the first photoresist layer corresponds to an amorphous silicon active layer obtained from an amorphous silicon layer under the first photoresist pattern and the second photoresist pattern, and corresponds to the third photoresist pattern.
  • Step S4 performing a first ashing treatment on the first photoresist layer, thinning the second photoresist pattern and the third photoresist pattern and removing the first photoresist pattern;
  • Step S5 Perform a second etching process using the first photoresist layer as a shielding layer to remove the N-type doped amorphous silicon layer, the first transparent conductive layer, and the source and drain metal layers without the first photoresist layer.
  • the covered portion corresponds to the source and drain metal layers under the second photoresist pattern corresponding to the source and drain electrodes located on both ends of the amorphous silicon active layer, and the N-type doped amorphous silicon layer corresponding to A source-drain contact area under the source and drain;
  • Step S6 performing a second ashing treatment on the first photoresist layer to thin the third photoresist pattern and remove the second photoresist pattern;
  • Step S7 Perform a third etching process using the first photoresist layer as a shielding layer to remove the source and drain metal layers corresponding to the pixel electrode to expose the pixel electrode; peel and remove the remaining first photoresist layer;
  • Step S8 A passivation layer covering the active layer, source electrode, drain electrode, and pixel electrode of the amorphous silicon is deposited on the base substrate, and the corresponding passivation layers are formed on the passivation layer through a second photomask process. And the first via hole and the second via hole above the pixel electrode;
  • Step S9 sequentially depositing a second transparent conductive layer and a gate metal layer on the passivation layer; coating a photoresist material on the source and drain metal layers and performing a third photomask process to form a second light A resist layer, the second photoresist layer having a fourth photoresist pattern and a fifth photoresist pattern which are sequentially increased in thickness;
  • Step S10 Perform the first etching process by using the second photoresist layer as a shielding layer, and remove portions of the second transparent conductive layer and the gate metal layer that are not covered by the second photoresist layer, corresponding to the A metal common electrode line corresponding to the gate and the gate spaced above the amorphous silicon active layer is obtained from the gate metal layer below the fourth photoresist pattern, corresponding to the first photoresist pattern below the fifth photoresist pattern.
  • the conductive connection block obtained from the two transparent conductive layers and the transparent common electrode line spaced from the conductive connection block, wherein the conductive connection block is in contact with the drain electrode and the pixel electrode through the first via hole and the second via hole, respectively, and then the drain electrode And the pixel electrode is electrically connected;
  • Step S11 performing a first ashing treatment on the second photoresist layer, thinning a five photoresist pattern and removing a fourth photoresist pattern;
  • Step S12 Perform a second etching process by using the second photoresist layer as a shielding layer to remove the gate metal layer corresponding to the conductive connection block and the transparent common electrode line; peel and remove the remaining second photoresist layer .
  • step S2 a first mask process is performed by using a grayscale mask.
  • step S9 a third mask process is performed by using a grayscale mask or a halftone.
  • the applied photoresist material is a positive type photoresist material.
  • the photoresist material is divided into those that gradually decrease from full exposure to non-exposure in the exposure degree. Four portions exposed at four exposure levels, and then the four portions that gradually decrease in exposure are removed after development, formed into the first photoresist pattern, formed into the second photoresist pattern, and formed into The third photoresist pattern.
  • the applied photoresist material is a positive type photoresist material.
  • the photoresist material is divided into three which are gradually reduced from full exposure to non-exposure in the exposure degree. The three parts exposed at this level of exposure, and then the three parts that gradually decrease in exposure are removed after development, formed into the fourth photoresist pattern, and formed into the fifth photoresist pattern.
  • the material of the first transparent conductive layer and the second transparent conductive layer is indium tin oxide.
  • step S1 the amorphous silicon layer, the N-type doped amorphous silicon layer, and the first transparent conductive layer are formed by chemical vapor deposition, and the source and drain metal layers are formed by sputtering.
  • step S8 the passivation layer is formed by chemical vapor deposition.
  • a second transparent conductive layer is formed by a chemical vapor deposition method, and the gate metal layer is formed by a sputtering method.
  • step S1 the N-type doped amorphous silicon layer is formed by adding phosphane during the deposition process.
  • a first photoresist layer having a photoresist pattern with three thicknesses is formed through a first exposure process, and three etching processes and two gray processes are performed. Patterning process, the first photoresist layer is used to complete the patterning of the four layers of the amorphous silicon layer, the N-type doped amorphous silicon layer, the first transparent conductive layer, and the source and drain metal layers, and then the second exposure process is performed. The passivation layer is patterned. Finally, a second photoresist layer having a photoresist pattern with two thicknesses is formed through a third exposure process.
  • the second photoresist layer is used to complete the second photoresist layer through two etching processes and one ashing process.
  • the transparent conductive layer and the gate metal layer are patterned.
  • FIG. 1 is a schematic flowchart of a manufacturing method of an amorphous silicon TFT substrate according to the present invention
  • step S1 is a schematic diagram of step S1 of a method for manufacturing an amorphous silicon TFT substrate according to the present invention
  • FIG. 3 is a schematic diagram of step S2 of the method for manufacturing an amorphous silicon TFT substrate according to the present invention
  • FIG. 4 is a schematic diagram of step S3 of the method for manufacturing an amorphous silicon TFT substrate according to the present invention.
  • FIG. 5 is a schematic diagram of step S4 of the method for manufacturing an amorphous silicon TFT substrate according to the present invention.
  • FIG. 6 is a schematic diagram of step S5 of the method for manufacturing an amorphous silicon TFT substrate according to the present invention.
  • FIG. 7 is a schematic diagram of step S6 of the method for manufacturing an amorphous silicon TFT substrate according to the present invention.
  • step S7 of the method for manufacturing an amorphous silicon TFT substrate according to the present invention are schematic views of step S7 of the method for manufacturing an amorphous silicon TFT substrate according to the present invention.
  • FIG. 10 is a schematic diagram of step S8 of the method for manufacturing an amorphous silicon TFT substrate according to the present invention.
  • FIG. 11 is a schematic diagram of step S9 of the method for manufacturing an amorphous silicon TFT substrate according to the present invention.
  • FIG. 12 is a schematic diagram of step S10 of a method for manufacturing an amorphous silicon TFT substrate according to the present invention.
  • FIG. 13 is a schematic diagram of step S11 of the method for manufacturing an amorphous silicon TFT substrate according to the present invention.
  • step S12 of a method for manufacturing an amorphous silicon TFT substrate according to the present invention are schematic diagrams of step S12 of a method for manufacturing an amorphous silicon TFT substrate according to the present invention.
  • the present invention provides a method for manufacturing an amorphous silicon TFT substrate, including the following steps:
  • Step S1 as shown in FIG. 2, a base substrate 10 is provided, and an amorphous silicon layer 20, an N-type doped amorphous silicon layer 30, a first transparent conductive layer 40, and Source and drain metal layer 50.
  • a material of the first transparent conductive layer 40 is indium tin oxide (ITO).
  • the amorphous silicon layer 20, the N-type doped amorphous silicon layer 30, and the first transparent conductive layer 40 are formed by chemical vapor deposition (CVD) deposition, and the sputtering method (Sputter method) ) Deposited and formed the source and drain metal layer 50, in addition, the amorphous silicon layer 20, the N-type doped amorphous silicon layer 30, the first transparent conductive layer 40, and the source may be formed by other manufacturing methods. Drain metal layer 50.
  • CVD chemical vapor deposition
  • Sputter method sputtering method
  • step S1 the N-type doped amorphous silicon layer 30 is formed by adding phosphane during the deposition process.
  • Step S2 As shown in FIG. 3, a photoresist material is coated on the source and drain metal layer 50 and a first photomask process is performed to form a first photoresist layer 90.
  • the first photoresist layer 90 has The first photoresist pattern 91, the second photoresist pattern 92, and the third photoresist pattern 93 are sequentially increased in thickness.
  • step S2 a first mask process is performed by using a gray mask (GTM).
  • GTM gray mask
  • the applied photoresist material is a positive type photoresist material.
  • the photoresist material is divided into gradually decreasing from a full exposure to an exposure level. Four portions exposed at four exposure levels without exposure, and then the four portions that gradually decrease in exposure are removed after being developed, formed into the first photoresist pattern 91, and formed into the second light
  • the resist pattern 92 is formed as the third photoresist pattern 93.
  • Step S3 a first etching process is performed using the first photoresist layer 90 as a shielding layer to remove the amorphous silicon layer 20, the N-type doped amorphous silicon layer 30, and the first transparent layer.
  • the portions of the conductive layer 40 and the source / drain metal layer 50 that are not covered by the first photoresist layer 90 correspond to the non-crystalline silicon layer 20 under the first photoresist pattern 91 and the second photoresist pattern 92.
  • the crystalline silicon active layer 21 corresponds to the pixel electrode 41 obtained from the first transparent conductive layer 40 under the third photoresist pattern 93.
  • Step S4 As shown in FIG. 5, the first photoresist layer 90 is subjected to a first ashing process, the second photoresist pattern 92 and the third photoresist pattern 93 are thinned and the first photoresist is removed. Pattern 91.
  • Step S5. As shown in FIG. 6, a second etching process is performed using the first photoresist layer 90 as a shielding layer to remove the N-type doped amorphous silicon layer 30, the first transparent conductive layer 40, and the source and drain metals.
  • the portion of the layer 50 that is not covered by the first photoresist layer 90 corresponds to the source 51 that is located above the two ends of the amorphous silicon active layer 21 by the source and drain metal layer 50 under the second photoresist pattern 92.
  • the drain 52, the source-drain contact region 31 corresponding to the source 51 and the drain 52 is obtained from the N-type doped amorphous silicon layer 30.
  • Step S6 As shown in FIG. 7, the first photoresist layer 90 is subjected to a second ashing process to thin the third photoresist pattern 93 and remove the second photoresist pattern 92.
  • Step S7 As shown in FIG. 8-9, a third etching process is performed using the first photoresist layer 90 as a shielding layer, and the source and drain metal layers 50 corresponding to the pixel electrode 41 are removed to expose the pixel electrode. 41; peel off and remove the remaining first photoresist layer 90.
  • Step S8 As shown in FIG. 10, a passivation layer 60 is formed on the base substrate 10 to cover the amorphous silicon active layer 21, the source 51, the drain 52, and the pixel electrode 41. A first via hole 61 and a second via hole 62 corresponding to the drain electrode 52 and the pixel electrode 41 are formed on the passivation layer 60, respectively.
  • the passivation layer 60 is formed by a chemical vapor deposition method.
  • Step S9 As shown in FIG. 11, a second transparent conductive layer 70 and a gate metal layer 80 are sequentially formed on the passivation layer 60; a photoresist material is coated on the source and drain metal layer 50 and performed.
  • a second photoresist layer 95 is formed, and the second photoresist layer 95 has a fourth photoresist pattern 96 and a fifth photoresist pattern 97 which are sequentially increased in thickness.
  • a third mask process is performed by using a gray scale mask or a halftone mask (HTM).
  • HTM halftone mask
  • the applied photoresist material is a positive type photoresist material
  • the photoresist material is divided into gradually decreasing from full exposure to no exposure at the exposure level. Three parts exposed at three exposure levels of exposure, and then the three parts that gradually decrease in exposure are removed after being developed, formed into the fourth photoresist pattern 96, and formed into the fifth photoresist Pattern 97.
  • a material of the second transparent conductive layer 70 is indium tin oxide.
  • a second transparent conductive layer 70 is formed by a chemical vapor deposition method, and the gate metal layer 80 is formed by a sputtering method.
  • the second method may be formed by other manufacturing methods.
  • the transparent conductive layer 70 and the gate metal layer 80 are formed by a chemical vapor deposition method, and the gate metal layer 80.
  • Step S10 As shown in FIG. 12, a first etching process is performed using the second photoresist layer 95 as a shielding layer to remove the second photoresist on the second transparent conductive layer 70 and the gate metal layer 80.
  • the portion covered by the layer 95 corresponds to a metal corresponding to the space between the gate 81 and the gate 81 above the amorphous silicon active layer 21 obtained by the gate metal layer 80 under the fourth photoresist pattern 96.
  • the common electrode line 82 corresponds to the conductive connection block 71 obtained by the second transparent conductive layer 70 under the five photoresist pattern 97 and the transparent common electrode line 72 spaced from the conductive connection block 71, wherein the conductive connection block 71 passes through
  • the first via hole 61 and the second via hole 62 are in contact with the drain electrode 52 and the pixel electrode 41, and further electrically conduct the drain electrode 52 and the pixel electrode 41.
  • Step S11 As shown in FIG. 13, performing the first ashing treatment on the second photoresist layer 95, thinning the five photoresist patterns 97 and removing the fourth photoresist pattern 96;
  • Step S12 As shown in FIGS. 14-15, a second etching process is performed using the second photoresist layer 95 as a shielding layer to remove the gate metal corresponding to the conductive connection block 71 and the transparent common electrode line 72. Layer 80; the remaining second photoresist layer 95 is removed by peeling.
  • a first photoresist layer 90 having a photoresist pattern with three thicknesses is first formed through a first exposure process, and a third etching process and two ashing processes are used.
  • a photoresist layer 90 completes the patterning of the four layers of the amorphous silicon layer 20, the N-type doped amorphous silicon layer 30, the first transparent conductive layer 40, and the source / drain metal layer 50, and then proceeds through the second exposure process.
  • the passivation layer 60 is patterned, and finally a second photoresist layer 95 having a photoresist pattern with two thicknesses is formed through a third exposure process.
  • the second photoresist layer 95 is used through two etching processes and one ashing process.
  • the patterning of the second transparent conductive layer 70 and the gate metal layer 80 is completed.
  • the present invention further saves a photomask process compared to the existing 4mask process, and realizes the 3mask manufacturing process of the amorphous silicon TFT substrate.
  • the production of the amorphous silicon TFT substrate is completed through the three mask process, so that the overall productivity of the factory can be improved and the cost can be reduced.
  • a first photoresist layer having a photoresist pattern with three thicknesses is first formed through a first exposure process, and three etch processes and two ashing processes are performed.
  • the first photoresist layer is used to complete the patterning of the four layers of the amorphous silicon layer, the N-type doped amorphous silicon layer, the first transparent conductive layer, and the source and drain metal layers, and then passivation is performed through the second exposure process.
  • the present invention further saves a photomask process compared to the existing 4mask process, and realizes the 3mask manufacturing process of the amorphous silicon TFT substrate, thereby improving the factory's Overall productivity and reduced costs.

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Abstract

一种非晶硅TFT基板的制作方法，首先经第一道曝光制程形成具有三个厚度的光阻图案的第一光阻层，并通过三次蚀刻制程和两次灰化制程，利用第一光阻层完成非晶硅层、N型掺杂非晶硅层、第一透明导电层及源漏极金属层这四层的图案化，然后经第二道曝光制程进行钝化层的图案化，最后经第三道曝光制程形成具有两个厚度的光阻图案的第二光阻层，通过两次蚀刻制程和一次灰化制程，利用第二光阻层完成第二透明导电层及栅极金属层这两层的图案化。

Description

非晶硅TFT基板的制作方法 技术领域
本发明涉及显示技术领域，尤其涉及一种非晶硅TFT基板的制作方法。
背景技术
在显示技术领域，液晶显示器(Liquid Crystal Display，LCD)和有源矩阵驱动式有机电致发光(Active Matrix Organic Light-Emitting Diode，AMOLED)显示器等平板显示装置因具有机身薄、高画质、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本屏幕等。
薄膜晶体管(Thin Film Transistor，TFT)阵列(Array)基板是目前LCD装置和AMOLED装置中的主要组成部件，直接关系到高性能平板显示装置的发展方向，用于向显示器提供驱动电路，通常设置有数条栅极扫描线和数条数据线，该数条栅极扫描线和数条数据线限定出多个像素单元，每个像素单元内设置有薄膜晶体管和像素电极，薄膜晶体管的栅极与相应的栅极扫描线相连，当栅极扫描线上的电压达到开启电压时，薄膜晶体管的源极和漏极导通，从而将数据线上的数据电压输入至像素电极，进而控制相应像素区域的显示。
按照TFT内半导体材料的不同，目前TFT主要分成非晶硅(A-Si)TFT及低温多晶硅(Low Temperature Poly-Silicon，LTPS)TFT。非晶硅TFT相对于LTPS TFT技术分辨率低、功耗高，但其制作周期较短、成本低、易于进行大面积制程，因此是市场中备受青睐的产品，在目前的半导体行业中应用也最为广泛。
在半导体生产的量产线中，曝光(Photo)设备是最核心、最昂贵的设备，因此量产产线的生产产能都是依据曝光设备而定，所以在半导体行业发展的过程中，节省使用光罩(Mask)进行的曝光工艺，提升产能，降低成本成为主要推进技术发展的需求。在非晶硅TFT的制作工艺中，通常使用的是6mask工艺，近期通过优化设计，逐渐过渡到5mask甚至是4mask工艺，但是这还是不能满足对TFT阵列基板日益增加的产能需求。
发明内容
本发明的目的在于提供一种非晶硅TFT基板的制作方法，通过3mask 工艺制作非晶硅TFT基板，可以提升工厂的整体产能，降低成本。
为实现上述目的，本发明提供一种非晶硅TFT基板的制作方法，包括如下步骤：
步骤S1、提供一衬底基板，在所述衬底基板上依次沉积形成非晶硅层、N型掺杂非晶硅层、第一透明导电层及源漏极金属层；
步骤S2、在所述源漏极金属层上涂布光阻材料并进行第一道光罩制程，形成第一光阻层，所述第一光阻层具有厚度依次增加的第一光阻图案、第二光阻图案及第三光阻图案；
步骤S3、以所述第一光阻层为遮蔽层进行第一次蚀刻制程，去除所述非晶硅层、N型掺杂非晶硅层、第一透明导电层及源漏极金属层上未被第一光阻层覆盖的部分，对应于所述第一光阻图案和第二光阻图案下方由非晶硅层得到的非晶硅有源层，对应于所述第三光阻图案下方由第一透明导电层得到的像素电极；
步骤S4、对所述第一光阻层进行第一次灰化处理，薄化第二光阻图案及第三光阻图案并去除第一光阻图案；
步骤S5、以所述第一光阻层为遮蔽层进行第二次蚀刻制程，去除N型掺杂非晶硅层、第一透明导电层及源漏极金属层上未被第一光阻层覆盖的部分，对应于所述第二光阻图案下方由源漏极金属层得到对应位于非晶硅有源层两端上方的源极和漏极，由N型掺杂非晶硅层得到对应于源极和漏极下方的源漏极接触区；
步骤S6、对所述第一光阻层进行第二次灰化处理，薄化第三光阻图案并去除第二光阻图案；
步骤S7、以所述第一光阻层为遮蔽层进行第三次蚀刻制程，去除对应于所述像素电极上方的源漏极金属层而露出像素电极；剥离去除剩余的第一光阻层；
步骤S8、在衬底基板上沉积形成覆盖非晶硅有源层、源极、漏极及像素电极的钝化层，通过第二道光罩制程在所述钝化层上形成分别对应于漏极和像素电极上方的第一过孔和第二过孔；
步骤S9、在所述钝化层上依次沉积形成第二透明导电层及栅极金属层；在所述源漏极金属层上涂布光阻材料并进行第三道光罩制程，形成第二光阻层，所述第二光阻层具有厚度依次增加的第四光阻图案及第五光阻图案；
步骤S10、以所述第二光阻层为遮蔽层进行第一次蚀刻制程，去除所述第二透明导电层及栅极金属层上未被第二光阻层覆盖的部分，对应于所述第四光阻图案下方由栅极金属层得到对应位于所述非晶硅有源层上方的栅 极与所述栅极相间隔的金属公共电极线，对应于所述五光阻图案下方由第二透明导电层得到的导电连接块及与导电连接块相间隔的透明公共电极线，其中导电连接块分别通过第一过孔和第二过孔与漏极和像素电极相接触，进而将漏极和像素电极电导通；
步骤S11、对所述第二光阻层进行第一次灰化处理，薄化五光阻图案并去除第四光阻图案；
步骤S12、以所述第二光阻层为遮蔽层进行第二次蚀刻制程，去除对应于所述导电连接块和透明公共电极线上方的栅极金属层；剥离去除剩余的第二光阻层。
所述步骤S2中通过灰阶光罩进行第一道光罩制程。
所述步骤S9中通过灰阶光罩或半色调进行第三道光罩制程。
所述步骤S2中，所涂布的光阻材料为正型光阻材料，在所述第一道光罩制程中，该光阻材料分为分别在曝光程度由完全曝光逐渐降低至不曝光的四种曝光程度下曝光的四个部分，然后该曝光程度逐渐降低的四个部分在显影后分别被去掉、形成为所述第一光阻图案、形成为所述第二光阻图案、形成为所述第三光阻图案。
所述步骤S9中，所涂布的光阻材料为正型光阻材料，在所述第三道光罩制程中，该光阻材料分为分别在曝光程度由完全曝光逐渐降低至不曝光的三种曝光程度下曝光的三个部分，然后该曝光程度逐渐降低的三个部分在显影后分别被去掉、形成为所述第四光阻图案、形成为所述第五光阻图案。
所述第一透明导电层和第二透明导电层的材料为氧化铟锡。
所述步骤S1中，通过化学气相沉积法沉积形成所述非晶硅层、N型掺杂非晶硅层、第一透明导电层，通过溅射法沉积形成所述源漏极金属层。
所述步骤S8中，通过化学气相沉积法沉积形成所述钝化层。
所述步骤S9中，通过化学气相沉积法沉积形成第二透明导电层，通过溅射法沉积形成所述栅极金属层。
所述步骤S1中在沉积过程中通过加入磷烷形成所述N型掺杂非晶硅层。
本发明的有益效果：本发明的非晶硅TFT基板的制作方法，首先经第一道曝光制程形成具有三个厚度的光阻图案的第一光阻层，并通过三次蚀刻制程和两次灰化制程，利用第一光阻层完成非晶硅层、N型掺杂非晶硅层、第一透明导电层及源漏极金属层这四层的图案化，然后经第二道曝光制程进行钝化层的图案化，最后经第三道曝光制程形成具有两个厚度的光阻图案的第二光阻层，通过两次蚀刻制程和一次灰化制程，利用第二光阻 层完成第二透明导电层及栅极金属层这两层的图案化，本发明通过优化工艺，相对于现有4mask工艺进一步节省了一道光罩制程，实现非晶硅TFT基板的3mask制作工艺，从而可以提升工厂的整体产能，降低成本。
附图说明
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。
附图中，
图1为本发明的非晶硅TFT基板的制作方法的流程示意图；
图2为本发明的非晶硅TFT基板的制作方法的步骤S1的示意图；
图3为本发明的非晶硅TFT基板的制作方法的步骤S2的示意图；
图4为本发明的非晶硅TFT基板的制作方法的步骤S3的示意图；
图5为本发明的非晶硅TFT基板的制作方法的步骤S4的示意图；
图6为本发明的非晶硅TFT基板的制作方法的步骤S5的示意图；
图7为本发明的非晶硅TFT基板的制作方法的步骤S6的示意图；
图8-9为本发明的非晶硅TFT基板的制作方法的步骤S7的示意图；
图10为本发明的非晶硅TFT基板的制作方法的步骤S8的示意图；
图11为本发明的非晶硅TFT基板的制作方法的步骤S9的示意图；
图12为本发明的非晶硅TFT基板的制作方法的步骤S10的示意图；
图13为本发明的非晶硅TFT基板的制作方法的步骤S11的示意图；
图14-15为本发明的非晶硅TFT基板的制作方法的步骤S12的示意图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请参阅图1，本发明提供一种非晶硅TFT基板的制作方法，包括如下步骤：
步骤S1、如图2所示，提供一衬底基板10，在所述衬底基板10上依次沉积形成非晶硅层20、N型掺杂非晶硅层30、第一透明导电层40及源漏极金属层50。
具体地，所述第一透明导电层40的材料为氧化铟锡(ITO)。
具体地，所述步骤S1中，通过化学气相沉积法(CVD)沉积形成所述 非晶硅层20、N型掺杂非晶硅层30、第一透明导电层40，通过溅射法(Sputter)沉积形成所述源漏极金属层50，除此之外，也可以采用其他制作方式形成所述非晶硅层20、N型掺杂非晶硅层30、第一透明导电层40及源漏极金属层50。
具体地，所述步骤S1中在沉积过程中通过加入磷烷形成所述N型掺杂非晶硅层30。
步骤S2、如图3所示，在所述源漏极金属层50上涂布光阻材料并进行第一道光罩制程，形成第一光阻层90，所述第一光阻层90具有厚度依次增加的第一光阻图案91、第二光阻图案92及第三光阻图案93。
具体地，所述步骤S2中通过灰阶光罩(Gray Tone Mask，GTM)进行第一道光罩制程。
进一步地，所述步骤S2中，所涂布的光阻材料为正型光阻材料，在所述第一道光罩制程中，该光阻材料分为分别在曝光程度由完全曝光逐渐降低至不曝光的四种曝光程度下曝光的四个部分，然后该曝光程度逐渐降低的四个部分在被显影后分别被去掉、形成为所述第一光阻图案91、形成为所述第二光阻图案92、形成为所述第三光阻图案93。
步骤S3、如图4所示，以所述第一光阻层90为遮蔽层进行第一次蚀刻制程，去除所述非晶硅层20、N型掺杂非晶硅层30、第一透明导电层40及源漏极金属层50上未被第一光阻层90覆盖的部分，对应于所述第一光阻图案91和第二光阻图案92下方由非晶硅层20得到的非晶硅有源层21，对应于所述第三光阻图案93下方由第一透明导电层40得到的像素电极41。
步骤S4、如图5所示，对所述第一光阻层90进行第一次灰化处理(Ashing)，薄化第二光阻图案92及第三光阻图案93并去除第一光阻图案91。
步骤S5、如图6所示，以所述第一光阻层90为遮蔽层进行第二次蚀刻制程，去除N型掺杂非晶硅层30、第一透明导电层40及源漏极金属层50上未被第一光阻层90覆盖的部分，对应于所述第二光阻图案92下方由源漏极金属层50得到对应位于非晶硅有源层21两端上方的源极51和漏极52，由N型掺杂非晶硅层30得到对应于源极51和漏极52下方的源漏极接触区31。
步骤S6、如图7所示，对所述第一光阻层90进行第二次灰化处理，薄化第三光阻图案93并去除第二光阻图案92。
步骤S7、如图8-9所示，以所述第一光阻层90为遮蔽层进行第三次蚀 刻制程，去除对应于所述像素电极41上方的源漏极金属层50而露出像素电极41；剥离去除剩余的第一光阻层90。
步骤S8、如图10所示，在衬底基板10上沉积形成覆盖非晶硅有源层21、源极51、漏极52及像素电极41的钝化层60，通过第二道光罩制程在所述钝化层60上形成分别对应于漏极52和像素电极41上方的第一过孔61和第二过孔62。
具体地，所述步骤S8中，通过化学气相沉积法沉积形成所述钝化层60。
步骤S9、如图11所示，在所述钝化层60上依次沉积形成第二透明导电层70及栅极金属层80；在所述源漏极金属层50上涂布光阻材料并进行第三道光罩制程，形成第二光阻层95，所述第二光阻层95具有厚度依次增加的第四光阻图案96及第五光阻图案97。
具体地，所述步骤S9中通过灰阶光罩或半色调光罩(Half Tone Mask，HTM)进行第三道光罩制程。
进一步地，所述步骤S9中，所涂布的光阻材料为正型光阻材料，在所述第三道光罩制程中，该光阻材料分为分别在曝光程度由完全曝光逐渐降低至不曝光的三种曝光程度下曝光的三个部分，然后该曝光程度逐渐降低的三个部分在被显影后分别被去掉、形成为所述第四光阻图案96、形成为所述第五光阻图案97。
具体地，所述第二透明导电层70的材料为氧化铟锡。
所述步骤S9中，通过化学气相沉积法沉积形成第二透明导电层70，通过溅射法沉积形成所述栅极金属层80，除此之外，也可以采用其他制作方式形成所述第二透明导电层70和栅极金属层80。
步骤S10、如图12所示，以所述第二光阻层95为遮蔽层进行第一次蚀刻制程，去除所述第二透明导电层70及栅极金属层80上未被第二光阻层95覆盖的部分，对应于所述第四光阻图案96下方由栅极金属层80得到对应位于所述非晶硅有源层21上方的栅极81与所述栅极81相间隔的金属公共电极线82，对应于所述五光阻图案97下方由第二透明导电层70得到的导电连接块71及与导电连接块71相间隔的透明公共电极线72，其中导电连接块71分别通过第一过孔61和第二过孔62与漏极52和像素电极41相接触，进而将漏极52和像素电极41电导通。
步骤S11、如图13所示，对所述第二光阻层95进行第一次灰化处理，薄化五光阻图案97并去除第四光阻图案96；
步骤S12、如图14-15所示，以所述第二光阻层95为遮蔽层进行第二 次蚀刻制程，去除对应于所述导电连接块71和透明公共电极线72上方的栅极金属层80；剥离去除剩余的第二光阻层95。
本发明的非晶硅TFT基板的制作方法，首先经第一道曝光制程形成具有三个厚度的光阻图案的第一光阻层90，并通过三次蚀刻制程和两次灰化制程，利用第一光阻层90完成非晶硅层20、N型掺杂非晶硅层30、第一透明导电层40及源漏极金属层50这四层的图案化，然后经第二道曝光制程进行钝化层60的图案化，最后经第三道曝光制程形成具有两个厚度的光阻图案的第二光阻层95，通过两次蚀刻制程和一次灰化制程，利用第二光阻层95完成第二透明导电层70及栅极金属层80这两层的图案化，本发明通过优化工艺，相对于现有4mask工艺进一步节省了一道光罩制程，实现非晶硅TFT基板的3mask制作工艺，通过三道光罩制程完成非晶硅TFT基板的制作，从而可以提升工厂的整体产能，降低成本。
综上所述，本发明的非晶硅TFT基板的制作方法，首先经第一道曝光制程形成具有三个厚度的光阻图案的第一光阻层，并通过三次蚀刻制程和两次灰化制程，利用第一光阻层完成非晶硅层、N型掺杂非晶硅层、第一透明导电层及源漏极金属层这四层的图案化，然后经第二道曝光制程进行钝化层的图案化，最后经第三道曝光制程形成具有两个厚度的光阻图案的第二光阻层，通过两次蚀刻制程和一次灰化制程，利用第二光阻层完成第二透明导电层及栅极金属层这两层的图案化，本发明通过优化工艺，相对于现有4mask工艺进一步节省了一道光罩制程，实现非晶硅TFT基板的3mask制作工艺，从而可以提升工厂的整体产能，降低成本。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (10)

  1. 一种非晶硅TFT基板的制作方法，包括如下步骤：
    步骤S1、提供一衬底基板，在所述衬底基板上依次沉积形成非晶硅层、N型掺杂非晶硅层、第一透明导电层及源漏极金属层；
    步骤S2、在所述源漏极金属层上涂布光阻材料并进行第一道光罩制程，形成第一光阻层，所述第一光阻层具有厚度依次增加的第一光阻图案、第二光阻图案及第三光阻图案；
    步骤S3、以所述第一光阻层为遮蔽层进行第一次蚀刻制程，去除所述非晶硅层、N型掺杂非晶硅层、第一透明导电层及源漏极金属层上未被第一光阻层覆盖的部分，对应于所述第一光阻图案和第二光阻图案下方由非晶硅层得到的非晶硅有源层，对应于所述第三光阻图案下方由第一透明导电层得到的像素电极；
    步骤S4、对所述第一光阻层进行第一次灰化处理，薄化第二光阻图案及第三光阻图案并去除第一光阻图案；
    步骤S5、以所述第一光阻层为遮蔽层进行第二次蚀刻制程，去除N型掺杂非晶硅层、第一透明导电层及源漏极金属层上未被第一光阻层覆盖的部分，对应于所述第二光阻图案下方由源漏极金属层得到对应位于非晶硅有源层两端上方的源极和漏极，由N型掺杂非晶硅层得到对应于源极和漏极下方的源漏极接触区；
    步骤S6、对所述第一光阻层进行第二次灰化处理，薄化第三光阻图案并去除第二光阻图案；
    步骤S7、以所述第一光阻层为遮蔽层进行第三次蚀刻制程，去除对应于所述像素电极上方的源漏极金属层而露出像素电极；剥离去除剩余的第一光阻层；
    步骤S8、在衬底基板上沉积形成覆盖非晶硅有源层、源极、漏极及像素电极的钝化层，通过第二道光罩制程在所述钝化层上形成分别对应于漏极和像素电极上方的第一过孔和第二过孔；
    步骤S9、在所述钝化层上依次沉积形成第二透明导电层及栅极金属层；在所述源漏极金属层上涂布光阻材料并进行第三道光罩制程，形成第二光阻层，所述第二光阻层具有厚度依次增加的第四光阻图案及第五光阻图案；
    步骤S10、以所述第二光阻层为遮蔽层进行第一次蚀刻制程，去除所述第二透明导电层及栅极金属层上未被第二光阻层覆盖的部分，对应于所述 第四光阻图案下方由栅极金属层得到对应位于所述非晶硅有源层上方的栅极与所述栅极相间隔的金属公共电极线，对应于所述五光阻图案下方由第二透明导电层得到的导电连接块及与导电连接块相间隔的透明公共电极线，其中导电连接块分别通过第一过孔和第二过孔与漏极和像素电极相接触，进而将漏极和像素电极电导通；
    步骤S11、对所述第二光阻层进行第一次灰化处理，薄化五光阻图案并去除第四光阻图案；
    步骤S12、以所述第二光阻层为遮蔽层进行第二次蚀刻制程，去除对应于所述导电连接块和透明公共电极线上方的栅极金属层；剥离去除剩余的第二光阻层。
  2. 如权利要求1所述的非晶硅TFT基板的制作方法，其中，所述步骤S2中通过灰阶光罩进行第一道光罩制程。
  3. 如权利要求1所述的非晶硅TFT基板的制作方法，其中，所述步骤S9中通过灰阶光罩或半色调进行第三道光罩制程。
  4. 如权利要求2所述的非晶硅TFT基板的制作方法，其中，所述步骤S2中，所涂布的光阻材料为正型光阻材料，在所述第一道光罩制程中，该光阻材料分为分别在曝光程度由完全曝光逐渐降低至不曝光的四种曝光程度下曝光的四个部分，然后该曝光程度逐渐降低的四个部分在显影后分别被去掉、形成为所述第一光阻图案、形成为所述第二光阻图案、形成为所述第三光阻图案。
  5. 如权利要求3所述的非晶硅TFT基板的制作方法，其中，所述步骤S9中，所涂布的光阻材料为正型光阻材料，在所述第三道光罩制程中，该光阻材料分为分别在曝光程度由完全曝光逐渐降低至不曝光的三种曝光程度下曝光的三个部分，然后该曝光程度逐渐降低的三个部分在显影后分别被去掉、形成为所述第四光阻图案、形成为所述第五光阻图案。
  6. 如权利要求1所述的非晶硅TFT基板的制作方法，其中，所述第一透明导电层和第二透明导电层的材料为氧化铟锡。
  7. 如权利要求1所述的非晶硅TFT基板的制作方法，其中，所述步骤S1中，通过化学气相沉积法沉积形成所述非晶硅层、N型掺杂非晶硅层、第一透明导电层，通过溅射法沉积形成所述源漏极金属层。
  8. 如权利要求1所述的非晶硅TFT基板的制作方法，其中，所述步骤S8中，通过化学气相沉积法沉积形成所述钝化层。
  9. 如权利要求1所述的非晶硅TFT基板的制作方法，其中，所述步骤S9中，通过化学气相沉积法沉积形成第二透明导电层，通过溅射法沉积 形成所述栅极金属层。
  10. 如权利要求1所述的非晶硅TFT基板的制作方法，其中，所述步骤S1中在沉积过程中通过加入磷烷形成所述N型掺杂非晶硅层。
PCT/CN2018/108074 2018-05-21 2018-09-27 非晶硅tft基板的制作方法 WO2019223208A1 (zh)

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