WO2017071054A1 - 一种显示面板及其制造方法 - Google Patents

一种显示面板及其制造方法 Download PDF

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Publication number
WO2017071054A1
WO2017071054A1 PCT/CN2015/099123 CN2015099123W WO2017071054A1 WO 2017071054 A1 WO2017071054 A1 WO 2017071054A1 CN 2015099123 W CN2015099123 W CN 2015099123W WO 2017071054 A1 WO2017071054 A1 WO 2017071054A1
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Prior art keywords
source
drain
substrate
channel
forming
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PCT/CN2015/099123
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English (en)
French (fr)
Inventor
龙芬
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深圳市华星光电技术有限公司
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Priority to US14/907,247 priority Critical patent/US9859307B2/en
Publication of WO2017071054A1 publication Critical patent/WO2017071054A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a display panel and a method of fabricating the same.
  • COA Color Filter on Array
  • FIG. 1 is a schematic structural view of a display panel prepared by using the current COA process.
  • the gate electrode 12 and the common electrode 13, the first insulating layer 14, the channel 15, the source/drain 16, the color photoresist 17 are sequentially formed on the substrate 11, and finally the pixel electrode 18 is formed.
  • the resistance increases the plate pitch of the storage capacitor formed by the common electrode 13 and the pixel electrode 18, thereby causing the storage capacitance in the display panel 100 to be small, and the storage capacitor is used to maintain the voltage of the pixel electrode 18 constant for a predetermined time. If the storage capacitor is too small, the charge for maintaining the voltage on the pixel electrode 18 may leak quickly, causing the voltage on the pixel electrode 18 to decrease prematurely, affecting the display effect of the display panel 100.
  • the invention mainly solves the technical problem that the pixel electrode is easy to leak due to the large spacing of the storage capacitor plates in the display panel prepared by the existing COA process.
  • the present invention provides a method of manufacturing a display panel, the method comprising the steps of: providing a substrate, wherein a source and a drain are formed on the substrate by the same process; between the source and the drain Forming a channel, and causing a channel to connect the source and the drain; depositing a first insulating layer on the substrate; forming a plurality of red, green, and blue photoresists formed on the first insulating layer at intervals
  • the substrate is sequentially arranged in the order of red photoresist, green photoresist and blue photoresist; and the source, the drain and the channel are located between two adjacent color photoresists; the gate and the common are formed by the same process
  • An electrode, and the gate is formed on the first insulating layer between two adjacent color photoresists, the common electrode is formed on the color photoresist; the second insulating layer is formed on the gate and the common electrode, and the second insulation
  • the layer has a via hole connected to the source;
  • the step of forming the spaced source and drain electrodes on the substrate by the same process further comprises the steps of: forming a black matrix on the substrate; forming the spaced source and drain electrodes on the substrate by the same process comprises: The same process forms spaced sources and drains on the black matrix.
  • the step of forming a source, a drain, and a channel on the substrate further includes sequentially forming a semiconductor layer and a metal layer on the substrate; forming a source and a drain of the metal layer by a mask process to form a channel of the semiconductor layer And the source and drain are spaced apart on the channel, and the channel is connected to the source and the drain.
  • the present invention further provides a method of manufacturing a display panel, the method comprising the steps of: providing a substrate, forming a source, a drain, and a channel on the substrate; depositing a first insulating layer on the substrate; Forming a plurality of spaced-apart color photoresists on the first insulating layer such that the source, the drain, and the channel are located between two adjacent color photoresists; the gate and the common electrode are formed by the same process, and a gate is formed on the first insulating layer between two adjacent color photoresists, a common electrode is formed on the color photoresist; a second insulating layer is formed on the gate electrode and the common electrode, and the second insulating layer has a connection a via hole of the source; a pixel electrode is formed on the second insulating layer, and the pixel electrode is in contact with the source through the via hole, and the pixel electrode further forms a storage capacitor with the common electrode.
  • the step of forming a plurality of color photoresists disposed at intervals includes: forming a plurality of red photoresists, blue photoresists, and green photoresists, and sequentially arranging the red photoresist, the green photoresist, and the blue photoresist on the substrate. .
  • the step of forming a source, a drain, and a channel on the substrate further includes: forming a spaced source and a drain on the substrate by the same process; forming a channel between the source and the drain, and making the trench The channel connects the source and drain.
  • the step of forming the spaced source and drain electrodes on the substrate by the same process further comprises the steps of: forming a black matrix on the substrate; forming the spaced source and drain electrodes on the substrate by the same process comprises: The same process forms spaced sources and drains on the black matrix.
  • the step of forming a source, a drain, and a channel on the substrate further includes sequentially forming a semiconductor layer and a metal layer on the substrate; forming a source and a drain of the metal layer by a mask process to form a channel of the semiconductor layer And the source and drain are spaced apart on the channel, and the channel is connected to the source and the drain.
  • the present invention further provides a display panel including a substrate on which a source, a drain and a channel are disposed, a first insulating layer, a plurality of color photoresists, a gate electrode, a common electrode, and a second insulation.
  • a layer and a pixel electrode wherein a first insulating layer is deposited on the substrate; a plurality of colored photoresists are formed on the first insulating layer and spaced apart, the source, the drain and the channel are located at two adjacent color photoresists Between; the gate and the common electrode are formed by the same process, and the gate is located on the first insulating layer between two adjacent color photoresists, the common electrode is located on the color photoresist; the second insulating layer is formed on the gate And the second insulating layer has a through hole communicating with the source; the pixel electrode is formed on the second insulating layer, and the pixel electrode is in contact with the source through the through hole, and the pixel electrode further forms a storage capacitor with the common electrode.
  • the color photoresist includes a red photoresist, a green photoresist, and a blue photoresist sequentially arranged on the substrate.
  • the source and the drain are formed on the substrate by the same process interval, the channel is formed between the source and the drain, and the channel is connected to the source and the drain.
  • the display panel further comprises a black matrix formed on the substrate, and the source and the drain are spaced apart on the black matrix.
  • the channel is located on the substrate, the source and the drain are spaced apart on the channel, and the channel is connected to the source and the drain.
  • the manufacturing method of the display panel of the present invention comprises the steps of providing a substrate, forming a source, a drain and a channel on the substrate; depositing a first insulating layer on the substrate; Forming a plurality of spaced-apart color photoresists on the insulating layer, and the source, the drain, and the channel are located between two adjacent color photoresists, so that the subsequently formed gates constitute the TFT unit; the same process Forming a gate electrode and a common electrode, the gate is on the first insulating layer between two adjacent color photoresists, the common electrode is on the color photoresist, and the second insulating layer is formed on the gate electrode and the common electrode, the second The insulating layer has a through hole communicating with the source; a pixel electrode is formed on the second insulating layer, the pixel electrode is in contact with the source through the through hole, and the pixel electrode and the common electrode form a storage capacitor, and the second insulating layer is between the two
  • the pitch of the storage capacitor of the display panel obtained by the manufacturing method of the present invention is reduced compared with the prior art, thereby using the COA process.
  • Panel storage capacitor is increased, improving the problem of leakage of the pixel electrodes, the display panel to improve display effect.
  • FIG. 1 is a schematic structural view of a display panel prepared by using a current COA process
  • FIG. 2 is a schematic flow chart of a first embodiment of a method for manufacturing a display panel of the present invention
  • FIG. 3 is a schematic structural view of a display panel prepared by the first embodiment of the manufacturing method shown in FIG. 2;
  • FIG. 4 is a schematic flow chart of a second embodiment of a method for manufacturing a display panel of the present invention.
  • FIG. 5 is a schematic structural view of a display panel prepared by the second embodiment of the manufacturing method shown in FIG. 4;
  • FIG. 6 is a schematic flow chart of a third embodiment of a method of manufacturing a display panel of the present invention.
  • FIG. 7 is a schematic structural view of a display panel produced by the third embodiment of the manufacturing method shown in FIG. 6.
  • FIG. 7 is a schematic structural view of a display panel produced by the third embodiment of the manufacturing method shown in FIG. 6.
  • FIG. 2 is a schematic flow chart of a first embodiment of a method for manufacturing a display panel of the present invention
  • FIG. 3 is a schematic structural view of a display panel obtained by the first embodiment of the manufacturing method of FIG. Manufacturing Method
  • the first embodiment produces the display panel 300, and the first embodiment includes the following steps.
  • the substrate 30 is made of a light transmissive material such as glass.
  • S202 forming a source, a drain, and a channel on the substrate.
  • a source 310, a drain 311, and a channel 33 are formed on the substrate 30.
  • the source 310 and the drain 311 are turned on through the channel 33, and electron-hole pairs flow in the channel 33 to form a current.
  • the channel 33 can be made closer to the substrate 30, and the source 310 and the drain 311 can be made closer to the substrate 30.
  • the source 310 and the drain 311 are selected.
  • the layer 310 is closer to the substrate 30, that is, the source 310 and the drain 311 are first formed on the substrate 30.
  • the steps of forming the source 310 and the drain 311 are as follows: firstly depositing a metal layer, which may be a Mo/Al composite material or a Mo/Cu composite material, and may also select other materials according to process conductivity requirements; Then, a mask process is performed on the metal layer to form a source 310 and a drain 311. Since the source 310 and the drain 311 extend in the same direction of the substrate, the source 310 and the drain 311 in this embodiment are Formed by the same process.
  • a metal layer which may be a Mo/Al composite material or a Mo/Cu composite material, and may also select other materials according to process conductivity requirements.
  • the step of forming the channel 33 is to first deposit a semiconductor layer which selects a-Si:H, that is, hydrogenated amorphous silicon, and then uses a mask process for the semiconductor layer to be used at the source 310 and the drain 311.
  • a channel 33 is formed between the source 310 and the drain 311.
  • the channel 33 in this embodiment is thinner than the channel 15 in FIG. Since in FIG. 1, the channel 15 is formed first, and then a metal layer is deposited on the channel 15, the metal layer is etched in the mask process so that there is no space between the source/drain electrodes 16 Residues need to be etched into the channel 15, that is, the channel 15 also needs to be etched a part. If the channel 15 is too thin after engraving, it will have a certain influence on the conduction between the source/drain 16. Therefore, the channel 15 in Comparative Document 1 needs to have a certain thickness. In the present embodiment, the source 310 and the drain 311 are formed first, so that there is no problem in FIG. 1, and the channel 33 can be set thinner.
  • ai-Si:H is hydrogenated amorphous silicon, and the substance is sensitive to light, and is easily affected by light to generate electron-hole pairs, and an electric current is formed under the action of an external electric field, causing light leakage.
  • the channel 33 is too thick, the light leakage increases and the electrical characteristics are poor.
  • the channel 33 is thin, the influence of the light can be reduced, thereby improving the light leakage and enhancing the electrical characteristics.
  • the source 310 and the drain 311 are turned on through the channel 33, and both the source 310 and the drain 311 need to be in contact with the channel 33.
  • the source 310, the drain 311 and the trench are provided.
  • the portion of the track 33 contact is also provided with an ohmic contact layer 32 which is a doped amorphous silicon film.
  • the deposition of the above metal layer adopts the Sputter method in physical vapor deposition.
  • the Sputter method uses a specific sputtering target as a material source, and uses a positive ion to bombard the target at a high speed under the action of an electric field, and the overflow target atoms and molecules are on the substrate.
  • the surface is deposited to obtain a metal layer.
  • the deposition speed is fast and the bonding property with the substrate 30 is good. Since the material of the metal layer is easily formed into a target, deposition is performed by means of a Sputter in the present embodiment.
  • the deposition of the above semiconductor layer is carried out by PECVD in chemical vapor deposition.
  • the method is to ionize the atomic gas of the semiconductor by microwave or radio frequency, and form a plasma locally.
  • the plasma chemical activity is strong and the film is easily deposited. This method is more suitable for the deposition of non-metallic materials.
  • the mask process described above specifically includes steps of coating photoresist, exposure, development, etching, and photoresist removal.
  • the mask process for different materials differs in the selection of the photoresist material in the photoresist process, the selection of the developer in the development process, and the like.
  • the mask process adopts the conventional means in the technical field, and details are not described herein.
  • S203 depositing a first insulating layer on the substrate.
  • the first insulating layer 34 is a TFT gate insulating layer.
  • the first insulating layer 34 is obtained by two depositions, and Silicon nitride is selected as the material of the first insulating layer 34, and the deposition method is PECVD.
  • a first thin deposition is performed to obtain a thin silicon nitride layer, and a slow speed can be formed between the silicon nitride and the channel 33.
  • a second rapid deposition results in a thicker silicon nitride layer, thereby forming a first insulating layer 34.
  • the display of one pixel point is implemented by using three primary colors of red, green and blue.
  • the plurality of color photoresists 35 are arranged at intervals, including a red photoresist, a green photoresist and a blue photoresist, and a red photoresist is formed on the substrate 30.
  • the order of the green photoresist and the blue photoresist is sequentially arranged, and may be arranged in other orders in other embodiments.
  • the three photoresists are respectively obtained by using the mask process of three repetitions in step S204.
  • the gate electrode 36 needs to be formed to form the TFT with the source 310 and the drain 311. Therefore, when the color mask 35 is formed at intervals in the mask process, the source 310 and the drain are also required. 311 and channel 33 are located between two adjacent colored photoresists 35.
  • the gate electrode 36 and the common electrode 37 on the substrate 30 extend in the same direction and the materials are the same, they are also formed by the same process.
  • the source 310 and the drain 311 are formed in the same manner, and the metal layer is deposited by a Sputter method, and the metal layer may be made of a material such as Mo/Al or Mo/Cu, and then the photomask is used to obtain the gate 36.
  • a common electrode 37 wherein the gate 36 is on the first insulating layer 34 between two adjacent colored photoresists 35, and the common electrode 37 is on the colored photoresist 35.
  • the second insulating layer 38 formed in this step S206 has a through hole 381 that communicates with the source 310.
  • a silicon nitride material having a relatively good density is also used.
  • a silicon nitride layer is deposited by PECVD, and then a via hole 381 is formed through a mask process.
  • a conductive layer is deposited on the second insulating layer 38 by a sputtering method, and the conductive layer is an ITO material, and then the pixel electrode 39 is obtained through a photomask process, and the pixel electrode 39 is in contact with the source 310 through the through hole 381.
  • the potential of the source 31 is made to pass to the pixel electrode 39.
  • a storage capacitor is formed between the pixel electrode 39 and the common electrode 37, and a second insulating layer 38 is spaced between the pixel electrode 39 and the common electrode 37, that is, the storage capacitor plate has a small pitch, so the storage capacitor Larger, which in turn improves the display effect of the display panel 300.
  • FIG. 4 is a schematic flow chart of a second embodiment of the manufacturing method of the display panel of the present invention
  • FIG. 5 is a schematic structural view of the display panel prepared by the second embodiment of the manufacturing method of FIG.
  • the second embodiment of the manufacturing method produces the display panel 500, and the second embodiment includes the following steps.
  • S403 The same process forms spaced source and drain electrodes on the black matrix.
  • S405 depositing a first insulating layer on the substrate.
  • the second embodiment differs from the first embodiment in the steps S402 and S403.
  • the other steps are similar, and the same steps are not described herein again.
  • step S402 since the channel 33 is formed between the source 310 and the drain 311 in the first embodiment, that is, the channel 33 at the interval between the source 310 and the drain 311 is directly formed on the substrate 30, and the substrate 30 is a transparent substrate.
  • the light generated by the backlight module affects the channel 33 on the substrate 30.
  • a black matrix 52 is first coated on the substrate 51 to achieve a light shielding effect, and then a source 530 and a drain 531 are respectively formed.
  • step S403 spaced source 530 and drain 531 are formed on black matrix 52. Since the organic material constituting the black matrix 52 easily contaminates the source 530 and the drain 531 made of metal, a dielectric insulating layer (not shown) is disposed between the black matrix 52 and the source 530 and the drain 531.
  • the dielectric insulating layer may be selected from silicon oxide or silicon nitride. Since silicon nitride has good compactness, silicon nitride is preferred.
  • FIG. 6 is a schematic flow chart of a third embodiment of the manufacturing method of the display panel of the present invention
  • FIG. 7 is a schematic structural view of the display panel obtained by the third embodiment of the manufacturing method of FIG.
  • the third embodiment of the manufacturing method produces the display panel 700, and the third embodiment includes the following steps.
  • S602 sequentially forming a semiconductor layer and a metal layer on the substrate.
  • S603 forming a source and a drain by a metal layer by a mask process to form a channel of the semiconductor layer.
  • S604 depositing a first insulating layer on the substrate.
  • S605 forming a plurality of color photoresists disposed at intervals on the first insulating layer.
  • S607 forming a second insulating layer on the gate electrode and the common electrode.
  • step S602 The difference between this embodiment and the first embodiment lies in step S602 and step S603, and other similar steps are not specifically described herein.
  • Step S602 and step S603 correspond to step S202 in the first embodiment, and in the present embodiment, the channel 71 is selected to be a layer closer to the substrate 70.
  • the semiconductor layer and the metal layer are sequentially formed in step S602, and then the source 730, the drain 731, and the channel 71 are obtained once by the mask process in step S603, and the mask in the mask process adopts GTM ( Gray Tone Mask, grayscale mask, HTM (Half Tone Mask) or SSM (Single Slit)
  • GTM Gray Tone Mask, grayscale mask, HTM (Half Tone Mask) or SSM (Single Slit)
  • GTM Gray Tone Mask, grayscale mask, HTM (Half Tone Mask) or SSM (Single Slit)
  • a special mask such as a mask or a slit mask can be used to form the source 730, the drain 730, and the channel 71 at a time, and the mask process is subtracted from the first embodiment.
  • the metal layer is etched by wet etching to obtain the source 730 and the drain 730, respectively, and the semiconductor layer is etched by dry etching to obtain the channel 71.
  • a black matrix can be formed between the channel 71 and the substrate 70 as in the second embodiment.
  • the manufacturing method of the display panel of the present invention comprises the steps of providing a substrate, forming a source, a drain and a channel on the substrate; depositing a first insulating layer on the substrate; forming a space on the insulating layer a plurality of color photoresists are disposed, and the source, the drain and the channel are located between two adjacent color photoresists such that the subsequently formed gates constitute the TFT unit; the same process forms the gate and the common electrode,
  • the gate is on the first insulating layer between two adjacent color photoresists, the common electrode is on the color photoresist, and a second insulating layer is formed on the gate and the common electrode, the second insulating layer having a source connected a via hole is formed on the second insulating layer, the pixel electrode is in contact with the source through the through hole, and the pixel electrode and the common electrode form a storage capacitor, and the second insulating layer is blocked between the two, and the thickness of the second insulating layer is
  • FIG. 3 For the display panel of the present invention, three embodiments are also given herein for explanation. Please refer to FIG. 3, FIG. 5 and FIG. 7 respectively, which respectively correspond to the first embodiment and the second embodiment of the above display panel manufacturing method. And the third embodiment.
  • the display panel 300 includes a substrate 30, a source 310, a drain 311, a channel 33, a first insulating layer 34, a color photoresist 35, a gate 36, a common electrode 37, a second insulating layer 38, and a pixel electrode. 39.
  • the source 310 and the drain 311 are spaced apart from each other on the substrate 30.
  • the channel 33 is connected to the source 310 and the drain 311, and the first insulating layer 34 is deposited on the substrate 30. Since the source 310 and the drain 311 need to be in contact with the channel 33, and the source 310 and the drain 311 are made of a metal material and the channel 33 is a semiconductor material, in order to reduce the contact resistance between the metal and the semiconductor, at the source 310
  • the portion of the drain 311 that is in contact with the channel 33 is further provided with an ohmic contact layer 32, which is a doped amorphous silicon film.
  • a plurality of color photoresists 35 are spaced apart from each other on the first insulating layer 34.
  • the color photoresist 35 is a red photoresist, a blue photoresist, and a green photoresist which are sequentially arranged on the substrate 30.
  • the gate electrode 36 and the common electrode 37 are formed by the same process, and the gate electrode 36 is located on the first insulating layer 34 between the adjacent two color photoresists 35, and the common electrode 37 is located on the color photoresist 35.
  • the source 310, the drain 311, the channel 33 and the gate 36 together form a TFT, and the formed TFT is located between two adjacent color photoresists 35.
  • the second insulating layer 38 is formed on the gate electrode 36 and the common electrode 37, and has a via hole 381 that communicates with the source electrode 310.
  • the pixel electrode 39 is formed on the second insulating layer 38, and further forms a storage capacitor with the common electrode 37.
  • a second insulating layer 38 is spaced between the pixel electrode 39 and the common electrode 37. Therefore, the storage capacitor plate has a small pitch and a large storage capacitance, and then the display panel 300 has a better display effect.
  • the display panel 500 is similar in structure to the display panel 300, and also includes a substrate, a source, a drain, a channel, a first insulating layer, a color photoresist, a gate, a common electrode, a second insulating layer, and a pixel electrode. The same part will not be described again.
  • the display panel 500 further includes a black matrix 52 formed on the substrate 51, and the source 530 and the drain 531 are formed on the black matrix 52 at intervals.
  • the specific action thereof has been described in the second embodiment of the display panel manufacturing method, and therefore will not be described in detail.
  • the display panel 700 is also similar in structure to the display panel 300, and includes a substrate 70, a source 730, a drain 731, a channel 71, a first insulating layer 74, a color photoresist 75, a gate 76, and a common electrode 77.
  • An ohmic contact layer 72 is also disposed between the channel 71 and the source 730 and the drain 731 in the display panel 700.
  • the same portions of the display panel 700 and the display panel 300 will not be described here, and the difference between them is the positional relationship between the source 730, the drain 731, the channel 71, and the gate 76.
  • the channel 71 is formed on the substrate 70, the source 730 and the drain 731 are spaced apart from each other on the channel, and the channel 71 is connected to the source 730 and the drain 731.
  • the source 730, the drain 731, and the channel 71 can be formed by one mask process, and the mask process is reduced as compared with the display panel 300 and the display panel 500, simplifying the process.
  • a second insulating layer is spaced between the pixel electrode and the common electrode in the display panel of the present invention, so that the storage capacitor plate has a small pitch and a corresponding storage capacitor is large, and then the display effect of the display panel of the present invention is also better. it is good.

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Abstract

一种显示面板（300）及其制造方法，该方法包括：提供基板（30），在其上形成源极（310）、漏极（311）和沟道（33）；沉积第一绝缘层（34），在其上形成间隔设置的多个彩色光阻（35）；由同一道制程形成位于第一绝缘层（34）上的栅极（36）和位于彩色光阻（35）上的公共电极（37）；并使源极（310）、漏极（311）、沟道（33）和栅极（36）均位于两相邻彩色光阻（35）之间；在栅极（36）和公共电极（37）上形成第二绝缘层（38），第二绝缘层（38）具有一连通源极（310）的通孔（381）；在第二绝缘层（38）上形成通过通孔（381）与源极（310）接触的像素电极（39），像素电极（39）与公共电极（37）形成存储电容。

Description

一种显示面板及其制造方法
【技术领域】
本发明涉及显示技术领域，特别涉及一种显示面板及其制造方法。
【背景技术】
在当前显示技术领域中，COA(Color Filter on Array)技术发展迅速，COA即将彩色光阻制作于TFT基板上的工艺技术，采用该工艺技术不会产生像素与彩色光阻的对位误差，而且能够降低寄生电容，且显示面板可具有较高的分辨率和像素开口率。
请参阅图1，图1是采用当前COA工艺制得的显示面板的结构示意图。现有技术是在基板11上依次形成栅极12和公共电极13、第一绝缘层14、沟道15、源极/漏极16、彩色光阻17，最后再形成像素电极18，其中彩色光阻增大了公共电极13和像素电极18所形成存储电容的极板间距，从而导致该显示面板100中的存储电容很小，而存储电容用于保持像素电极18的电压在预定时间内维持固定值，若存储电容过小，则像素电极18上用于维持电压的电荷会快速泄露，导致像素电极18上的电压过早降低，影响显示面板100的显示效果。
【发明内容】
本发明主要解决现有COA工艺制得的显示面板中存储电容极板间距较大导致像素电极容易漏电的技术问题。
为解决上述技术问题，本发明提出一种显示面板的制造方法，该方法包括步骤：提供一基板，由同一道制程在基板上形成间隔的源极和漏极；在源极和漏极之间形成沟道，且使得沟道连接源极和漏极；在基板上沉积第一绝缘层；在第一绝缘层上形成间隔设置的形成多个红色光阻、绿色光阻以及蓝色光阻，在基板上以红色光阻、绿色光阻以及蓝色光阻的顺序依次排列；且使得源极、漏极和沟道位于两个相邻的彩色光阻之间；由同一道制程形成栅极和公共电极，且使得栅极形成于两个相邻的彩色光阻之间的第一绝缘层上，公共电极形成于彩色光阻上；在栅极和公共电极上形成第二绝缘层，第二绝缘层具有一连通源极的通孔；在第二绝缘层上形成像素电极，像素电极通过通孔与源极接触，像素电极进一步与公共电极形成存储电容。
其中，由同一道制程在基板上形成间隔的源极和漏极的步骤之前进一步包括步骤：在基板上形成黑矩阵；由同一制程在基板上形成间隔的源极和漏极的步骤包括：由同一制程在黑矩阵上形成间隔的源极和漏极。
其中，在基板上形成源极、漏极以及沟道的步骤进一步包括：在基板上依次形成半导体层和金属层；通过光罩制程使金属层形成源极和漏极，使半导体层形成沟道，且源极和漏极间隔位于沟道上，沟道连接源极和漏极。
为解决上述技术问题，本发明又提出一种显示面板的制造方法，该方法包括步骤：提供一基板，在基板上形成源极、漏极和沟道；在基板上沉积第一绝缘层；在第一绝缘层上形成间隔设置的多个彩色光阻，且使得源极、漏极和沟道位于两个相邻的彩色光阻之间；由同一道制程形成栅极和公共电极，且使得栅极形成于两个相邻的彩色光阻之间的第一绝缘层上，公共电极形成于彩色光阻上；在栅极和公共电极上形成第二绝缘层，第二绝缘层具有一连通源极的通孔；在第二绝缘层上形成像素电极，像素电极通过通孔与源极接触，像素电极进一步与公共电极形成存储电容。
其中，形成间隔设置的多个彩色光阻的步骤包括：形成多个红色光阻、蓝色光阻以及绿色光阻，且在基板上以红色光阻、绿色光阻以及蓝色光阻的顺序依次排列。
其中，在基板上形成源极、漏极以及沟道的步骤进一步包括：由同一道制程在基板上形成间隔的源极和漏极；在源极和漏极之间形成沟道，且使得沟道连接源极和漏极。
其中，由同一道制程在基板上形成间隔的源极和漏极的步骤之前进一步包括步骤：在基板上形成黑矩阵；由同一制程在基板上形成间隔的源极和漏极的步骤包括：由同一制程在黑矩阵上形成间隔的源极和漏极。
其中，在基板上形成源极、漏极以及沟道的步骤进一步包括：在基板上依次形成半导体层和金属层；通过光罩制程使金属层形成源极和漏极，使半导体层形成沟道，且源极和漏极间隔位于沟道上，沟道连接源极和漏极。
为解决上述技术问题，本发明还提出一种显示面板，其包括设置有源极、漏极和沟道的基板，第一绝缘层，多个彩色光阻，栅极，公共电极，第二绝缘层以及像素电极；其中，第一绝缘层沉积在基板上；多个彩色光阻形成于第一绝缘层上，且间隔设置，源极、漏极和沟道位于两个相邻的彩色光阻之间；栅极和公共电极由同一道制程形成，且栅极位于两个相邻的彩色光阻之间的第一绝缘层上，公共电极位于彩色光阻上；第二绝缘层形成于栅极和公共电极上，且第二绝缘层具有一连通源极的通孔；像素电极形成于第二绝缘层上，像素电极通过通孔与源极接触，像素电极进一步与公共电极形成存储电容。
其中，彩色光阻包括在基板上依次排列的红色光阻、绿色光阻以及蓝色光阻。
其中，源极和漏极由同一道制程间隔形成于基板上，沟道形成于源极和漏极之间，且沟道连接源极和漏极。
其中，显示面板进一步包括黑矩阵，黑矩阵形成在基板上，源极和漏极间隔形成在黑矩阵上。
其中，沟道位于基板上，源极和漏极间隔位于沟道上，沟道连接源极和漏极。
本发明的有益效果是，区别于现有技术，本发明显示面板的制造方法包括步骤，提供一基板，在基板上形成源极、漏极和沟道；在该基板上沉积第一绝缘层；在该绝缘层上形成间隔设置的多个彩色光阻，且源极、漏极和沟道位于两个相邻的彩色光阻之间，使得与后续形成的栅极构成TFT单元；同一道制程形成栅极和公共电极，栅极在两个相邻彩色光阻之间的第一绝缘层上，公共电极在彩色光阻上，在栅极和公共电极上形成第二绝缘层，该第二绝缘层具有连通源极的通孔；在第二绝缘层上形成像素电极，像素电极通过上述通孔与源极接触，且像素电极与公共电极形成存储电容，两者之间由第二绝缘层阻隔，第二绝缘层厚度小于彩色光阻层厚度，因此由本发明的制造方法得到显示面板的存储电容的极板间距相较于现有技术有所减小，由此采用COA工艺的显示面板的存储电容增大，改善了像素电极的漏电问题，提高显示面板的显示效果。
【附图说明】
图1是采用当前COA工艺制得的显示面板的结构示意图；
图2是本发明显示面板的制造方法第一实施方式的流程示意图；
图3是图2所示制造方法第一实施方式制得显示面板的结构示意图；
图4是本发明显示面板的制造方法第二实施方式的流程示意图；
图5是图4所示制造方法第二实施方式制得显示面板的结构示意图；
图6是本发明显示面板的制造方法第三实施方式的流程示意图；
图7是图6所示制造方法第三实施方式制得显示面板的结构示意图。
【具体实施方式】
参阅图2和图3，图2是本发明显示面板的制造方法第一实施方式的流程示意图，图3是图2所示制造方法第一实施方式制得的显示面板的结构示意图。制造方法第一实施方式制得显示面板300，该第一实施方式包括以下步骤。
S201：提供一基板。
一般来说该基板30由玻璃等透光材料制成。
S202：在基板上形成源极、漏极和沟道。
基板30上形成有源极310、漏极311和沟道33。源极310和漏极311通过沟道33导通，电子空穴对在沟道33中流动形成电流。
在本步骤S202中可以使沟道33为更靠近基板30的层，也可使源极310和漏极311为更靠近基板30的层，本实施方式中选择使源极310和漏极311为更靠近基板30的层，即首先在基板30上形成源极310和漏极311。
具体来说，形成源极310和漏极311的步骤是：首先沉积一金属层，该金属层可以为Mo/Al复合材料或Mo/Cu复合材料，也可根据制程导电等要求选择其他材料；然后对该金属层采用光罩制程，以形成源极310和漏极311，由于源极310和漏极311在基板的同一方向上延伸，因此本实施方式中源极310和漏极311是由同一道制程形成的。
沟道33形成的步骤则是：首先沉积一半导体层，该半导体层选择a-Si:H即氢化非晶硅，然后对该半导体层采用光罩制程，以在源极310和漏极311之间形成沟道33，该沟道33连接源极310和漏极311。
本实施方式中的沟道33相较于图1中的沟道15更薄。由于在图1中，先形成沟道15，然后在沟道15上沉积一金属层，在光罩制程中对该金属层进行刻蚀，为了使源极/漏极16之间的间隔区域没有残余，需要过刻至沟道15，即沟道15也需要被刻蚀一部分，若过刻后的沟道15太薄，会对源极/漏极16之间的导通产生一定的影响，因此对比文件1中沟道15需要有一定的厚度。而本实施方式中是先形成源极310和漏极311，因此不存在图1中的问题，沟道33可设置的更薄。而较薄沟道33的设计有利于减少半导体层的沉积时间,同时提高了电学特性。本实施方式中所采用的是ai-Si:H即氢化非晶硅，而该物质对光较为敏感，容易受光照影响产生电子空穴对，在外界电场作用下形成电流，造成光漏电，若沟道33过厚，则光漏电将增大，电学特性较差，而本实施方式中，沟道33较薄，则可减少光照的影响，从而改善光漏电的情况，增强电学特性。
源极310和漏极311通过沟道33导通，源极310和漏极311均需要与沟道33接触，为了降低金属与半导体之间的接触电阻，在源极310、漏极311与沟道33接触的部分还设置有欧姆接触层32，该欧姆接触层32为掺杂的非晶硅薄膜。
上述金属层的沉积采用物理气相沉积中的Sputter方式，Sputter方式是以特定的溅射靶材作为材料源，使用正离子在电场的作用下高速轰击靶材，溢出的靶材原子和分子在基板30表面沉积，从而得到金属层，该方式沉积速度快，且与基板30的结合性能好，由于金属层的材料容易制成靶材，因此本实施方式中采用Sputter的方式进行沉积。
上述半导体层的沉积则采用化学气相沉积中的PECVD方式，该方式是借助微波或射频使半导体的原子气体电离，在局部形成等离子体，等离子体化学活性较强，容易沉积出薄膜。该方法更适用于非金属材料的沉积。
上述光罩制程则具体包括涂布光阻、曝光、显影、刻蚀，去光阻等步骤。针对不同材料的光罩制程，其不同之处在于涂布光阻工序中光阻材料的选择，显影工序中显影液的选择等。光罩制程采用本技术领域的常规手段，具体不做赘述。
S203：在基板上沉积第一绝缘层。
该第一绝缘层34为TFT栅极绝缘层，为了保证TFT的电学特性，对于该第一绝缘层34的要求较高，因此本实施方式中利用两次沉积得到该第一绝缘层34，且选择氮化硅作为第一绝缘层34的材料，沉积方式为PECVD方式，首先第一次慢速沉积得到较薄的氮化硅层，慢速可以使的氮化硅与沟道33之间形成较好的界面，第二次快速沉积得到较厚的氮化硅层，由此形成第一绝缘层34。
S204：在第一绝缘层上形成间隔设置的多个彩色光阻。
本实施方式中采用红绿蓝三原色实现一个像素点的显示，该步骤S204中间隔设置多个彩色光阻35包括红色光阻、绿色光阻和蓝色光阻，且在基板30上以红色光阻、绿色光阻和蓝色光阻的顺序依次排列，其他实施方式中也可以其他顺序排列。
由于红色光阻、蓝色光阻和绿色光阻的形成所采用的材料均不同，因此本步骤S204中采用三次重复的光罩制程分别得到以上三个光阻。
在形成彩色光阻35后，还需要形成栅极36以与源极310、漏极311构成TFT，因此在光罩制程形成间隔设置的彩色光阻35时，还需使得源极310、漏极311和沟道33位于两个相邻的彩色光阻35之间。
S205：同一道制程形成栅极和公共电极。
由于基板30上栅极36和公共电极37在同一方向延伸，且两者材料相同，因此也是采用同一道制程形成。与源极310和漏极311的形成方式相同，也是采用Sputter方式沉积金属层，且金属层可选用Mo/Al、或Mo/Cu等材料，然后对该金属层采用光罩制程得到栅极36和公共电极37，其中栅极36在两个相邻彩色光阻35之间的第一绝缘层34上，公共电极37在彩色光阻35上。本步骤S205完成后栅极35、源极310、漏极311和沟道33构成了TFT。
S206：在栅极和公共电极上形成第二绝缘层。
本步骤S206中所形成的第二绝缘层38具有一连通源极310的通孔381。本实施方式中也是采用致密性较好的氮化硅材料，首先通过PECVD方式沉积一氮化硅层，然后通过光罩制程形成通孔381。
S207：在第二绝缘层上形成像素电极。
本实施方式中，在第二绝缘层38利用Sputter方式沉积一导电层，该导电层为ITO材料，然后经光罩制程得到像素电极39，该像素电极39通过通孔381与源极310接触，使得源极31的电位传至像素电极39。该步骤S207完成后，像素电极39与公共电极37之间则形成存储电容，像素电极39与公共电极37之间间隔一第二绝缘层38，即该存储电容极板间距较小，因此存储电容较大，继而提高显示面板300的显示效果。
请参阅图4和图5，图4是本发明显示面板的制造方法第二实施方式的流程示意图，图5是图4所示制造方法第二实施方式制得的显示面板的结构示意图。制造方法的第二实施方式制得显示面板500，该第二实施方式包括以下步骤。
S401：提供一基板。
S402：在基板上形成黑矩阵。
S403：同一制程在黑矩阵上形成间隔的源极和漏极。
S404：在源极和漏极之间形成沟道。
S405：在基板上沉积第一绝缘层。
S406：在第一绝缘层上形成间隔设置的多个彩色光阻。
S407：同一道制程形成栅极和公共电极。
S408：在栅极和公共电极上形成第二绝缘层。
S409：在第二绝缘层上形成像素电极。
本第二实施方式与第一实施方式的不同在于步骤S402和步骤S403，其他步骤均类似，对于相同的步骤在此不再赘述。
对于步骤S402，由于第一实施方式中沟道33形成于源极310和漏极311之间，即源极310和漏极311间隔处的沟道33是直接形成在基板30上的，而基板30为透明基板，在显示面板300工作时，背光模组产生的光会对基板30上的沟道33产生影响，如步骤S202中所描述的，容易发生光漏电现象，从而影响电学特性。因此本实施方式步骤S402中在基板51上先涂布一层黑矩阵52，以实现遮光作用，然后再分别形成源极530和漏极531。
对于步骤S403，在黑矩阵52上形成间隔的源极530和漏极531。由于构成黑矩阵52的有机材料容易对金属制得的源极530和漏极531造成污染，因此黑矩阵52与源极530、漏极531之间还设置有一介电绝缘层（图未示），该介电绝缘层可选用氧化硅或氮化硅，由于氮化硅致密性较好，因此优先选择氮化硅。
请参阅图6和图7，图6是本发明显示面板的制造方法第三实施方式的流程示意图，图7是图6所示制造方法第三实施方式制得的显示面板的结构示意图。制造方法的第三实施方式制得显示面板700，该第三实施方式包括以下步骤。
S601：提供一基板。
S602：在基板上依次形成半导体层和金属层。
S603：通过光罩制程使金属层形成源极和漏极，使半导体层形成沟道。
S604：在基板上沉积第一绝缘层。
S605：在第一绝缘层上形成间隔设置的多个彩色光阻。
S606：同一道制程形成栅极和公共电极。
S607：在栅极和公共电极上形成第二绝缘层。
S608：在第二绝缘层上形成像素电极。
本实施方式与第一实施方式的不同在于步骤S602和步骤S603，其他类似的步骤具体不再赘述。
步骤S602和步骤S603对应于第一实施方式中的步骤S202，本实施方式中选择使沟道71为更靠近基板70的层。
具体来说首先在步骤S602中依次形成半导体层和金属层，然后在步骤S603中通过光罩制程一次得到源极730、漏极731和沟道71，该光罩制程中的光罩采用GTM（Gray Tone Mask，灰阶光罩）、HTM（Half Tone Mask，半色调光罩）或SSM（Single Slit Mask，狭缝光罩）等特殊光罩，因此可以一次形成源极730、漏极730和沟道71，相比于第一实施方式减去了一次光罩制程。在显影工序后，再分别通过湿刻蚀来刻蚀金属层以得到源极730和漏极730，通过干刻蚀来刻蚀半导体层以得到沟道71。
由于本实施方式中沟道71直接形成在基板70上，因此与第二实施方式相同，也可在沟道71和基板70之间形成一黑矩阵。
区别于现有技术，本发明显示面板的制造方法包括步骤，提供一基板，在基板上形成源极、漏极和沟道；在该基板上沉积第一绝缘层；在该绝缘层上形成间隔设置的多个彩色光阻，且源极、漏极和沟道位于两个相邻的彩色光阻之间，使得与后续形成的栅极构成TFT单元；同一道制程形成栅极和公共电极，栅极在两个相邻彩色光阻之间的第一绝缘层上，公共电极在彩色光阻上，在栅极和公共电极上形成第二绝缘层，该第二绝缘层具有连通源极的通孔；在第二绝缘层上形成像素电极，像素电极通过上述通孔与源极接触，且像素电极与公共电极形成存储电容，两者之间由第二绝缘层阻隔，第二绝缘层厚度小于彩色光阻层厚度，因此由本发明的制造方法得到显示面板的存储电容的极板间距相较于现有技术有所减小，由此存储电容增大，改善了像素电极的漏电问题，提高显示面板的显示效果。
对于本发明显示面板，在此也给出三个实施方式以做说明，请分别参阅图3、图5和图7，其分别对应于上述显示面板制造方法的第一实施方式、第二实施方式和第三实施方式。
图3中，显示面板300包括基板30、源极310、漏极311、沟道33、第一绝缘层34、彩色光阻35、栅极36、公共电极37、第二绝缘层38以及像素电极39。
其中源极310、漏极311在基板30上间隔设置，沟道33连接源极310和漏极311，第一绝缘层34沉积在基板30上。由于源极310和漏极311需要与沟道33接触，且源极310和漏极311为金属材料、沟道33为半导体材料，因此为了降低金属与半导体之间的接触电阻，在源极310、漏极311与沟道33接触的部分还设置有欧姆接触层32，该欧姆接触层32为掺杂的非晶硅薄膜。
多个彩色光阻35间隔设置形成在第一绝缘层34上。本实施方式中彩色光阻35为基板30上依次排列的红色光阻、蓝色光阻和绿色光阻。
栅极36和公共电极37由同一道制程形成，且栅极36位于相邻两个彩色光阻35之间的第一绝缘层34上，公共电极37位于彩色光阻35上。源极310、漏极311、沟道33与栅极36共同构成TFT，且所构成的TFT位于相邻两个彩色光阻35之间。
第二绝缘层38形成于栅极36和公共电极37上，且具有一连通源极310的通孔381，像素电极39形成于第二绝缘层38上，进一步与公共电极37形成存储电容。像素电极39与公共电极37之间间隔一第二绝缘层38，因此存储电容极板间距较小，存储电容较大，继而显示面板300的显示效果也较好。
图5中，显示面板500与显示面板300结构类似，也包括基板、源极、漏极、沟道、第一绝缘层、彩色光阻、栅极、公共电极、第二绝缘层以及像素电极。相同部分不再赘述。
不同之处在于，显示面板500中还包括黑矩阵52，黑矩阵52形成在基板51上，且源极530和漏极531间隔形成在黑矩阵52上。其具体作用在显示面板制造方法第二实施方式中已作描述，因此不再做具体说明。
图7中，显示面板700也与显示面板300结构类似，包括基板70、源极730、漏极731、沟道71、第一绝缘层74、彩色光阻75、栅极76、公共电极77、第二绝缘层78以及像素电极79。
且显示面板700中沟道71与源极730、漏极731之间也设置有欧姆接触层72。显示面板700与显示面板300的相同部分在此不再说明，两者不同之处在于源极730、漏极731、沟道71、栅极76之间的位置关系。
具体来说，显示面板700中，沟道71形成于基板70上，源极730和漏极731间隔设置在沟道上，且沟道71连接源极730和漏极731。
采用此结构，能够通过一次光罩制程形成源极730、漏极731和沟道71，相较于显示面板300和显示面板500减去了一次光罩制程，简化工艺。
区别于现有技术，本发明显示面板中像素电极与公共电极之间间隔一第二绝缘层，因此存储电容极板间距较小，相应存储电容较大，继而本发明显示面板的显示效果也较好。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种显示面板的制造方法，其中，所述方法包括步骤：
    提供一基板，由同一道制程在所述基板上形成间隔的源极和漏极；
    在所述源极和所述漏极之间形成沟道，且使得所述沟道连接所述源极和所述漏极；
    在所述基板上沉积第一绝缘层；
    在所述第一绝缘层上形成间隔设置的形成多个红色光阻、绿色光阻以及蓝色光阻，在所述基板上以红色光阻、绿色光阻以及蓝色光阻的顺序依次排列；且使得所述源极、漏极和沟道位于两个相邻的所述彩色光阻之间；
    由同一道制程形成栅极和公共电极，且使得所述栅极形成于两个相邻的所述彩色光阻之间的第一绝缘层上，所述公共电极形成于所述彩色光阻上；
    在所述栅极和公共电极上形成第二绝缘层，所述第二绝缘层具有一连通所述源极的通孔；
    在所述第二绝缘层上形成像素电极，所述像素电极通过所述通孔与所述源极接触，所述像素电极进一步与所述公共电极形成存储电容。
  2. 根据权利要求1所述的制造方法，其中，所述由同一道制程在所述基板上形成间隔的源极和漏极的步骤之前进一步包括步骤：
    在所述基板上形成黑矩阵；
    所述由同一制程在所述基板上形成间隔的源极和漏极的步骤包括：
    由同一制程在所述黑矩阵上形成间隔的源极和漏极。
  3. 根据权利要求1所述的制造方法，其中，所述在所述基板上形成源极、漏极以及沟道的步骤进一步包括：
    在所述基板上依次形成半导体层和金属层；
    通过光罩制程使所述金属层形成源极和漏极，使所述半导体层形成沟道，且所述源极和所述漏极间隔位于所述沟道上，所述沟道连接所述源极和所述漏极。
  4. 一种显示面板的制造方法，其中，所述方法包括步骤：
    提供一基板，在所述基板上形成源极、漏极和沟道；
    在所述基板上沉积第一绝缘层；
    在所述第一绝缘层上形成间隔设置的多个彩色光阻，且使得所述源极、漏极和沟道位于两个相邻的所述彩色光阻之间；
    由同一道制程形成栅极和公共电极，且使得所述栅极形成于两个相邻的所述彩色光阻之间的第一绝缘层上，所述公共电极形成于所述彩色光阻上；
    在所述栅极和公共电极上形成第二绝缘层，所述第二绝缘层具有一连通所述源极的通孔；
    在所述第二绝缘层上形成像素电极，所述像素电极通过所述通孔与所述源极接触，所述像素电极进一步与所述公共电极形成存储电容。
  5. 根据权利要求4所述的制造方法，其中，所述形成间隔设置的多个彩色光阻的步骤包括：
    形成多个红色光阻、绿色光阻以及蓝色光阻，且在所述基板上以红色光阻、绿色光阻以及蓝色光阻的顺序依次排列。
  6. 根据权利要求4所述的制造方法，其中，所述在所述基板上形成源极、漏极以及沟道的步骤进一步包括：
    由同一道制程在所述基板上形成间隔的源极和漏极；
    在所述源极和所述漏极之间形成沟道，且使得所述沟道连接所述源极和所述漏极。
  7. 根据权利要求6所述的制造方法，其中，所述由同一道制程在所述基板上形成间隔的源极和漏极的步骤之前进一步包括步骤：
    在所述基板上形成黑矩阵；
    所述由同一制程在所述基板上形成间隔的源极和漏极的步骤包括：
    由同一制程在所述黑矩阵上形成间隔的源极和漏极。
  8. 根据权利要求4所述的制造方法，其中，所述在所述基板上形成源极、漏极以及沟道的步骤进一步包括：
    在所述基板上依次形成半导体层和金属层；
    通过光罩制程使所述金属层形成源极和漏极，使所述半导体层形成沟道，且所述源极和所述漏极间隔位于所述沟道上，所述沟道连接所述源极和所述漏极。
  9. 一种显示面板，其中，所述显示面板包括设置有源极、漏极和沟道的基板，第一绝缘层，多个彩色光阻，栅极，公共电极，第二绝缘层以及像素电极；
    其中，所述第一绝缘层沉积在所述基板上；
    所述多个彩色光阻形成于所述第一绝缘层上，且间隔设置，所述源极、漏极和沟道位于两个相邻的所述彩色光阻之间；
    所述栅极和所述公共电极由同一道制程形成，且所述栅极位于两个相邻的所述彩色光阻之间的第一绝缘层上，所述公共电极位于所述彩色光阻上；
    所述第二绝缘层形成于所述栅极和所述公共电极上，且所述第二绝缘层具有一连通所述源极的通孔；
    所述像素电极形成于所述第二绝缘层上，所述像素电极通过所述通孔与所述源极接触，所述像素电极进一步与所述公共电极形成存储电容。
  10. 根据权利要求9所述的显示面板，其中，所述彩色光阻包括在所述基板上依次排列的红色光阻、绿色光阻以及蓝色光阻。
  11. 根据权利要求9所述的显示面板，其中，所述源极和漏极由同一道制程间隔形成于所述基板上，所述沟道形成于所述源极和所述漏极之间，且所述沟道连接所述源极和所述漏极。
  12. 根据权利要求11所述的显示面板，其中，所述显示面板进一步包括黑矩阵，所述黑矩阵形成在所述基板上，所述源极和漏极间隔形成在所述黑矩阵上。
  13. 根据权利要求9所述的显示面板，其中，所述沟道位于所述基板上，所述源极和所述漏极间隔位于所述沟道上，所述沟道连接所述源极和所述漏极。
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