CN104503127A - 阵列基板及其制作方法 - Google Patents

阵列基板及其制作方法 Download PDF

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Publication number
CN104503127A
CN104503127A CN201410717233.3A CN201410717233A CN104503127A CN 104503127 A CN104503127 A CN 104503127A CN 201410717233 A CN201410717233 A CN 201410717233A CN 104503127 A CN104503127 A CN 104503127A
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China
Prior art keywords
layer
passivation protection
array base
electrode layer
tft
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CN201410717233.3A
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CN104503127B (zh
Inventor
宋利旺
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to CN201410717233.3A priority Critical patent/CN104503127B/zh
Priority to US14/424,007 priority patent/US9804459B2/en
Priority to PCT/CN2015/072469 priority patent/WO2016086531A1/zh
Publication of CN104503127A publication Critical patent/CN104503127A/zh
Priority to US15/714,852 priority patent/US9891488B2/en
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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Abstract

本发明提供一种阵列基板及其制作方法。所述阵列基板通过将黑色矩阵和色阻层均设置于阵列基板上，并且将色阻层设置于TFT层上，避免了TFT制备过程中的高温制程对色阻层产生不良影响，同时为防止阵列基板漏电，TFT层采用顶栅型TFT结构，从而使得液晶面板具有较高的显示品质。所述阵列基板的制作方法，首先在基板上形成黑色矩阵，其次在黑色矩阵上进行TFT制程，然后在TFT制作完成后再形成色阻层，从而实现将黑色矩阵和色阻层均制作于阵列基板上，并且由于在TFT制程之后形成色阻层，避免了TFT制备过程中的高温制程中色阻挥发产生气体而导致产生气泡等不良现象，有效提升了液晶面板的显示品质，并且提高了产品良率。

Description

阵列基板及其制作方法
技术领域
本发明涉及显示技术领域，尤其涉及一种阵列基板及其制作方法。
背景技术
液晶显示装置(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用，如：移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等。现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括背光模组(Backlight module)及结合于背光模组上的液晶面板。
在TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)中，通常会在基板上制作一层BM(Black Matrix，黑色矩阵)，用于分割相邻色阻，遮挡色彩的空隙，防止漏光或者混色，将黑色矩阵制备在TFT阵列基板的技术叫做BOA(BM On Array，黑色矩阵贴附于阵列基板)，BOA可以解决上下基板错位导致遮光区域不匹配的问题。
同时，为了提升TFT-LCD(Thin Film Transistor Liquid Crystal Display，薄膜晶体管液晶显示器)的显示品质，还提出了一种COA(Color Filter On Array，色阻层贴附于阵列基板)技术。
如图1所示，当BOA和COA技术都应用在阵列基板100上，通常为了使用喷涂技术而把黑色矩阵200和色阻层300做在同一层，这样色阻层300会经历TFT制备过程中的PVD(物理气相沉积)和CVD(化学气相沉积)的高温制程，对色阻层300的性能会有严重的影响，此外，高温制程会使得色阻层300挥发产生气体，成为气泡的来源，降低产品良率。
发明内容
本发明的目的在于提供一种阵列基板，通过将黑色矩阵和色阻层均设置于阵列基板上，并且将色阻层设置于TFT层上，避免了TFT制备过程中的高温制程对色阻层产生不良影响，从而使得液晶面板具有较高的显示品质。
本发明的目的还在于提供一种阵列基板的制作方法，首先在基板上形成黑色矩阵，其次在黑色矩阵上进行TFT制程，然后在TFT制作完成后再形成色阻层，从而实现将黑色矩阵和色阻层均制作于阵列基板上，并且由于在TFT制程之后形成色阻层，避免了TFT制备过程中的高温制程中色阻挥发产生气体而导致的气泡等不良现象，有效提升了液晶面板的显示品质，并且提高了产品良率。
为实现上述目的，本发明提供一种阵列基板，包括基板，设于所述基板上的黑色矩阵，设于所述黑色矩阵上的TFT层，设于所述TFT层上的色阻层、第二钝化保护层、及像素电极层；
所述TFT层包括设于所述黑色矩阵上的源/漏极、设于所述源/漏极上的半导体层、设于所述半导体层上的栅极绝缘层、设于所述栅极绝缘层上的栅极、以及设于所述栅极上的第一钝化保护层。
所述色阻层位于第一钝化保护层上，所述第二钝化保护层位于色阻层上，所述像素电极层位于所述第二钝化保护层上，所述阵列基板还包括一贯穿第二钝化保护层、色阻层、第一钝化保护层、栅极绝缘层和半导体层的过孔，所述像素电极层经由过孔与所述源/漏极电性连接。
所述像素电极层包括第一ITO电极层和第二ITO电极层，所述第一ITO电极层位于第一钝化保护层上，所述阵列基板还包括一贯穿第一钝化保护层、栅极绝缘层和半导体层的过孔，所述第一ITO电极层经由过孔与所述源/漏极相接触，所述色阻层位于第一ITO电极层上，所述第二钝化保护层位于色阻层上，所述第二ITO电极层位于所述第二钝化保护层上，并且所述第一ITO电极层和第二ITO电极层相连，共同形成像素电极层。
所述源/漏极和栅极的材料为铜或铝。
所述半导体层是由非晶硅层和重掺杂的N型硅层组成的双层结构，也可以是由铟镓锌氧化物层构成的单层结构。
本发明还提供一种阵列基板的制作方法，包括以下步骤：
步骤1、提供基板，在所述基板上形成黑色矩阵；
步骤2、在所述黑色矩阵上制作TFT层；
步骤3、在所述TFT层和基板上形成色阻层、第二钝化保护层、及像素电极层；
所述步骤2包括以下具体步骤：
步骤21、在所述黑色矩阵上沉积并图案化第一金属层，形成源/漏极；
步骤22、在所述源/漏极上形成半导体层，在所述半导体层上形成栅极绝缘层；
步骤23、在所述栅极绝缘层上沉积并图案化第二金属层，形成栅极；
步骤24、在所述栅极上形成钝化保护层。
所述步骤3包括如下具体步骤：
步骤31、在所述第一钝化保护层上形成色阻层，并在所述色阻层上形成第二钝化保护层；
步骤32、在所述第二钝化保护层、色阻层、第一钝化保护层、栅极绝缘层、及半导体层上形成过孔；
步骤33、在所述第二钝化保护层上形成像素电极层，所述像素电极层经由所述过孔与所述源/漏极电性连接。
所述步骤3包括如下具体步骤：
步骤31、在所述第一钝化保护层、栅极绝缘层和半导体层上形成过孔；
步骤32、在所述第一钝化保护层上形成第一ITO电极层，所述第一ITO电极层经由过孔与所述源/漏极相接触；
步骤33、在所述第一ITO电极层上形成色阻层，并在所述色阻层上形成第二钝化保护层；
步骤34、在所述第二钝化保护层上形成第二ITO电极层，并且所述第一ITO电极层和第二ITO电极层相连，共同形成像素电极层。
所述源/漏极和栅极的材料为铜或铝。
所述半导体层是由非晶硅层和重掺杂的N型硅层组成的双层结构，也可以是由铟镓锌氧化物层构成的单层结构。
本发明的有益效果：本发明提供的一种阵列基板，将BOA和COA技术同时应用于阵列基板上，即将黑色矩阵和色阻层均设置于阵列基板上，为避免色阻层受到TFT制备过程中的高温制程的影响，消除液晶显示面板中气泡的来源，将色阻层设置于TFT层和黑色矩阵之上，同时为防止BOA型结构的阵列基板漏电，TFT层采用顶栅型TFT结构，有效提升了液晶显示面板的显示品质。本发明提供的一种阵列基板的制作方法，将BOA和COA技术同时应用于阵列基板上，首先在基板上形成黑色矩阵，其次在黑色矩阵上进行TFT制程，然后在TFT制作完成后再形成色阻层，从而实现将黑色矩阵和色阻层均制作于阵列基板上，并且由于在TFT制程之后形成色阻层，避免了TFT制备过程中的高温制程中色阻挥发产生气体而导致液晶显示面板产生气泡等不良现象，同时为防止BOA型结构的阵列基板漏电，TFT层采用顶栅型TFT结构，有效提升了液晶面板的显示品质，并且提高了产品良率。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种现有TFT基板结构的剖面示意图；
图2为本发明TFT基板结构的第一实施例的剖面示意图；
图3为本发明TFT基板结构的第二实施例的剖面示意图；
图4为本发明TFT基板制作方法的示意流程图。
具体实施方式
为更进一步阐述本发明所采取的技术手段极其效果，以下结合本发明的优选实施例及其附图进行详细描述。
本发明提供一种阵列基板，将BOA和COA技术同时应用于阵列基板上，即将黑色矩阵和色阻层均设置于阵列基板上，为避免色阻层受到TFT制备过程中的高温制程的影响，消除液晶显示面板中气泡的来源，将色阻层设置于TFT层和黑色矩阵之上，请参阅图2，为本发明阵列基板的第一实施例的剖面示意图，在该第一实施例中，所述阵列基板包括基板1，设于所述基板1上的黑色矩阵2，设于所述黑色矩阵2上的TFT层21，设于所述TFT层21上的色阻层8、第二钝化保护层9、及像素电极层11。
优选的，所述基板1为玻璃基板。
优选的，为防止BOA型结构的阵列基板漏电，所述TFT层21选择顶栅型TFT结构，所述TFT层21包括设于所述黑色矩阵2上的源/漏极3、设于所述源/漏极3上的半导体层4、设于所述半导体层4上的栅极绝缘层5、设于所述栅极绝缘层5上的栅极6、以及设于所述栅极6上的第一钝化保护层7。
所述半导体层4可以是由a-Si(非晶硅)层和n+Si(重掺杂的N型硅)层组成的双层结构，也可以是由IGZO(铟镓锌氧化物)层构成的单层结构。
优选的，所述源/漏极3和栅极6的材料为铜或铝。
优选的，所述栅极绝缘层5的材料为氮化硅。
其中，所述色阻层8位于第一钝化保护层7上，所述第二钝化保护层9位于色阻层8上，所述像素电极层11位于所述第二钝化保护层9上，所述阵列基板还包括一贯穿第二钝化保护层9、色阻层8、第一钝化保护层7、栅极绝缘层5和半导体层4的过孔10，所述像素电极层11经由过孔10与所述源/漏极3电性连接。
优选的，所述第一钝化保护层7与第二钝化保护层9的材料均为氮化硅。
优选的，所述像素电极层11的材料为氧化铟锡。
请参阅图4，为本发明TFT基板制作方法的示意流程图，为获得本发明第一实施例的阵列基板，本发明还提供上述第一实施例的阵列基板的制作方法，其包括以下步骤：
步骤1、提供基板1，在所述基板1上形成黑色矩阵2。
具体的，所述基板1为玻璃基板，在基板1上通过涂布工艺制作所述黑色矩阵2。
步骤2、在所述黑色矩阵2上制作TFT层21。
优选的，为防止BOA型结构的阵列基板漏电，所述TFT层21选择顶栅型TFT结构。
具体的，所述步骤2包括以下具体步骤：
步骤21、在所述黑色矩阵2上沉积并图案化第一金属层，形成源/漏极3；
优选的，所述源/漏极3的材料为铜或铝；
步骤22、在所述源/漏极3上形成半导体层4，在所述半导体层4上形成栅极绝缘层5；
所述半导体层4可以是由a-Si(非晶硅)层和n+Si(重掺杂的N型硅)层组成的双层结构，也可以是由IGZO(铟镓锌氧化物)层构成的单层结构；
优选的，所述栅极绝缘层5的材料为氮化硅；
步骤23、在所述栅极绝缘层5上沉积并图案化第二金属层，形成栅极6；
优选的，所述栅极6的材料为铜或铝；
步骤24、在所述栅极6上形成第一钝化保护层7；
优选的，所述第一钝化保护层7的材料为氮化硅。
步骤3、在所述TFT层21和基板1上形成色阻层8、第二钝化保护层9和像素电极层11。
具体的，所述步骤3包括如下具体步骤：
步骤31、在所述第一钝化保护层7上形成色阻层8，并在所述色阻层8上形成第二钝化保护层9；
具体的，采用涂布工艺形成所述色阻层8；
优选的，所述第一钝化保护层7与第二钝化保护层9的材料均为氮化硅；
步骤32、在所述第二钝化保护层9、色阻层8、第一钝化保护层7、栅极绝缘层5和半导体层4上形成过孔10；
具体的，通过干蚀刻工艺形成所述过孔10；
步骤33、在所述第二钝化保护层9上形成像素电极层11，所述像素电极层11经由所述过孔10与所述源/漏极3相接触；
具体的，通过真空镀膜技术及湿蚀刻工艺形成像素电极层11；
优选的，所述像素电极层11的材料为氧化铟锡。
请参阅图3，为本发明阵列基板的第二实施例的剖面示意图，在该第二实施例中，所述阵列基板包括基板1，设于所述基板1上的黑色矩阵2，设于所述黑色矩阵2上的TFT层21，设于所述TFT层21上的色阻层8、第二钝化保护层9、及像素电极层11。
优选的，所述基板1为玻璃基板。
其中，所述TFT层21为顶栅型TFT，所述TFT层21包括设于所述黑色矩阵2上的源/漏极3、设于所述源/漏极3上的半导体层4、设于所述半导体层4上的栅极绝缘层5、设于所述栅极绝缘层5上的栅极6、以及设于所述栅极6上的第一钝化保护层7。
所述半导体层4可以是由a-Si(非晶硅)层和n+Si(重掺杂的N型硅)层组成的双层结构，也可以是由IGZO(铟镓锌氧化物)层构成的单层结构。
优选的，所述源/漏极3和栅极6的材料为铜或铝。
优选的，所述栅极绝缘层5的材料为氮化硅。
其中，所述像素电极层11包括第一ITO电极层112和第二ITO电极层114，所述第一ITO电极层112位于第一钝化保护层7上，所述阵列基板还包括一贯穿第一钝化保护层7、栅极绝缘层5和半导体层4的过孔10’，所述第一ITO电极层112经由过孔10’与所述源/漏极3相接触，所述色阻层8位于第一ITO电极层112上，所述第二钝化保护层9位于色阻层8上，所述第二ITO电极层114位于所述第二钝化保护层9上，并且所述第一ITO电极层112和第二ITO电极层114相连，共同形成像素电极层11。
优选的，所述第一钝化保护层7与第二钝化保护层9的材料均为氮化硅。
优选的，所述第一ITO电极层112和第二ITO电极层114的材料均为氧化铟锡。
与本发明第一实施例的阵列基板相比，本发明第二实施例的阵列基板的优点在于，没有在色阻层上形成过孔，从而可以更好地保持TFT基板的平坦化。
请参阅图4，为本发明TFT基板制作方法的示意流程图，为获得本发明第二实施例的阵列基板，本发明还提供上述第二实施例的阵列基板的制作方法，其包括以下步骤：
步骤1、提供基板1，在所述基板1上形成黑色矩阵2。
具体的，所述步骤1中的基板1为玻璃基板，在基板1上通过涂布工艺制作所述黑色矩阵2。
步骤2、在所述黑色矩阵2上制作TFT层21。
具体的，所述步骤2包括以下具体步骤：
步骤21、在所述黑色矩阵2上沉积并图案化第一金属层，形成源/漏极3；
优选的，所述源/漏极3的材料为铜或铝；
步骤22、在所述源/漏极3上形成半导体层4，在所述半导体层4上形成栅极绝缘层5；
所述半导体层4可以是由a-Si(非晶硅)层和n+Si(重掺杂的N型硅)层组成的双层结构，也可以是由IGZO(铟镓锌氧化物)层构成的单层结构；
优选的，所述栅极绝缘层5的材料为氮化硅；
步骤23、在所述栅极绝缘层5上沉积并图案化第二金属层，形成栅极6；
优选的，所述栅极6的材料为铜或铝；
步骤24、在所述栅极6上形成第一钝化保护层7；
优选的，所述第一钝化保护层7的材料均为氮化硅。
步骤3、在所述TFT层21和基板1上形成色阻层8、第二钝化保护层9、及像素电极层11。
具体的，所述步骤3包括如下具体步骤：
步骤31、在所述第一钝化保护层7、栅极绝缘层5、及半导体层4上形成过孔10；
具体地，通过干蚀刻工艺形成所述过孔10’；
步骤32、在所述第一钝化保护层7上形成第一ITO电极层112，所述第一ITO电极层112经由过孔10’与所述源/漏极3相接触；
具体的，通过真空镀膜技术及湿蚀刻工艺形成第一ITO电极层112；
步骤33、在所述第一ITO电极层112上形成色阻层8，并在所述色阻层8上形成第二钝化保护层9；
具体的，采用涂布工艺形成所述色阻层8；
优选的，所述第二钝化保护层9的材料为氮化硅；
步骤34、在所述第二钝化保护层9上形成第二ITO电极层114，并且所述第一ITO电极层112和第二ITO电极层114相连，共同形成像素电极层11；
具体的，通过真空镀膜技术及湿蚀刻工艺形成第二ITO电极层114；
优选的，所述第一ITO电极层112和第二ITO电极层114的材料均为氧化铟锡。
与本发明阵列基板第一实施例的制作方法相比，本发明阵列基板第二实施例的制作方法的优点在于，没有在色阻层上形成过孔，从而可以更好地保持TFT基板的平坦化。
综上所述，本发明提供的一种阵列基板，将BOA和COA技术同时应用于阵列基板上，即将黑色矩阵和色阻层均设置于阵列基板上，为避免色阻层受到TFT制备过程中的高温制程的影响，消除液晶显示面板中气泡的来源，将色阻层设置于TFT层和黑色矩阵之上，同时为防止BOA型结构的阵列基板漏电，TFT层采用顶栅型TFT结构，有效提升了液晶显示面板的显示品质。本发明提供的一种阵列基板的制作方法，将BOA和COA技术同时应用于阵列基板上，首先在基板上形成黑色矩阵，其次在黑色矩阵上进行TFT制程，然后在TFT制作完成后再形成色阻层，从而实现将黑色矩阵和色阻层均制作于阵列基板上，并且由于在TFT制程之后形成色阻层，避免了TFT制备过程中的高温制程中色阻挥发产生气体而导致液晶显示面板产生气泡等不良现象，同时为防止BOA型结构的阵列基板漏电，TFT层采用顶栅型TFT结构，有效提升了液晶面板的显示品质，并且提高了产品良率。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (10)

1.一种阵列基板，其特征在于，包括基板(1)，设于所述基板(1)上的黑色矩阵(2)，设于所述黑色矩阵(2)上的TFT层(21)，设于所述TFT层(21)上的色阻层(8)、第二钝化保护层(9)、及像素电极层(11)；
所述TFT层(21)包括设于所述黑色矩阵(2)上的源/漏极(3)、设于所述源/漏极(3)上的半导体层(4)、设于所述半导体层(4)上的栅极绝缘层(5)、设于所述栅极绝缘层(5)上的栅极(6)、以及设于所述栅极(6)上的第一钝化保护层(7)。
2.如权利要求1所述的阵列基板，其特征在于，所述色阻层(8)位于第一钝化保护层(7)上，所述第二钝化保护层(9)位于色阻层(8)上，所述像素电极层(11)位于所述第二钝化保护层(9)上，所述阵列基板还包括一贯穿第二钝化保护层(9)、色阻层(8)、第一钝化保护层(7)、栅极绝缘层(5)和半导体层(4)的过孔(10)，所述像素电极层(11)经由过孔(10)与所述源/漏极(3)电性连接。
3.如权利要求1所述的阵列基板，其特征在于，所述像素电极层(11)包括第一ITO电极层(112)和第二ITO电极层(114)，所述第一ITO电极层(112)位于第一钝化保护层(7)上，所述阵列基板还包括一贯穿第一钝化保护层(7)、栅极绝缘层(5)和半导体层(4)的过孔(10’)，所述第一ITO电极层(112)经由过孔(10’)与所述源/漏极(3)相接触，所述色阻层(8)位于第一ITO电极层(112)上，所述第二钝化保护层(9)位于色阻层(8)上，所述第二ITO电极层(114)位于所述第二钝化保护层(9)上，并且所述第一ITO电极层(112)和第二ITO电极层(114)相连，共同形成像素电极层(11)。
4.如权利要求1所述的阵列基板，其特征在于，所述源/漏极(3)和栅极(6)的材料为铜或铝。
5.如权利要求1所述的阵列基板，其特征在于，所述半导体层(4)是由非晶硅层和重掺杂的N型硅层组成的双层结构，或者是由铟镓锌氧化物层构成的单层结构。
6.一种阵列基板的制作方法，其特征在于，包括以下步骤：
步骤1、提供基板(1)，在所述基板(1)上形成黑色矩阵(2)；
步骤2、在所述黑色矩阵(2)上制作TFT层(21)；
步骤3、在所述TFT层(21)和基板(1)上形成色阻层(8)、第二钝化保护层(9)、及像素电极层(11)；
所述步骤2包括以下具体步骤：
步骤21、在所述黑色矩阵(2)上沉积并图案化第一金属层，形成源/漏极(3)；
步骤22、在所述源/漏极(3)上形成半导体层(4)，在所述半导体层(4)上形成栅极绝缘层(5)；
步骤23、在所述栅极绝缘层(5)上沉积并图案化第二金属层，形成栅极(6)；
步骤24、在所述栅极(6)上形成第一钝化保护层(7)。
7.如权利要求6所述的阵列基板的制作方法，其特征在于，所述步骤3包括如下具体步骤：
步骤31、在所述第一钝化保护层(7)上形成色阻层(8)，并在所述色阻层(8)上形成第二钝化保护层(9)；
步骤32、在所述第二钝化保护层(9)、色阻层(8)、第一钝化保护层(7)、栅极绝缘层(5)和半导体层(4)上形成过孔(10)；
步骤33、在所述第二钝化保护层(9)上形成像素电极层(11)，所述像素电极层(11)经由所述过孔(10)与所述源/漏极(3)电性连接。
8.如权利要求6所述的阵列基板的制作方法，其特征在于，所述步骤3包括如下具体步骤：
步骤31、在所述第一钝化保护层(7)、栅极绝缘层(5)、及半导体层(4)上形成过孔(10’)；
步骤32、在所述第一钝化保护层(7)上形成第一ITO电极层(112)，所述第一ITO电极层(112)经由过孔(10’)与所述源/漏极(3)相接触；
步骤33、在所述第一ITO电极层(112)上形成色阻层(8)，并在所述色阻层(8)上形成第二钝化保护层(9)；
步骤34、在所述第二钝化保护层(9)上形成第二ITO电极层(114)，并且所述第一ITO电极层(112)和第二ITO电极层(114)相连，共同形成像素电极层(11)。
9.如权利要求6所述的阵列基板的制作方法，其特征在于，所述源/漏极(3)和栅极(6)的材料为铜或铝。
10.如权利要求6所述的阵列基板的制作方法，其特征在于，所述半导体层(4)是由非晶硅层和重掺杂的N型硅层组成的双层结构，或者是由铟镓锌氧化物层构成的单层结构。
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