WO2019174261A1 - 阵列基板 - Google Patents

阵列基板 Download PDF

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Publication number
WO2019174261A1
WO2019174261A1 PCT/CN2018/113287 CN2018113287W WO2019174261A1 WO 2019174261 A1 WO2019174261 A1 WO 2019174261A1 CN 2018113287 W CN2018113287 W CN 2018113287W WO 2019174261 A1 WO2019174261 A1 WO 2019174261A1
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WO
WIPO (PCT)
Prior art keywords
layer
disposed
via hole
peripheral region
pfa
Prior art date
Application number
PCT/CN2018/113287
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English (en)
French (fr)
Inventor
周平
赵国鹏
Original Assignee
深圳市华星光电半导体显示技术有限公司
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Publication of WO2019174261A1 publication Critical patent/WO2019174261A1/zh

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to an array substrate capable of reducing the risk of peeling of a peripheral PFA layer.
  • TFT-LCD Active Thin Film Transistor-LCD
  • CF color filter
  • Thin Film thin film transistor substrate
  • Transistor, TFT liquid crystal sandwiched between the color film substrate and the thin film transistor substrate
  • Sealant Sealant
  • COA Color-filter on Array
  • COA Color-filter on Array
  • the array substrate generally includes a base substrate, a TFT layer formed on the base substrate, a first passivation layer (PV1) formed on the TFT layer, and a first passivation layer. a color resist layer, a second passivation layer (PV2) disposed on the color resist layer, and a pixel electrode layer disposed on the second passivation layer, wherein the TFT layer specifically includes the base substrate a gate metal layer, a gate insulating layer (GI) disposed on the gate metal layer, a semiconductor layer disposed on the gate insulating layer, and the semiconductor layer and the gate insulating layer a source/drain metal layer; in addition, a via hole is formed on the first passivation layer (PV1) and the second passivation layer (PV2), specifically including a display area of the array substrate (Active A via in the drain and pixel electrodes of the thin film transistor and a via via in the peripheral integrated circuit region; but the color resist layer does not cover the peripheral region, that is
  • the array substrate includes a substrate substrate 11 disposed in order from bottom to top, a data line 12 disposed on the substrate substrate 11, and a substrate line 11 disposed on the substrate substrate 11. And a gate insulating layer 13 on the data line 12, a semiconductor layer 14 provided on the gate insulating layer 13, a gate line 15 provided on the semiconductor layer 14 and the gate insulating layer 13, and a gate line 15 a first passivation layer 16 on the gate insulating layer 13 and the gate line 15, a second passivation layer 17 disposed on the first passivation layer 16, and a pixel electrode layer 18 disposed on the second passivation layer 17, A via hole 19 is disposed above the gate line 15 and the data line 12, and the pixel electrode layer 18 is connected to the gate line 15 and the data line 12 through the via hole 19.
  • TFT-LCDs are gradually developing in the direction of large size, high resolution, and curved display.
  • the cell is thicker (cell) Gaps such as uneven brightness (Mura) caused by poor uniformity of the gap will be more noticeable. Therefore, in the process of fabricating a large-size liquid crystal display panel, a substrate on which a thin film transistor has been formed is usually covered with a transparent PFA (Polymer Film On Array) layer instead of the second passivation layer.
  • PFA Polymer Film On Array
  • a peripheral circuit region PFA layer 20 of the array substrate of the PFA product is provided on the first passivation layer 16 instead of the second passivation layer 17.
  • the adhesion force between the PFA layer and the color resist layer is better than that of the first passivation layer, and the via hole of the PFA layer in the display region is disposed in the via of the color resist layer.
  • the PFA layer is not easily peeled off when the air knife blows during the fabrication process of the array substrate, and there is no color resistance behind the via hole of the PFA layer in the peripheral display area, the air knife When blowing, it is easy to blow up the PFA layer in the peripheral display area, causing the PFA layer to peel off at the peripheral via holes, and the peeling of the PFA layer may cause the conductive layer to contact abnormally, eventually causing the lighting picture to be abnormal.
  • the purpose of the present disclosure is to provide an array substrate having a color resist layer between a peripheral passivation layer and a peripheral region PFA layer, and a via hole of the peripheral region PFA layer is disposed in the color resist layer to improve the peripheral region PFA layer. Adhesion reduces the risk of flaking of the PFA layer in the peripheral zone, thereby increasing the yield of PFA products.
  • the present disclosure provides an array substrate including a display area and a peripheral circuit area located at a periphery of the display area;
  • the peripheral circuit area includes: a peripheral area substrate; and a peripheral area TFT layer disposed in the peripheral area a peripheral region passivation layer is disposed on the peripheral region TFT layer;
  • a color resist layer is disposed on the peripheral region passivation layer and is provided with a first via hole;
  • a peripheral region PFA layer is disposed at the substrate a hole wall on the color resist layer covering the first via hole, wherein the peripheral region PFA layer is correspondingly provided with a second via hole corresponding to the first via hole, and the hole wall of the second via hole
  • the peripheral layer PFA layer; and the connection line layer are disposed on the peripheral region PFA layer, wherein the peripheral region passivation layer is correspondingly disposed under the second via hole and the second via hole a through via third via, the corresponding second via and the third via together form a via via;
  • the connecting layer passes through the via
  • the peripheral region TFT layer includes a data line and a gate line;
  • the transit via includes a first via via and a second via via, the first turn The via hole is correspondingly disposed above the data line, and the second via hole is correspondingly disposed above the gate line.
  • the peripheral region TFT layer specifically includes: the data line is disposed on the peripheral region substrate; a gate insulating layer is disposed on the peripheral region substrate and the data line on;
  • a semiconductor layer disposed on the gate insulating layer; and the gate line disposed on the semiconductor layer.
  • the gate insulating layer is correspondingly disposed with a fourth via hole penetrating the first via via under the first via via, the connecting line The layer connects the data line and the gate line through the first via via, the fourth via, and the second via.
  • the semiconductor layer includes an amorphous silicon layer and an N-type doped source-drain contact layer disposed on the amorphous silicon layer; Silicon nitride.
  • the array substrate is a COA type array substrate
  • the display area includes: a display area substrate; a display area TFT layer disposed on the display area substrate; and a display area passivation layer, Provided on the TFT layer of the display area;
  • a color film layer disposed on the passivation layer of the display area; a display area PFA layer disposed on the color film layer;
  • a pixel electrode layer is disposed on the PFA layer of the display area.
  • the peripheral area substrate is connected to the display area substrate and belongs to the same substrate;
  • the peripheral area TFT layer is disposed in the same layer as the display area TFT layer;
  • the layer is disposed in the same layer as the passivation layer of the display area, and has the same material;
  • the color resist layer is disposed in the same layer as the color film layer, and has the same material;
  • the peripheral area PFA layer and the display The PFA layer is disposed in the same layer and has the same material;
  • the connecting wire layer is disposed in the same layer as the pixel electrode layer and has the same material.
  • the material of the connection line layer and the pixel electrode layer is indium tin oxide.
  • the display region TFT layer includes a TFT device, the TFT device includes a drain, and a connection via is disposed above the drain, and the pixel electrode layer passes through the connection via It is in contact with the drain of the TFT device.
  • the color film layer is provided with a fifth via hole above the drain
  • the display area PFA layer is correspondingly provided with a sixth via hole in the fifth via hole.
  • the hole wall of the sixth via hole belongs to the PFA layer of the display area, and the passivation layer of the display area correspondingly has a seventh via hole penetrating the sixth via hole under the sixth via hole.
  • the corresponding sixth via and the seventh via together constitute the connection via.
  • the present disclosure also provides an array substrate including a display area and a peripheral circuit area located at a periphery of the display area;
  • the peripheral circuit region includes a peripheral region substrate, a peripheral region TFT layer disposed on the peripheral region substrate, a peripheral region passivation layer disposed on the peripheral region TFT layer, and a color resist layer disposed on the peripheral region passivation layer, and is disposed on the peripheral layer substrate a peripheral region PFA layer on the color resist layer and a connecting line layer disposed on the peripheral region PFA layer;
  • the color resist layer is provided with a first via hole
  • the peripheral region PFA layer is correspondingly provided with a second via hole in the first via hole
  • the hole wall of the second via hole belongs to the peripheral region a PFA layer
  • the peripheral passivation layer correspondingly has a third via hole penetrating the second via hole under the second via hole, and the corresponding second via hole and the third via hole together form a transfer a via hole
  • the connection line layer is in contact with the peripheral region TFT layer through the via via.
  • the peripheral region TFT layer includes a data line and a gate line; the transit via includes a first via via and a second via via, wherein the first via via is correspondingly disposed on the data line Upper, the second via via is correspondingly disposed above the gate line.
  • the peripheral region TFT layer specifically includes a data line disposed on the peripheral region substrate, a gate insulating layer disposed on the peripheral region substrate and the data line, a semiconductor layer disposed on the gate insulating layer, and a gate insulating layer And a gate line on the semiconductor layer.
  • the gate insulating layer is correspondingly disposed with a fourth via hole penetrating the first via via hole, and the connecting line layer passes through the first transit via hole, A four via and a second via are connected to the data line and the gate line.
  • the semiconductor layer includes an amorphous silicon layer and an N-type doped source and drain contact layer disposed on the amorphous silicon layer;
  • the material of the gate insulating layer is silicon nitride.
  • the array substrate is a COA type array substrate; the display area comprises a display area substrate, a display area TFT layer disposed on the display area substrate, a display area passivation layer disposed on the TFT layer of the display area, and a display area blunt a color film layer on the layer, a PFA layer disposed on the color film layer, and a pixel electrode layer disposed on the PFA layer of the display region.
  • the peripheral area substrate is connected to the display area substrate and belongs to the same substrate; the peripheral area TFT layer is disposed in the same layer as the display area TFT layer; the peripheral area passivation layer is the same as the display area passivation layer
  • the layers are disposed and have the same material; the color resist layer is disposed in the same layer as the color film layer and has the same material; the peripheral region PFA layer is disposed in the same layer as the display region PFA layer, and has the same
  • the material of the connection line is disposed in the same layer as the pixel electrode layer and has the same material.
  • connection line layer and the pixel electrode layer is indium tin oxide.
  • the TFT of the display region includes a TFT device including a drain, and a connection via is disposed above the drain, and the pixel electrode layer is in contact with a drain of the TFT device through the connection via.
  • the color filter layer is provided with a fifth via hole above the drain, and the display region PFA layer is correspondingly provided with a sixth via hole in the fifth via hole, and the hole wall of the sixth via hole belongs to a display region PFA layer, the display region passivation layer correspondingly has a seventh via hole penetrating through the sixth via hole, and a corresponding sixth via hole and a seventh via hole Together, the connection vias are formed.
  • An array substrate provided by the present disclosure includes a display area and a peripheral circuit area located at a periphery of the display area;
  • the peripheral circuit area includes a peripheral area substrate sequentially disposed from bottom to top, a peripheral area TFT layer, a peripheral area passivation layer, and a color a resistive layer, a peripheral region PFA layer and a connecting line layer, wherein the color resist layer is provided with a first via hole, and the peripheral region PFA layer is correspondingly provided with a second via hole in the first via hole, the second The hole wall of the via hole belongs to the PFA layer of the peripheral region, and the passivation layer of the peripheral region correspondingly has a third via hole penetrating the second via hole under the second via hole, and the corresponding second pass The via and the third via together form a via via, the strap layer being in contact with the peripheral TFT layer through the via via; the present disclosure provides color resist between the passivation layer in the peripheral region and the PFA layer in the peripheral region The layer and the via hole for
  • 1 is a plan view showing a conventional array substrate in a peripheral circuit region
  • FIG. 2 is a schematic cross-sectional structural view of an array substrate of a non-PFA product taken along line A-A of FIG. 1;
  • FIG. 3 is a cross-sectional structural view of the array substrate of the PFA product taken along line A-A of FIG. 1;
  • FIG. 4 is a schematic plan view showing a peripheral circuit region of the array substrate of the present disclosure.
  • FIG. 5 is a cross-sectional structural view of the array substrate of the present disclosure taken along line B-B of FIG. 4;
  • FIG. 6 is a schematic cross-sectional view showing the display region of the array substrate of the present disclosure at a connection via.
  • the present disclosure provides an array substrate including a display area 6 and a peripheral circuit area 3 located at the periphery of the display area 6.
  • the peripheral circuit region 3 includes a peripheral region substrate 31, a peripheral region TFT layer 32 disposed on the peripheral region substrate 31, a peripheral region passivation layer 33 disposed on the peripheral region TFT layer 32, and a peripheral region passivation layer 33. a color resist layer 34, a peripheral region PFA layer 35 disposed on the color resist layer 34, and a connection line layer 36 disposed on the peripheral region PFA layer 35; wherein the color resist layer 34 is provided with a first via 51
  • the peripheral area PFA layer 35 covers the hole wall of the first via hole 51, and the peripheral area PFA layer 35 is correspondingly provided with the second via hole 52 in the first via hole 51, the second via hole
  • the wall of the hole 52 belongs to the peripheral region PFA layer 35.
  • the peripheral region passivation layer 33 is correspondingly disposed with a third via hole 53 extending through the second via hole 52, corresponding to the second via hole 53.
  • the second via 52 and the third via 53 together form a via via 55; the via layer 36 is in contact with the peripheral TFT layer 32 through the via via 55.
  • the array substrate of the present disclosure is provided with a color resist layer 34 between the peripheral region passivation layer 33 and the peripheral region PFA layer 35.
  • the color resist layer 34 is provided with a first via 51 and the peripheral region PFA layer 35 is used for transfer.
  • the third via hole 53 is disposed in the first via hole 51 of the color resist layer 34, which can improve the adhesion of the PFA layer 35 in the peripheral region, and reduce the risk of peeling of the PFA layer 35 in the peripheral region, thereby improving the quality of the PFA product. rate.
  • the peripheral region TFT layer 32 includes a data line 37 and a gate line 40;
  • the transit via 55 includes a first via via 56 and a second via via 57, the first switch
  • the via hole 56 is correspondingly disposed above the data line 37, and the second via via 57 is correspondingly disposed above the gate line 40.
  • the peripheral region TFT layer 32 specifically includes a data line 37 disposed on the peripheral region substrate 31, a gate insulating layer 38 disposed on the peripheral region substrate 31 and the data line 37, and is disposed on the gate insulating layer 38.
  • the semiconductor layer 39 and the gate lines 40 provided on the gate insulating layer 38 and the semiconductor layer 39.
  • the gate insulating layer 38 is correspondingly disposed under the first via via 56 with a fourth via 54 extending through the first via via 56, and the connecting layer 36 passes through the The first via via 56, the fourth via 54 and the second via via 57 connect the data line 37 and the gate line 40.
  • the semiconductor layer 39 includes an amorphous silicon layer (a-Si) 41 and an N-type doped source-drain contact layer (N+a-Si) 42 disposed on the amorphous silicon layer 41.
  • a-Si amorphous silicon layer
  • N+a-Si N-type doped source-drain contact layer
  • the material of the gate insulating layer 38 is silicon nitride (SiNx).
  • the array substrate is a COA type array substrate; as shown in FIG. 6, the display area 6 includes a display area substrate 61, a display area TFT layer 62 disposed on the display area substrate 61, and a TFT layer disposed in the display area. a display region passivation layer 63 on 62, a color film layer 64 disposed on the passivation layer 63 of the display region, a display region PFA layer 65 disposed on the color film layer 64, and a pixel electrode disposed on the PFA layer 65 of the display region Layer 66.
  • the peripheral area substrate 31 is connected to the display area substrate 61 and belongs to the same substrate; the peripheral area TFT layer 32 is disposed in the same layer as the display area TFT layer 62; the peripheral area passivation layer 33 and The display region passivation layer 63 is disposed in the same layer and has the same material; the color resist layer 34 is disposed in the same layer as the color film layer 64 and has the same material; the peripheral region PFA layer 35 and the The display region PFA layer 65 is disposed in the same layer and has the same material; the connection line layer 36 is disposed in the same layer as the pixel electrode layer 66 and has the same material.
  • connection line layer 36 and the pixel electrode layer 66 is indium tin oxide (ITO).
  • the display region TFT layer 62 includes a TFT device T
  • the TFT device T includes a drain 67
  • a connection via 77 is disposed above the drain 67
  • the pixel electrode layer 66 passes through the connection via 77 is in contact with the drain 67 of the TFT device T.
  • the color filter layer 64 is provided with a fifth via hole 74 above the drain 67, and the display region PFA layer 65 is correspondingly provided with a sixth via hole 75 in the fifth via hole 74.
  • the hole wall of the sixth via hole 75 belongs to the display area PFA layer 65, and the display area passivation layer 63 is correspondingly provided with a seventh pass penetrating the sixth via hole 75 under the sixth via hole 75.
  • the holes 76, the corresponding sixth vias 75 and the seventh vias 76 together constitute the connection vias 77.
  • the present disclosure provides an array substrate including a display area and a peripheral circuit area located at a periphery of the display area.
  • the peripheral circuit area includes a peripheral area substrate 31 and a peripheral area TFT layer 32 disposed in order from bottom to top. a peripheral passivation layer 33, a color resist layer 34, a peripheral region PFA layer 35, and a connection line layer 36.
  • the color resist layer 34 is provided with a first via 51, and the peripheral region PFA layer 35 is in the first pass.
  • a second via hole 52 is defined in the hole 51.
  • the hole wall of the second via hole 52 belongs to the peripheral region PFA layer 35, and the peripheral region passivation layer 33 is correspondingly disposed under the second via hole 52.
  • the corresponding second via 52 and the third via 53 together form a via via 55, and the connecting layer 36 passes through the via 55.
  • the present disclosure provides a color resist layer 34 between the peripheral region passivation layer 33 and the peripheral region PFA layer 35, and the via for the via of the peripheral region PFA layer 35 is provided
  • the adhesion of the PFA layer in the peripheral region can be improved, and the risk of peeling of the PFA layer in the peripheral region can be reduced, thereby improving the yield of the PFA product.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

一种阵列基板，其外围电路区域（3）包括由下至上依次设置的外围区基板（31）、外围区TFT层（32）、外围区钝化层（33）、色阻层（34）、外围区PFA层（35）及连接线层（36），色阻层（34）设有第一过孔（51），外围区PFA层（35）在第一过孔（51）中对应设有第二过孔（52），第二过孔（52）的孔壁属于外围区PFA层（35），外围区钝化层（33）在第二过孔（52）下方对应设有与第二过孔（52）相贯通的第三过孔（53），相对应的第二过孔（52）和第三过孔（53）共同组成转接过孔（55），连接线层（36）通过转接过孔（55）与外围区TFT层（32）相接触，通过在外围区钝化层（33）和外围区PFA层（35）之间设置色阻层（34），并将外围区PFA层（35）的用于转接的第三过孔（53）设于色阻层（34）中，能提高外围区PFA层（35）的粘附性，降低外围区PFA层（35）发生剥落的风险，从而提高PFA产品的良率。

Description

阵列基板 技术领域
本揭示涉及显示技术领域，尤其涉及一种能够降低外围PFA层剥落风险的阵列基板。
 背景技术
主动式薄膜晶体管液晶显示器（Thin Film Transistor-LCD，TFT-LCD）近年来得到了飞速的发展和广泛的应用。现有市场上的液晶显示装置大部分为背光型液晶显示装置，其包括液晶显示面板及背光模组（backlight module）。通常液晶显示面板由彩膜（Color Filter，CF）基板、薄膜晶体管基板（Thin Film Transistor，TFT）、夹于彩膜基板与薄膜晶体管基板之间的液晶（Liquid Crystal，LC）及密封框胶（Sealant）组成。
COA（Color-filter on Array）技术是一种将彩色色阻层直接制作在阵列基板上的一种集成技术，能够有效解决液晶显示装置对盒工艺中因对位偏差造成的漏光等问题，并能显着提升显示开口率。
传统的COA型显示面板中，阵列基板通常包括衬底基板、形成于衬底基板上的TFT层、形成于TFT层上的第一钝化层（PV1）、设于第一钝化层上的彩色色阻层、设于彩色色阻层上的第二钝化层（PV2）及设于第二钝化层上的像素电极层，其中，所述TFT层具体包括设于所述衬底基板上的栅极金属层、设于栅极金属层上的栅极绝缘层（GI）、设于所述栅极绝缘层上的半导体层、及设于所述半导体层、及栅极绝缘层上的源漏极金属层；另外，第一钝化层（PV1）和第二钝化层（PV2）上需形成过孔，具体包括阵列基板的显示区域（Active Area，AA）中连接薄膜晶体管漏极和像素电极的过孔、以及外围集成电路区域中的转接过孔；但是该彩色色阻层并不覆盖外围区域，即该阵列基板在转接过孔处并不设置彩色色阻层。
如图1-2所示，所述阵列基板在外围电路区域包括由下至上依次设置的衬底基板11、设于衬底基板11上的数据线（Date line）12、设于衬底基板11及数据线12上的栅极绝缘层13、设于栅极绝缘层13上的半导体层14、设于半导体层14及栅极绝缘层13上的栅极线（Gate line）15、设于栅极绝缘层13及栅极线15上的第一钝化层16、设于第一钝化层16上的第二钝化层17以及设于第二钝化层17上的像素电极层18，其中，所述栅极线15和数据线12上方对应设有转接孔19，所述像素电极层18通过所述转接孔19连接栅极线15和数据线12。
随着消费者对液晶显示装置要求越来越高，TFT-LCD正逐渐向大尺寸、高解析度、曲面显示等方向发展。随着液晶显示装置尺寸增大，由液晶盒盒厚（cell gap）的均一性不佳导致的显示亮度不均（Mura）等不良将会更加明显。因此，在大尺寸液晶显示面板的制作过程中，已经形成薄膜晶体管的基板上通常需要覆盖一层透明的PFA（Polymer Film on Array，阵列基板侧有机膜）层来代替第二钝化层，以改变下层膜表面的平整性，防止电场互相干扰，从而可有效改善由于地形因素造成的液晶显示装置的显示Mura，降低寄生电容，减少由电负载（RC loading）过大造成的闪烁等显示异常，提升显示装置的品质。如图3所示，在PFA产品的阵列基板的外围电路区域PFA层20代替第二钝化层17设于第一钝化层16上。但在PFA制程中，很容易产生PFA层的剥落（Peeling）不良，特别是面外转接孔区域，PFA层剥落的发生率很高，而面内过孔区域PFA层剥落的发生率则很低。现有PFA产品的阵列基板上，PFA层在外围电路区域易发生剥落不良，究其原因，一是其外围电路区域中PFA层直接设于第一钝化层上，而在显示区域中PFA层是设置在彩色色阻层上，PFA层与彩色色阻层的黏附力比与第一钝化层的黏附力好，二是显示区域中PFA层的过孔设于彩色色阻层的过孔内，PFA层的过孔后方存在色阻，那么在阵列基板的制作过程中当风刀吹过的时候PFA层不容易剥落，而外围显示区域中PFA层的过孔后方没有色阻，风刀吹的时候容易将外围显示区域的PFA层吹起，造成PFA层在外围的过孔处剥落，而PFA层剥落会导致导电层接触异常，最终造成点灯画面异常。
 技术问题
本揭示的目的在于提供一种阵列基板，其外围区钝化层和外围区PFA层之间设有色阻层，外围区PFA层的过孔设于色阻层中，能提高外围区PFA层的粘附性，降低外围区PFA层发生剥落的风险，从而提高PFA产品的良率。
 技术解决方案
为实现上述目的，本揭示提供一种阵列基板，包括显示区域及位于所述显示区域外围的外围电路区域；所述外围电路区域包括：外围区基板；外围区TFT层，设于所述外围区基板上；外围区钝化层，设于所述外围区TFT层上；色阻层，设于所述外围区钝化层上，且设有第一过孔；外围区PFA层，设于所述色阻层上且覆盖所述第一过孔的孔壁，其中所述外围区PFA层对应设有与所述第一过孔对应的第二过孔，所述第二过孔的孔壁属于所述外围区PFA层；及连接线层，设于所述外围区PFA层上，其中所述外围区钝化层在所述第二过孔下方对应设有与所述第二过孔相贯通的第三过孔，相对应的所述第二过孔和所述第三过孔共同组成转接过孔；所述连接线层通过所述转接过孔与所述外围区TFT层相接触。
本揭示其中之一优选实施例中，所述外围区TFT层包括数据线和栅极线；所述转接过孔包括第一转接过孔和第二转接过孔，所述第一转接过孔对应设于所述数据线上方，所述第二转接过孔对应设于所述栅极线上方。
本揭示其中之一优选实施例中，所述外围区TFT层具体包括：所述数据线，设于所述外围区基板上；栅极绝缘层，设于所述外围区基板及所述数据线上；
半导体层，设于所述栅极绝缘层上；以及所述栅极线，设于所述半导体层上。
本揭示其中之一优选实施例中，所述栅极绝缘层在所述第一转接过孔下方对应设有与所述第一转接过孔相贯通的第四过孔，所述连接线层通过所述第一转接过孔、所述第四过孔和所述第二转接过孔连接所述数据线和所述栅极线。
本揭示其中之一优选实施例中，所述半导体层包括非晶硅层及设于所述非晶硅层上经N型掺杂的源漏极接触层；所述栅极绝缘层的材料为氮化硅。
本揭示其中之一优选实施例中，所述阵列基板为COA型阵列基板；所述显示区域包括：显示区基板；显示区TFT层，设于所述显示区基板上；显示区钝化层，设于所述显示区TFT层上；
彩膜层，设于所述显示区钝化层上；显示区PFA层，设于所述彩膜层上；及
像素电极层，设于所述显示区PFA层上。
本揭示其中之一优选实施例中，所述外围区基板与所述显示区基板相连并属于同一基板；所述外围区TFT层与所述显示区TFT层同层设置；所述外围区钝化层与所述显示区钝化层同层设置，并具有相同的材料；所述色阻层与所述彩膜层同层设置，并具有相同的材料；所述外围区PFA层与所述显示区PFA层同层设置，并具有相同的材料；所述连接线层与所述像素电极层同层设置，并具有相同的材料。
本揭示其中之一优选实施例中，所述连接线层与所述像素电极层的材料为氧化铟锡。
本揭示其中之一优选实施例中，所述显示区TFT层包括TFT器件，所述TFT器件包括漏极，所述漏极上方设有连接过孔，所述像素电极层通过所述连接过孔和TFT器件的漏极相接触。
本揭示其中之一优选实施例中，所述彩膜层在所述漏极上方设有第五过孔，所述显示区PFA层在所述第五过孔中对应设有第六过孔，所述第六过孔的孔壁属于所述显示区PFA层，所述显示区钝化层在所述第六过孔下方对应设有与所述第六过孔相贯通的第七过孔，相对应的所述第六过孔和所述第七过孔共同组成所述连接过孔。
本揭示还提供一种阵列基板，包括显示区域及位于显示区域外围的外围电路区域；
所述外围电路区域包括外围区基板、设于外围区基板的外围区TFT层、设于外围区TFT层上的外围区钝化层、设于外围区钝化层上的色阻层、设于色阻层上的外围区PFA层及设于外围区PFA层上的连接线层；
其中，所述色阻层设有第一过孔，所述外围区PFA层在所述第一过孔中对应设有第二过孔，所述第二过孔的孔壁属于所述外围区PFA层，所述外围区钝化层在所述第二过孔下方对应设有与第二过孔相贯通的第三过孔，相对应的第二过孔和第三过孔共同组成转接过孔；所述连接线层通过转接过孔与外围区TFT层相接触。
所述外围区TFT层包括数据线和栅极线；所述转接过孔包括第一转接过孔和第二转接过孔，所述第一转接过孔对应设于所述数据线上方，所述第二转接过孔对应设于所述栅极线上方。
所述外围区TFT层具体包括设于外围区基板上的数据线、设于外围区基板及数据线上的栅极绝缘层、设于栅极绝缘层上的半导体层以及设于栅极绝缘层及半导体层上的栅极线。
所述栅极绝缘层在所述第一转接过孔下方对应设有与第一转接过孔相贯通的第四过孔，所述连接线层通过所述第一转接过孔、第四过孔和第二转接过孔连接所述数据线和栅极线。
所述半导体层包括非晶硅层及设于非晶硅层上经N型掺杂的源漏极接触层；
所述栅极绝缘层的材料为氮化硅。
所述阵列基板为COA型阵列基板；所述显示区域包括显示区基板、设于显示区基板上的显示区TFT层、设于显示区TFT层上的显示区钝化层、设于显示区钝化层上的彩膜层、设于彩膜层上的显示区PFA层及设于显示区PFA层上的像素电极层。
所述外围区基板与所述显示区基板相连并属于同一基板；所述外围区TFT层与所述显示区TFT层同层设置；所述外围区钝化层与所述显示区钝化层同层设置，并具有相同的材料；所述色阻层与所述彩膜层同层设置，并具有相同的材料；所述外围区PFA层与所述显示区PFA层同层设置，并具有相同的材料；所述连接线层与所述像素电极层同层设置，并具有相同的材料。
所述连接线层与所述像素电极层的材料为氧化铟锡。
所述显示区TFT层包括TFT器件，所述TFT器件包括漏极，所述漏极上方设有连接过孔，所述像素电极层通过所述连接过孔和TFT器件的漏极相接触。
所述彩膜层在所述漏极上方设有第五过孔，所述显示区PFA层在所述第五过孔中对应设有第六过孔，所述第六过孔的孔壁属于所述显示区PFA层，所述显示区钝化层在所述第六过孔下方对应设有与第六过孔相贯通的第七过孔，相对应的第六过孔和第七过孔共同组成所述连接过孔。
 有益效果
本揭示提供的一种阵列基板，包括显示区域及位于显示区域外围的外围电路区域；所述外围电路区域包括由下至上依次设置的外围区基板、外围区TFT层、外围区钝化层、色阻层、外围区PFA层及连接线层，所述色阻层设有第一过孔，所述外围区PFA层在所述第一过孔中对应设有第二过孔，所述第二过孔的孔壁属于所述外围区PFA层，所述外围区钝化层在所述第二过孔下方对应设有与第二过孔相贯通的第三过孔，相对应的第二过孔和第三过孔共同组成转接过孔，所述连接线层通过转接过孔与外围区TFT层相接触；本揭示通过在外围区钝化层和外围区PFA层之间设置色阻层，并将外围区PFA层的用于转接的过孔设于色阻层中，能提高外围区PFA层的粘附性，降低外围区PFA层发生剥落的风险，从而提高PFA产品的良率。
 附图说明
为了能更进一步了解本揭示的特征以及技术内容，请参阅以下有关本揭示的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本揭示加以限制。
附图中，
图1为现有一种阵列基板在外围电路区域的平面示意图；
图2为非PFA产品的阵列基板沿图1中A-A线的剖面结构示意图；
图3为PFA产品的阵列基板沿图1中A-A线的剖面结构示意图；
图4为本揭示的阵列基板的外围电路区域的平面示意图；
图5为本揭示的阵列基板沿图4中B-B线的剖面结构示意图；
图6为本揭示的阵列基板的显示区域在连接过孔处的剖面结构示意图。
 本发明的实施方式
为更进一步阐述本揭示所采取的技术手段及其效果，以下结合本揭示的优选实施例及其附图进行详细描述。
请参阅图4-6，本揭示提供一种阵列基板，包括显示区域6及位于显示区域6外围的外围电路区域3。
所述外围电路区域3包括外围区基板31、设于外围区基板31上的外围区TFT层32、设于外围区TFT层32上的外围区钝化层33、设于外围区钝化层33上的色阻层34、设于色阻层34上的外围区PFA层35及设于外围区PFA层35上的连接线层36；其中，所述色阻层34设有第一过孔51，所述外围区PFA层35覆盖第一过孔51的孔壁，并且所述外围区PFA层35在所述第一过孔51中对应设有第二过孔52，所述第二过孔52的孔壁属于所述外围区PFA层35，所述外围区钝化层33在所述第二过孔52下方对应设有与第二过孔52相贯通的第三过孔53，相对应的第二过孔52和第三过孔53共同组成转接过孔55；所述连接线层36通过所述转接过孔55与所述外围区TFT层32相接触。
本揭示阵列基板在外围区钝化层33和外围区PFA层35之间设置色阻层34，所述色阻层34设有第一过孔51，并将外围区PFA层35的用于转接的第三过孔53设于色阻层34的第一过孔51中，能提高外围区PFA层35的粘附性，降低外围区PFA层35发生剥落的风险，从而提高PFA产品的良率。
具体地，所述外围区TFT层32包括数据线37和栅极线40；所述转接过孔55包括第一转接过孔56和第二转接过孔57，所述第一转接过孔56对应设于所述数据线37上方，所述第二转接过孔57对应设于所述栅极线40上方。
具体地，所述外围区TFT层32具体包括设于外围区基板31上的数据线37、设于外围区基板31及数据线37上的栅极绝缘层38、设于栅极绝缘层38上的半导体层39以及设于栅极绝缘层38及半导体层39上的栅极线40。
具体地，所述栅极绝缘层38在所述第一转接过孔56下方对应设有与第一转接过孔56相贯通的第四过孔54，所述连接线层36通过所述第一转接过孔56、第四过孔54和第二转接过孔57连接所述数据线37和栅极线40。
具体地，所述半导体层39包括非晶硅层（a-Si）41及设于非晶硅层41上经N型掺杂的源漏极接触层（N+a-Si）42。
具体地，所述栅极绝缘层38的材料为氮化硅（SiNx）。
具体地，所述阵列基板为COA型阵列基板；如图6所示，所述显示区域6包括显示区基板61、设于显示区基板61上的显示区TFT层62、设于显示区TFT层62上的显示区钝化层63、设于显示区钝化层63上的彩膜层64、设于彩膜层64上的显示区PFA层65及设于显示区PFA层65上的像素电极层66。
具体地，所述外围区基板31与所述显示区基板61相连并属于同一基板；所述外围区TFT层32与所述显示区TFT层62同层设置；所述外围区钝化层33与所述显示区钝化层63同层设置，并具有相同的材料；所述色阻层34与所述彩膜层64同层设置，并具有相同的材料；所述外围区PFA层35与所述显示区PFA层65同层设置，并具有相同的材料；所述连接线层36与所述像素电极层66同层设置，并具有相同的材料。
具体地，所述连接线层36与所述像素电极层66的材料为氧化铟锡（ITO）。
具体地，所述显示区TFT层62包括TFT器件T，所述TFT器件T包括漏极67，所述漏极67上方设有连接过孔77，所述像素电极层66通过所述连接过孔77和TFT器件T的漏极67相接触。
具体地，所述彩膜层64在所述漏极67上方设有第五过孔74，所述显示区PFA层65在所述第五过孔74中对应设有第六过孔75，所述第六过孔75的孔壁属于所述显示区PFA层65，所述显示区钝化层63在所述第六过孔75下方对应设有与第六过孔75相贯通的第七过孔76，相对应的第六过孔75和第七过孔76共同组成所述连接过孔77。
综上所述，本揭示提供的一种阵列基板，包括显示区域及位于显示区域外围的外围电路区域；所述外围电路区域包括由下至上依次设置的外围区基板31、外围区TFT层32、外围区钝化层33、色阻层34、外围区PFA层35及连接线层36，所述色阻层34设有第一过孔51，所述外围区PFA层35在所述第一过孔51中对应设有第二过孔52，所述第二过孔52的孔壁属于所述外围区PFA层35，所述外围区钝化层33在所述第二过孔52下方对应设有与第二过孔52相贯通的第三过孔53，相对应的第二过孔52和第三过孔53共同组成转接过孔55，所述连接线层36通过转接过孔55与外围区TFT层32相接触；本揭示通过在外围区钝化层33和外围区PFA层35之间设置色阻层34，并将外围区PFA层35的用于转接的过孔设于色阻层中，能提高外围区PFA层的粘附性，降低外围区PFA层发生剥落的风险，从而提高PFA产品的良率。
以上所述，对于本领域的普通技术人员来说，可以根据本揭示的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本揭示权利要求的保护范围。

Claims (20)

  1. 一种阵列基板，包括显示区域及位于所述显示区域外围的外围电路区域；
    所述外围电路区域包括：
    外围区基板；
    外围区TFT层，设于所述外围区基板上；
    外围区钝化层，设于所述外围区TFT层上；
    色阻层，设于所述外围区钝化层上，且设有第一过孔；
    外围区PFA层，设于所述色阻层上且覆盖所述第一过孔的孔壁，其中所述外围区PFA层对应设有与所述第一过孔对应的第二过孔，所述第二过孔的孔壁属于所述外围区PFA层；及
    连接线层，设于所述外围区PFA层上，
    其中所述外围区钝化层在所述第二过孔下方对应设有与所述第二过孔相贯通的第三过孔，相对应的所述第二过孔和所述第三过孔共同组成转接过孔；所述连接线层通过所述转接过孔与所述外围区TFT层相接触。
  2. 如权利要求1所述的阵列基板，其中所述外围区TFT层包括数据线和栅极线；所述转接过孔包括第一转接过孔和第二转接过孔，所述第一转接过孔对应设于所述数据线上方，所述第二转接过孔对应设于所述栅极线上方。
  3. 如权利要求2所述的阵列基板，其中所述外围区TFT层具体包括：
    所述数据线，设于所述外围区基板上；
    栅极绝缘层，设于所述外围区基板及所述数据线上；
    半导体层，设于所述栅极绝缘层上；以及
    所述栅极线，设于所述半导体层上。
  4. 如权利要求3所述的阵列基板，其中所述栅极绝缘层在所述第一转接过孔下方对应设有与所述第一转接过孔相贯通的第四过孔，所述连接线层通过所述第一转接过孔、所述第四过孔和所述第二转接过孔连接所述数据线和所述栅极线。
  5. 如权利要求3所述的阵列基板，其中所述半导体层包括非晶硅层及设于所述非晶硅层上经N型掺杂的源漏极接触层；
    所述栅极绝缘层的材料为氮化硅。
  6. 如权利要求1所述的阵列基板，其中所述阵列基板为COA型阵列基板；所述显示区域包括：
    显示区基板；
    显示区TFT层，设于所述显示区基板上；
    显示区钝化层，设于所述显示区TFT层上；
    彩膜层，设于所述显示区钝化层上；
    显示区PFA层，设于所述彩膜层上；及
    像素电极层，设于所述显示区PFA层上。
  7. 如权利要求6所述的阵列基板，其中所述外围区基板与所述显示区基板相连并属于同一基板；所述外围区TFT层与所述显示区TFT层同层设置；所述外围区钝化层与所述显示区钝化层同层设置，并具有相同的材料；所述色阻层与所述彩膜层同层设置，并具有相同的材料；所述外围区PFA层与所述显示区PFA层同层设置，并具有相同的材料；所述连接线层与所述像素电极层同层设置，并具有相同的材料。
  8. 如权利要求7所述的阵列基板，其中所述连接线层与所述像素电极层的材料为氧化铟锡。
  9. 如权利要求6所述的阵列基板，其中所述显示区TFT层包括TFT器件，所述TFT器件包括漏极，所述漏极上方设有连接过孔，所述像素电极层通过所述连接过孔和TFT器件的漏极相接触。
  10. 如权利要求9所述的阵列基板，其中所述彩膜层在所述漏极上方设有第五过孔，所述显示区PFA层在所述第五过孔中对应设有第六过孔，所述第六过孔的孔壁属于所述显示区PFA层，所述显示区钝化层在所述第六过孔下方对应设有与所述第六过孔相贯通的第七过孔，相对应的所述第六过孔和所述第七过孔共同组成所述连接过孔。
  11. 一种阵列基板，包括显示区域及位于所述显示区域外围的外围电路区域；
    所述外围电路区域包括外围区基板、设于所述外围区基板上的外围区TFT层、设于所述外围区TFT层上的外围区钝化层、设于所述外围区钝化层上的色阻层、设于所述色阻层上的外围区PFA层及设于所述外围区PFA层上的连接线层；
    其中，所述色阻层设有第一过孔，所述外围区PFA层在所述第一过孔中对应设有第二过孔，所述第二过孔的孔壁属于所述外围区PFA层，所述外围区钝化层在所述第二过孔下方对应设有与所述第二过孔相贯通的第三过孔，相对应的所述第二过孔和所述第三过孔共同组成转接过孔；所述连接线层通过所述转接过孔与所述外围区TFT层相接触。
  12. 如权利要求11所述的阵列基板，其中所述外围区TFT层包括数据线和栅极线；所述转接过孔包括第一转接过孔和第二转接过孔，所述第一转接过孔对应设于所述数据线上方，所述第二转接过孔对应设于所述栅极线上方。
  13. 如权利要求12所述的阵列基板，其中所述外围区TFT层具体包括设于所述外围区基板上的所述数据线、设于所述外围区基板及所述数据线上的栅极绝缘层、设于所述栅极绝缘层上的半导体层以及设于所述栅极绝缘层及所述半导体层上的所述栅极线。
  14. 如权利要求13所述的阵列基板，其中所述栅极绝缘层在所述第一转接过孔下方对应设有与所述第一转接过孔相贯通的第四过孔，所述连接线层通过所述第一转接过孔、所述第四过孔和所述第二转接过孔连接所述数据线和所述栅极线。
  15. 如权利要求13所述的阵列基板，其中所述半导体层包括非晶硅层及设于所述非晶硅层上经N型掺杂的源漏极接触层；
    所述栅极绝缘层的材料为氮化硅。
  16. 如权利要求11所述的阵列基板，其中所述阵列基板为COA型阵列基板；所述显示区域包括显示区基板、设于所述显示区基板上的显示区TFT层、设于所述显示区TFT层上的显示区钝化层、设于所述显示区钝化层上的彩膜层、设于所述彩膜层上的显示区PFA层及设于所述显示区PFA层上的像素电极层。
  17. 如权利要求16所述的阵列基板，其中所述外围区基板与所述显示区基板相连并属于同一基板；所述外围区TFT层与所述显示区TFT层同层设置；所述外围区钝化层与所述显示区钝化层同层设置，并具有相同的材料；所述色阻层与所述彩膜层同层设置，并具有相同的材料；所述外围区PFA层与所述显示区PFA层同层设置，并具有相同的材料；所述连接线层与所述像素电极层同层设置，并具有相同的材料。
  18. 如权利要求17所述的阵列基板，其中所述连接线层与所述像素电极层的材料为氧化铟锡。
  19. 如权利要求16所述的阵列基板，其中所述显示区TFT层包括TFT器件，所述TFT器件包括漏极，所述漏极上方设有连接过孔，所述像素电极层通过所述连接过孔和TFT器件的漏极相接触。
  20. 如权利要求19所述的阵列基板，其中所述彩膜层在所述漏极上方设有第五过孔，所述显示区PFA层在所述第五过孔中对应设有第六过孔，所述第六过孔的孔壁属于所述显示区PFA层，所述显示区钝化层在所述第六过孔下方对应设有与所述第六过孔相贯通的第七过孔，相对应的所述第六过孔和所述第七过孔共同组成所述连接过孔。
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