WO2017128597A1 - 液晶显示面板、tft基板及其制造方法 - Google Patents

液晶显示面板、tft基板及其制造方法 Download PDF

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Publication number
WO2017128597A1
WO2017128597A1 PCT/CN2016/085465 CN2016085465W WO2017128597A1 WO 2017128597 A1 WO2017128597 A1 WO 2017128597A1 CN 2016085465 W CN2016085465 W CN 2016085465W WO 2017128597 A1 WO2017128597 A1 WO 2017128597A1
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metal layer
substrate
groove
layer
tft substrate
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PCT/CN2016/085465
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English (en)
French (fr)
Inventor
谢应涛
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武汉华星光电技术有限公司
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Priority to US15/109,903 priority Critical patent/US20180095320A1/en
Publication of WO2017128597A1 publication Critical patent/WO2017128597A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L2021/775—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate comprising a plurality of TFTs on a non-semiconducting substrate, e.g. driving circuits for AMLCDs

Definitions

  • the present invention relates to the field of liquid crystal technology, and in particular to a liquid crystal display panel, a TFT substrate, and a method of fabricating the same.
  • the liquid crystal display panel is currently the most widely used flat panel display panel, and it has gradually become widely used in various electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or notebook screens, and has high resolution. Rate display panel for color screens.
  • PDAs personal digital assistants
  • Rate display panel for color screens With the development of liquid crystal display panel technology, people have put forward higher requirements on the display quality, design, low cost and high transmittance of liquid crystal display panels.
  • a TFT substrate thin film transistor array substrate of a liquid crystal display panel in the present display field includes a base substrate 11 , a first metal layer 12 disposed on the base substrate 11 , and a first metal layer 12 .
  • the thickness of the TFT substrate is relatively high, which is disadvantageous for realizing an ultrathin liquid crystal display panel; and the first metal layer
  • the insulating layer 13 of the 12 corner regions is poor in film quality and is easily broken by the driving voltage, which also affects the display quality of the liquid crystal display panel.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display panel, a TFT substrate, and a method of manufacturing the same, which can realize an ultra-thin liquid crystal display panel and improve the display quality of the liquid crystal display panel.
  • a technical solution adopted by the present invention is to provide a method for manufacturing a TFT substrate, the method comprising: providing a groove in a substrate; filling the groove with a metal material to form a first metal layer, The first metal layer serves as a gate of the TFT substrate; an insulating layer is disposed on the first metal layer and the substrate; a semiconductor material layer and a second metal layer are sequentially disposed on the insulating layer, wherein the second metal layer forms a TFT substrate The drain and source, the semiconductor material layer is disposed between the drain and the gate.
  • the thickness of the first metal layer is less than or equal to the depth of the groove.
  • the difference between the thickness of the first metal layer and the depth of the groove ranges from 0 to 20 nm.
  • the step of disposing the groove on the base substrate comprises: applying a photoresist on the base substrate; etching the region of the substrate substrate to which the photoresist is not applied by a dry etching process or a wet etching process to form a groove.
  • the step of filling the recess into the metal material to form the first metal layer comprises: depositing a metal material on the groove by a magnetron sputtering process or a thermal evaporation process; immersing the substrate in the degumming solution to The photoresist applied to the base substrate is removed by degumming to form a first metal layer in the recess.
  • the step of filling the recess into the metal material to form the first metal layer comprises: immersing the base substrate in the degumming liquid to remove the photoresist applied on the base substrate by removing the glue; The printing process drops metal conductive ink into the grooves to form a first metal layer in the grooves.
  • a TFT substrate comprising: a substrate substrate provided with a groove; and a first metal layer disposed on the substrate substrate, wherein a metal layer is disposed in the recess, the first metal layer is a gate of the TFT substrate; an insulating layer disposed on the first metal layer and the base substrate; and a semiconductor material layer and a second metal layer sequentially disposed on the insulating layer,
  • the second metal layer forms a drain and a source of the TFT substrate, and the semiconductor material layer is disposed between the drain and the gate.
  • the thickness of the first metal layer is less than or equal to the depth of the groove.
  • the difference between the thickness of the first metal layer and the depth of the groove ranges from 0 to 20 nm.
  • another technical solution adopted by the present invention is to provide a liquid crystal display panel including the above TFT substrate.
  • the manufacturing method of the TFT substrate of the present invention includes: providing a groove in the substrate; filling the groove with a metal material to form the first metal layer; An insulating layer is disposed on the metal layer and the base substrate; and the semiconductor material layer and the second metal layer are sequentially disposed on the insulating layer.
  • the present invention can reduce the thickness of the TFT substrate by disposing the first metal layer in the base substrate, thereby facilitating the realization of the ultra-thin liquid crystal display panel.
  • the first metal layer is disposed in the base substrate, The thickness of the insulating layer in the corner region above the first metal layer is kept uniform, and is not easily broken by the driving voltage, thereby effectively improving the display quality of the liquid crystal display panel.
  • FIG. 1 is a schematic structural view of a TFT substrate of the prior art
  • FIG. 2 is a schematic structural view of a first embodiment of a TFT substrate of the present invention.
  • FIG. 3 is a schematic structural view of a second embodiment of a TFT substrate of the present invention.
  • FIG. 4 is a schematic flow chart of a method of manufacturing a TFT substrate of the present invention.
  • Figure 5 is a physical structure diagram corresponding to step S101 in Figure 4.
  • FIG. 6 is a schematic flow chart of a sub-step of step S101 in FIG. 4;
  • Figure 7 is a physical structure diagram corresponding to step S102 in Figure 4.
  • FIG. 8 is a schematic flow chart of a first embodiment of the sub-step of step S102 in FIG. 4;
  • FIG. 9 is a schematic flow chart of a second embodiment of the sub-step of step S102 in FIG. 4;
  • Figure 10 is a physical structure diagram corresponding to step 103 in Figure 4.
  • Figure 11 is a flow chart showing the first embodiment of the sub-step of step S104;
  • Figure 12 is a physical structure diagram corresponding to step S1041 in Figure 11;
  • Figure 13 is a physical structure diagram corresponding to step S1042 in Figure 11;
  • step S104 in FIG. 4 is a schematic flow chart of a second embodiment of the sub-step of step S104 in FIG. 4;
  • Figure 15 is a physical structure diagram corresponding to step S2041 in Figure 14;
  • Fig. 16 is a view showing a physical structure corresponding to step S2042 of Fig. 14.
  • the present invention discloses a liquid crystal display panel including a CF substrate (color filter array substrate) and a TFT substrate (thin film transistor array substrate) which are spaced apart from each other.
  • FIG. 2 is a schematic structural view of a first embodiment of a TFT substrate of the present invention.
  • the TFT substrate includes a base substrate 21, a first metal layer 22, an insulating layer 23, a semiconductor material layer 24, and a second metal layer 25.
  • the base substrate 21 is provided with a recess 211, and the first metal layer 22 is disposed in the recess 211.
  • the first metal layer 22 is the gate of the TFT substrate.
  • the thickness of the first metal layer 22 is less than or equal to the depth of the groove 211.
  • the difference between the thickness of the first metal layer 22 and the depth of the groove 211 ranges from 0 to 20 nm (nanometer). That is, the thickness of the first metal layer 22 is smaller than the depth of the groove 211 in the range of 0-20 nm.
  • the present invention does not limit that the thickness of the first metal layer 22 is less than the depth of the groove 111 is 0-20 nm.
  • the thickness and the groove of the first metal layer 22 may be specifically set according to actual needs. The specific value of the depth of 211.
  • the present invention does not limit the thickness of the first metal layer 22 to be less than or equal to the depth of the groove.
  • the thickness of the first metal layer 22 may be greater than the depth of the groove 211, preferably, the first The thickness of the metal layer 22 is greater than the depth of the groove 211 in the range of 0-20 nm.
  • the specific value of the thickness of the first metal layer 22 and the depth of the groove 211 may be specifically set according to actual needs.
  • the insulating layer 23 is disposed on the first metal layer 22 and the base substrate 21.
  • the thickness of the insulating layer 23 ranges from 5 to 500. Nm.
  • a layer of semiconductor material 24 is disposed on the insulating layer 13.
  • the thickness of the semiconductor material layer 24 ranges from 10 to 200 nm.
  • the second metal layer 25 is disposed on the semiconductor material layer 24.
  • the second metal layer 25 forms a drain and a source of the TFT substrate, and the semiconductor material 24 is disposed between the drain and the gate.
  • the thickness of the second metal layer 25 ranges from 100 to 300. Nm.
  • the thickness of the TFT substrate is reduced, which solves the problem that the edge position caused by the first raised metal layer is difficult to deposit the insulating layer, and can be reduced at the same time.
  • the thickness of the insulating layer increases the capacitance between the first metal layer and the second metal layer, reduces the driving voltage of the TFT substrate, and improves the display quality of the liquid crystal display panel.
  • FIG. 3 is a schematic structural view of a second embodiment of the TFT substrate of the present invention.
  • the main difference between the TFT substrate shown in FIG. 3 and the TFT substrate shown in FIG. 2 is:
  • the second metal layer 35 is disposed on the insulating layer 33, and the semiconductor material layer 34 is disposed on the second metal layer 35, and the thickness of the first metal layer 32 is greater than the depth of the recess 311.
  • the thickness of the first metal layer 32 is greater than the depth of the recess 311, a portion of the first metal layer 32 may be exposed on the base substrate 31 in order to avoid the corners of the raised first metal layer 32.
  • the problem that the insulating layer 33 is not easily deposited is so that the convex corner portion of the first metal layer 32 is cut away in the present embodiment, that is, the convex portion of the first metal layer 32 is set at an oblique angle, which facilitates deposition. Insulation.
  • the corner portion of the first metal layer 32 may be directly disposed at an oblique angle without providing a groove, so that the insulating layer can be conveniently deposited.
  • FIG. 4 is a flow chart showing the method of manufacturing the TFT substrate of the present invention. The method includes the following steps:
  • Step S101 A groove 211 is provided on the base substrate 21.
  • step S101 The physical map corresponding to step S101 is as shown in FIG. 5, and the groove 211 is directly disposed on the base substrate 21.
  • the specific manufacturing process is as shown in FIG. 6, and the step S101 includes the following sub-steps:
  • Step S1011 Applying a photoresist on the base substrate 21.
  • the photoresist can protect the base substrate 21 from being photoetched.
  • Step S1012 etching the region of the substrate substrate 21 to which the photoresist is not applied by a dry etching process or a wet etching process to form the recess 211.
  • step S1012 the dry etching process or the wet etching process may etch the grooves 211 of the vertical angle.
  • Step S102 filling the recess 211 with a metal material to form the first metal layer 22.
  • the first metal layer 22 serves as a gate of the TFT substrate.
  • Step S102 includes the following sub-steps:
  • Step S1021 depositing a metal material on the groove 211 by a magnetron sputtering process or a thermal evaporation process.
  • Step S1022 The base substrate 21 is immersed in the degumming liquid to remove the photoresist applied on the base substrate 21 by the degumming liquid, thereby forming the first metal layer 22 in the recess 211.
  • step S102 further includes the following sub-steps:
  • Step S2021 The base substrate 21 is immersed in the degumming liquid to remove the photoresist applied on the base substrate 21 by the degumming liquid.
  • Step S2022 Metal conductive ink is dropped into the groove 211 by an inkjet printing process to form the first metal layer 22 in the groove 211.
  • the thickness of the first metal layer 22 is less than or equal to the depth of the groove 211.
  • the difference between the thickness of the first metal layer 22 and the depth of the groove 211 ranges from 0 to 20 nm (nanometer). That is, the thickness of the first metal layer 22 is smaller than the depth of the groove 211 in the range of 0-20 nm. It should be understood that the present invention does not limit that the thickness of the first metal layer 22 is less than the depth of the groove 111 is 0-20 nm, and the specific value of the thickness of the first metal layer 22 and the depth of the groove 211 may be specifically set according to actual needs. .
  • the thickness of the first metal layer 22 may be greater than the depth of the groove 211.
  • the thickness of the first metal layer 22 is greater than the depth of the groove 211 by 0-20 nm, depending on the actual A specific value of the thickness of the first metal layer 22 and the depth of the groove 211 is required to be specifically set.
  • Step S103 An insulating layer 23 is provided on the first metal layer 22 and the base substrate 21.
  • the physical map corresponding to step S103 is as shown in FIG. 10, and an insulating layer 23 is directly formed on the first metal layer 22 and the base substrate 21.
  • step S103 by a magnetron sputtering process, a plasma enhanced chemical vapor deposition process (PECVD, Plasma) Enhanced Chemical Vapor Deposition ), Atomic Layer Deposition Process (ALD, Atomic Layer) Deposition) or a solution process forms an insulating layer 23 having a thickness ranging from 5 to 500 nm on the first metal layer 22 and the base substrate 21.
  • PECVD plasma enhanced chemical vapor deposition process
  • ALD Atomic Layer Deposition Process
  • ALD Atomic Layer Deposition Process
  • solution process forms an insulating layer 23 having a thickness ranging from 5 to 500 nm on the first metal layer 22 and the base substrate 21.
  • Step S104 The semiconductor material layer 24 and the second metal layer 25 are sequentially disposed on the insulating layer 23.
  • the second metal layer 25 forms a drain and a source of the TFT substrate, and the semiconductor material layer 24 is disposed between the drain and the gate.
  • the step S104 includes the following sub-steps:
  • Step S1041 A semiconductor material layer 24 is provided on the insulating layer 23.
  • the physical map corresponding to step S1041 is as shown in FIG. 12, and a semiconductor material layer 24 is directly formed on the insulating layer 23.
  • a thickness ranging from 10 to 200 is formed on the insulating layer 23 by a magnetron sputtering process, a plasma enhanced chemical vapor deposition process, an atomic layer deposition process, or a solution process.
  • Step S1042 A second metal layer 25 is disposed on the semiconductor material layer 24.
  • step S1042 The physical map corresponding to step S1042 is as shown in FIG. 13, and the second metal layer 25 is directly formed on the semiconductor material layer 24.
  • a thickness ranging from 100 to 300 is formed on the semiconductor material layer 24 by a magnetron sputtering process, an atomic layer deposition process, or a solution process.
  • step S104 further includes the following sub-steps:
  • Step S2041 A second metal layer 35 is provided on the insulating layer 33.
  • step S2041 The physical map corresponding to step S2041 is as shown in FIG. 15, and the second metal layer 35 is directly formed on the insulating layer 33.
  • step S2041 a thickness ranging from 100 to 300 is formed on the insulating layer 33 by a magnetron sputtering process, an atomic layer deposition process, or a solution process.
  • the second metal layer 35 of nm.
  • Step S2042 A semiconductor material layer 34 is provided on the second metal layer 35.
  • step S2042 The physical map corresponding to step S2042 is as shown in FIG. 16, and the semiconductor material layer 34 is directly formed on the second metal layer 35.
  • a thickness ranging from 10 to 200 is formed on the second metal layer 35 by a magnetron sputtering process, a plasma enhanced chemical vapor deposition process, an atomic layer deposition process, or a solution process.
  • the thickness of the TFT substrate is reduced, which solves the problem that the edge position caused by the first raised metal layer is difficult to deposit the insulating layer, and can be increased at the same time.
  • the capacitance between the large first metal layer and the second metal layer reduces the driving voltage of the TFT substrate and improves the display quality of the liquid crystal display panel.
  • the method for fabricating a TFT substrate of the present invention includes: providing a recess in the base substrate; filling the recess with a metal material to form a first metal layer; and providing an insulating layer on the first metal layer and the base substrate; A semiconductor material layer and a second metal layer are sequentially disposed on the insulating layer.
  • the present invention can reduce the thickness of the TFT substrate by disposing the first metal layer in the base substrate, thereby facilitating the realization of the ultra-thin liquid crystal display panel.
  • the first metal layer is disposed in the base substrate, The thickness of the insulating layer in the corner region above the first metal layer is kept uniform, and is not easily broken by the driving voltage, thereby effectively improving the display quality of the liquid crystal display panel.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
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Abstract

一种TFT基板及其制造方法，该方法包括：在衬底基板（21）设置凹槽（211）；在凹槽中填充金属材料以形成第一金属层（22），其中第一金属层作为TFT基板的栅极；在第一金属层和衬底基板上设置绝缘层（23）；在绝缘层上依次设置半导体材料层（24）和第二金属层（25），其中，第二金属层形成TFT基板的漏极和源极，半导体材料层间隔设置于漏极和栅极之间。通过该方式，能够降低TFT基板的厚度，有利于实现超薄化液晶显示面板，且能够提升液晶显示面板的显示品质。

Description

液晶显示面板、TFT基板及其制造方法
【技术领域】
本发明涉及液晶技术领域，特别是涉及一种液晶显示面板、TFT基板及其制造方法。
【背景技术】
液晶显示面板是目前使用最广泛的一种平板显示面板，其已经逐渐成为各种电子设备如移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕所广泛应用且具有高分辨率彩色屏幕的显示面板。随着液晶显示面板技术的发展进步，人们对液晶显示面板的显示品质、外观设计、低成本和高穿透率等提出了更高的要求。
而低功耗及超薄的液晶显示面板也成为显示技术领域的潮流。如图1所示，目前显示领域中的液晶显示面板的TFT基板（薄膜晶体管阵列基板）包括衬底基板11、设置在衬底基板11上的第一金属层12、设置在第一金属层12上的绝缘层13、设置在绝缘层13上的半导体材料层14以及设置在半导体材料层14上的第二金属层15。由于第一金属层12设置在衬底基板11上以及绝缘层13设置在第一金属层12上，使得TFT基板的厚度相对较高，不利于实现超薄化液晶显示面板；且第一金属层12边角区域的绝缘层13的膜质较差，易于被驱动电压击穿，也会影响液晶显示面板的显示品质。
综上所述，有必要提供一种液晶显示面板、TFT基板及其制造方法以解决上述问题。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示面板、TFT基板及其制造方法，能够实现超薄化液晶显示面板，提升液晶显示面板的显示品质。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种TFT基板的制造方法，该方法包括：在衬底基板设置凹槽；在凹槽中填充金属材料以形成第一金属层，其中第一金属层作为TFT基板的栅极；在第一金属层和衬底基板上设置绝缘层；在绝缘层上依次设置半导体材料层和第二金属层，其中，第二金属层形成TFT基板的漏极和源极，半导体材料层设置于漏极和栅极之间。
其中，第一金属层的厚度小于或等于凹槽的深度。
其中，第一金属层的厚度与凹槽的深度的差值范围为0-20nm。
其中，在衬底基板设置凹槽的步骤包括：在衬底基板上涂抹光刻胶；利用干刻工艺或湿刻工艺刻蚀衬底基板中未涂抹光刻胶的区域，以形成凹槽。
其中，在凹槽中填充金属材料以形成第一金属层的步骤包括：通过磁控溅射工艺或者热蒸镀工艺在凹槽上沉积金属材料；将衬底基板浸泡在去胶液中，以通过去胶液去除涂抹在衬底基板上的光刻胶，从而在凹槽中形成第一金属层。
其中，在凹槽中填充金属材料以形成第一金属层的步骤包括：将衬底基板浸泡在去胶液中，以通过去胶液去除涂抹在衬底基板上的光刻胶；通过喷墨打印工艺在凹槽中滴入金属导电墨水，以在凹槽中形成第一金属层。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种TFT基板，其包括：衬底基板，设置有凹槽；设置在衬底基板上的第一金属层，其中，第一金属层设置在凹槽中，第一金属层为TFT基板的栅极；设置在第一金属层和衬底基板上的绝缘层；依次设置在绝缘层上的半导体材料层和第二金属层，其中，第二金属层形成TFT基板的漏极和源极，半导体材料层设置于漏极和栅极之间。
其中，第一金属层的厚度小于或等于凹槽的深度。
其中，第一金属层的厚度与凹槽的深度的差值范围为0-20nm。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板，该液晶显示面板包括上述TFT基板。
本发明的有益效果是：区别于现有技术的情况，本发明的TFT基板的制造方法包括：在衬底基板设置凹槽；在凹槽中填充金属材料以形成第一金属层；在第一金属层和衬底基板上设置绝缘层；在绝缘层上依次设置半导体材料层和第二金属层。通过上述方式，本发明通过将第一金属层设置在衬底基板内，能够降低TFT基板的厚度，有利于实现超薄化液晶显示面板；同时，由于第一金属层设置在衬底基板内，第一金属层上方的边角区域的绝缘层的厚度保持一致，不容易被驱动电压击穿，有效提升液晶显示面板的显示品质。
【附图说明】
图1是现有技术TFT基板的结构示意图；
图2是本发明TFT基板的第一实施例的结构示意图；
图3是本发明TFT基板的第二实施例的结构示意图；
图4是本发明TFT基板的制造方法的流程示意图；
图5是图4中步骤S101所对应的实物结构图；
图6是图4中步骤S101的子步骤流程示意图；
图7是图4中步骤S102所对应的实物结构图；
图8是图4中步骤S102的子步骤的第一实施例的流程示意图；
图9是图4中步骤S102的子步骤的第二实施例的流程示意图；
图10是图4中步骤103所对应的实物结构图；
图11是步骤S104的子步骤的第一实施例的流程示意图；
图12是图11中步骤S1041所对应的实物结构图；
图13是图11中步骤S1042所对应的实物结构图；
图14是图4中步骤S104的子步骤的第二实施例的流程示意图；
图15是图14中步骤S2041所对应的实物结构图；
图16是图14中步骤S2042所对应的实物结构图。
【具体实施方式】
为了使本发明所要解决的技术问题、技术方案及有益效果更加清楚、明白，以下结合附图和实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明公开一种液晶显示面板，该液晶显示面板包括间隔设置的CF基板（彩色滤光阵列基板）和TFT基板（薄膜晶体管阵列基板）。如图2所示，图2是本发明TFT基板的第一实施例的结构示意图。TFT基板包括衬底基板21、第一金属层22、绝缘层23、半导体材料层24和第二金属层25。
其中，衬底基板21设置有凹槽211，第一金属层22设置在凹槽211中。第一金属层22为TFT基板的栅极。在本实施例中，第一金属层22的厚度小于或等于凹槽211的深度，优选地，第一金属层22的厚度与凹槽211的深度的差值范围为0-20nm（纳米），即第一金属层22的厚度小于凹槽211的深度的范围为0-20nm。应理解，本发明并不限定第一金属层22的厚度小于凹槽111的深度的范围为0-20nm，在其他实施例中，可以根据实际需要特定设置第一金属层22的厚度与凹槽211的深度的具体数值。
在应理解，本发明并不限定第一金属层22的厚度小于或等于凹槽的深度，在其他实施例中，第一金属层22的厚度可以大于凹槽211的深度，优选地，第一金属层22的厚度大于凹槽211的深度的范围为0-20nm，当然，可以根据实际需要特定设置第一金属层22的厚度与凹槽211的深度的具体数值。
绝缘层23设置在第一金属层22和衬底基板21上。在本实施例中，绝缘层23的厚度范围为5-500 nm。
半导体材料层24设置在绝缘层13上。在本实施例中，半导体材料层24的厚度范围为10-200 nm。
第二金属层25设置在半导体材料层24上。其中，第二金属层25形成TFT基板的漏极和源极，半导体材料24设置于漏极和栅极之间。在本实施例中，第二金属层25的厚度范围为100-300 nm。
本实施例通过将第一金属层设置在衬底基板内，使得TFT基板的厚度降低，解决了传统凸起的第一金属层所带来的边角位置不易沉积绝缘层的问题，同时可以降低绝缘层的厚度而增大第一金属层与第二金属层之间电容，降低TFT基板的驱动电压，提升液晶显示面板的显示品质。
如图3所示，图3是本发明TFT基板的第二实施例的结构示意图。图3中所示的TFT基板与图2中所示的TFT基板主要区别在于：
第二金属层35设置在绝缘层33上，半导体材料层34设置在第二金属层35上，且第一金属层32的厚度大于凹槽311的深度。
应理解，由于第一金属层32的厚度大于凹槽311的深度，因此在衬底基板31上会露出部分第一金属层32，为了避免凸起的第一金属层32所带来的边角位置不易沉积绝缘层33的问题，因此在本实施例中将第一金属层32中凸起的边角部分切除，即将第一金属层32中凸起的部分设置成倾斜角度，这样能够方便沉积绝缘层。当然，在其他实施例中，可以不设置凹槽，直接将第一金属层32边角部分设置成倾斜角度，这样能够方便沉积绝缘层。
为了更清楚地理解本发明，以下对TFT基板制程进行详细说明，如图4所示，图4是本发明TFT基板的制造方法的流程示意图。该方法包括以下步骤：
步骤S101：在衬底基板21设置凹槽211。
步骤S101所对应的实物图如图5所示，直接在衬底基板21设置凹槽211，具体制程步骤如图6所示，步骤S101包括以下子步骤：
步骤S1011：在衬底基板21上涂抹光刻胶。其中，光刻胶可以保护衬底基板21不被光刻蚀。
步骤S1012：利用干刻工艺或湿刻工艺刻蚀衬底基板21中未涂抹光刻胶的区域，以形成凹槽211。
应理解，在步骤S1012中，干刻工艺或湿刻工艺可以蚀刻出垂直角度的凹槽211。
步骤S102：在凹槽211中填充金属材料以形成第一金属层22。其中，第一金属层22作为TFT基板的栅极。
步骤S102所对应的实物图如图7所示，将金属材料填充在凹槽211中从而形成第一金属层22，具体制程步骤如图8所示，步骤S102包括以下子步骤：
步骤S1021：通过磁控溅射工艺或者热蒸镀工艺在凹槽211上沉积金属材料。
步骤S1022：将衬底基板21浸泡在去胶液中，以通过去胶液去除涂抹在衬底基板21上的光刻胶，从而在凹槽211中形成第一金属层22。
应理解，为了完成如图7所示的结构，在其他实施例中，如图9所示，步骤S102还包括以下子步骤：
步骤S2021：将衬底基板21浸泡在去胶液中，以通过去胶液去除涂抹在衬底基板21上的光刻胶。
步骤S2022：通过喷墨打印工艺在凹槽211中滴入金属导电墨水，以在凹槽211中形成第一金属层22。
在本实施例中，第一金属层22的厚度小于或等于凹槽211的深度，优选地，第一金属层22的厚度与凹槽211的深度的差值范围为0-20nm（纳米），即第一金属层22的厚度小于凹槽211的深度的范围为0-20nm。应理解，本发明并不限定第一金属层22的厚度小于凹槽111的深度的范围为0-20nm，可以根据实际需要特定设置第一金属层22的厚度与凹槽211的深度的具体数值。当然，在其他实施例中，第一金属层22的厚度可以大于凹槽211的深度，优选地，第一金属层22的厚度大于凹槽211的深度的范围为0-20nm，具体可以根据实际需要特定设置第一金属层22的厚度与凹槽211的深度的具体数值。
步骤S103：在第一金属层22和衬底基板21上设置绝缘层23。
步骤S103所对应的实物图如图10所示，直接在第一金属层22和衬底基板21上生成绝缘层23。
在步骤S103中，通过磁控溅射工艺、等离子体增强化学气相沉积工艺（PECVD ， Plasma Enhanced Chemical Vapor Deposition ）、原子层沉积工艺（ALD，Atomic Layer Deposition）或者溶液法工艺在第一金属层22和衬底基板21形成厚度范围为5-500 nm的绝缘层23。
步骤S104：在绝缘层23上依次设置半导体材料层24和第二金属层25。其中，第二金属层25形成TFT基板的漏极和源极，半导体材料层24设置于漏极和栅极之间。
如图11所示，该步骤S104包括以下子步骤：
步骤S1041：在绝缘层23上设置半导体材料层24。
步骤S1041所对应的实物图如图12所示，直接在绝缘层23上生成半导体材料层24。
在步骤S1041中，通过磁控溅射工艺、等离子体增强化学气相沉积工艺、原子层沉积工艺或者溶液法工艺在绝缘层23上形成厚度范围为10-200 nm的半导体材料层24。
步骤S1042：在半导体材料层24上设置第二金属层25。
步骤S1042所对应的实物图如图13所示，直接在半导体材料层24上生成第二金属层25。
在步骤S1042中，通过磁控溅射工艺、原子层沉积工艺或者溶液法工艺在半导体材料层24上形成厚度范围为100-300 nm的第二金属层25。
应理解，在其他实施例中，步骤S104还包括以下子步骤：
步骤S2041：在绝缘层33上设置第二金属层35。
步骤S2041所对应的实物图如图15所示，直接在绝缘层33上生成第二金属层35。
在步骤S2041中，通过磁控溅射工艺、原子层沉积工艺或者溶液法工艺在绝缘层33上形成厚度范围为100-300 nm的第二金属层35。
步骤S2042：在第二金属层35上设置半导体材料层34。
步骤S2042所对应的实物图如图16所示，直接在第二金属层35上生成半导体材料层34。
在步骤S2042中，通过磁控溅射工艺、等离子体增强化学气相沉积工艺、原子层沉积工艺或者溶液法工艺在第二金属层35上形成厚度范围为10-200 nm的半导体材料层34。
本实施例通过将第一金属层设置在衬底基板内，使得TFT基板的厚度降低，解决了传统凸起的第一金属层所带来的边角位置不易沉积绝缘层的问题，同时能够增大第一金属层与第二金属层之间电容，降低TFT基板的驱动电压，提升液晶显示面板的显示品质。
综上，本发明的TFT基板的制造方法包括：在衬底基板设置凹槽；在凹槽中填充金属材料以形成第一金属层；在第一金属层和衬底基板上设置绝缘层；在绝缘层上依次设置半导体材料层和第二金属层。通过上述方式，本发明通过将第一金属层设置在衬底基板内，能够降低TFT基板的厚度，有利于实现超薄化液晶显示面板；同时，由于第一金属层设置在衬底基板内，第一金属层上方的边角区域的绝缘层的厚度保持一致，不容易被驱动电压击穿，有效提升液晶显示面板的显示品质。
以上参照附图说明了本发明的优选实施例，并非因此局限本发明的权利范围。本领域技术人员不脱离本发明的范围和实质内所作的任何修改、等同替换和改进，均应在本发明的权利范围之内。

Claims (10)

  1. 一种TFT基板的制造方法，其中，所述方法包括：
    在衬底基板设置凹槽；
    在所述凹槽中填充金属材料以形成第一金属层，其中所述第一金属层作为所述TFT基板的栅极；
    在所述第一金属层和所述衬底基板上设置绝缘层；
    在所述绝缘层上依次设置半导体材料层和第二金属层，其中，所述第二金属层形成所述TFT基板的漏极和源极，所述半导体材料层设置于所述漏极和所述栅极之间。
  2. 根据权利要求1所述的方法，其中，所述第一金属层的厚度小于或等于所述凹槽的深度。
  3. 根据权利要求2所述的方法，其中，所述第一金属层的厚度与所述凹槽的深度的差值范围为0-20nm。
  4. 根据权利要求1所述的方法，其中，所述在衬底基板设置凹槽的步骤包括：
    在所述衬底基板上涂抹光刻胶；
    利用干刻工艺或湿刻工艺刻蚀所述衬底基板中未涂抹所述光刻胶的区域，以形成所述凹槽。
  5. 根据权利要求4所述的方法，其中，在所述凹槽中填充金属材料以形成第一金属层的步骤包括：
    通过磁控溅射工艺或者热蒸镀工艺在所述凹槽上沉积所述金属材料；
    将所述衬底基板浸泡在去胶液中，以通过所述去胶液去除涂抹在所述衬底基板上的光刻胶，从而在所述凹槽中形成所述第一金属层。
  6. 根据权利要求4所述的方法，其中，在所述凹槽中填充金属材料以形成第一金属层的步骤包括：
    将所述衬底基板浸泡在去胶液中，以通过所述去胶液去除涂抹在所述衬底基板上的光刻胶；
    通过喷墨打印工艺在所述凹槽中滴入金属导电墨水，以在所述凹槽中形成所述第一金属层。
  7. 一种TFT基板，其中，所述TFT基板包括：
    衬底基板，设置有凹槽；
    设置在所述衬底基板上的第一金属层，其中，所述第一金属层设置在所述凹槽中，所述第一金属层为所述TFT基板的栅极；
    设置在所述第一金属层和所述衬底基板上的绝缘层；
    依次设置在所述绝缘层上的半导体材料层和第二金属层，其中，所述第二金属层形成所述TFT基板的漏极和源极，半导体材料层设置于漏极和栅极之间。
  8. 根据权利要求7所述的TFT基板，其中，所述第一金属层的厚度小于或等于所述凹槽的深度。
  9. 根据权利要求8所述的TFT基板，其中，所述第一金属层的厚度与所述凹槽的深度的差值范围为0-20nm。
  10. 一种液晶显示面板，其中，所述液晶显示面板包括如权利要求7所述的TFT基板。
PCT/CN2016/085465 2016-01-29 2016-06-12 液晶显示面板、tft基板及其制造方法 WO2017128597A1 (zh)

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