WO2017063207A1 - 阵列基板及其制造方法 - Google Patents

阵列基板及其制造方法 Download PDF

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Publication number
WO2017063207A1
WO2017063207A1 PCT/CN2015/092552 CN2015092552W WO2017063207A1 WO 2017063207 A1 WO2017063207 A1 WO 2017063207A1 CN 2015092552 W CN2015092552 W CN 2015092552W WO 2017063207 A1 WO2017063207 A1 WO 2017063207A1
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Prior art keywords
gate
insulating layer
layer
forming
drain
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PCT/CN2015/092552
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English (en)
French (fr)
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苏长义
徐洪远
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深圳市华星光电技术有限公司
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Priority to US14/893,523 priority Critical patent/US20170104033A1/en
Publication of WO2017063207A1 publication Critical patent/WO2017063207A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • the present invention relates to the field of display, and in particular to an array substrate and a method of fabricating the same.
  • the wearable device is a new field of display development, but the current display is a glass substrate display, which cannot be effectively bent. Therefore, it is necessary to develop a flexible display that requires a completely different substrate than the glass substrate, such as a plastic base plate.
  • materials such as amorphous silicon, silicon nitride, and silicon oxide which were originally used cannot be used as materials for flexible displays due to problems such as mobility, hardness, curvature, and processing techniques.
  • the use of organic materials as a semiconductor layer and an insulating layer can be effectively improved, and a new display is developed: a flexible display.
  • the technical problem to be solved by the present invention is to provide an array substrate which can be applied to a flexible display and a method of manufacturing the same.
  • a technical solution adopted by the present invention is to provide a method for fabricating an array substrate, comprising forming a top gate type thin film transistor, specifically comprising: forming a source and a drain on a substrate; forming a connection source a data line and a transfer pad connected to the drain; an organic semiconductor layer, a first insulating layer and a gate are sequentially stacked on the source and the drain; and the first insulating is performed by a dry etching technique using the gate as a hard film
  • the layers and the semiconductor layers are patterned one by one.
  • the manufacturing method further includes: forming a scan line connecting the gate electrodes; and forming a transparent electrode layer connecting the transfer pads.
  • the step of forming a scan line connecting the gates includes: forming a second insulating layer above the gate, the second insulating layer having a first via corresponding to the gate and a second via corresponding to the transfer pad; A scan line is formed on the second insulating layer, and the scan line is electrically connected to the gate through the first via.
  • the step of forming a transparent electrode layer connecting the transmission pads comprises: forming a third insulating layer over the second insulating layer, the third insulating layer having a third via formed in the second via; and the third insulating layer A transparent electrode layer is formed thereon, and the transparent electrode layer is electrically connected to the transfer pad through the second via hole.
  • the etching technique is dry etching.
  • the step of sequentially forming an organic semiconductor layer, a first insulating layer and a gate on the source and the drain includes: depositing an organic semiconductor layer on the source and the drain; and depositing a first insulating layer on the organic semiconductor layer; A gate metal layer is deposited over the first insulating layer, and a gate metal layer is patterned using a gate mask process to form a gate.
  • another technical solution adopted by the present invention is to provide a method for fabricating an array substrate, comprising forming a top gate type thin film transistor, specifically comprising: forming a source and a drain on a substrate; The organic semiconductor layer, the first insulating layer and the gate are sequentially stacked on the drain; the first insulating layer and the semiconductor layer are patterned one by one by an etching technique using a gate as a hard film.
  • the manufacturing method further comprises: forming a data line connecting the source and a transfer pad connecting the drain.
  • the manufacturing method further includes: forming a scan line connecting the gate electrodes; and forming a transparent electrode layer connecting the transfer pads.
  • the step of forming a scan line connecting the gates includes: forming a second insulating layer above the gate, the second insulating layer having a first via corresponding to the gate and a second via corresponding to the transfer pad; A scan line is formed on the second insulating layer, and the scan line is electrically connected to the gate through the first via.
  • the step of forming a transparent electrode layer connecting the transmission pads comprises: forming a third insulating layer over the second insulating layer, the third insulating layer having a third via formed in the second via; and the third insulating layer A transparent electrode layer is formed thereon, and the transparent electrode layer is electrically connected to the transfer pad through the second via hole.
  • the etching technique is dry etching.
  • the step of sequentially forming an organic semiconductor layer, a first insulating layer and a gate on the source and the drain includes: depositing an organic semiconductor layer on the source and the drain; and depositing a first insulating layer on the organic semiconductor layer; A gate metal layer is deposited over the first insulating layer, and a gate metal layer is patterned using a gate mask process to form a gate.
  • the present invention adopts a technical solution to provide an array substrate including: a substrate and a top gate type thin film transistor formed on the substrate, the thin film transistor including a source, a drain, and a gate; An organic semiconductor layer and an insulating layer, the source and the drain are disposed on the substrate in the same layer, the organic semiconductor layer, the insulating layer and the gate are sequentially stacked on the source and the drain, and the patterning of the organic semiconductor layer and the insulating layer is performed by using a gate Extremely hard film obtained by one etching.
  • the substrate is a flexible substrate.
  • the array substrate further includes a data line, a scan line, a transmission pad and a transparent electrode layer, the scan line is connected to the gate, the data line is connected to the source, the transmission pad is connected to the drain and the transparent electrode layer, and the data line and the transmission pad are different from the source.
  • the same process of the pole/drain is made, and the data line/transfer pad has better etching resistance than the source/drain.
  • the invention has the beneficial effects that the manufacturing method of the array substrate of the present invention obtains a top gate type thin film transistor compared with the prior art, and the first insulating layer and the organic semiconductor layer are sequentially patterned by using the gate as a hard film.
  • the process is simple and can avoid damage to the organic material during the process of patterning the organic semiconductor layer.
  • FIG. 1 is a flow chart showing a method of manufacturing an array substrate according to a first embodiment of the present invention
  • FIG. 2 is a flow chart showing lamination of an organic semiconductor layer, an insulating layer, and a gate electrode in the manufacturing method shown in FIG. 1;
  • FIG. 3 is a flow chart showing a method of manufacturing an array substrate according to a second embodiment of the present invention.
  • FIG. 4A-4F are schematic structural views of an array substrate in the manufacturing process of the manufacturing method shown in FIG. 3;
  • FIG. 5 is a schematic structural view of an array substrate prepared by the manufacturing method shown in FIG. 3.
  • FIG. 5 is a schematic structural view of an array substrate prepared by the manufacturing method shown in FIG. 3.
  • a method for fabricating an array substrate according to a first embodiment of the present invention includes forming a top gate type thin film transistor, and the steps of forming a top gate type thin film transistor specifically include:
  • the substrate is selected from a substrate having good bending properties, that is, being easily bent, so that the manufacturing method of the array substrate of the present invention is applied to a flexible display.
  • a substrate which can be used for a bending performance in a flexible display includes a plastic substrate or the like.
  • the present invention can also be applied to a non-bendable display, and the substrate can be a glass substrate having poor bending properties.
  • the step of forming a source and a drain on the substrate specifically includes depositing a first metal layer on the substrate and patterning the first metal layer by a first mask process to form spaced apart source and drain electrodes.
  • This step specifically includes:
  • This step can also be understood as depositing an organic semiconductor layer covering the source and the drain on the substrate.
  • the insulating layer used in the flexible display is made of amorphous silicon, silicon nitride, silicon oxide or the like, there are problems in mobility, hardness, curvature, and processing techniques. Therefore, preferably, the first insulating layer is an organic material layer.
  • the gate metal layer is the second metal layer; the gate mask process is the second mask process.
  • the etching technique in this step is a dry etching technique.
  • the gate is directly used as a hard film, and the etching rate difference between the metal and the organic material is dry etched to complete the patterning.
  • the gate is a metal layer that resists dry etching, while the first insulating layer and the organic semiconductor layer are not resistant to dry etching; when the gate is used as a hard film, the first insulating layer is located underneath The organic semiconductor layer is retained, and the first insulating layer and the organic semiconductor layer of the other portion without the gate protection are etched away.
  • the gate electrode, the first insulating layer and the semiconductor layer completely overlap in their lamination direction.
  • the top gate type thin film transistor is completed.
  • the thin film transistor is required to establish an electrical connection with an external circuit.
  • the method for manufacturing the array substrate according to the second embodiment of the present invention which specifically includes:
  • the substrate is selected from a substrate having good bending properties, that is, being easily bent, so that the manufacturing method of the array substrate of the present invention is applied to a flexible display.
  • a substrate which can be used for a bending performance in a flexible display includes a plastic substrate or the like.
  • the present invention can also be applied to a non-bendable display, and the substrate can be a glass substrate having poor bending properties.
  • the step of forming a source and a drain on the substrate specifically includes depositing a first metal layer on the substrate and patterning the first metal layer by a first mask process to form spaced apart source and drain electrodes.
  • the first metal layer is made of a material having high electrical conductivity.
  • FIG. 4A is a front view showing the source electrode 111 and the drain electrode 112 obtained after the first mask process is performed on the first metal layer deposited on the substrate 10.
  • a second metal layer is deposited on the substrate and the second metal layer is patterned by a second mask process, and patterned to form a data line connecting the source and a transfer pad connected to the drain.
  • the second metal layer is made of a material different from the first metal layer, and the second metal layer is a material having better etching resistance.
  • FIG. 4B is a front view of the data line 12 connecting the source 11 and the transmission pad 13 connected to the drain 112 obtained after performing the second mask process on the second metal layer deposited on the substrate 10. .
  • This step specifically includes:
  • the gate metal layer deposited during the formation of the gate in this step is the third metal layer; the gate mask process is the third mask process.
  • the gate layer is used as a hard film, and the insulating layer and the semiconductor layer are patterned one by one by an etching technique.
  • the etching technique in this step is a dry etching technique.
  • the gate is directly used as a hard film, and the etching rate difference between the metal and the organic material is dry patterned to complete the patterning.
  • the gate is a metal layer that resists dry etching, while the first insulating layer and the organic semiconductor layer are not resistant to dry etching; when the gate is used as a hard film, the first insulating layer is located underneath The organic semiconductor layer is retained, and the first insulating layer and the organic semiconductor layer of the other portion without the gate protection are etched away.
  • the gate electrode, the first insulating layer and the semiconductor layer completely overlap in their lamination direction.
  • the data line 12 and the transfer pad 13 are made of a material having better etching resistance, etching is prevented during the patterning of the first insulating layer and the organic semiconductor layer.
  • FIG. 4C shows the first insulating layer 114 and the organic semiconductor layer obtained by patterning the first insulating layer and the organic semiconductor layer by dry etching through the gate electrode 115 as a hard film. 113.
  • the step specifically includes: forming a second insulating layer above the gate, the second insulating layer having a first via corresponding to the gate and a second via corresponding to the transfer pad; forming a scan line on the second insulating layer The scan line is electrically connected to the gate through the first via.
  • the second insulating layer is formed by depositing a layer of insulating material over the gate and patterning the layer of insulating material through a fourth mask process. After patterning, a second insulating layer 16 having a first via 161 communicating with the gate 115 and a second via 162 communicating with the transfer pad 13 as shown in FIG. 4D is obtained.
  • the process of forming a scan line on the second insulating layer is specifically: depositing a fourth metal layer over the second insulating layer, and patterning the fourth metal layer by a fifth mask process. After patterning, a scan line 14 connecting the gate electrodes 115 as shown in FIG. 4E is obtained.
  • the step specifically includes: forming a third insulating layer over the second insulating layer, the third insulating layer having a third via formed in the second via, forming a transparent electrode layer on the third insulating layer, the transparent electrode layer Electrically connected to the transfer pad through the second via.
  • the third insulating layer is formed by depositing a layer of insulating material over the second insulating layer and the scan line, and patterning the layer of insulating material through a sixth mask process. After patterning, a third insulating layer 17 having a third via 171 communicating with the transfer pad 13 and located in the second via 162 is obtained as shown in FIG. 4F.
  • the process of forming the transparent electrode layer specifically includes depositing a transparent electrode layer over the third insulating layer, and patterning the transparent electrode layer by a seventh mask process. After patterning, an array substrate as shown in FIG. 5 was obtained.
  • the manufacturing method of the array substrate of the present invention obtains a top gate type thin film transistor, and sequentially patterns the first insulating layer and the organic semiconductor layer by using the gate as a hard film, which is not only simple in process, but also avoids graphics.
  • Organic materials cause damage to organic materials.
  • the difference in etching rate between the metal material and the organic material by dry etching is completed to avoid patterning of the organic semiconductor material.
  • the source/drain are made of a highly conductive metal material, and the data lines and the transfer pads are made of a material having a good etching resistance, which ensures excellent conductivity of the thin film transistor and avoids data during the patterning of the organic semiconductor layer. Lines and transfer pads bring damage.
  • the present invention further provides an array substrate 100.
  • the array substrate 100 is produced by the method of manufacturing the array substrate of the foregoing embodiment.
  • the array substrate 100 includes a substrate 10, a thin film transistor 11, a data line 12, a transfer pad 13, a scanning line 14, and a transparent electrode layer 15.
  • the thin film transistor 11 is a top gate type thin film transistor.
  • the thin film transistor 11 includes a source electrode 111, a drain electrode 112, a gate electrode 115, an organic semiconductor layer 113, and an insulating layer 114.
  • the source electrode 111 and the drain electrode 112 are disposed on the substrate 10 in the same layer, and the organic semiconductor layer 113, the insulating layer 114, and the gate electrode.
  • the electrodes 115 are sequentially stacked on the source electrode 111 and the drain electrode 112; the patterning of the organic semiconductor layer 113 and the insulating layer 114 is obtained by a dry etching process using the gate electrode 115 as a hard film.
  • the substrate 10 is a flexible substrate, and the insulating layer is an organic material.
  • the array substrate 100 of the present invention can be applied to an organic display panel, and can also be applied to an electrophoretic display panel, a flexible touch panel or a flexible inductor.
  • the scan line 14 is connected to the gate electrode 115, the data line 12 is connected to the source electrode 111, and the transfer pad 13 is connected to the drain electrode 112 and the transparent electrode layer 15.
  • the data line 12 and the transfer pad 13 are formed by the same process different from the source/drain.
  • the source 111 and the drain 112 have better conductivity, and the data line 12 and the transfer pad 13 have better etching resistance than the source/ Drain.

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Abstract

一种阵列基板（100）及其制造方法。阵列基板（100）的制造方法包括形成顶栅型的薄膜晶体管（11），具体包括：在基板（10）上形成源极（111）和漏极（112）；在源极（111）、漏极（112）上依次层叠形成有机半导体层（113）、第一绝缘层（114）和栅极（115）；以栅极（115）作为硬膜，采用蚀刻技术，将第一绝缘层（114）和有机半导体层（113）逐一图形化。利用栅极（115）当做硬膜对第一绝缘层（114）和有机半导体层（113）依次图形化，不仅制程简单，且可以避免在图形化有机半导体层（113）的过程中对有机材料造成损害。

Description

阵列基板及其制造方法
【技术领域】
本发明涉及显示领域，尤其涉及一种阵列基板及其制造方法。
【背景技术】
穿戴装置是一个显示器发展的全新领域，然而目前的显示器皆为玻璃基板显示器，无法有效的弯曲。因此要开发柔性显示器需要与玻璃基板完全不同的基板，如塑料基版。另一方面，原先使用的非晶硅、氮化硅、氧化硅等材料，由于迁移率、硬度、曲率及加工工艺等等的问题，无法被用来作为柔性显示器的材料。采用有机材料作为半导体层及绝缘层可以有效的改善，并开发出全新的显示器：柔性显示器。
【发明内容】
本发明主要解决的技术问题是提供一种能够应用于柔性显示器中的阵列基板及其制造方法。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板的制造方法，包括形成顶栅型的薄膜晶体管，具体包括：在基板上形成源极和漏极；形成连接源极的数据线和连接漏极的传输垫；在源极、漏极上依次层叠形成有机半导体层、第一绝缘层和栅极；以栅极作为硬膜，采用干式蚀刻技术，将第一绝缘层和半导体层逐一图形化。
其中，以栅极作为硬膜，采用蚀刻技术，将绝缘层和半导体层逐一图形化的步骤之后，制造方法进一步包括：形成连接栅极的扫描线；形成连接传输垫的透明电极层。
其中，形成连接栅极的扫描线的步骤包括：在栅极的上方形成第二绝缘层，第二绝缘层具有与栅极对应的第一过孔和与传输垫对应的第二过孔；在第二绝缘层上形成扫描线，且扫描线穿过第一过孔与栅极电连接。
其中，形成连接传输垫的透明电极层的步骤包括：在第二绝缘层的上方形成第三绝缘层，第三绝缘层具有形成于第二过孔中的第三过孔；在第三绝缘层上形成透明电极层，且透明电极层穿过第二过孔与传输垫电连接。
其中，蚀刻技术为干式蚀刻。
其中，在源极、漏极上依次层叠形成有机半导体层、第一绝缘层和栅极的步骤包括：在源极、漏极上沉积有机半导体层；在有机半导体层上方沉积第一绝缘层；在第一绝缘层上方沉积栅极金属层，并采用栅极光罩制程图案化栅极金属层，以形成栅极。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板的制造方法，包括形成顶栅型的薄膜晶体管，具体包括：在基板上形成源极和漏极；在源极、漏极上依次层叠形成有机半导体层、第一绝缘层和栅极；以栅极作为硬膜，采用蚀刻技术，将第一绝缘层和半导体层逐一图形化。
其中，在基板上形成源极和漏极的步骤之后，制造方法进一步包括：形成连接源极的数据线和连接漏极的传输垫。
其中，以栅极作为硬膜，采用蚀刻技术，将绝缘层和半导体层逐一图形化的步骤之后，制造方法进一步包括：形成连接栅极的扫描线；形成连接传输垫的透明电极层。
其中，形成连接栅极的扫描线的步骤包括：在栅极的上方形成第二绝缘层，第二绝缘层具有与栅极对应的第一过孔和与传输垫对应的第二过孔；在第二绝缘层上形成扫描线，且扫描线穿过第一过孔与栅极电连接。
其中，形成连接传输垫的透明电极层的步骤包括：在第二绝缘层的上方形成第三绝缘层，第三绝缘层具有形成于第二过孔中的第三过孔；在第三绝缘层上形成透明电极层，且透明电极层穿过第二过孔与传输垫电连接。
其中，蚀刻技术为干式蚀刻。
其中，在源极、漏极上依次层叠形成有机半导体层、第一绝缘层和栅极的步骤包括：在源极、漏极上沉积有机半导体层；在有机半导体层上方沉积第一绝缘层；在第一绝缘层上方沉积栅极金属层，并采用栅极光罩制程图案化栅极金属层，以形成栅极。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，其包括：基板和形成于基板上的顶栅型的薄膜晶体管，薄膜晶体管包括源极、漏极、栅极、有机半导体层和绝缘层，源极和漏极同层设置于基板上，有机半导体层、绝缘层和栅极依次层叠于源极和漏极上，有机半导体层和绝缘层的图形化是采用栅极为硬膜一次蚀刻得到的。
其中，基板为柔性基板。
其中，阵列基板还包括数据线、扫描线、传输垫和透明电极层，扫描线连接栅极，数据线连接源极，传输垫连接漏极和透明电极层，数据线和传输垫采用不同于源极/漏极的同一制程制得，且数据线/传输垫的抗蚀刻能力优于源极/漏极。
本发明的有益效果是：与现有技术相比，本发明阵列基板的制造方法得到顶栅型的薄膜晶体管，且利用栅极当做硬膜对第一绝缘层和有机半导体层依次图形化，不仅制程简单，且可以避免在图形化有机半导体层的过程中对有机材料造成损害。
【附图说明】
图1 是本发明第一实施例阵列基板的制造方法的流程图；
图2是图1所示制造方法中层叠形成有机半导体层、绝缘层和栅极的流程图；
图3是本发明第二实施例阵列基板的制造方法的流程图；
图4A-4F是图3所示制作方法在制作过程中的阵列基板的结构示意图；
图5是图3所示制作方法制得的阵列基板的结构示意图。
【具体实施方式】
请参照图1和图2，本发明第一实施例阵列基板的制造方法包括形成顶栅型的薄膜晶体管，形成顶栅型的薄膜晶体管的步骤具体包括：
S11，在基板上形成源极和漏极。
本步骤中，优选地，基板选择弯曲性能较好、即容易弯曲的基板，以使本发明阵列基板的制造方法应用于柔性显示器中。可以用于柔性显示器中的弯曲性能较好的基板包括塑料基板等。当然，本发明亦可以应用于不可弯曲的显示器中，基板可以是弯曲性能较差的玻璃基板。
在基板上形成源极和漏极的步骤具体包括：在基板上沉积第一金属层并通过第一道光罩制程图案化第一金属层，以形成间隔设置的源极和漏极。
S12，在源极和漏极上依次层叠形成有机半导体层、绝缘层和栅极。
本步骤具体包括：
S121，在源极和漏极上沉积有机半导体层。
本步骤亦可以理解为，在基板上沉积覆盖源极及漏极的有机半导体层。
S122，在有机半导体层上方沉积第一绝缘层。
用于柔性显示器中的绝缘层假如采用非晶硅、氮化硅、氧化硅等材料，则在迁移率、硬度、曲率及加工工艺等方面存在问题。因此，优选地，第一绝缘层为有机材料层。
S123，在第一绝缘层上方沉积栅极金属层，并采用栅极光罩制程图案化栅极金属层，以形成栅极。
由于源极和漏极的形成过程中沉积了一金属层，而本步骤栅极的形成过程中沉积了另一金属层。本实施例形成顶栅型的薄膜晶体管过程中，为了与前文第一金属层相对应，栅极金属层即第二金属层；栅极光罩制程即第二道光罩制程。
S13，以栅极作为硬膜，采用蚀刻技术，将绝缘层和半导体层逐一图形化。
具体地，由于有机半导体层非常容易因为湿式蚀刻造成污染，因此本步骤中的蚀刻技术为干式蚀刻技术。在形成栅极之后，直接采用栅极作为硬膜，利用干式蚀刻对金属和有机材料的蚀刻速率差异而完成图形化。换句话说，栅极为金属层，其可以抵挡干式蚀刻，而第一绝缘层和有机半导体层却不能够抵挡干式蚀刻；当采用栅极当做硬膜时，位于其下方的第一绝缘层和有机半导体层得以保留，而没有栅极保护的其他部分的第一绝缘层和有机半导体层则被蚀刻掉。本步骤完成后，栅极、第一绝缘层和半导体层在它们的层叠方向上完全重叠。
经过上述步骤顶栅型的薄膜晶体管制作完成。
当然，在制造阵列基板时除了制得薄膜晶体管，还需要薄膜晶体管与外部电路建立电连接。具体请参照图3所示本发明第二实施例阵列基板的制造方法，具体包括：
S21，在基板上形成源极和漏极。
本步骤中，优选地，基板选择弯曲性能较好、即容易弯曲的基板，以使本发明阵列基板的制造方法应用于柔性显示器中。可以用于柔性显示器中的弯曲性能较好的基板包括塑料基板等。当然，本发明亦可以应用于不可弯曲的显示器中，基板可以是弯曲性能较差的玻璃基板。
在基板上形成源极和漏极的步骤具体包括：在基板上沉积第一金属层并通过第一道光罩制程图案化第一金属层，以形成间隔设置的源极和漏极。第一金属层采用高导电特性的材料。
请一并参照图4A，图4A为对沉积于基板10的第一金属层进行第一道光罩制程后得到的源极111和漏极112的主视示意图。
S22，形成连接源极的数据线和连接漏极的传输垫。
具体地，在基板上沉积第二金属层并通过第二道光罩制程图案化第二金属层，图案化后形成连接源极的数据线和连接漏极的传输垫。为了后续工艺，第二金属层采用不同于第一金属层的材质，第二金属层为抗蚀刻能力较佳的材料。
请一并参照图4B，图4B为对沉积于基板10的第二金属层进行第二道光罩制程后得到的连接源极11的数据线12和连接漏极112的传输垫13的主视示意图。
S23，在源极和漏极上依次层叠形成有机半导体层、绝缘层和栅极。
本步骤具体包括：
在源极和漏极上沉积有机半导体层；在有机半导体层上方沉积第一绝缘层；在第一绝缘层上方沉积栅极金属层，并采用栅极光罩制程图案化栅极金属层，以形成栅极。
与本实施例前文的第一金属层和第二金属层相对应，而本步骤栅极的形成过程中沉积的栅极金属层即第三金属层；栅极光罩制程即第三道光罩制程。
S24，以栅极作为硬膜，采用蚀刻技术，将绝缘层和半导体层逐一图形化。
具体地，由于有机半导体层非常容易因为湿式蚀刻造成污染，因此本步骤中的蚀刻技术为干式蚀刻技术。在形成栅极之后，直接采用栅极作为硬膜板，利用干式蚀刻对金属和有机材料的蚀刻速率差异而完成图形化。换句话说，栅极为金属层，其可以抵挡干式蚀刻，而第一绝缘层和有机半导体层却不能够抵挡干式蚀刻；当采用栅极当做硬膜时，位于其下方的第一绝缘层和有机半导体层得以保留，而没有栅极保护的其他部分的第一绝缘层和有机半导体层则被蚀刻掉。本步骤完成后，栅极、第一绝缘层和半导体层在它们的层叠方向上完全重叠。
进一步地，由于数据线12和传输垫13选用抗蚀刻能力较佳的材料，从而避免在第一绝缘层和有机半导体层图案化的过程中被蚀刻到。
请一并参考图4C，图4C所示为通过栅极115作为硬膜，利用干式蚀刻的方式，将第一绝缘层和有机半导体层图案化后得到的第一绝缘层114和有机半导体层113。
S25，形成连接栅极的扫描线。
本步骤具体包括：在栅极的上方形成第二绝缘层，第二绝缘层具有与栅极对应的第一过孔和与传输垫对应的第二过孔；在第二绝缘层上形成扫描线，扫描线穿过第一过孔与栅极电连接。
第二绝缘层的形成具体为：在栅极的上方沉积一层绝缘材料，并通过第四道光罩制程对该层绝缘材料进行图案化。图案化后得到如图4D所示的具有连通栅极115的第一过孔161和连通传输垫13的第二过孔162的第二绝缘层16。
在第二绝缘层上形成扫描线的工艺具体为：在第二绝缘层的上方沉积第四金属层，并通过第五道光罩制程对第四金属层进行图案化。图案化后得到如图4E所示的连接栅极115的扫描线14。
S26，形成连接传输垫的透明电极层。
本步骤具体包括：在第二绝缘层的上方形成第三绝缘层，第三绝缘层具有形成于第二过孔中的第三过孔，在第三绝缘层上形成透明电极层，透明电极层穿过第二过孔与传输垫电连接。
第三绝缘层的形成具体为：在第二绝缘层和扫描线的上方沉积一层绝缘材料，并通过第六道光罩制程对该层绝缘材料进行图案化。图案化后得到如图4F所示的具有连通传输垫13且位于第二过孔162中的第三过孔171的第三绝缘层17。
形成透明电极层的工艺具体包括：在第三绝缘层的上方沉积透明电极层，并通过第七道光罩制程对透明电极层进行图案化。图案化后得到如图5所示的阵列基板。
区别于现有技术，本发明阵列基板的制造方法得到顶栅型的薄膜晶体管，且利用栅极当做硬膜对第一绝缘层和有机半导体层依次图形化，不仅制程简单，且可以避免在图形化有机半导体的过程中对有机材料造成损害。进一步地，利用干式蚀刻对金属材料和有机材料的蚀刻速率差异，完成图形化，避免对有机半导体材料造成污染。源/漏极采用高导电性金属材料，而数据线和传输垫采用抗蚀刻能力较佳的材料制成，既确保薄膜晶体管具有优良的导电性，又能避免有机半导体层图案化过程中对数据线和传输垫带来损伤。
请参照图5，本发明进一步提供一种阵列基板100。阵列基板100采用前述实施例阵列基板的制造方法制得。
阵列基板100包括基板10、薄膜晶体管11、数据线12、传输垫13、扫描线14和透明电极层15。其中，薄膜晶体管11为顶栅型的薄膜晶体管。薄膜晶体管11包括源极111、漏极112、栅极115、有机半导体层113和绝缘层114；源极111和漏极112同层设置于基板10上，有机半导体层113、绝缘层114和栅极115依次层叠设置于源极111和漏极112上；有机半导体层113和绝缘层114的图形化是采用栅极115为硬膜经过干式蚀刻工艺得到的。优选地，基板10为柔性基板，绝缘层为有机材料。本发明阵列基板100可以应用于有机显示面板中，也可以应用于电泳显示面板中，柔性触控面板中或者柔性感应器中等。
扫描线14连接栅极115，数据线12连接源极111，传输垫13连接漏极112和透明电极层15。数据线12和传输垫13采用不同于源/漏极的同一制程制得，源极111和漏极112具有较佳的导电能力，而数据线12和传输垫13的抗蚀刻能力优于源/漏极。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种阵列基板的制造方法，其中，所述制造方法包括形成顶栅型的薄膜晶体管，具体包括:
    在基板上形成源极和漏极；
    形成连接所述源极的数据线和连接所述漏极的传输垫；
    在所述源极、漏极上依次层叠形成有机半导体层、第一绝缘层和栅极；
    以所述栅极作为硬膜，采用干式蚀刻技术，将所述第一绝缘层和所述半导体层逐一图形化。
  2. 根据权利要求1所述的制造方法，其中，以所述栅极作为硬膜，采用蚀刻技术，将所述绝缘层和所述半导体层逐一图形化的步骤之后，所述制造方法进一步包括：
    形成连接所述栅极的扫描线；
    形成连接所述传输垫的透明电极层。
  3. 根据权利要求2所述的制造方法，其中，所述形成连接所述栅极的扫描线的步骤包括：
    在所述栅极的上方形成第二绝缘层，所述第二绝缘层具有与所述栅极对应的第一过孔和与所述传输垫对应的第二过孔；
    在所述第二绝缘层上形成所述扫描线，且所述扫描线穿过所述第一过孔与所述栅极电连接。
  4. 根据权利要求3所述的制造方法，其中，所述形成连接所述传输垫的透明电极层的步骤包括：
    在所述第二绝缘层的上方形成第三绝缘层，所述第三绝缘层具有形成于所述第二过孔中的第三过孔；
    在所述第三绝缘层上形成所述透明电极层，且所述透明电极层穿过所述第二过孔与所述传输垫电连接。
  5. 根据权利要求1所述的制造方法，其中，所述在所述源极、漏极上依次层叠形成有机半导体层、第一绝缘层和栅极的步骤包括：
    在所述源极、漏极上沉积有机半导体层；
    在所述有机半导体层上方沉积第一绝缘层；
    在所述第一绝缘层上方沉积栅极金属层，并采用栅极光罩制程图案化所述栅极金属层，以形成所述栅极。
  6. 一种阵列基板的制造方法，其中，所述制造方法包括形成顶栅型的薄膜晶体管，具体包括:
    在基板上形成源极和漏极；
    在所述源极、漏极上依次层叠形成有机半导体层、第一绝缘层和栅极；
    以所述栅极作为硬膜，采用蚀刻技术，将所述第一绝缘层和所述半导体层逐一图形化。
  7. 根据权利要求6所述的制造方法，其中，所述在基板上形成源极和漏极的步骤之后，所述制造方法进一步包括：
    形成连接所述源极的数据线和连接所述漏极的传输垫。
  8. 根据权利要求7所述的制造方法，其中，以所述栅极作为硬膜，采用蚀刻技术，将所述绝缘层和所述半导体层逐一图形化的步骤之后，所述制造方法进一步包括：
    形成连接所述栅极的扫描线；
    形成连接所述传输垫的透明电极层。
  9. 根据权利要求8所述的制造方法，其中，所述形成连接所述栅极的扫描线的步骤包括：
    在所述栅极的上方形成第二绝缘层，所述第二绝缘层具有与所述栅极对应的第一过孔和与所述传输垫对应的第二过孔；
    在所述第二绝缘层上形成所述扫描线，且所述扫描线穿过所述第一过孔与所述栅极电连接。
  10. 根据权利要求9所述的制造方法，其中，所述形成连接所述传输垫的透明电极层的步骤包括：
    在所述第二绝缘层的上方形成第三绝缘层，所述第三绝缘层具有形成于所述第二过孔中的第三过孔；
    在所述第三绝缘层上形成所述透明电极层，且所述透明电极层穿过所述第二过孔与所述传输垫电连接。
  11. 根据权利要求6所述的制造方法，其中，所述蚀刻技术为干式蚀刻。
  12. 根据权利要求6所述的制造方法，其中，所述在所述源极、漏极上依次层叠形成有机半导体层、第一绝缘层和栅极的步骤包括：
    在所述源极、漏极上沉积有机半导体层；
    在所述有机半导体层上方沉积第一绝缘层；
    在所述第一绝缘层上方沉积栅极金属层，并采用栅极光罩制程图案化所述栅极金属层，以形成所述栅极。
  13. 一种阵列基板，其中，所述阵列基板包括：基板和形成于基板上的顶栅型的薄膜晶体管，所述薄膜晶体管包括源极、漏极、栅极、有机半导体层和绝缘层，所述源极和漏极同层设置于所述基板上，所述有机半导体层、绝缘层和所述栅极依次层叠于所述源极和漏极上，所述有机半导体层和所述绝缘层的图形化是采用所述栅极为硬膜一次蚀刻得到的。
  14. 根据权利要求13所述的阵列基板，其中，所述基板为柔性基板。
  15. 根据权利要求13所述的阵列基板，其中，所述阵列基板还包括数据线、扫描线、传输垫和透明电极层，所述扫描线连接所述栅极，所述数据线连接所述源极，所述传输垫连接所述漏极和所述透明电极层，所述数据线和所述传输垫采用不同于所述源极/漏极的同一制程制得，且所述数据线/传输垫的抗蚀刻能力优于所述源极/漏极。
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