WO2015085618A1 - 薄膜晶体管阵列基板、制造方法及液晶显示装置 - Google Patents

薄膜晶体管阵列基板、制造方法及液晶显示装置 Download PDF

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WO2015085618A1
WO2015085618A1 PCT/CN2013/089917 CN2013089917W WO2015085618A1 WO 2015085618 A1 WO2015085618 A1 WO 2015085618A1 CN 2013089917 W CN2013089917 W CN 2013089917W WO 2015085618 A1 WO2015085618 A1 WO 2015085618A1
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layer
substrate
film transistor
thin film
transistor array
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PCT/CN2013/089917
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English (en)
French (fr)
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陈彩琴
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深圳市华星光电技术有限公司
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Priority to US14/234,429 priority Critical patent/US20150168773A1/en
Publication of WO2015085618A1 publication Critical patent/WO2015085618A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/13606—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit having means for reducing parasitic capacitance

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a thin film transistor array substrate, a manufacturing method thereof, and a liquid crystal display device.
  • Liquid crystal display devices have now become flat display devices that are widely used.
  • Liquid crystal display devices generally include thin film transistors (Thin Film Transistor, TFT) array substrate and color film substrate.
  • FIG. 1A is a schematic plan view of a conventional thin film transistor array substrate;
  • FIG. 1B is a cross-sectional view taken along line A-A' of FIG. 1A.
  • the thin film transistor array substrate 10 includes a source layer 11, a drain layer 12, a gate layer 13, an insulating layer 14, a semiconductor layer 15, an ohmic contact layer 16, a passivation layer 17, and a pixel electrode layer 18, wherein the pixel electrode layer 18 It can be connected to the drain 12 through the via 19 .
  • the bottom of the conventional thin film transistor array substrate 10 is provided with a gate layer 13 which, in addition to functioning as a corresponding gate, also needs to prevent light from entering the semiconductor layer 15 from the bottom surface and the side surface of the transistor array substrate 10.
  • the area of the gate layer 13 is set relatively large.
  • the large-area gate layer 13 easily generates parasitic capacitance between the source layer and the drain layer, and also causes the feedthrough voltage (feed). The generation of through voltage greatly affects the display effect of the liquid crystal display device.
  • An object of the present invention is to provide a thin film transistor array substrate, a manufacturing method, and a liquid crystal display device which have small parasitic capacitance and can reduce generation of photo-generated current, and solve the problem of the conventional thin film transistor array substrate, the manufacturing method, and the liquid crystal display device.
  • a thin film transistor array substrate comprising:
  • An ohmic contact layer located on the semiconductor layer separated from each other by a first region and a second region;
  • a second conductive layer comprising a source layer and a drain layer, the source layer being connected to an ohmic contact layer of the first region, the drain layer being connected to an ohmic contact layer of the second region;
  • a passivation layer on the source layer and the drain layer;
  • a transparent conductive layer is disposed on the passivation layer and electrically connected to the drain layer through a via hole, wherein the pixel electrode is formed by patterning the transparent conductive layer;
  • a gap exists between a projection area of the gate layer on the substrate substrate and a projection area of the source layer on the substrate substrate.
  • the black matrix layer is disposed between the substrate substrate and the semiconductor layer for shielding light from being emitted from the substrate substrate side to the semiconductor layer .
  • the black matrix is a chromium-based material or a resin-based material.
  • the gate layer, the source layer, and the drain layer are metal layers, and the insulating layer and the passivation layer are silicon nitride layers, and a semiconductor
  • the layer is an amorphous silicon layer, and the ohmic contact layer is an amorphous silicon layer doped with phosphorus ions.
  • the transparent conductive layer is made of indium tin oxide.
  • a method of fabricating a thin film transistor array substrate comprises the steps of:
  • the layered structure being a black matrix layer
  • the second metal layer Graphically processing the second metal layer to form a second conductive layer, wherein the second conductive layer includes a source layer and a drain layer, and the ohmic contact layer of the source layer and the first region Connecting, the drain layer is connected to the ohmic contact layer of the second region;
  • a gap exists between a projection area of the gate layer on the substrate substrate and a projection area of the source layer on the substrate substrate.
  • the black matrix layer is disposed between the substrate substrate and the semiconductor layer for shielding light from being emitted from the side of the substrate substrate Said semiconductor layer.
  • the black matrix is a chromium-based material or a resin-based material.
  • the gate layer, the source layer, and the drain layer are metal layers, and the insulating layer and the passivation layer are silicon nitride.
  • the layer, the semiconductor layer is an amorphous silicon layer, and the ohmic contact layer is an amorphous silicon layer doped with phosphorus ions.
  • the transparent conductive layer is made of indium tin oxide.
  • liquid crystal display device comprising:
  • a color filter substrate a thin film transistor array substrate, and a liquid crystal layer disposed between the color film substrate and the thin film transistor array substrate;
  • the thin film transistor array substrate includes:
  • An ohmic contact layer located on the semiconductor layer separated from each other by a first region and a second region;
  • a second conductive layer comprising a source layer and a drain layer, the source layer being connected to an ohmic contact layer of the first region, the drain layer being connected to an ohmic contact layer of the second region;
  • a passivation layer on the source layer and the drain layer;
  • a transparent conductive layer is disposed on the passivation layer and electrically connected to the drain layer through a via hole, wherein the pixel electrode is formed by patterning the transparent conductive layer;
  • a gap exists between a projection area of the gate layer on the substrate substrate and a projection area of the source layer on the substrate substrate.
  • the black matrix layer is disposed between the substrate substrate and the semiconductor layer to block light from being emitted from the substrate substrate side to the semiconductor layer.
  • no black matrix layer is provided on the color filter substrate.
  • the black matrix is a chromium-based material or a resin-based material.
  • the gate layer, the source layer, and the drain layer are metal layers, and the insulating layer and the passivation layer are silicon nitride layers and semiconductor layers.
  • the ohmic contact layer is an amorphous silicon layer doped with phosphorus ions.
  • the transparent conductive layer is made of indium tin oxide.
  • the thin film transistor array substrate, the manufacturing method, and the liquid crystal display device of the present invention reduce the generation of photo-generated current by providing a black matrix layer on the array substrate, and at the same time
  • the area of the small gate layer reduces the parasitic capacitance between the gate layer and the source layer and the drain layer; and solves the problem that the existing thin film transistor array substrate, the manufacturing method, and the liquid crystal display device have large parasitic capacitance or photogenerated current Excessive technical problems.
  • 1A is a schematic top plan view of a conventional thin film transistor array substrate
  • Figure 1B is a cross-sectional view taken along line A-A' of Figure 1A;
  • FIG. 2 is a schematic structural view of a preferred embodiment of a thin film transistor array substrate of the present invention
  • FIG. 3 is a flow chart of a preferred embodiment of a method of fabricating a thin film transistor array substrate of the present invention
  • FIG. 4A is a schematic top plan view showing a step S101 of a preferred embodiment of a method for fabricating a thin film transistor array substrate according to the present invention
  • Figure 4B is a cross-sectional view taken along line B-B' of Figure 4A;
  • 5A is a schematic top plan view showing a step S102 of a preferred embodiment of a method of fabricating a thin film transistor array substrate according to the present invention
  • Figure 5B is a cross-sectional view taken along line C-C' of Figure 5A;
  • 6A is a schematic top plan view showing a step S104 of a preferred embodiment of a method for fabricating a thin film transistor array substrate according to the present invention
  • Figure 6B is a cross-sectional view taken along line D-D' of Figure 6A;
  • FIG. 7A is a schematic top plan view showing a step S105 of a preferred embodiment of a method of fabricating a thin film transistor array substrate according to the present invention.
  • Figure 7B is a cross-sectional view taken along line E-E' of Figure 7A;
  • Fig. 8 is a top plan view showing a step S106 of a preferred embodiment of the method of fabricating the thin film transistor array substrate of the present invention.
  • FIG. 2 is a schematic structural view of a preferred embodiment of the thin film transistor array substrate of the present invention.
  • the thin film transistor array substrate 20 of the preferred embodiment includes a substrate substrate 201 and a black matrix layer 202, a gate layer 203, an insulating layer 204, a semiconductor layer 205, and an ohmic contact layer 206 which are sequentially formed on the substrate substrate 201 from bottom to top. a second conductive layer, a passivation layer 207, and a transparent conductive layer 208.
  • the ohmic contact layer 206 is located on the first and second regions separated from each other on the semiconductor layer 205; the second conductive layer includes a source layer 209 and a drain layer 210, and the source layer 209 is connected to the ohmic contact layer 206 of the first region.
  • the drain layer 210 is connected to the ohmic contact layer 206 of the second region; the passivation layer 207 is located on the source layer 209 and the drain layer 210; and the transparent conductive layer 208 (see FIGS. 7 and 8). Shown on the passivation layer 207 and electrically connected to the drain layer 210 through vias 211 (shown in FIGS. 7 and 8) on the passivation layer 207.
  • the black matrix layer 202 is used to shield the light leakage of the backlight outside the pixel region while preventing the color mixture of adjacent RGB sub-pixels on the corresponding color film substrate (the portion of the black matrix is not shown in the figure) And to prevent the writing of background light.
  • the black matrix layer 202 may be a chromium-based material or a resin-based material, and is formed on the substrate substrate 201 by a patterning process.
  • the gate layer 203 is a metal layer such as germanium, molybdenum, aluminum, copper, titanium, tantalum or tungsten.
  • the insulating layer 204 may be a silicon nitride layer or the like.
  • the semiconductor layer 205 may be an amorphous silicon layer.
  • the ohmic contact layer 206 can be an amorphous silicon layer doped with phosphorus ions.
  • the source layer 209 and the drain layer 210 are metal layers.
  • the passivation layer 207 can be a silicon nitride layer.
  • the transparent conductive layer 208 may be composed of indium-tin-oxide (ITO).
  • the pixel electrode can be formed by patterning the transparent conductive layer. There is a gap between a projection area of the gate layer 203 on the substrate substrate 201 and a projection area of the drain layer 210 on the substrate substrate 201, and a projection area of the gate layer 203 on the substrate substrate 201 is opposite to the source layer 209.
  • the projection area on the substrate substrate 201 there is also a gap in the projection area on the substrate substrate 201; that is, the projection area of the gate layer 203 on the substrate substrate 201 does not overlap with the projection area of the drain layer 210 on the substrate substrate 201, and the gate layer 203 is on the substrate.
  • the projection area on the substrate 201 and the projection area of the source layer 209 on the substrate substrate 201 also do not overlap.
  • the black array layer 202 is disposed between the substrate substrate 201 and the semiconductor layer 205, the black matrix layer 202 can well block light from one side of the substrate substrate 201.
  • the semiconductor layer 205 is directed to avoid generation of photo-generated current in the semiconductor layer 205.
  • the gate layer 203 and the source layer 209 on the substrate substrate 201 are not overlapped, which greatly reduces
  • the parasitic capacitance between the gate layer 203 and the source layer 209 and the parasitic capacitance between the gate layer 203 and the drain layer 210 improve the display effect of the corresponding liquid crystal display device.
  • the thin film transistor array substrate of the present invention reduces the generation of photo-generated current by providing a black matrix layer on the array substrate while reducing the area between the gate layer and the source layer and the drain layer by reducing the area of the gate layer. Parasitic capacitance.
  • FIG. 3 is a flow chart of a preferred embodiment of a method for fabricating a thin film transistor array substrate of the present invention.
  • the manufacturing method of the thin film transistor array substrate of the preferred embodiment includes:
  • Step S101 forming a layered structure on the substrate substrate, the layered structure is a black matrix layer; and patterning the black matrix layer;
  • Step S102 forming a first metal layer on the layered structure, and patterning the first metal layer to form a gate layer;
  • Step S103 sequentially forming an insulating layer, a semiconductor layer, an ohmic contact layer, and a second metal layer on the layered structure, wherein the ohmic contact layer is located on the semiconductor layer and the first region and the second region are separated from each other;
  • Step S104 patterning the second metal layer to form a second conductive layer, wherein the second conductive layer comprises a source layer and a drain layer, the source layer is connected with the ohmic contact layer of the first region, and the drain layer Connecting with an ohmic contact layer of the second region;
  • Step S105 forming a passivation layer on the layered structure, and patterning the passivation layer to form via holes of the passivation layer;
  • Step S106 forming a transparent conductive layer on the layered structure, wherein the transparent conductive layer is electrically connected to the drain layer through the via hole;
  • step S106 The method of fabricating the thin film transistor array substrate of the preferred embodiment ends in step S106.
  • FIG. 4A is a top plan view showing a step S101 of a preferred embodiment of the method for fabricating a thin film transistor array substrate of the present invention
  • FIG. 4B is a cross-sectional view taken along line BB' of FIG. 4A
  • FIG. 5B is a cross-sectional view taken along line C-C' of FIG. 5A
  • FIG. 6A is a cross-sectional view of the thin film transistor array substrate of the present invention
  • FIG. 6B is a cross-sectional view taken along line DD' of FIG. 6A
  • FIG. 7A is a cross-sectional view along line D-D' of FIG.
  • FIG. 7A is a step S105 of a preferred embodiment of the method for fabricating the thin film transistor array substrate of the present invention.
  • FIG. 7B is a cross-sectional view taken along line EE' of FIG. 7A; and
  • FIG. 8 is a top plan view showing a step S106 of a preferred embodiment of the method for fabricating a thin film transistor array substrate of the present invention.
  • a layered structure is formed on the substrate substrate 201, and the layered structure is a black matrix layer 202 for shielding light leakage of the backlight outside the pixel region while preventing the corresponding color film substrate.
  • the color mixture of the adjacent RGB sub-pixels (the portion of the black matrix is not shown in the figure) and the prevention of writing of the background light.
  • the black matrix layer 202 may be a chromium-based material or a resin-based material.
  • the black matrix layer 202 can be formed on the substrate substrate 201 by a patterning process using a corresponding lithography plate, and the structure of the thin film transistor array substrate after the patterning process is as shown in FIG. 4B. Then it proceeds to step S102.
  • a first metal layer is formed on the layered structure, and the material of the first metal layer may be tantalum, molybdenum, aluminum, copper, titanium, tantalum or tungsten.
  • the first metal layer is then patterned by polarity using a corresponding lithography plate to form a gate layer 203, and the structure of the thin film transistor substrate after the patterning process is as shown in FIG. 5B. Then it proceeds to step S103.
  • an insulating layer 204, a semiconductor layer 205, an ohmic contact layer 206, and a second metal layer are sequentially deposited on the layered structure, and the ohmic contact layer 206 is located on the semiconductor layer 205 in a first region and a second region separated from each other.
  • the insulating layer 204 is a silicon nitride layer or the like
  • the semiconductor layer 205 may be an amorphous silicon layer
  • the ohmic contact layer 206 may be an amorphous silicon layer doped with phosphorus ions
  • the material of the second metal layer may be tantalum, molybdenum, aluminum, Copper, titanium, tantalum or tungsten.
  • the second metal layer is patterned using a corresponding lithography plate to form a second conductive layer.
  • the second conductive layer includes a source layer 209 and a drain layer 210, the source layer 209 is connected to the ohmic contact layer 206 of the first region, and the drain layer 210 is connected to the ohmic contact layer 206 of the second region; Between the projection area on the substrate substrate 201 and the projection area of the drain layer 210 on the substrate substrate 201, a projection area of the gate layer 203 on the substrate substrate 201 and the source layer 209 are on the substrate substrate 201.
  • the projection area of the gate layer 203 on the substrate substrate 201 does not overlap with the projection area of the drain layer 210 on the substrate substrate 201, and the gate layer 203 is on the substrate substrate 201.
  • the projection area of the projection area and the source layer 209 on the substrate substrate 201 also do not overlap; the structure of the thin film transistor substrate after the patterning process is as shown in FIG. 6B. Then it proceeds to step S105.
  • a passivation layer 207 is formed on the layered structure, and a passivation layer 207 is patterned using a corresponding lithographic plate to form a via 211 of the passivation layer 207; the passivation layer 207 may be nitrided. Silicon layer.
  • the structure of the thin film transistor substrate after the patterning process is as shown in Fig. 7B. Then it proceeds to step S106.
  • a transparent conductive layer 208 is formed on the layered structure, and the transparent conductive layer 208 is patterned by using a corresponding photoresist plate, so that the transparent conductive layer 208 passes through the via 211 and the drain layer 210 of the passivation layer 207.
  • the transparent conductive layer 208 is made of indium-tin-oxide (ITO), and the pixel electrode can be formed by patterning the transparent conductive layer.
  • ITO indium-tin-oxide
  • the structure of the thin film transistor substrate after the patterning is as shown in Figs. 8 and 7B (the cross-sectional view taken along the line F-F' of Fig. 8 is the same as Fig. 7B).
  • the thin film transistor array substrate produced by the method of fabricating the thin film transistor array substrate of the preferred embodiment has a black array layer 202 disposed between the substrate substrate 201 and the semiconductor layer 205, so that the black matrix layer 202 can block light from the substrate lining.
  • One side of the bottom 201 is incident on the semiconductor layer 205, avoiding generation of photo-generated current in the semiconductor layer 205.
  • the gate layer 203 and the source layer 209 on the substrate substrate 201 are not overlapped, which greatly reduces
  • the parasitic capacitance between the gate layer 203 and the source layer 209 and the parasitic capacitance between the gate layer 203 and the drain layer 210 improve the display effect of the corresponding liquid crystal display device.
  • the method for fabricating the thin film transistor array substrate of the present invention reduces the generation of photo-generated current by providing a black matrix layer on the array substrate, while reducing the gate layer and the source layer and the drain layer by reducing the area of the gate layer. Parasitic capacitance between.
  • the present invention also provides a liquid crystal display device comprising a color film substrate, a thin film transistor array substrate, and a liquid crystal layer disposed between the color film substrate and the thin film transistor array substrate.
  • the thin film transistor array substrate includes a substrate substrate and a black matrix layer, a gate layer, an insulating layer, a semiconductor layer, an ohmic contact layer, a second conductive layer, a passivation layer, and a transparent conductive layer which are sequentially formed on the substrate substrate from bottom to top. .
  • the ohmic contact layer is located on the semiconductor layer and the first region and the second region are separated from each other;
  • the second conductive layer comprises a source layer and a drain layer, the source layer is connected with the ohmic contact layer of the first region, and the drain layer is The ohmic contact layer of the two regions is connected;
  • the passivation layer is located on the source layer and the drain layer;
  • the transparent conductive layer is on the passivation layer, and is electrically connected to the drain layer through the via holes on the passivation layer, wherein
  • the transparent conductive layer is patterned to form a pixel electrode.
  • the projection area of the gate layer on the substrate substrate and the projection area of the drain layer on the substrate substrate have a gap
  • the projection area of the gate layer on the substrate substrate and the projection area of the source layer on the substrate substrate There is a gap.
  • a black matrix layer is disposed between the substrate substrate and the semiconductor layer for shielding light from being emitted from the substrate substrate side toward the semiconductor layer. Since the black matrix layer is already disposed on the thin film transistor array substrate, the black matrix layer may not be disposed on the color filter substrate to reduce the manufacturing cost of the liquid crystal display device.
  • the thin film transistor array substrate, the manufacturing method and the liquid crystal display device of the invention reduce the generation of photo-generated current by providing a black matrix layer on the array substrate, and at the same time reduce the gate layer and the source layer and the drain by reducing the area of the gate layer.
  • the parasitic capacitance between the pole layers solves the technical problems of the conventional thin film transistor array substrate, the manufacturing method, and the large parasitic capacitance or excessive photocurrent of the liquid crystal display device.

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Abstract

　本发明提供一种薄膜晶体管阵列基板、制作方法及液晶显示装置。该薄膜晶体管阵列基板包括基板衬底、黑色矩阵层、栅极层、绝缘层、半导体层、欧姆接触层、第二导电层、钝化层以及透明导电层；第二导电层包括源极层和漏极层，栅极层在基板衬底上的投影区域与漏极层在基板衬底上的投影区域存在间隙。本发明还提供一种薄膜晶体管阵列基板的制作方法及液晶显示装置。本发明提升了相应液晶显示装置的显示效果。

Description

薄膜晶体管阵列基板、制造方法及液晶显示装置 技术领域
本发明涉及液晶显示领域，特别是涉及一种薄膜晶体管阵列基板、制作方法及液晶显示装置。
 背景技术
液晶显示装置现在已成为被人们广泛使用的平板显示装置。液晶显示装置一般包括薄膜晶体管（Thin Film Transistor,TFT）阵列基板以及彩膜基板。请参照图1A和图1B，图1A为现有的薄膜晶体管阵列基板的俯视结构示意图；图1B为沿图1A的A-A’截面线的截面图。该薄膜晶体管阵列基板10包括源极层11、漏极层12、栅极层13、绝缘层14、半导体层15、欧姆接触层16、钝化层17以及像素电极层18，其中像素电极层18可通过过孔19与漏极12连接。
现有的薄膜晶体管阵列基板10的底部设置有栅极层13，该栅极层13除了起到相应的栅极作用，还需要阻止光从晶体管阵列基板10的底面和侧面射入到半导体层15中，防止光生电流的产生。因此栅极层13的面积设置得比较大。但是大面积的栅极层13易与源极层或漏极层之间产生寄生电容，同时也导致了馈通电压（feed through voltage）的产生，大大影响了液晶显示装置的显示效果。
 技术问题
本发明的目的在于提供一种寄生电容小，且可减少光生电流的产生的薄膜晶体管阵列基板、制作方法及液晶显示装置；以解决现有的薄膜晶体管阵列基板、制作方法及液晶显示装置的寄生电容较大或光生电流过大的技术问题。
 技术解决方案
本发明提供的技术方案如下：
提供一种薄膜晶体管阵列基板，其包括：
基板衬底，以及
从下向上依次形成在所述基板衬底上的黑色矩阵层、栅极层，绝缘层，半导体层，
欧姆接触层，所述欧姆接触层位于所述半导体层上相互分离的第一区域和第二区域；
第二导电层，包括源极层以及漏极层，所述源极层与所述第一区域的欧姆接触层连接，所述漏极层与所述第二区域的欧姆接触层连接；
钝化层：位于所述源极层以及所述漏极层上；以及
透明导电层：位于所述钝化层上，并通过过孔与所述漏极层电性连接，其中通过对所述透明导电层进行图形化处理，形成像素电极；
其中所述栅极层在所述基板衬底上的投影区域与所述漏极层在所述基板衬底上的投影区域存在间隙。
在本发明所述的薄膜晶体管阵列基板中，所述栅极层在所述基板衬底上的投影区域与所述源极层在所述基板衬底上的投影区域存在间隙。
在本发明所述的薄膜晶体管阵列基板中，所述黑色矩阵层设置在所述基板衬底与所述半导体层之间，用于遮挡光线从所述基板衬底一侧射向所述半导体层。
在本发明所述的薄膜晶体管阵列基板中，所述黑色矩阵为铬系材料或树脂系材料。
在本发明所述的薄膜晶体管阵列基板中，所述栅极层、所述源极层以及所述漏极层为金属层，所述绝缘层和所述钝化层为氮化硅层，半导体层为非晶硅层，欧姆接触层为掺杂磷离子的非晶硅层。
在本发明所述的薄膜晶体管阵列基板中，所述透明导电层有氧化锡铟构成。
还提供一种薄膜晶体管阵列基板的制作方法，其包括步骤：
形成分层结构于基板衬底上，所述分层结构为黑色矩阵层；
对所述黑色矩阵层进行图形化处理；
在所述分层结构上形成第一金属层；
对所述第一金属层进行图形化处理，以形成栅极层；
在所述分层结构上依次形成绝缘层、半导体层、欧姆接触层以及第二金属层，其中所述欧姆接触层位于所述半导体层上相互分离的第一区域和第二区域；
对所述第二金属层进行图形化处理，以形成第二导电层，其中所述第二导电层包括源极层以及漏极层，所述源极层与所述第一区域的欧姆接触层连接，所述漏极层与所述第二区域的欧姆接触层连接；
在所述分层结构上形成钝化层，并对所述钝化层进行图形化处理，以形成所述钝化层的过孔；
在所述分层结构上形成透明导电层，其中所述透明导电层通过所述过孔与所述漏极层电性连接，通过对所述透明导电层进行图形化处理，形成像素电极；
其中所述栅极层在所述基板衬底上的投影区域与所述漏极层在所述基板衬底上的投影区域存在间隙。
在本发明所述的薄膜晶体管阵列基板的制作方法中，所述栅极层在所述基板衬底上的投影区域与所述源极层在所述基板衬底上的投影区域存在间隙。
在本发明所述的薄膜晶体管阵列基板的制作方法中，所述黑色矩阵层设置在所述基板衬底与所述半导体层之间，用于遮挡光线从所述基板衬底一侧射向所述半导体层。
在本发明所述的薄膜晶体管阵列基板的制作方法中，所述黑色矩阵为铬系材料或树脂系材料。
在本发明所述的薄膜晶体管阵列基板的制作方法中，所述栅极层、所述源极层以及所述漏极层为金属层，所述绝缘层和所述钝化层为氮化硅层，半导体层为非晶硅层，欧姆接触层为掺杂磷离子的非晶硅层。
在本发明所述的薄膜晶体管阵列基板的制作方法中，所述透明导电层有氧化锡铟构成。
还提供一种液晶显示装置，其包括：
彩膜基板、薄膜晶体管阵列基板以及设置在所述彩膜基板与所述薄膜晶体管阵列基板之间的液晶层；其中
所述薄膜晶体管阵列基板，包括：
基板衬底，以及
从下向上依次形成在所述基板衬底上的黑色矩阵层、栅极层，绝缘层，半导体层，
欧姆接触层，所述欧姆接触层位于所述半导体层上相互分离的第一区域和第二区域；
第二导电层，包括源极层以及漏极层，所述源极层与所述第一区域的欧姆接触层连接，所述漏极层与所述第二区域的欧姆接触层连接；
钝化层：位于所述源极层以及所述漏极层上；以及
透明导电层：位于所述钝化层上，并通过过孔与所述漏极层电性连接，其中通过对所述透明导电层进行图形化处理，形成像素电极；
其中所述栅极层在所述基板衬底上的投影区域与所述漏极层在所述基板衬底上的投影区域存在间隙。
在本发明所述的液晶显示装置中，所述栅极层在所述基板衬底上的投影区域与所述源极层在所述基板衬底上的投影区域存在间隙。
在本发明所述的液晶显示装置中，所述黑色矩阵层设置在所述基板衬底与所述半导体层之间，用于遮挡光线从所述基板衬底一侧射向所述半导体层。
在本发明所述的液晶显示装置中，所述彩膜基板上没有设置黑色矩阵层。
在本发明所述的液晶显示装置中，所述黑色矩阵为铬系材料或树脂系材料。
在本发明所述的液晶显示装置中，所述栅极层、所述源极层以及所述漏极层为金属层，所述绝缘层和所述钝化层为氮化硅层，半导体层为非晶硅层，欧姆接触层为掺杂磷离子的非晶硅层。
在本发明所述的液晶显示装置中，所述透明导电层有氧化锡铟构成。
 有益效果
相较于现有的薄膜晶体管阵列基板、制作方法及液晶显示装置，本发明的薄膜晶体管阵列基板、制作方法及液晶显示装置通过在阵列基板上设置黑色矩阵层减少光生电流的产生，同时通过减小栅极层的面积减小了栅极层与源极层、漏极层之间的寄生电容；解决了现有的薄膜晶体管阵列基板、制作方法及液晶显示装置的寄生电容较大或光生电流过大的技术问题。
 附图说明
图1A为现有的薄膜晶体管阵列基板的俯视结构示意图；
图1B为沿图1A的A-A’截面线的截面图；
图2为本发明的薄膜晶体管阵列基板的优选实施例的结构示意图；
图3为本发明的薄膜晶体管阵列基板的制作方法的优选实施例的流程图；
图4A为本发明的薄膜晶体管阵列基板的制作方法的优选实施例的步骤S101时的俯视结构示意图；
图4B为沿图4A的B-B’截面线的截面图；
图5A为本发明的薄膜晶体管阵列基板的制作方法的优选实施例的步骤S102时的俯视结构示意图；
图5B为沿图5A的C-C’截面线的截面图；
图6A为本发明的薄膜晶体管阵列基板的制作方法的优选实施例的步骤S104时的俯视结构示意图；
图6B为沿图6A的D-D’截面线的截面图；
图7A为本发明的薄膜晶体管阵列基板的制作方法的优选实施例的步骤S105时的俯视结构示意图；
图7B为沿图7A的E-E’截面线的截面图；
图8为本发明的薄膜晶体管阵列基板的制作方法的优选实施例的步骤S106时的俯视结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
请参照图2，图2为本发明的薄膜晶体管阵列基板的优选实施例的结构示意图。本优选实施例的薄膜晶体管阵列基板20包括基板衬底201以及从下向上依次形成在基板衬底201上的黑色矩阵层202、栅极层203、绝缘层204、半导体层205、欧姆接触层206、第二导电层、钝化层207以及透明导电层208。其中欧姆接触层206位于半导体层205上相互分离的第一区域和第二区域；第二导电层包括源极层209以及漏极层210，源极层209与第一区域的欧姆接触层206连接，漏极层210与第二区域的欧姆接触层206连接；钝化层207位于源极层209和漏极层210上；透明导电层208（如图7和图8 所示）位于钝化层207上，并通过钝化层207上的过孔211（如图7和图8 所示）与漏极层210电性连接。
在本优选实施例中，黑色矩阵层202用于遮蔽像素区域之外的背光源的漏光，同时防止相应彩膜基板上相邻RGB亚像素的混色（该部分黑色矩阵在图中未示出）以及防止背景光的写入。该黑色矩阵层202可为铬系材料或树脂系材料，通过图形化处理的方式形成在基板衬底201上。栅极层203为金属层，例如，锘、钼、铝、铜、钛、钽或钨等。绝缘层204可为氮化硅层等。半导体层205可为非晶硅层。欧姆接触层206可为掺杂磷离子的非晶硅层。源极层209以及漏极层210为金属层。钝化层207可为氮化硅层。透明导电层208为可由氧化锡铟（ITO，indium-tin-oxide）构成。可通过对透明导电层进行图形化处理，形成像素电极。其中栅极层203在基板衬底201上的投影区域与漏极层210在基板衬底201上的投影区域存在间隙，栅极层203在基板衬底201上的投影区域与源极层209在基板衬底201上的投影区域也存在间隙；即栅极层203在基板衬底201上的投影区域与漏极层210在基板衬底201上的投影区域没有交叠，栅极层203在基板衬底201上的投影区域与源极层209在基板衬底201上的投影区域也没有交叠。
本优选实施例的薄膜晶体管阵列基板20使用时，由于黑色阵列层202设置在基板衬底201与半导体层205之间，因此黑色矩阵层202可很好的遮挡光线从基板衬底201的一侧射向半导体层205，避免了半导体层205内光生电流的产生。同时通过减小栅极层203的设置区域，使得栅极层203与漏极层210、栅极层203与源极层209在基板衬底201上的投影区域均没有交叠，这样大大减小了栅极层203与源极层209的寄生电容以及栅极层203与漏极层210之间的寄生电容，从而提高了相应的液晶显示装置的显示效果。
因此，本发明的薄膜晶体管阵列基板通过在阵列基板上设置黑色矩阵层减少光生电流的产生，同时通过减小栅极层的面积减小了栅极层与源极层、漏极层之间的寄生电容。
请参照图3，图3为本发明的薄膜晶体管阵列基板的制作方法的优选实施例的流程图。本优选实施例的薄膜晶体管阵列基板的制作方法包括：
步骤S101，形成分层结构于基板衬底上，分层结构为黑色矩阵层；对黑色矩阵层进行图形化处理；
步骤S102，在分层结构上形成第一金属层，对第一金属层进行图形化处理，以形成栅极层；
步骤S103，在分层结构上依次形成绝缘层、半导体层、欧姆接触层以及第二金属层，其中欧姆接触层位于半导体层上相互分离的第一区域和第二区域；
步骤S104，对第二金属层进行图形化处理，以形成第二导电层，其中第二导电层包括源极层以及漏极层，源极层与第一区域的欧姆接触层连接，漏极层与第二区域的欧姆接触层连接；
步骤S105，在分层结构上形成钝化层，并对钝化层进行图形化处理，以形成钝化层的过孔；
步骤S106，在分层结构上形成透明导电层，其中透明导电层通过过孔与漏极层电性连接；
本优选实施例的薄膜晶体管阵列基板的制作方法结束于步骤S106。
下面通过图4A-图8B详细说明本优选实施例的薄膜晶体管阵列基板的制作方法的具体步骤。图4A为本发明的薄膜晶体管阵列基板的制作方法的优选实施例的步骤S101时的俯视结构示意图；图4B为沿图4A的B-B’截面线的截面图；图5A为本发明的薄膜晶体管阵列基板的制作方法的优选实施例的步骤S102时的俯视结构示意图；图5B为沿图5A的C-C’截面线的截面图；图6A为本发明的薄膜晶体管阵列基板的制作方法的优选实施例的步骤S104时的俯视结构示意图；图6B为沿图6A的D-D’截面线的截面图；图7A为本发明的薄膜晶体管阵列基板的制作方法的优选实施例的步骤S105时的俯视结构示意图；图7B为沿图7A的E-E’截面线的截面图；图8为本发明的薄膜晶体管阵列基板的制作方法的优选实施例的步骤S106时的俯视结构示意图。
在步骤S101中，在基板衬底201上形成分层结构，该分层结构为黑色矩阵层202，该黑色矩阵层202用于遮蔽像素区域之外的背光源的漏光，同时防止相应彩膜基板上相邻的RGB亚像素的混色（该部分黑色矩阵在图中未示出）以及防止背景光的写入。该黑色矩阵层202可为铬系材料或树脂系材料。该黑色矩阵层202可使用相应的光刻板通过图形化处理的方式形成在基板衬底201上，图形化处理之后的薄膜晶体管阵列基板的结构如图4B所示。随后转到步骤S102。
在步骤S102中，在分层结构上形成第一金属层，该第一金属层的材料可为锘、钼、铝、铜、钛、钽或钨等。随后使用相应的光刻板对该第一金属层极性图形化处理，以形成栅极层203，图形化处理之后的薄膜晶体管基板的结构如图5B所示。随后转到步骤S103。
在步骤S103中，在分层结构上依次沉积绝缘层204、半导体层205、欧姆接触层206以及第二金属层，欧姆接触层206位于半导体层205上相互分离的第一区域和第二区域。绝缘层204为氮化硅层等，半导体层205可为非晶硅层，欧姆接触层206可为掺杂磷离子的非晶硅层，第二金属层的材料可为锘、钼、铝、铜、钛、钽或钨等。随后转到步骤S104。
在步骤S104中，使用相应的光刻板对第二金属层进行图形化处理，以形成第二导电层。该第二导电层包括源极层209以及漏极层210，源极层209与第一区域的欧姆接触层206连接，漏极层210与第二区域的欧姆接触层206连接；这里栅极层203在基板衬底201上的投影区域与漏极层210在基板衬底201上的投影区域存在间隙，栅极层203在基板衬底201上的投影区域与源极层209在基板衬底201上的投影区域也存在间隙，即栅极层203在基板衬底201上的投影区域与漏极层210在基板衬底201上的投影区域没有交叠，栅极层203在基板衬底201上的投影区域与源极层209在基板衬底201上的投影区域也没有交叠；图形化处理之后的薄膜晶体管基板的结构如图6B所示。随后转到步骤S105。
在步骤S105中，在分层结构上形成钝化层207，使用相应的光刻板并对钝化层207进行图形化处理，形成钝化层207的过孔211；钝化层207可为氮化硅层。图形化处理之后的薄膜晶体管基板的结构如图7B所示。随后转到步骤S106。
在步骤S106中，在分层结构上形成透明导电层208，使用相应的光刻板对透明导电层208进行图形化处理，使得透明导电层208通过钝化层207的过孔211与漏极层210电性连接；透明导电层208为可由氧化锡铟（ITO，indium-tin-oxide）构成，可通过对透明导电层进行图形化处理，形成像素电极。图形化处理之后的薄膜晶体管基板的结构如图8和图7B所示（沿图8的F-F’截面线的截面图与图7B相同）。
这样即完成了本优选实施例的薄膜晶体管阵列基板的制作过程。
本优选实施例的薄膜晶体管阵列基板的制作方法制作的薄膜晶体管阵列基板由于黑色阵列层202设置在基板衬底201与半导体层205之间，因此黑色矩阵层202可很好的遮挡光线从基板衬底201的一侧射向半导体层205，避免了半导体层205内光生电流的产生。同时通过减小栅极层203的设置区域，使得栅极层203与漏极层210、栅极层203与源极层209在基板衬底201上的投影区域均没有交叠，这样大大减小了栅极层203与源极层209的寄生电容以及栅极层203与漏极层210之间的寄生电容，从而提高了相应的液晶显示装置的显示效果。
因此，本发明的薄膜晶体管阵列基板的制作方法通过在阵列基板上设置黑色矩阵层减少光生电流的产生，同时通过减小栅极层的面积减小了栅极层与源极层、漏极层之间的寄生电容。
本发明还提供一种液晶显示装置，该液晶显示装置包括彩膜基板、薄膜晶体管阵列基板以及设置在彩膜基板与薄膜晶体管阵列基板之间的液晶层。
薄膜晶体管阵列基板包括基板衬底以及从下向上依次形成在基板衬底上的黑色矩阵层、栅极层、绝缘层、半导体层、欧姆接触层、第二导电层、钝化层以及透明导电层。其中欧姆接触层位于半导体层上相互分离的第一区域和第二区域；第二导电层包括源极层以及漏极层，源极层与第一区域的欧姆接触层连接，漏极层与第二区域的欧姆接触层连接；钝化层位于源极层和漏极层上；透明导电层位于钝化层上，并通过钝化层上的过孔与漏极层电性连接，其中通过对透明导电层进行图形化处理，形成像素电极。
其中栅极层在基板衬底上的投影区域与漏极层在基板衬底上的投影区域存在间隙，栅极层在基板衬底上的投影区域与源极层在基板衬底上的投影区域存在间隙。黑色矩阵层设置在基板衬底与半导体层之间，用于遮挡光线从基板衬底一侧射向半导体层。由于在薄膜晶体管阵列基板已设置有黑色矩阵层，因此彩膜基板上可不设置黑色矩阵层，以降低液晶显示装置的制作成本。
本发明的液晶显示装置的具体工作原理与上述的薄膜晶体管阵列基板的优选实施例中的相关描述相同。具体请参见上述薄膜晶体管阵列基板的优选实施例中的相关描述。
本发明的薄膜晶体管阵列基板、制作方法及液晶显示装置通过在阵列基板上设置黑色矩阵层减少光生电流的产生，同时通过减小栅极层的面积减小了栅极层与源极层、漏极层之间的寄生电容；解决了现有的薄膜晶体管阵列基板、制作方法及液晶显示装置的寄生电容较大或光生电流过大的技术问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
 本发明的实施方式
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Claims (19)

  1. 一种薄膜晶体管阵列基板，其包括：
    基板衬底，以及
    从下向上依次形成在所述基板衬底上的黑色矩阵层、栅极层，绝缘层，半导体层，
    欧姆接触层，所述欧姆接触层位于所述半导体层上相互分离的第一区域和第二区域；
    第二导电层，包括源极层以及漏极层，所述源极层与所述第一区域的欧姆接触层连接，所述漏极层与所述第二区域的欧姆接触层连接；
    钝化层：位于所述源极层以及所述漏极层上；以及
    透明导电层：位于所述钝化层上，并通过过孔与所述漏极层电性连接，其中通过对所述透明导电层进行图形化处理，形成像素电极；
    其中所述栅极层在所述基板衬底上的投影区域与所述漏极层在所述基板衬底上的投影区域存在间隙。
  2. 根据权利要求1所述的薄膜晶体管阵列基板，其中所述栅极层在所述基板衬底上的投影区域与所述源极层在所述基板衬底上的投影区域存在间隙。
  3. 根据权利要求1所述的薄膜晶体管阵列基板，其中所述黑色矩阵层设置在所述基板衬底与所述半导体层之间，用于遮挡光线从所述基板衬底一侧射向所述半导体层。
  4. 根据权利要求1所述的薄膜晶体管阵列基板，其中所述黑色矩阵为铬系材料或树脂系材料。
  5. 根据权利要求1所述的薄膜晶体管阵列基板，其中所述栅极层、所述源极层以及所述漏极层为金属层，所述绝缘层和所述钝化层为氮化硅层，半导体层为非晶硅层，欧姆接触层为掺杂磷离子的非晶硅层。
  6. 根据权利要求1所述的薄膜晶体管阵列基板，其中所述透明导电层有氧化锡铟构成。
  7. 一种薄膜晶体管阵列基板的制作方法，其包括步骤：
    形成分层结构于基板衬底上，所述分层结构为黑色矩阵层；
    对所述黑色矩阵层进行图形化处理；
    在所述分层结构上形成第一金属层；
    对所述第一金属层进行图形化处理，以形成栅极层；
    在所述分层结构上依次形成绝缘层、半导体层、欧姆接触层以及第二金属层，其中所述欧姆接触层位于所述半导体层上相互分离的第一区域和第二区域；
    对所述第二金属层进行图形化处理，以形成第二导电层，其中所述第二导电层包括源极层以及漏极层，所述源极层与所述第一区域的欧姆接触层连接，所述漏极层与所述第二区域的欧姆接触层连接；
    在所述分层结构上形成钝化层，并对所述钝化层进行图形化处理，以形成所述钝化层的过孔；
    在所述分层结构上形成透明导电层，其中所述透明导电层通过所述过孔与所述漏极层电性连接，通过对所述透明导电层进行图形化处理，形成像素电极；
    其中所述栅极层在所述基板衬底上的投影区域与所述漏极层在所述基板衬底上的投影区域存在间隙。
  8. 根据权利要求7所述的薄膜晶体管阵列基板的制作方法，其中所述栅极层在所述基板衬底上的投影区域与所述源极层在所述基板衬底上的投影区域存在间隙。
  9. 根据权利要求7所述的薄膜晶体管阵列基板的制作方法，其中所述黑色矩阵层设置在所述基板衬底与所述半导体层之间，用于遮挡光线从所述基板衬底一侧射向所述半导体层。
  10. 根据权利要求7所述的薄膜晶体管阵列基板的制作方法，其中所述黑色矩阵为铬系材料或树脂系材料。
  11. 根据权利要求7所述的薄膜晶体管阵列基板的制作方法，其中所述栅极层、所述源极层以及所述漏极层为金属层，所述绝缘层和所述钝化层为氮化硅层，半导体层为非晶硅层，欧姆接触层为掺杂磷离子的非晶硅层。
  12. 根据权利要求7所述的薄膜晶体管阵列基板的制作方法，其中所述透明导电层有氧化锡铟构成。
  13. 一种液晶显示装置，其包括：
    彩膜基板、薄膜晶体管阵列基板以及设置在所述彩膜基板与所述薄膜晶体管阵列基板之间的液晶层；其中
    所述薄膜晶体管阵列基板，包括：
    基板衬底，以及
    从下向上依次形成在所述基板衬底上的黑色矩阵层、栅极层，绝缘层，半导体层，
    欧姆接触层，所述欧姆接触层位于所述半导体层上相互分离的第一区域和第二区域；
    第二导电层，包括源极层以及漏极层，所述源极层与所述第一区域的欧姆接触层连接，所述漏极层与所述第二区域的欧姆接触层连接；
    钝化层：位于所述源极层以及所述漏极层上；以及
    透明导电层：位于所述钝化层上，并通过过孔与所述漏极层电性连接，其中通过对所述透明导电层进行图形化处理，形成像素电极；
    其中所述栅极层在所述基板衬底上的投影区域与所述漏极层在所述基板衬底上的投影区域存在间隙。
  14. 根据权利要求13所述的液晶显示装置，其中所述栅极层在所述基板衬底上的投影区域与所述源极层在所述基板衬底上的投影区域存在间隙。
  15. 根据权利要求13所述的液晶显示装置，其中所述黑色矩阵层设置在所述基板衬底与所述半导体层之间，用于遮挡光线从所述基板衬底一侧射向所述半导体层。
  16. 根据权利要求13所述的液晶显示装置，其中所述彩膜基板上没有设置黑色矩阵层。
  17. 根据权利要求13所述的液晶显示装置，其中所述黑色矩阵为铬系材料或树脂系材料。
  18. 根据权利要求13所述的液晶显示装置，其中所述栅极层、所述源极层以及所述漏极层为金属层，所述绝缘层和所述钝化层为氮化硅层，半导体层为非晶硅层，欧姆接触层为掺杂磷离子的非晶硅层。
  19. 根据权利要求13所述的液晶显示装置，其中所述透明导电层有氧化锡铟构成。
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