WO2019015077A1 - 一种阵列基板及其制造方法、液晶显示装置 - Google Patents

一种阵列基板及其制造方法、液晶显示装置 Download PDF

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Publication number
WO2019015077A1
WO2019015077A1 PCT/CN2017/102538 CN2017102538W WO2019015077A1 WO 2019015077 A1 WO2019015077 A1 WO 2019015077A1 CN 2017102538 W CN2017102538 W CN 2017102538W WO 2019015077 A1 WO2019015077 A1 WO 2019015077A1
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Prior art keywords
auxiliary line
scan
line
line segment
data
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PCT/CN2017/102538
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English (en)
French (fr)
Inventor
郝思坤
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/577,223 priority Critical patent/US10365526B2/en
Publication of WO2019015077A1 publication Critical patent/WO2019015077A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G02F1/133516—Methods for their manufacture, e.g. printing, electro-deposition or photolithography
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136259—Repairing; Defects
    • G02F1/136272—Auxiliary lines
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/122—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode having a particular pattern

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to an array substrate, a method of manufacturing the same, and a liquid crystal display device.
  • the liquid crystal display device Due to its light weight, small size, and low function, the liquid crystal display device has become the most widely used flat panel display device and is used in electronic devices such as mobile phones, digital cameras, and computers.
  • the inventor of the present application found in the long-term research and development that as the resolution of the liquid crystal display device increases, the pixel charging time is shortened, and the charging rate of the pixel is lowered due to the constant load of the pixel; meanwhile, due to the liquid crystal display device There are a large number of overlapping regions between the scan line and the data line, and a parasitic capacitance is formed during charging, which simultaneously acts with the resistance of the scan line and the data line itself, and becomes a main factor of signal delay, and also affects the charging rate of the pixel, and reduces the liquid crystal display device. The display effect.
  • the invention provides an array substrate, a manufacturing method thereof and a liquid crystal display device, which solve the technical problem of low signal delay and low charging rate in the liquid crystal display device in the prior art.
  • an array substrate including:
  • each of the scan lines and/or each of the data lines respectively correspond to at least one auxiliary line segment, and the scan line and/or the data line are capacitively coupled with the corresponding auxiliary line segment to Reducing signal delay times on the scan lines and/or the data lines.
  • another technical solution adopted by the present invention is to provide a method for manufacturing an array substrate, including:
  • each of the pixel electrodes is connected to a drain of a corresponding one of the thin film transistors
  • each of the scan lines and/or each of the data lines respectively correspond to at least one auxiliary line segment, and the scan line and/or the data line are capacitively coupled with the corresponding auxiliary line segment to reduce the scan line And/or signal delay time on the data line.
  • another technical solution adopted by the present invention is to provide a liquid crystal display device including the above array substrate.
  • the invention provides at least one auxiliary line segment correspondingly on each scan line and/or each data line of the array substrate, so as to reduce signal delay time on the scan line and/or the data line, improve the charging rate, and improve the display effect.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic diagram of a pixel structure of an embodiment of an array substrate of the present invention.
  • FIG. 3 is a schematic diagram of an equivalent circuit of an array substrate of an embodiment of an array substrate of the present invention.
  • FIG. 4 is a schematic diagram of a pixel charging waveform of an embodiment of an array substrate of the present invention.
  • FIG. 5 is a schematic flow chart of an embodiment of a method for manufacturing an array substrate of the present invention.
  • 6a-6g are schematic diagrams showing a process flow of an array substrate in an embodiment of a method for fabricating an array substrate of the present invention
  • FIG. 7 is a schematic diagram showing a pixel structure of a VA mode of an embodiment of a method for fabricating an array substrate of the present invention.
  • FIG. 8 is a schematic diagram of a pixel structure of an IPS mode according to an embodiment of a method for fabricating an array substrate of the present invention
  • Figure 9 is a schematic view showing the structure of an embodiment of a liquid crystal display device of the present invention.
  • an embodiment of an array substrate of the present invention includes:
  • a plurality of data lines 20, and a plurality of scan lines 10 are arranged to cross each other, thereby defining a plurality of pixel regions 30;
  • each of the scan lines 10 and/or each of the data lines 20 respectively correspond to at least one auxiliary line segment, and the scan line 10 and/or the data line 20 are capacitively coupled with the corresponding auxiliary line segment to reduce the scan line 10 and/or Or the signal delay time on data line 20.
  • the auxiliary line segment includes a first auxiliary line segment 40 and a second auxiliary line segment 50, wherein the first auxiliary line segment 40 is parallel to the data line 20 and is disposed in the same layer as the scan line 10, and each data line 20 corresponds to one
  • the portions of the pixel region 30 correspond to a first auxiliary line segment 40, respectively, and the length of the first auxiliary line segment 40 is smaller than the portion of the data line 20 corresponding to one pixel region 30 such that the first auxiliary line segment 40 does not overlap the scan line 10 and the data.
  • the overlapping portion of the line 20; and the second auxiliary line segment 50 is parallel to the scan line 10 and disposed in the same layer as the data line 20, and the portion of the corresponding one of the pixel areas 30 of each of the scan lines 10 corresponds to a second auxiliary line segment 50, and the length of the second auxiliary line segment 50 is smaller than a portion of the scanning line 10 corresponding to one pixel region 30 such that the second auxiliary line segment 50 does not overlap the overlapping portion of the scanning line 10 and the data line 20.
  • the auxiliary line segment is in a floating state to form a capacitive coupling with the scan line 10 or the data line 20.
  • each of the pixel regions 30 includes a thin film transistor 301 and a pixel electrode 302.
  • the gate 3011 of the thin film transistor 301 is electrically connected to a corresponding scan line 10, and the source 3012 of the thin film transistor 301 is electrically connected to a strip.
  • Corresponding data line 20, and drain 3013 of thin film transistor 301 is electrically connected to pixel electrode 302.
  • the gate 3011 of the thin film transistor 301 is disposed in the same layer as the first auxiliary line segment 40, and the source 3012 and the drain 3013 of the thin film transistor 301 are disposed in the same layer as the second auxiliary line segment 50.
  • the array substrate may be provided with only the first auxiliary line segment 40, parallel to the data line 20, and disposed in the same layer as the scan line 10.
  • the data line 20 in each pixel region 30 is equivalent to a resistor R1, and the scan line 10 overlaps the data line 20 to generate a parasitic capacitance C1.
  • Each first auxiliary line segment 40 is equivalent to a resistor R2, and the first auxiliary line segment 40 In the floating state, the capacitor C2 is coupled with the data line 20; the data line 20 is grounded through the liquid crystal capacitor Clc; and one end of the liquid crystal capacitor Clc is connected to the pixel electrode, and one end is grounded.
  • 4 is a graph showing the relationship between the voltage across the liquid crystal capacitor Clc and the time, that is, the pixel charging waveform, including the curve 801 of the voltage across the liquid crystal capacitor Clc in the prior art, and the liquid crystal capacitor Clc at both ends in the present embodiment.
  • the voltage 802 in the embodiment of the present invention increases the voltage across the liquid crystal capacitor Clc with increasing time, and the pixel charging rate is significantly higher than the pixel charging rate in the prior art.
  • the array substrate may also be provided with only the second auxiliary line segment 50, parallel to the scan line 10, and disposed in the same layer as the data line 20.
  • the second auxiliary line segment 50 is in a floating state to form a capacitive coupling with the scan line 10.
  • At least one auxiliary line segment is respectively disposed correspondingly on each scan line and/or each data line of the array substrate, so as to reduce signal delay time on the scan line and/or the data line, improve the charging rate, and improve the display effect.
  • an embodiment of a method for manufacturing an array substrate of the present invention includes:
  • the first common electrode 303 is formed on the same layer of the plurality of scan lines 10 and the plurality of first auxiliary line segments 40.
  • each scan line 10 corresponds to a second auxiliary line segment 50 corresponding to a portion of the pixel area, and the length of the second auxiliary line segment 50 is smaller than a portion of the scan line 10 corresponding to one pixel area to enable the second auxiliary line segment. 50 does not overlap the overlapping portion of the scan line 10 and the data line 20;
  • Each of the data lines 20 corresponds to a first auxiliary line segment 40 corresponding to a portion of the pixel area, and the length of the first auxiliary line segment 40 is smaller than a portion of the data line 20 corresponding to one pixel area such that the first auxiliary line segment 40 is non-overlapping.
  • the overlapping portion of the scan line 10 and the data line 20 corresponds to a first auxiliary line segment 40 corresponding to a portion of the pixel area, and the length of the first auxiliary line segment 40 is smaller than a portion of the data line 20 corresponding to one pixel area such that the first auxiliary line segment 40 is non-overlapping.
  • each scan line 10 and/or each data line 20 corresponds to at least one auxiliary line segment, respectively, and the scan line 10 and/or the data line 20 are capacitively coupled with the corresponding auxiliary line segment to reduce the scan line 10 and/or the data line 20 Signal delay time.
  • the color filter layer may also be disposed on the color filter substrate of the liquid crystal display device and the array substrate.
  • a plurality of through holes 70 are correspondingly disposed in the color filter layer 60 to connect each of the pixel electrodes 302 to the drain 3013 of a corresponding thin film transistor 301 when the plurality of pixel electrodes 302 are formed.
  • each pixel electrode 302 is connected to a drain 3113 of a corresponding thin film transistor 301;
  • the second common electrode 304 is formed in the same layer of the pixel electrode 302.
  • the array substrate can be VA (Vertical Alignment mode, the pixel structure is shown in FIG. 7, the pixel electrode 3021 is connected to the drain 3013 of the thin film transistor through the via 70; the array substrate may also be an IPS (In-plane) Switching, on-board switching mode, the pixel structure thereof is shown in FIG. 8, and the pixel electrode 3022 is connected to the drain 3013 of the thin film transistor 301 through the via 70.
  • VA Vertical Alignment mode
  • the pixel structure is shown in FIG. 7
  • the pixel electrode 3021 is connected to the drain 3013 of the thin film transistor through the via 70
  • the array substrate may also be an IPS (In-plane) Switching, on-board switching mode, the pixel structure thereof is shown in FIG. 8, and the pixel electrode 3022 is connected to the drain 3013 of the thin film transistor 301 through the via 70.
  • IPS In-plane
  • the array substrate can also be TN (Twist Nematic) mode, MVA (Multi-domain) Vertical Alignment mode or FFS (Fringe Field Switching) mode.
  • TN Transmission Nematic
  • MVA Multi-domain Vertical Alignment
  • FFS Ringe Field Switching
  • At least one auxiliary line segment is respectively disposed correspondingly on each scan line and/or each data line of the array substrate, so as to reduce signal delay time on the scan line and/or the data line, improve the charging rate, and improve the display effect.
  • an embodiment of a liquid crystal display device of the present invention includes the array substrate 901 described above, a column substrate 902 , and a liquid crystal layer disposed between the array substrate 901 and the alignment substrate 902 .
  • At least one auxiliary line segment is respectively disposed correspondingly on each scan line and/or each data line of the array substrate, so as to reduce signal delay time on the scan line and/or the data line, improve the charging rate, and improve the display effect.

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Abstract

一种阵列基板（901）及其制造方法、液晶显示装置，阵列基板（901）包括多条扫描线（10）；多条数据线（20），与多条扫描线（10）彼此交叉设置，从而定义出多个像素区域（30）；多条辅助线段（40、50），其中，每条扫描线（10）和/或每条数据线（20）分别对应至少一条辅助线段（40、50），扫描线（10）和/或数据线（20）与对应的辅助线段（40、50）电容耦合。能够降低扫描线（10）和/或数据线（20）上的信号延迟时间，提高充电率，改善显示效果。

Description

一种阵列基板及其制造方法、液晶显示装置
【技术领域】
本发明涉及液晶显示技术领域，特别涉及一种阵列基板及其制造方法、液晶显示装置。
【背景技术】
液晶显示装置因其重量轻、体积小、功能低等优点，已经成为目前使用最广泛的平板显示装置，应用于手机、数字相机、计算机等电子设备中。
本申请的发明人在长期的研发中发现，随着液晶显示装置解析度的增加，像素充电时间减短，由于像素的负载不变，使得像素的充电率下降；同时，由于液晶显示装置中的扫描线和数据线存在大量交叠区域，在充电时形成寄生电容，与扫描线和数据线本身的电阻同时作用，成为信号延迟的主要因素，也对像素的充电率造成影响，降低液晶显示装置的显示效果。
【发明内容】
本发明提供一种阵列基板及其制造方法、液晶显示装置，以解决现有技术中液晶显示装置中的信号延迟、充电率低的技术问题。
为解决上述技术问题，本发明采用的一个技术方案是提供一种阵列基板，包括：
多条扫描线；
多条数据线，与所述多条扫描线彼此交叉设置，从而定义出多个像素区域；
多条辅助线段，其中，每条所述扫描线和/或每条所述数据线分别对应至少一条辅助线段，所述扫描线和/或所述数据线与所述对应的辅助线段电容耦合以降低所述扫描线和/或所述数据线上的信号延迟时间。
为解决上述技术问题，本发明采用的另一个技术方案是提供一种阵列基板的制造方法，包括：
在基板上形成多条扫描线、多条第一辅助线段和多个薄膜晶体管的栅极，其中，每个所述薄膜晶体管的栅极与一条对应的所述扫描线相连；
形成所述多个薄膜晶体管的半导体层；
形成多条数据线、多条第二辅助线段和所述多个薄膜晶体管的源极和漏极，其中，每个所述薄膜晶体管的源极与一条对应的所述数据线相连；
形成多个像素电极，其中，每个所述像素电极与一个对应的所述薄膜晶体管的漏极相连；
其中，每条所述扫描线和/或每条所述数据线分别对应至少一条辅助线段，所述扫描线和/或所述数据线与所述对应的辅助线段电容耦合以降低所述扫描线和/或所述数据线上的信号延迟时间。
为解决上述技术问题，本发明采用的又一个技术方案是提供一种液晶显示装置，包括上述的阵列基板。
本发明通过在阵列基板的每条扫描线和/或每条数据线分别对应设置至少一条辅助线段，以降低扫描线和/或数据线上的信号延迟时间，提高充电率，改善显示效果。
【附图说明】
图1是本发明阵列基板实施例的结构示意图；
图2是本发明阵列基板实施例的像素结构示意图；
图3是本发明阵列基板实施例的阵列基板等效电路示意图；
图4是本发明阵列基板实施例的像素充电波形示意图；
图5是本发明阵列基板的制造方法实施例的流程示意图；
图6a-6g是本发明阵列基板的制造方法实施例中阵列基板的工艺流程示意图；
图7是本发明阵列基板的制造方法实施例的VA模式的像素结构示意图；
图8是本发明阵列基板的制造方法实施例的IPS模式的像素结构示意图；
图9本发明液晶显示装置实施例的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述。
参见图1和图2，本发明阵列基板实施例包括：
多条扫描线10；
多条数据线20，与多条扫描线10彼此交叉设置，从而定义出多个像素区域30；
多条辅助线段，其中，每条扫描线10和/或每条数据线20分别对应至少一条辅助线段，扫描线10和/或数据线20与对应的辅助线段电容耦合以降低扫描线10和/或数据线20上的信号延迟时间。
可选的，辅助线段包括第一辅助线段40和第二辅助线段50，其中，第一辅助线段40平行于数据线20，且与扫描线10设置在同一层中，每条数据线20对应一个像素区域内30的部分分别对应一条第一辅助线段40，且第一辅助线段40的长度小于数据线20对应一个像素区域30内的部分以使第一辅助线段40非重叠于扫描线10和数据线20的重叠部分；而第二辅助线段50平行于扫描线10，且与数据线20设置在同一层中，每条扫描线10中对应一个像素区域30内的部分分别对应一条第二辅助线段50，且第二辅助线段50的长度小于扫描线10对应一个像素区域30内的部分以使第二辅助线段50非重叠于扫描线10和数据线20的重叠部分。
可选的，辅助线段处于浮接状态，以与扫描线10或者数据线20形成电容耦合。
可选的，每个像素区域30包括薄膜晶体管301和像素电极302，其中，薄膜晶体管301的栅极3011电性连接至一条对应的扫描线10，薄膜晶体管301的源极3012电性连接至一条对应的数据线20，而薄膜晶体管301的漏极3013电性连接至像素电极302。
其中，薄膜晶体管301的栅极3011与第一辅助线段40设置在同一层中，而薄膜晶体管301的源极3012和漏极3013与第二辅助线段50设置在同一层中。
参见图1至图4，在其他实施例中，阵列基板可以只设有第一辅助线段40，平行于数据线20，且与扫描线10设置在同一层中。
其中，每个像素区域30内的数据线20等效为电阻R1，扫描线10与数据线20交叠产生寄生电容C1，每个第一辅助线段40等效为电阻R2，第一辅助线段40处于浮接状态，以与数据线20形成电容C2耦合；数据线20通过液晶电容Clc接地；液晶电容Clc一端的接像素电极，一端接地。图4为液晶电容Clc两端的电压随时间的变化关系图，即像素充电波形图，包括现有技术中液晶电容Clc两端的电压随时间的变化曲线801，和本实施例中液晶电容Clc两端的电压随时间的变化曲线802，本发明实施例中液晶电容Clc两端的电压随时间的增加，上升得更快，像素充电率明显高于现有技术中的像素充电率。
可选的，在其他实施例中，阵列基板也可以只设有第二辅助线段50，平行于扫描线10，且与数据线20设置在同一层中。其中，第二辅助线段50处于浮接状态，以与扫描线10形成电容耦合。
本发明实施例通过在阵列基板的每条扫描线和/或每条数据线分别对应设置至少一条辅助线段，以降低扫描线和/或数据线上的信号延迟时间，提高充电率，改善显示效果。
参见图5和图6a-图6g，本发明阵列基板的制造方法实施例包括：
S101、在基板100上形成多条扫描线10、多条第一辅助线段40和多个薄膜晶体管301的栅极3011，其中，每个薄膜晶体管301的栅极3011与一条对应的扫描线10相连；
可选的，在多条扫描线10和多条第一辅助线段40的同一层形成第一公共电极303。
S102、形成多个薄膜晶体管301的半导体层3014；
S103、形成多条数据线20、多条第二辅助线段50和多个薄膜晶体管301的源极3012和漏极3013，其中，每个薄膜晶体管301的源极3012与一条对应的数据线20相连；
可选的，每条扫描线10对应一个像素区域内的部分分别对应一条第二辅助线段50，且第二辅助线段50的长度小于扫描线10对应一个像素区域内的部分以使第二辅助线段50非重叠于扫描线10和数据线20的重叠部分；
每条数据线20对应一个像素区域内的部分分别对应一条第一辅助线段40，且第一辅助线段40的长度小于数据线20对应一个像素区域内的部分以使第一辅助线段40非重叠于扫描线10和数据线20的重叠部分。
其中，每条扫描线10和/或每条数据线20分别对应至少一条辅助线段，扫描线10和/或数据线20与对应的辅助线段电容耦合以降低扫描线10和/或数据线20上的信号延迟时间。
S104、形成彩色滤光层60；
可选的，彩色滤光层还可以设置在液晶显示装置中与阵列基板对列的彩膜基板上。
S105、在彩色滤光层60中对应设置多个通孔70，以在形成多个像素电极302时使每个像素电极302与一个对应的薄膜晶体管301的漏极3013相连。
S106、形成多个像素电极302，其中，每个像素电极302与一个对应的薄膜晶体管301的漏极3013相连；
可选的，在像素电极302的同一层形成第二公共电极304。
可选的，阵列基板可以是VA（Vertical Alignment，垂直排列）模式，其像素结构参见图7，像素电极3021通过过孔70与薄膜晶体管的漏极3013相连；阵列基板还可以是IPS（In-plane Switching，板内切换）模式，其像素结构参见图8，像素电极3022通过过孔70与薄膜晶体管301的漏极3013相连。
可选的，阵列基板还可以是TN（Twist Nematic，扭曲向列型）模式、MVA（Multi-domain Vertical Alignment，多域垂直排列）模式或FFS（Fringe Field Switching，广视角）模式等。
本发明实施例通过在阵列基板的每条扫描线和/或每条数据线分别对应设置至少一条辅助线段，以降低扫描线和/或数据线上的信号延迟时间，提高充电率，改善显示效果。
参见图9，本发明液晶显示装置实施例包括上述的阵列基板901，对列基板902及设置于阵列基板901与对列基板902间的液晶层。
具体的，本发明实施例中阵列基板的结构参见上述阵列基板实施例，在此不再赘述。
本发明实施例通过在阵列基板的每条扫描线和/或每条数据线分别对应设置至少一条辅助线段，以降低扫描线和/或数据线上的信号延迟时间，提高充电率，改善显示效果。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (14)

  1. 一种液晶显示装置，其中，包括阵列基板，所述阵列基板包括：
    多条扫描线；
    多条数据线，与所述多条扫描线彼此交叉设置，从而定义出多个像素区域；
    多条辅助线段，其中，每条所述扫描线和/或每条所述数据线分别对应至少一条辅助线段，所述扫描线和/或所述数据线与所述对应的辅助线段电容耦合以降低所述扫描线和/或所述数据线上的信号延迟时间；
    其中，所述辅助线段包括第一辅助线段和第二辅助线段，其中，所述第一辅助线段平行于所述数据线，且与所述扫描线设置在同一层中；而所述第二辅助线段平行于所述扫描线，且与所述数据线设置在同一层中；
    所述辅助线段处于浮接状态，以与所述扫描线或者所述数据线形成电容耦合。
  2. 根据权利要求1所述的液晶显示装置，其中，每条所述扫描线对应一个所述像素区域内的部分分别对应一条所述第二辅助线段，且所述第二辅助线段的长度小于所述扫描线对应一个所述像素区域内的部分以使所述第二辅助线段非重叠于所述扫描线和所述数据线的重叠部分；
    每条所述数据线对应一个所述像素区域内的部分分别对应一条所述第一辅助线段，且所述第一辅助线段的长度小于所述数据线对应一个所述像素区域内的部分以使所述第一辅助线段非重叠于所述扫描线和所述数据线的重叠部分。
  3. 根据权利要求2所述的液晶显示装置，其中，每个所述像素区域包括薄膜晶体管和像素电极，其中，所述薄膜晶体管的栅极电性连接至一条对应的扫描线，所述薄膜晶体管的源极电性连接至一条对应的数据线，而薄膜晶体管的漏极电性连接至所述像素电极。
  4. 根据权利要求3所述的液晶显示装置，其中，所述薄膜晶体管的栅极与所述第一辅助线段设置在同一层中，而所述薄膜晶体管的源极和漏极与所述第二辅助线段设置在同一层中。
  5. 根据权利要求1所述的液晶显示装置，其中，所述阵列基板为VA模式、IPS模式、TN模式、MVA模式或FFS模式。
  6. 一种阵列基板，其中，包括：
    多条扫描线；
    多条数据线，与所述多条扫描线彼此交叉设置，从而定义出多个像素区域；
    多条辅助线段，其中，每条所述扫描线和/或每条所述数据线分别对应至少一条辅助线段，所述扫描线和/或所述数据线与所述对应的辅助线段电容耦合以降低所述扫描线和/或所述数据线上的信号延迟时间。
  7. 根据权利要求6所述的阵列基板，其中，所述辅助线段包括第一辅助线段和第二辅助线段，其中，所述第一辅助线段平行于所述数据线，且与所述扫描线设置在同一层中；而所述第二辅助线段平行于所述扫描线，且与所述数据线设置在同一层中。
  8. 根据权利要求7所述的阵列基板，其中，每条所述扫描线对应一个所述像素区域内的部分分别对应一条所述第二辅助线段，且所述第二辅助线段的长度小于所述扫描线对应一个所述像素区域内的部分以使所述第二辅助线段非重叠于所述扫描线和所述数据线的重叠部分；
    每条所述数据线对应一个所述像素区域内的部分分别对应一条所述第一辅助线段，且所述第一辅助线段的长度小于所述数据线对应一个所述像素区域内的部分以使所述第一辅助线段非重叠于所述扫描线和所述数据线的重叠部分。
  9. 根据权利要求8所述的阵列基板，其中，每个所述像素区域包括薄膜晶体管和像素电极，其中，所述薄膜晶体管的栅极电性连接至一条对应的扫描线，所述薄膜晶体管的源极电性连接至一条对应的数据线，而薄膜晶体管的漏极电性连接至所述像素电极。
  10. 根据权利要求9所述的阵列基板，其中，所述薄膜晶体管的栅极与所述第一辅助线段设置在同一层中，而所述薄膜晶体管的源极和漏极与所述第二辅助线段设置在同一层中。
  11. 根据权利要求6所述的阵列基板，其中，所述辅助线段处于浮接状态，以与所述扫描线或者所述数据线形成电容耦合。
  12. 一种阵列基板的制造方法，其中，包括：
    在基板上形成多条扫描线、多条第一辅助线段和多个薄膜晶体管的栅极，其中，每个所述薄膜晶体管的栅极与一条对应的所述扫描线相连；
    形成所述多个薄膜晶体管的半导体层；
    形成多条数据线、多条第二辅助线段和所述多个薄膜晶体管的源极和漏极，其中，每个所述薄膜晶体管的源极与一条对应的所述数据线相连；
    形成多个像素电极，其中，每个所述像素电极与一个对应的所述薄膜晶体管的漏极相连；
    其中，每条所述扫描线和/或每条所述数据线分别对应至少一条辅助线段，所述扫描线和/或所述数据线与所述对应的辅助线段电容耦合以降低所述扫描线和/或所述数据线上的信号延迟时间。
  13. 根据权利要求12所述的制造方法，其中，在所述形成多条数据线、多条第二辅助线段和所述多个薄膜晶体管的源极和漏极的步骤之后，进一步包括：
    形成彩色滤光层，并在所述彩色滤光层中对应设置多个通孔，以在形成所述多个像素电极时使每个所述像素电极与一个对应的所述薄膜晶体管的漏极相连。
  14. 根据权利要求12所述的制造方法，其中，每条所述扫描线对应一个像素区域内的部分分别对应一条所述第二辅助线段，且所述第二辅助线段的长度小于所述扫描线对应一个所述像素区域内的部分以使所述第二辅助线段非重叠于所述扫描线和所述数据线的重叠部分；
    每条所述数据线对应一个像素区域内的部分分别对应一条所述第一辅助线段，且所述第一辅助线段的长度小于所述数据线对应一个所述像素区域内的部分以使所述第一辅助线段非重叠于所述扫描线和所述数据线的重叠部分。
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