WO2016078204A1 - 一种液晶显示面板及阵列基板 - Google Patents

一种液晶显示面板及阵列基板 Download PDF

Info

Publication number
WO2016078204A1
WO2016078204A1 PCT/CN2015/070439 CN2015070439W WO2016078204A1 WO 2016078204 A1 WO2016078204 A1 WO 2016078204A1 CN 2015070439 W CN2015070439 W CN 2015070439W WO 2016078204 A1 WO2016078204 A1 WO 2016078204A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
pixel region
pixel
liquid crystal
region
Prior art date
Application number
PCT/CN2015/070439
Other languages
English (en)
French (fr)
Inventor
韩丙
王金杰
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/437,488 priority Critical patent/US20170140714A1/en
Publication of WO2016078204A1 publication Critical patent/WO2016078204A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0871—Several active elements per pixel in active matrix panels with level shifting

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a liquid crystal display panel and an array substrate.
  • the prior art In order to improve this situation, the prior art generally divides one pixel into three different sub-pixels, provides scan signals through three scan signal drive lines, and provides different signal voltages through three data signal drive lines.
  • the frequency of the data signal is three times the frequency of the scanning signal, and the lines are numerous and complicated, which increases the design cost.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display panel and an array substrate, which can solve the problem of large-view character bias, simplify circuit design, and reduce cost.
  • the present invention adopts a technical solution to provide a liquid crystal display panel, and the liquid crystal display panel includes:
  • the first substrate includes:
  • Each of the pixel regions includes at least a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region, and driving voltages of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region All are derived from a data voltage provided by the same data line corresponding to the pixel area, and when driving, the driving voltage of the first sub-pixel area is greater than the driving voltage of the second sub-pixel area, and the The driving voltage of the second pixel region is greater than the driving voltage of the third sub-pixel region.
  • the first sub-pixel region and the second sub-pixel region are respectively connected to one scan line corresponding to the pixel region and the data line corresponding to the pixel region, to utilize the pixel Controlling, by the scan line corresponding to the region, on and off of the first sub-pixel region and the second sub-pixel region, and conducting in the first sub-pixel region and the second sub-pixel region Writing a data voltage to the first sub-pixel region and the second sub-pixel region, respectively, by using the data line corresponding to the pixel region;
  • the third sub-pixel region is connected to a next scan line and the second sub-pixel region adjacent to the scan line corresponding to the pixel region to utilize the scan line corresponding to the pixel region Controlling conduction and deactivation of the third sub-pixel region by adjacent next scan lines, after the first sub-pixel region and the second sub-pixel region are written into the data voltage and in the
  • the second sub-pixel region charges the third sub-pixel region to lower the driving voltage of the second sub-pixel region; when the third sub-pixel region is turned off
  • the third sub-pixel region pulls down a driving voltage of the third sub-pixel region according to a charge coupling effect.
  • the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region respectively include a switching element, a liquid crystal capacitor, and a storage capacitor;
  • the gates of the switching elements of the first sub-pixel region and the second sub-pixel region are electrically connected to the scan lines corresponding to the pixel regions, and the sources thereof are electrically connected.
  • a drain of the switching element in the first sub-pixel region is respectively connected to the liquid crystal capacitor and the storage capacitor in the first sub-pixel region a first end, and a drain of the switching element in the second sub-pixel region is respectively connected to the liquid crystal capacitor in the second sub-pixel region and a first end of the storage capacitor;
  • a gate of the switching element in the third sub-pixel region is electrically connected to a next scan line adjacent to the scan line corresponding to the pixel region, and a source thereof is electrically connected to the second time
  • the liquid crystal capacitor in the pixel region and the first end of the storage capacitor, and the drain thereof is electrically connected to the liquid crystal capacitor in the third sub-pixel region and the first end of the storage capacitor,
  • the second ends of the storage capacitors in the first pixel region and the second sub-pixel region are electrically connected to the common line, respectively, and the second end of the storage capacitor in the third sub-pixel region is electrically connected
  • the next scan line adjacent to the scan line corresponding to the pixel area is connected.
  • the switching element of the first sub-pixel region and the switching element of the second sub-pixel region are the same switching element.
  • the switching elements in the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region are respectively implemented by using a thin film transistor.
  • the pixel electrode in each of the pixel regions is divided into a first sub-pixel electrode, a second sub-pixel electrode, and a third sub-pixel electrode, and the first sub-pixel electrode, the second sub-pixel electrode, and The third sub-pixel electrode is respectively used as a first end of the liquid crystal capacitor in the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region; and in the pixel region
  • the common electrode corresponds to the second end of the liquid crystal capacitor in the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region.
  • the pixel electrode and the common electrode in each of the pixel regions are disposed on the first substrate.
  • an array substrate and the array substrate includes:
  • Each of the pixel regions includes at least a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region, and driving voltages of the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region All are derived from a data voltage provided by the same data line corresponding to the pixel area, and when driving, the driving voltage of the first sub-pixel area is greater than the driving voltage of the second sub-pixel area, and the The driving voltage of the second pixel region is greater than the driving voltage of the third sub-pixel region.
  • the first sub-pixel region and the second sub-pixel region are respectively connected to one scan line corresponding to the pixel region and the data line corresponding to the pixel region, to utilize the pixel Controlling, by the scan line corresponding to the region, on and off of the first sub-pixel region and the second sub-pixel region, and conducting in the first sub-pixel region and the second sub-pixel region Writing a data voltage to the first sub-pixel region and the second sub-pixel region, respectively, by using the data line corresponding to the pixel region;
  • the third sub-pixel region is connected to a next scan line and the second sub-pixel region adjacent to the scan line corresponding to the pixel region to utilize the scan line corresponding to the pixel region Controlling conduction and deactivation of the third sub-pixel region by adjacent next scan lines, after the first sub-pixel region and the second sub-pixel region are written into the data voltage and in the
  • the second sub-pixel region charges the third sub-pixel region to lower the driving voltage of the second sub-pixel region; when the third sub-pixel region is turned off
  • the third sub-pixel region pulls down a driving voltage of the third sub-pixel region according to a charge coupling effect.
  • the first sub-pixel region, the second sub-pixel region, and the third sub-pixel region respectively include a switching element and a storage capacitor;
  • the gates of the switching elements of the first sub-pixel region and the second sub-pixel region are electrically connected to the scan lines corresponding to the pixel regions, and the sources thereof are electrically connected.
  • a drain of the switching element in the first sub-pixel region is connected to a first end of the storage capacitor in the first sub-pixel region, and a drain of the switching element in the second sub-pixel region is connected to a first end of the storage capacitor in the second sub-pixel region;
  • a gate of the switching element in the third sub-pixel region is electrically connected to a next scan line adjacent to the scan line corresponding to the pixel region, and a source thereof is electrically connected to the second time a first end of the storage capacitor in a pixel region, and a drain thereof electrically connected to a first end of the storage capacitor in the third sub-pixel region, the first sub-pixel region and the second a second end of the storage capacitor in the sub-pixel region is electrically connected to the common line, and a second end of the storage capacitor in the third sub-pixel region is electrically connected to the pixel region The next scan line adjacent to the scan line.
  • the present invention divides each pixel region into three sub-pixel regions, and when driving, causes the driving voltage of the first sub-pixel region to be greater than the second time.
  • the driving voltage of the pixel region, and the driving voltage of the second sub-pixel region is greater than the driving voltage of the third sub-pixel region, which can effectively improve the problem of the large-view character bias, and at the same time, the first sub-pixel in the present invention
  • the driving voltages of the region, the second sub-pixel region and the third sub-pixel region are all derived from the data voltages provided by the same data line corresponding to the pixel regions, thereby avoiding using three different data lines to respectively give three sub-pixels
  • the area provides the data voltage, which simplifies the circuit design and reduces the cost.
  • FIG. 1 is an equivalent circuit diagram of an embodiment of a first substrate in a liquid crystal display panel of the present invention
  • FIG 2 is an equivalent circuit diagram of an embodiment of an array substrate of the present invention.
  • Embodiments of the present invention provide a liquid crystal display panel including a first substrate and a second substrate disposed opposite to each other, and a liquid crystal layer interposed between the first substrate and the second substrate.
  • the first substrate is provided with a plurality of scan lines and a plurality of data lines, the scan lines and the data lines are disposed on a side of the first substrate adjacent to the liquid crystal layer, and the plurality of data lines and the plurality of scan lines cross each other to divide the liquid crystal display panel into a plurality of pixel regions; generally, more
  • the data lines are arranged in parallel with each other, and the plurality of scan lines are arranged in parallel with each other, and the data lines and the scan lines are perpendicularly intersected with each other.
  • the plurality of data lines and the plurality of scan lines may also be used in other manners. Arrangement.
  • each pixel region is divided into at least three sub-pixel regions: a first sub-pixel region Sub1, a second sub-pixel region Sub2, and a third sub-pixel region Sub3, a first sub-pixel region Sub1, and a second sub-pixel region Sub2
  • the driving voltage of the third sub-pixel area Sub3 is derived from the data voltage (ie, the pixel voltage or the display voltage) provided by the same data line D corresponding to the pixel area, that is, corresponding to the first sub-pixel area Sub1, the second time.
  • the pixel area Sub2 and the third sub-pixel area Sub3 have only one data line D, and when driving, the driving voltages of the first sub-pixel area Sub1, the second sub-pixel area Sub2, and the third sub-pixel area Sub3 are different.
  • the driving voltage of the first sub-pixel region Sub1 is larger than the driving voltage of the second sub-pixel region Sub2
  • the driving voltage of the second sub-pixel region Sub2 is larger than the driving voltage of the third sub-pixel region Sub3.
  • the embodiment of the present invention divides each pixel region into three sub-pixel regions.
  • the driving voltage of the first sub-pixel region Sub1 is greater than the driving voltage of the second sub-pixel region Sub2, and the second The driving voltage of the sub-pixel area Sub2 is larger than the driving voltage of the third sub-pixel area Sub3, which can effectively improve the problem of the large-view character bias.
  • the driving voltage of the pixel region Sub3 is derived from the data voltage provided by the same data line D corresponding to the pixel region, thereby avoiding the use of three different data lines to respectively supply data voltages to the three sub-pixel regions, so that the circuit design is obtained. Simplified and the cost is reduced.
  • the first sub-pixel area Sub1 and the second sub-pixel area Sub2 are respectively connected to one scan line G1 corresponding to the pixel area and the data line D corresponding to the pixel area to utilize the scan line G1 corresponding to the pixel area. Controlling the on and off of the first sub-pixel area Sub1 and the second sub-pixel area Sub2, and when the first sub-pixel area Sub1 and the second sub-pixel area Sub2 are turned on, using the data line D corresponding to the pixel area The material voltages are written into the first sub-pixel area Sub1 and the second sub-pixel area Sub2, respectively, so that the driving voltages of the first sub-pixel area Sub1 and the second sub-pixel area Sub2 are the same.
  • the third pixel area Sub3 is connected to the next scanning line G2 and the second sub-pixel area Sub2 adjacent to the scanning line G1 corresponding to the pixel area to utilize the next scanning line adjacent to the scanning line G1 corresponding to the pixel area G2 controls the turn-on and turn-off of the third sub-pixel region Sub3, and when the first sub-pixel region Sub1 and the second sub-pixel region Sub2 are written with the data voltage and the third sub-pixel region Sub3 is turned on, the second time
  • the pixel region Sub2 charges the third sub-pixel region Sub3 to lower the driving voltage of the second sub-pixel region Sub2 so that the driving voltage of the second sub-pixel region Sub2 is smaller than the driving voltage of the first sub-pixel region Sub1;
  • the third sub-pixel region Sub3 lowers the driving voltage of the third sub-pixel region Sub3 according to the charge coupling effect, so that the driving voltage of the third sub-pixel region Sub3 is smaller than the driving voltage of the second sub-pixel region Sub2.
  • the first sub-pixel area Sub1, the second sub-pixel area Sub2, and the third sub-pixel area Sub3 respectively include a switching element, a liquid crystal capacitor, and a storage capacitor, which are a first switching element T1, a second switching element T2, and a third switch, respectively.
  • the second sub-pixel region Sub2 and the third sub-pixel region Sub3 are turned on and off, and the liquid crystal capacitor is a capacitance generated by the liquid crystal layer between the first substrate and the second substrate.
  • the gates of the first switching element T1 and the second switching element T2 of the first pixel region Sub1 and the second sub-pixel region Sub2 are electrically connected to the scanning line G1 corresponding to the pixel region, and the sources thereof are electrically connected.
  • a data line D corresponding to the pixel region;
  • a drain of the first switching element T1 in the first sub-pixel region Sub1 is respectively connected to the first liquid crystal capacitor Clc1 and the first storage capacitor Cst1 in the first sub-pixel region Sub1
  • the drain of the second switching element T2 in the second sub-pixel region Sub2 is connected to the first end of the second liquid crystal capacitor Clc2 and the second storage capacitor Cst2 in the second sub-pixel region Sub2, respectively.
  • the gate of the third switching element T3 in the third pixel region Sub3 is electrically connected to the next scanning line G2 adjacent to the scanning line G1 corresponding to the pixel region, and the source thereof is electrically connected to the second sub-pixel region Sub2.
  • the first end of the second liquid crystal capacitor Clc2 and the second storage capacitor Cst2, and the drain thereof is electrically connected to the first end of the third liquid crystal capacitor Clc3 and the third storage capacitor Cst3 in the third sub-pixel region Sub3, first The second ends of the first storage capacitor Cst1 and the second storage capacitor Cst2 in the sub-pixel area Sub1 and the second sub-pixel area Sub2 are electrically connected to the common line COM respectively, and the common line has a common electrode layer on the second substrate The same voltage is applied, and the second end of the third storage capacitor Cst3 in the third sub-pixel region Sub3 is electrically connected to the next scan line G2 adjacent to the scan line G1 corresponding to the pixel region.
  • the first switching element T1 corresponding to the first sub-pixel area Sub1 and the second switching element T2 corresponding to the second sub-pixel area Sub2 are turned on, and the data line corresponding to the pixel area
  • the first liquid crystal capacitor Cl1, the first storage capacitor Cst1, the second liquid crystal capacitor Clc2, and the second storage capacitor Cst2 are charged by the first switching element T1 and the second switching element T2, so that the driving voltage of the first sub-pixel region Sub1 and the first The driving voltages of the secondary pixel region Sub2 are equal.
  • the third switching element T3 When the scanning signal is scanned to the next scanning line G2 adjacent to the scanning line G1 corresponding to the pixel region, the third switching element T3 is turned on, and the second liquid crystal capacitor Clc2 and the second The storage capacitor Cst2 charges the third liquid crystal capacitor Clc3 and the third storage capacitor Cst3 through the third switching element T3, so that the driving voltage of the second sub-pixel region Sub2 is less than the driving voltage of the first sub-pixel region Sub1, when the scanning signal continues When scanning to the next scan line, the next scan line G2 adjacent to the scan line G1 corresponding to the pixel area is electrically connected to the second end of the third storage capacitor Cst3. The voltage of the trace line G2 will be lowered.
  • the voltage of the third storage capacitor Cst3 will also decrease, and the voltage of the third storage capacitor Cst3 connected to the third liquid crystal capacitor Clc3 will also be The lowering causes the driving voltage of the third sub-pixel region Sub3 to be lower than the driving voltage of the second sub-pixel region Sub2 as a whole.
  • the switching elements of the first sub-pixel region Sub1 and the switching elements of the second sub-pixel region Sub2 are the same switching element (not shown), that is, the first sub-pixel region Sub1 A switching element is shared with the second pixel area Sub2, which further simplifies the design and saves costs.
  • the gate of the switching element is electrically connected to the scan line G1 corresponding to the pixel region, and the source thereof is electrically connected to the data line D corresponding to the pixel region;
  • the drains of the switching elements are respectively connected a first liquid crystal capacitor Clc1 in the primary pixel region Sub1 and a first end of the first storage capacitor Cst1 and a second liquid crystal capacitor Clc2 and a second storage capacitor Cst2 in the second sub-pixel region Sub2;
  • the gate of the third switching element T3 in the pixel region Sub3 is electrically connected to the next scanning line G2 adjacent to the scanning line G1 corresponding to the pixel region, and the source thereof is electrically connected to the second of the second sub-pixel region Sub2.
  • the first switching element T1, the second switching element T2, and the third switching element T3 in the first sub-pixel region Sub1, the second sub-pixel region Sub2, and the third sub-pixel region Sub3 are realized by thin film transistors, respectively.
  • the pixel electrode in each pixel region is divided into a first sub-pixel electrode, a second sub-pixel electrode, and a third sub-pixel electrode, and the first sub-pixel electrode, the second sub-pixel electrode, and the third sub-pixel electrode respectively The first end of the liquid crystal capacitor in the first sub-pixel area Sub1, the second sub-pixel area Sub2, and the third sub-pixel area Sub3; and the common electrode in the pixel area corresponds to the first sub-pixel area Sub1 and the second sub-pixel The second end of the liquid crystal capacitor in the region Sub2 and the third sub-pixel region Sub3.
  • the pixel electrode and the common electrode in each pixel region are disposed on the first substrate.
  • the specific process of the first substrate in the embodiment of the present invention is: forming a PEP ((photo-etching-process)) layer on the glass substrate by exposure, development, etching, etc., as a scan line electrode and a common electrode, and then TFT (Thin Film Transistor, thin film transistor) is formed into a PEP2 layer, and then a data line electrode and a TFT are formed by a metal material, and a via hole, that is, a PEP 4 layer, is formed at a position where metal conduction is required, and finally a pixel electrode, that is, an ITO (Indium Tin Oxide) layer is completed.
  • PEP5 photo-etching-process
  • Another embodiment of the present invention provides an array substrate including a plurality of scan lines and a plurality of data lines, wherein the plurality of data lines and the plurality of scan lines cross each other to divide the liquid crystal display panel into a plurality of pixel regions; generally, The data lines are arranged in parallel with each other, and the plurality of scan lines are arranged in parallel with each other, and the data lines and the scan lines are perpendicularly intersected with each other. In other embodiments, the plurality of data lines and the plurality of scan lines may also be used in other manners. Arrangement.
  • each pixel region is divided into at least three sub-pixel regions: a first sub-pixel region Sub1, a second sub-pixel region Sub2, and a third sub-pixel region Sub3, a first sub-pixel region Sub1, a second sub-pixel region Sub2
  • the driving voltage of the third sub-pixel region Sub3 is derived from the data voltage (ie, pixel voltage, display voltage) provided by the same data line D corresponding to the pixel region, that is, corresponding to the first sub-pixel region Sub1 and the second sub-pixel.
  • the area Sub2 and the third sub-pixel area Sub3 have only one data line D, and when driving, the driving voltages of the first sub-pixel area Sub1, the second sub-pixel area Sub2, and the third sub-pixel area Sub3 are different.
  • the driving voltage of the first sub-pixel region Sub1 is greater than the driving voltage of the second sub-pixel region Sub2
  • the driving voltage of the second sub-pixel region Sub2 is greater than the driving voltage of the third sub-pixel region Sub3.
  • the embodiment of the present invention divides each pixel region into three sub-pixel regions.
  • the driving voltage of the first sub-pixel region Sub1 is greater than the driving voltage of the second sub-pixel region Sub2, and the second The driving voltage of the sub-pixel area Sub2 is larger than the driving voltage of the third sub-pixel area Sub3, which can effectively improve the problem of the large-view character bias.
  • the driving voltage of the pixel region Sub3 is derived from the data voltage provided by the same data line corresponding to the pixel region, thereby avoiding the use of three different data lines to respectively supply the data voltage to the three sub-pixel regions, thereby simplifying the circuit design. The cost is reduced.
  • the first sub-pixel area Sub1 and the second sub-pixel area Sub2 are respectively connected to one scan line G1 corresponding to the pixel area and the data line D corresponding to the pixel area to utilize the scan line G1 corresponding to the pixel area. Controlling the on and off of the first sub-pixel area Sub1 and the second sub-pixel area Sub2, and when the first sub-pixel area Sub1 and the second sub-pixel area Sub2 are turned on, using the data line D corresponding to the pixel area The material voltages are written into the first sub-pixel area Sub1 and the second sub-pixel area Sub2, respectively, so that the driving voltages of the first sub-pixel area Sub1 and the second sub-pixel area Sub2 are the same.
  • the third pixel area Sub3 is connected to the next scanning line G2 and the second sub-pixel area Sub2 adjacent to the scanning line G1 corresponding to the pixel area to utilize the next scanning line adjacent to the scanning line G1 corresponding to the pixel area G2 controls the turn-on and turn-off of the third sub-pixel region Sub3, and when the first sub-pixel region Sub1 and the second sub-pixel region Sub2 are written with the data voltage and the third sub-pixel region Sub3 is turned on, the second time
  • the pixel region Sub2 charges the third sub-pixel region Sub3 to lower the driving voltage of the second sub-pixel region Sub2 so that the driving voltage of the second sub-pixel region Sub2 is smaller than the driving voltage of the first sub-pixel region Sub1;
  • the third sub-pixel region Sub3 lowers the driving voltage of the third sub-pixel region Sub3 according to the charge coupling effect, so that the driving voltage of the third sub-pixel region Sub3 is smaller than the second sub-pixel region.
  • the first sub-pixel area Sub1, the second sub-pixel area Sub2, and the third sub-pixel area Sub3 respectively include switching elements T1, T2, T3 and storage capacitors Cst1, Cst2, Cst3; the switching element is used to control the first sub-pixel area The turn-on and turn-off of Sub1, the second sub-pixel area Sub2, and the third sub-pixel area Sub3.
  • the gates of the switching elements T1 and T2 of the first pixel region Sub1 and the second sub-pixel region Sub2 are electrically connected to the scanning line G1 corresponding to the pixel region, and the source thereof is electrically connected to the pixel region.
  • the data line D; the drain of the switching element T1 in the first sub-pixel area Sub1 is connected to the first end of the storage capacitor Cst1 in the first sub-pixel area Sub1, and the drain of the switching element T2 in the second sub-pixel area Sub2
  • the first end of the storage capacitor Cst2 in the second sub-pixel area Sub2 is connected.
  • the gate of the switching element T3 in the third pixel region Sub3 is electrically connected to the next scanning line G2 adjacent to the scanning line G1 corresponding to the pixel region, and the source thereof is electrically connected to the storage in the second sub-pixel region Sub2.
  • the first end of the capacitor Cst2, and the drain thereof is electrically connected to the first end of the storage capacitor Cst3 in the third sub-pixel region Sub3, and the second end of the storage capacitor in the first sub-pixel region Sub1 and the second sub-pixel region Sub2
  • the second ends of the storage capacitors Cst3 in the third sub-pixel region Sub3 are electrically connected to the next scan line G2 adjacent to the scan lines corresponding to the pixel regions.
  • the switching element T1 corresponding to the first sub-pixel area Sub1 and the switching element T2 corresponding to the second sub-pixel area Sub2 are turned on, and the data line corresponding to the pixel area passes through the pair of switching elements.
  • the storage capacitors in the first pixel region Sub1 and the second sub-pixel region Sub2 are charged such that the driving voltage of the first sub-pixel region Sub1 and the driving voltage of the second sub-pixel region Sub2 are equal, when the scanning signal is scanned to the pixel region
  • the switching element T3 of the third sub-pixel area Sub3 is turned on, and the storage capacitor Cst2 of the second sub-pixel area Sub2 passes through the switching element of the third sub-pixel area Sub3 to the third
  • the storage capacitor of the sub-pixel region Sub3 is charged such that the driving voltage of the second sub-pixel region Sub2 is less than the driving voltage of the first sub-pixel region Sub1, and corresponds to the pixel region when the scanning signal continues to scan to the next scanning line.
  • the next scan line adjacent to the scan line that is, the second end of the storage capacitor of the third sub-pixel area Sub3 is electrically connected to the scan line G2, and the voltage will drop. Since it is connected to the storage capacitor Cst3 of the third sub-pixel region Sub3, the voltage of the storage capacitor of the third sub-pixel region Sub3 is also lowered, so that the driving voltage of the third sub-pixel region Sub3 is reduced to the second time.
  • the driving voltage of the pixel area Sub2 is small.
  • the switching elements of the first sub-pixel region Sub1 and the switching elements of the second sub-pixel region Sub2 are the same switching element, that is, the first sub-pixel region Sub1 and the second sub-pixel region Sub2. Sharing one switching element further simplifies the design and saves costs.
  • the gate of the switching element is electrically connected to the scan line G1 corresponding to the pixel region, and the source thereof is electrically connected to the data line D corresponding to the pixel region;
  • the drains of the switching elements are respectively connected The first end of the storage capacitor Cst1 in the primary pixel area Sub1 and the first end of the storage capacitor Cst2 in the second sub-pixel area Sub2;
  • the gate of the third switching element T3 in the third sub-pixel area Sub3 is electrically connected
  • the next scan line G2 adjacent to the scan line G1 corresponding to the pixel region is electrically connected to the first end of the storage capacitor Cst2 in the second sub-pixel region Sub2, and the drain thereof is electrically connected to the third sub-pixel.
  • the first end of the storage capacitor Cst3 in the area Sub3, the second end of the first storage capacitor Cst1 and the second storage capacitor Cst2 in the first sub-pixel area Sub1 and the second sub-pixel area Sub2 are electrically connected to the common line COM, respectively.
  • the second end of the third storage capacitor Cst3 in the third sub-pixel region Sub3 is electrically connected to the next scan line G2 adjacent to the scan line G1 corresponding to the pixel region.
  • the first switching element, the second switching element, and the third switching element in the first sub-pixel region Sub1, the second sub-pixel region Sub2, and the third sub-pixel region Sub3 are realized by thin film transistors, respectively.
  • the specific process of the array substrate in the embodiment of the present invention is: forming a PEP ((photo-etching-process)) layer on the glass substrate by exposure, development, etching, etc., as a scan line electrode and a common electrode, and then in the TFT.
  • PEP photo-etching-process
  • TFT TFT
  • Thin Film Transistor, thin film transistor is formed into a PEP2 layer, and then a data line electrode and a TFT are formed by a metal material, and a via hole, that is, a PEP 4 layer, is formed at a position where metal conduction is required, and finally a pixel electrode, that is, an ITO (Indium Tin Oxide) layer is completed.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Power Engineering (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种液晶显示面板即阵列基板，所述液晶显示面板第一基板、第二基板以及夹设在第一基板和第二基板之间的液晶层，第一基板包括多条扫描线（G1，G2）和多条数据线（D），其中，每个所述像素区域至少包括第一次像素区域（Sub1）、第二次像素区域（Sub2）和第三次像素区域（Sub3），所述第一次像素区域（Sub1）、第二次像素区域（Sub2）和第三次像素区域（Sub3）的驱动电压均源自所述像素区域所对应的同一条数据线（D）所提供的资料电压，且在驱动时，所述第一次像素区域（Sub1）的驱动电压大于所述第二次像素区域（Sub2）的驱动电压，而所述第二次像素区域（Sub2）的驱动电压大于所述第三次像素区域（Sub3）的驱动电压。通过上述方式，能解决大视角色偏问题，同时简化线路设计，降低成本。

Description

一种液晶显示面板及阵列基板
【技术领域】
本发明涉及液晶显示器技术领域，特别是涉及一种液晶显示面板及阵列基板。
【背景技术】
因为液晶显示的内在因素，在液晶显示器不同位置观察到的图像始终会存在差异，在正视观察到正常的图片在大视角的情况下显示不正常，这就是液晶显示器大视角色偏问题。
为了改善这种状况，现有技术通常是将一个像素分成三个不同的子像素，通过三条扫描信号驱动线提供扫描信号，并通过三条数据信号驱动线来提供不同的信号电压，这种方式中，数据信号的频率为扫描信号频率的三倍，且线路众多繁杂，增加了设计成本。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示面板及阵列基板，能够解决大视角色偏问题，同时简化线路设计，降低成本。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种液晶显示面板，所述液晶显示面板包括：
第一基板，包括：
多条扫描线，设置在所述第一基板上；
多条数据线，设置在所述第一基板上，且所述多条数据线与所述多条扫描线相互交叉以将所述液晶显示面板划分成多个像素区域；
第二基板，与所述第一基板相对设置；
液晶层，夹设在所述第一基板与所述第二基板之间；
其中，每个所述像素区域至少包括第一次像素区域、第二次像素区域和第三次像素区域，所述第一次像素区域、第二次像素区域和第三次像素区域的驱动电压均源自所述像素区域所对应的同一条数据线所提供的资料电压，且在驱动时，所述第一次像素区域的驱动电压大于所述第二次像素区域的驱动电压，而所述第二次像素区域的驱动电压大于所述第三次像素区域的驱动电压。
其中，所述第一次像素区域和所述第二次像素区域分别连接与所述像素区域相对应的一条扫描线和与所述像素区域相对应的所述数据线，以利用与所述像素区域相对应的所述扫描线而控制所述第一次像素区域和所述第二次像素区域的导通和截止，并在所述第一次像素区域和所述第二次像素区域导通时，利用与所述像素区域相对应的所述数据线而将资料电压分别写入所述第一次像素区域和所述第二次像素区域；
所述第三次像素区域连接与所述像素区域相对应的所述扫描线相邻的下一条扫描线和所述第二次像素区域，以利用与所述像素区域相对应的所述扫描线相邻的下一条扫描线而控制所述第三次像素区域的导通和截止，当所述第一次像素区域和所述第二次像素区域被写入所述资料电压后且在所述第三次像素区域导通时，所述第二次像素区域对所述第三次像素区域进行充电以拉低所述第二次像素区域的驱动电压；当所述第三次像素区域截止时，所述第三次像素区域根据电荷耦合效应从而拉低所述第三次像素区域的驱动电压。
其中，所述第一次像素区域、所述第二次像素区域和所述第三次像素区域分别包括开关元件、液晶电容和存储电容；
其中，所述第一次像素区域和所述第二次像素区域的所述开关元件的栅极均电性连接与所述像素区域相对应的所述扫描线，而其源极均电性连接与所述像素区域相对应的所述数据线；所述第一次像素区域中的所述开关元件的漏极分别连接所述第一次像素区域中的所述液晶电容和所述存储电容的第一端，而所述第二次像素区域中的所述开关元件的漏极分别连接所述第二次像素区域中的所述液晶电容和所述存储电容的第一端；
所述第三次像素区域中的所述开关元件的栅极电性连接与所述像素区域相对应的所述扫描线相邻的下一条扫描线，其源极电性连接所述第二次像素区域中的所述液晶电容和所述存储电容的第一端，而其漏极电性连接所述第三次像素区域中的所述液晶电容和所述存储电容的第一端，所述第一次像素区域和所述第二次像素区域中的所述存储电容的第二端分别电性连接至公共线，而所述第三次像素区域中的所述存储电容的第二端电性连接与所述像素区域相对应的所述扫描线相邻的下一条扫描线。
其中，所述第一次像素区域的开关元件与所述第二次像素区域的开关元件为同一个开关元件。
其中，所述第一次像素区域、所述第二次像素区域和所述第三次像素区域中的所述开关元件分别采用薄膜晶体管而实现。
其中，每个所述像素区域中的像素电极被划分成第一次像素电极、第二次像素电极和第三次像素电极，且所述第一次像素电极、所述第二次像素电极和所述第三次像素电极分别作为所述第一次像素区域、所述第二次像素区域和所述第三次像素区域中的所述液晶电容的第一端；而所述像素区域中的公共电极对应作为所述第一次像素区域、所述第二次像素区域和所述第三次像素区域中的所述液晶电容的第二端。
其中，每个所述像素区域中的像素电极和公共电极均设置在所述第一基板上。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，所述阵列基板包括：
多条扫描线；
多条数据线，与所述多条扫描线相互交叉以将所述阵列基板划分成多个像素区域；
其中，每个所述像素区域至少包括第一次像素区域、第二次像素区域和第三次像素区域，所述第一次像素区域、第二次像素区域和第三次像素区域的驱动电压均源自所述像素区域所对应的同一条数据线所提供的资料电压，且在驱动时，所述第一次像素区域的驱动电压大于所述第二次像素区域的驱动电压，而所述第二次像素区域的驱动电压大于所述第三次像素区域的驱动电压。
其中，所述第一次像素区域和所述第二次像素区域分别连接与所述像素区域相对应的一条扫描线和与所述像素区域相对应的所述数据线，以利用与所述像素区域相对应的所述扫描线而控制所述第一次像素区域和所述第二次像素区域的导通和截止，并在所述第一次像素区域和所述第二次像素区域导通时，利用与所述像素区域相对应的所述数据线而将资料电压分别写入所述第一次像素区域和所述第二次像素区域；
所述第三次像素区域连接与所述像素区域相对应的所述扫描线相邻的下一条扫描线和所述第二次像素区域，以利用与所述像素区域相对应的所述扫描线相邻的下一条扫描线而控制所述第三次像素区域的导通和截止，当所述第一次像素区域和所述第二次像素区域被写入所述资料电压后且在所述第三次像素区域导通时，所述第二次像素区域对所述第三次像素区域进行充电以拉低所述第二次像素区域的驱动电压；当所述第三次像素区域截止时，所述第三次像素区域根据电荷耦合效应从而拉低所述第三次像素区域的驱动电压。
其中，所述第一次像素区域、所述第二次像素区域和所述第三次像素区域分别包括开关元件和存储电容；
其中，所述第一次像素区域和所述第二次像素区域的所述开关元件的栅极均电性连接与所述像素区域相对应的所述扫描线，而其源极均电性连接与所述像素区域相对应的所述数据线；所述第一次像素区域中的所述开关元件的漏极连接所述第一次像素区域中的所述存储电容的第一端，而所述第二次像素区域中的所述开关元件的漏极连接所述第二次像素区域中的所述存储电容的第一端；
所述第三次像素区域中的所述开关元件的栅极电性连接与所述像素区域相对应的所述扫描线相邻的下一条扫描线，其源极电性连接所述第二次像素区域中的所述存储电容的第一端，而其漏极电性连接所述第三次像素区域中的所述存储电容的第一端，所述第一次像素区域和所述第二次像素区域中的所述存储电容的第二端分别电性连接至公共线，而所述第三次像素区域中的所述存储电容的第二端电性连接与所述像素区域相对应的所述扫描线相邻的下一条扫描线。
本发明的有益效果是：区别于现有技术的情况，本发明将每个像素区域分成三个次像素区域，在驱动时，使所述第一次像素区域的驱动电压大于所述第二次像素区域的驱动电压，而所述第二次像素区域的驱动电压大于所述第三次像素区域的驱动电压，可有效改善大视角色偏的问题，同时，本发明中所述第一次像素区域、第二次像素区域和第三次像素区域的驱动电压均源自所述像素区域所对应的同一条数据线所提供的资料电压，避免了使用三条不同的数据线分别给三个次像素区域提供资料电压的情况，使线路设计得到简化，成本得到降低。
【附图说明】
图1是本发明液晶显示面板中第一基板一实施方式的等效电路图；
图2是本发明阵列基板一实施方式的等效电路图。
【具体实施方式】
本发明实施方式提供一种液晶显示面板，包括相对设置的第一基板和第二基板以及夹设在第一基板与第二基板之间的液晶层，第一基板上设有多条扫描线和多条数据线，扫描线和数据线设在第一基板的靠近液晶层的一面，且多条数据线与多条扫描线相互交叉以将液晶显示面板划分成多个像素区域；一般地，多条数据线之间相互平行设置，多条扫描线之间相互平行设置，数据线和扫描线之间相互垂直交叉，在其它实施方式中，多条数据线和多条扫描线也可采用其它的布置方式。
如图1，每个像素区域分成至少三个次像素区域：第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3，第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3的驱动电压均源自像素区域所对应的同一条数据线D所提供的资料电压（即像素电压、或者显示电压），即对应第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3只有一条数据线D，且在驱动时，使第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3的驱动电压各不相同，在本实施方式中，第一次像素区域Sub1的驱动电压大于第二次像素区域Sub2的驱动电压，而第二次像素区域Sub2的驱动电压大于第三次像素区域Sub3的驱动电压。
区别于现有技术，本发明实施方式将每个像素区域分成三个次像素区域，在驱动时，使第一次像素区域Sub1的驱动电压大于第二次像素区域Sub2的驱动电压，而第二次像素区域Sub2的驱动电压大于第三次像素区域Sub3的驱动电压，可有效改善大视角色偏的问题，同时，本发明中第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3的驱动电压均源自像素区域所对应的同一条数据线D所提供的资料电压，避免了使用三条不同的数据线分别给三个次像素区域提供资料电压的情况，使线路设计得到简化，成本得到降低。
其中，第一次像素区域Sub1和第二次像素区域Sub2分别连接与像素区域相对应的一条扫描线G1和与像素区域相对应的数据线D，以利用与像素区域相对应的扫描线G1而控制第一次像素区域Sub1和第二次像素区域Sub2的导通和截止，并在第一次像素区域Sub1和第二次像素区域Sub2导通时，利用与像素区域相对应的数据线D而将资料电压分别写入第一次像素区域Sub1和第二次像素区域Sub2，使第一次像素区域Sub1和第二次像素区域Sub2的驱动电压相同。
第三次像素区域Sub3连接与像素区域相对应的扫描线G1相邻的下一条扫描线G2和第二次像素区域Sub2，以利用与像素区域相对应的扫描线G1相邻的下一条扫描线G2而控制第三次像素区域Sub3的导通和截止，当第一次像素区域Sub1和第二次像素区域Sub2被写入资料电压后且在第三次像素区域Sub3导通时，第二次像素区域Sub2对第三次像素区域Sub3进行充电以拉低第二次像素区域Sub2的驱动电压，使第二次像素区域Sub2的驱动电压小于第一次像素区域Sub1的驱动电压；当第三次像素区域Sub3截止时，第三次像素区域Sub3根据电荷耦合效应从而拉低第三次像素区域Sub3的驱动电压，使第三次像素区域Sub3的驱动电压小于第二次像素区域Sub2的驱动电压。
其中，第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3分别包括开关元件、液晶电容和存储电容，分别为第一开关元件T1、第二开关元件T2、第三开关元件T3，第一液晶电容Clc1、第二液晶电容Clc2、第三液晶电容Clc3，第一存储电容Cst1、第二存储电容Cst2、第三存储电容Cst3；开关元件用于控制第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3的导通和截止，液晶电容为第一基板和第二基板之间的液晶层产生的电容。
第一次像素区域Sub1和第二次像素区域Sub2的第一开关元件T1和第二开关元件T2的栅极均电性连接与像素区域相对应的扫描线G1，而其源极均电性连接与像素区域相对应的数据线D；第一次像素区域Sub1中的第一开关元件T1的漏极分别连接第一次像素区域Sub1中的第一液晶电容Clc1和第一存储电容Cst1的第一端，而第二次像素区域Sub2中的第二开关元件T2的漏极分别连接第二次像素区域Sub2中的第二液晶电容Clc2和第二存储电容Cst2的第一端。
第三次像素区域Sub3中的第三开关元件T3的栅极电性连接与像素区域相对应的扫描线G1相邻的下一条扫描线G2，其源极电性连接第二次像素区域Sub2中的第二液晶电容Clc2和第二存储电容Cst2的第一端，而其漏极电性连接第三次像素区域Sub3中的第三液晶电容Clc3和第三存储电容Cst3的第一端，第一次像素区域Sub1和第二次像素区域Sub2中的第一存储电容Cst1和第二存储电容Cst2的第二端分别电性连接至公共线COM，该公共线具有与第二基板上的公共电极层相同的电压，而第三次像素区域Sub3中的第三存储电容Cst3的第二端电性连接与像素区域相对应的扫描线G1相邻的下一条扫描线G2。
当扫描信号扫描到像素区域对应的扫描线G1时，第一次像素区域Sub1对应的第一开关元件T1和第二次像素区域Sub2对应的第二开关元件T2导通，像素区域对应的数据线通过第一开关元件T1和第二开关元件T2对第一液晶电容Clc1、第一存储电容Cst1、第二液晶电容Clc2和第二存储电容Cst2充电，使第一次像素区域Sub1的驱动电压和第二次像素区域Sub2的驱动电压相等，当扫描信号扫描到与像素区域相对应的扫描线G1相邻的下一条扫描线G2时，第三开关元件T3导通，第二液晶电容Clc2和第二存储电容Cst2通过第三开关元件T3给第三液晶电容Clc3和第三存储电容Cst3充电，使第二次像素区域Sub2的驱动电压将至小于第一次像素区域Sub1的驱动电压，当扫描信号继续扫描到下一条扫描线时，与像素区域相对应的扫描线G1相邻的下一条扫描线G2，即与第三存储电容Cst3的第二端电性连接扫描线G2电压将会降低，由于其与第三存储电容Cst3连接，则第三存储电容Cst3的电压也会跟着降低，而第三存储电容Cst3又将与其连接的第三液晶电容Clc3的电压也降低，使第三次像素区域Sub3的驱动电压整体降低至比第二次像素区域Sub2的驱动电压小。
其中，在本发明的其它实施方式中，第一次像素区域Sub1的开关元件与第二次像素区域Sub2的开关元件为同一个开关元件（图中未示出），即第一次像素区域Sub1和第二次像素区域Sub2共用一个开关元件，这样能进一步简化设计，节省成本。在这种情况下，该开关元件的栅极电性连接像素区域对应的扫描线G1，而其源极均电性连接与像素区域相对应的数据线D；该开关元件的漏极分别连接第一次像素区域Sub1中的第一液晶电容Clc1和第一存储电容Cst1的第一端和第二次像素区域Sub2中的第二液晶电容Clc2和第二存储电容Cst2的第一端；第三次像素区域Sub3中的第三开关元件T3的栅极电性连接与像素区域相对应的扫描线G1相邻的下一条扫描线G2，其源极电性连接第二次像素区域Sub2中的第二液晶电容Clc2和第二存储电容Cst2的第一端，而其漏极电性连接第三次像素区域Sub3中的第三液晶电容Clc3和第三存储电容Cst3的第一端，第一次像素区域Sub1和第二次像素区域Sub2中的第一存储电容Cst1和第二存储电容Cst2的第二端分别电性连接至公共线COM，该公共线具有与第二基板上的公共电极层相同的电压，而第三次像素区域Sub3中的第三存储电容Cst3的第二端电性连接与像素区域相对应的扫描线G1相邻的下一条扫描线G2。
其中，第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3中的第一开关元件T1、第二开关元件T2和第三开关元件T3分别采用薄膜晶体管而实现。
其中，每个像素区域中的像素电极被划分成第一次像素电极、第二次像素电极和第三次像素电极，且第一次像素电极、第二次像素电极和第三次像素电极分别作为第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3中的液晶电容的第一端；而像素区域中的公共电极对应作为第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3中的液晶电容的第二端。
其中，每个像素区域中的像素电极和公共电极均设置在第一基板上。
本发明实施方式第一基板的具体制程为：在玻璃基板上先通过曝光显影蚀刻等步骤形成PEP（(photo-etching-process，光蚀刻工艺）1层，作为扫描线电极和公共电极，然后在TFT（Thin Film Transistor，薄膜晶体管）位置形成PEP2层，接下来用金属材料形成数据线电极和TFT，在需要金属导通的位置形成导通孔，即PEP4层，最后完成像素电极即ITO（氧化铟锡）层PEP5。
本发明另一个实施方式提供一种阵列基板，包括多条扫描线和多条数据线，多条数据线与多条扫描线相互交叉以将液晶显示面板划分成多个像素区域；一般地，多条数据线之间相互平行设置，多条扫描线之间相互平行设置，数据线和扫描线之间相互垂直交叉，在其它实施方式中，多条数据线和多条扫描线也可采用其它的布置方式。
参阅图2，每个像素区域分成至少三个次像素区域：第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3，第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3的驱动电压均源自像素区域所对应的同一条数据线D所提供的资料电压（即像素电压、显示电压），即对应第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3只有一条数据线D，且在驱动时，使第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3的驱动电压各不相同，在本实施方式中，第一次像素区域Sub1的驱动电压大于第二次像素区域Sub2的驱动电压，而第二次像素区域Sub2的驱动电压大于第三次像素区域Sub3的驱动电压。
区别于现有技术，本发明实施方式将每个像素区域分成三个次像素区域，在驱动时，使第一次像素区域Sub1的驱动电压大于第二次像素区域Sub2的驱动电压，而第二次像素区域Sub2的驱动电压大于第三次像素区域Sub3的驱动电压，可有效改善大视角色偏的问题，同时，本发明中第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3的驱动电压均源自像素区域所对应的同一条数据线所提供的资料电压，避免了使用三条不同的数据线分别给三个次像素区域提供资料电压的情况，使线路设计得到简化，成本得到降低。
其中，第一次像素区域Sub1和第二次像素区域Sub2分别连接与像素区域相对应的一条扫描线G1和与像素区域相对应的数据线D，以利用与像素区域相对应的扫描线G1而控制第一次像素区域Sub1和第二次像素区域Sub2的导通和截止，并在第一次像素区域Sub1和第二次像素区域Sub2导通时，利用与像素区域相对应的数据线D而将资料电压分别写入第一次像素区域Sub1和第二次像素区域Sub2，使第一次像素区域Sub1和第二次像素区域Sub2的驱动电压相同。
第三次像素区域Sub3连接与像素区域相对应的扫描线G1相邻的下一条扫描线G2和第二次像素区域Sub2，以利用与像素区域相对应的扫描线G1相邻的下一条扫描线G2而控制第三次像素区域Sub3的导通和截止，当第一次像素区域Sub1和第二次像素区域Sub2被写入资料电压后且在第三次像素区域Sub3导通时，第二次像素区域Sub2对第三次像素区域Sub3进行充电以拉低第二次像素区域Sub2的驱动电压，使第二次像素区域Sub2的驱动电压小于第一次像素区域Sub1的驱动电压；当第三次像素区域Sub3截止时，第三次像素区域Sub3根据电荷耦合效应从而拉低第三次像素区域Sub3的驱动电压，使第三次像素区域Sub3的驱动电压小于第二次像素区
其中，第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3分别包括开关元件T1、T2、T3和存储电容Cst1、Cst2、Cst3；开关元件用于控制第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3的导通和截止。
第一次像素区域Sub1和第二次像素区域Sub2的开关元件T1、T2的栅极均电性连接与像素区域相对应的扫描线G1，而其源极均电性连接与像素区域相对应的数据线D；第一次像素区域Sub1中的开关元件T1的漏极连接第一次像素区域Sub1中的存储电容Cst1的第一端，而第二次像素区域Sub2中的开关元件T2的漏极连接第二次像素区域Sub2中的存储电容Cst2的第一端。
第三次像素区域Sub3中的开关元件T3的栅极电性连接与像素区域相对应的扫描线G1相邻的下一条扫描线G2，其源极电性连接第二次像素区域Sub2中的存储电容Cst2的第一端，而其漏极电性连接第三次像素区域Sub3中的存储电容Cst3的第一端，第一次像素区域Sub1和第二次像素区域Sub2中的存储电容第二端分别电性连接至公共线COM，而第三次像素区域Sub3中的存储电容Cst3的第二端电性连接与像素区域相对应的扫描线相邻的下一条扫描线G2。
当扫描信号扫描到像素区域对应的扫描线G1时，第一次像素区域Sub1对应的开关元件T1和第二次像素区域Sub2对应的开关元件T2导通，像素区域对应的数据线通过开关元件对第一次像素区域Sub1和第二次像素区域Sub2中的存储电容充电，使第一次像素区域Sub1的驱动电压和第二次像素区域Sub2的驱动电压相等，当扫描信号扫描到与像素区域相对应的扫描线相邻的下一条扫描线G2时，第三次像素区域Sub3的开关元件T3导通，第二次像素区域Sub2的存储电容Cst2通过第三次像素区域Sub3的开关元件给第三次像素区域Sub3的存储电容充电，使第二次像素区域Sub2的驱动电压将至小于第一次像素区域Sub1的驱动电压，当扫描信号继续扫描到下一条扫描线时，与像素区域相对应的扫描线相邻的下一条扫描线，即与第三次像素区域Sub3的存储电容的第二端电性连接扫描线G2电压将会降低，由于其与第三次像素区域Sub3的存储电容Cst3连接，则第三次像素区域Sub3的存储电容的电压也会跟着降低，使第三次像素区域Sub3的驱动电压整体降低至比第二次像素区域Sub2的驱动电压小。
其中，在本发明的其它实施方式中，第一次像素区域Sub1的开关元件与第二次像素区域Sub2的开关元件为同一个开关元件，即第一次像素区域Sub1和第二次像素区域Sub2共用一个开关元件，这样能进一步简化设计，节省成本。在这种情况下，该开关元件的栅极电性连接像素区域对应的扫描线G1，而其源极均电性连接与像素区域相对应的数据线D；该开关元件的漏极分别连接第一次像素区域Sub1中的存储电容Cst1的第一端和第二次像素区域Sub2中的存储电容Cst2的第一端；第三次像素区域Sub3中的第三开关元件T3的栅极电性连接与像素区域相对应的扫描线G1相邻的下一条扫描线G2，其源极电性连接第二次像素区域Sub2中存储电容Cst2的第一端，而其漏极电性连接第三次像素区域Sub3中的存储电容Cst3的第一端，第一次像素区域Sub1和第二次像素区域Sub2中的第一存储电容Cst1和第二存储电容Cst2的第二端分别电性连接至公共线COM，而第三次像素区域Sub3中的第三存储电容Cst3的第二端电性连接与像素区域相对应的扫描线G1相邻的下一条扫描线G2。
其中，第一次像素区域Sub1、第二次像素区域Sub2和第三次像素区域Sub3中的第一开关元件、第二开关元件和第三开关元件分别采用薄膜晶体管而实现。
本发明实施方式阵列基板的具体制程为：在玻璃基板上先通过曝光显影蚀刻等步骤形成PEP（(photo-etching-process，光蚀刻工艺）1层，作为扫描线电极和公共电极，然后在TFT（Thin Film Transistor，薄膜晶体管）位置形成PEP2层，接下来用金属材料形成数据线电极和TFT，在需要金属导通的位置形成导通孔，即PEP4层，最后完成像素电极即ITO（氧化铟锡）层PEP5。
以上仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其它相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

  1. 一种液晶显示面板，其中，所述液晶显示面板包括：
    第一基板，包括：
    多条扫描线，设置在所述第一基板上；
    多条数据线，设置在所述第一基板上，且所述多条数据线与所述多条扫描线相互交叉以将所述液晶显示面板划分成多个像素区域；
    第二基板，与所述第一基板相对设置；
    液晶层，夹设在所述第一基板与所述第二基板之间；
    其中，每个所述像素区域至少包括第一次像素区域、第二次像素区域和第三次像素区域，所述第一次像素区域、第二次像素区域和第三次像素区域的驱动电压均源自所述像素区域所对应的同一条数据线所提供的资料电压，且在驱动时，所述第一次像素区域的驱动电压大于所述第二次像素区域的驱动电压，而所述第二次像素区域的驱动电压大于所述第三次像素区域的驱动电压。
  2. 根据权利要求1所述的液晶显示面板，其中，所述第一次像素区域和所述第二次像素区域分别连接与所述像素区域相对应的一条扫描线和与所述像素区域相对应的所述数据线，以利用与所述像素区域相对应的所述扫描线而控制所述第一次像素区域和所述第二次像素区域的导通和截止，并在所述第一次像素区域和所述第二次像素区域导通时，利用与所述像素区域相对应的所述数据线而将资料电压分别写入所述第一次像素区域和所述第二次像素区域；
    所述第三次像素区域连接与所述像素区域相对应的所述扫描线相邻的下一条扫描线和所述第二次像素区域，以利用与所述像素区域相对应的所述扫描线相邻的下一条扫描线而控制所述第三次像素区域的导通和截止，当所述第一次像素区域和所述第二次像素区域被写入所述资料电压后且在所述第三次像素区域导通时，所述第二次像素区域对所述第三次像素区域进行充电以拉低所述第二次像素区域的驱动电压；当所述第三次像素区域截止时，所述第三次像素区域根据电荷耦合效应从而拉低所述第三次像素区域的驱动电压。
  3. 根据权利要求2所述的液晶显示面板，其中，所述第一次像素区域、所述第二次像素区域和所述第三次像素区域分别包括开关元件、液晶电容和存储电容；
    其中，所述第一次像素区域和所述第二次像素区域的所述开关元件的栅极均电性连接与所述像素区域相对应的所述扫描线，而其源极均电性连接与所述像素区域相对应的所述数据线；所述第一次像素区域中的所述开关元件的漏极分别连接所述第一次像素区域中的所述液晶电容和所述存储电容的第一端，而所述第二次像素区域中的所述开关元件的漏极分别连接所述第二次像素区域中的所述液晶电容和所述存储电容的第一端；
    所述第三次像素区域中的所述开关元件的栅极电性连接与所述像素区域相对应的所述扫描线相邻的下一条扫描线，其源极电性连接所述第二次像素区域中的所述液晶电容和所述存储电容的第一端，而其漏极电性连接所述第三次像素区域中的所述液晶电容和所述存储电容的第一端，所述第一次像素区域和所述第二次像素区域中的所述存储电容的第二端分别电性连接至公共线，而所述第三次像素区域中的所述存储电容的第二端电性连接与所述像素区域相对应的所述扫描线相邻的下一条扫描线。
  4. 根据权利要求3所述的液晶显示面板，其中，所述第一次像素区域的开关元件与所述第二次像素区域的开关元件为同一个开关元件。
  5. 根据权利要求3或4所述的液晶显示面板，其中，所述第一次像素区域、所述第二次像素区域和所述第三次像素区域中的所述开关元件分别采用薄膜晶体管而实现。
  6. 根据权利要求3或4所述的液晶显示面板，其中，每个所述像素区域中的像素电极被划分成第一次像素电极、第二次像素电极和第三次像素电极，且所述第一次像素电极、所述第二次像素电极和所述第三次像素电极分别作为所述第一次像素区域、所述第二次像素区域和所述第三次像素区域中的所述液晶电容的第一端；而所述像素区域中的公共电极对应作为所述第一次像素区域、所述第二次像素区域和所述第三次像素区域中的所述液晶电容的第二端。
  7. 根据权利要求6所述的液晶显示面板，其中，每个所述像素区域中的像素电极和公共电极均设置在所述第一基板上。
  8. 一种阵列基板，其中，所述阵列基板包括：
    多条扫描线；
    多条数据线，与所述多条扫描线相互交叉以将所述阵列基板划分成多个像素区域；
    其中，每个所述像素区域至少包括第一次像素区域、第二次像素区域和第三次像素区域，所述第一次像素区域、第二次像素区域和第三次像素区域的驱动电压均源自所述像素区域所对应的同一条数据线所提供的资料电压，且在驱动时，所述第一次像素区域的驱动电压大于所述第二次像素区域的驱动电压，而所述第二次像素区域的驱动电压大于所述第三次像素区域的驱动电压。
  9. 根据权利要求8所述的阵列基板，其中，所述第一次像素区域和所述第二次像素区域分别连接与所述像素区域相对应的一条扫描线和与所述像素区域相对应的所述数据线，以利用与所述像素区域相对应的所述扫描线而控制所述第一次像素区域和所述第二次像素区域的导通和截止，并在所述第一次像素区域和所述第二次像素区域导通时，利用与所述像素区域相对应的所述数据线而将资料电压分别写入所述第一次像素区域和所述第二次像素区域；
    所述第三次像素区域连接与所述像素区域相对应的所述扫描线相邻的下一条扫描线和所述第二次像素区域，以利用与所述像素区域相对应的所述扫描线相邻的下一条扫描线而控制所述第三次像素区域的导通和截止，当所述第一次像素区域和所述第二次像素区域被写入所述资料电压后且在所述第三次像素区域导通时，所述第二次像素区域对所述第三次像素区域进行充电以拉低所述第二次像素区域的驱动电压；当所述第三次像素区域截止时，所述第三次像素区域根据电荷耦合效应从而拉低所述第三次像素区域的驱动电压。
  10. 根据权利要求9所述的阵列基板，其中，所述第一次像素区域、所述第二次像素区域和所述第三次像素区域分别包括开关元件和存储电容；
    其中，所述第一次像素区域和所述第二次像素区域的所述开关元件的栅极均电性连接与所述像素区域相对应的所述扫描线，而其源极均电性连接与所述像素区域相对应的所述数据线；所述第一次像素区域中的所述开关元件的漏极连接所述第一次像素区域中的所述存储电容的第一端，而所述第二次像素区域中的所述开关元件的漏极连接所述第二次像素区域中的所述存储电容的第一端；
    所述第三次像素区域中的所述开关元件的栅极电性连接与所述像素区域相对应的所述扫描线相邻的下一条扫描线，其源极电性连接所述第二次像素区域中的所述存储电容的第一端，而其漏极电性连接所述第三次像素区域中的所述存储电容的第一端，所述第一次像素区域和所述第二次像素区域中的所述存储电容的第二端分别电性连接至公共线，而所述第三次像素区域中的所述存储电容的第二端电性连接与所述像素区域相对应的所述扫描线相邻的下一条扫描线。
PCT/CN2015/070439 2014-11-21 2015-01-09 一种液晶显示面板及阵列基板 WO2016078204A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/437,488 US20170140714A1 (en) 2014-11-21 2015-01-09 Liquid crystal display panel and array substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410677501.3A CN104360556B (zh) 2014-11-21 2014-11-21 一种液晶显示面板及阵列基板
CN201410677501.3 2014-11-21

Publications (1)

Publication Number Publication Date
WO2016078204A1 true WO2016078204A1 (zh) 2016-05-26

Family

ID=52527832

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2015/070439 WO2016078204A1 (zh) 2014-11-21 2015-01-09 一种液晶显示面板及阵列基板

Country Status (3)

Country Link
US (1) US20170140714A1 (zh)
CN (1) CN104360556B (zh)
WO (1) WO2016078204A1 (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106782377B (zh) 2016-12-27 2018-01-23 惠科股份有限公司 液晶显示器件及其驱动方法
CN106773413A (zh) * 2017-01-03 2017-05-31 深圳市华星光电技术有限公司 一种阵列基板及显示装置
CN106950768B (zh) * 2017-03-03 2019-12-24 深圳市华星光电技术有限公司 像素单元及其驱动方法
CN106802524A (zh) * 2017-03-23 2017-06-06 深圳市华星光电技术有限公司 阵列基板和液晶显示面板
US10423041B2 (en) 2017-03-23 2019-09-24 Shenzhen China Star Optoelectronics Technology Co., Ltd Array substrate and liquid crystal display panel
CN107728352B (zh) * 2017-11-22 2020-05-05 深圳市华星光电半导体显示技术有限公司 一种像素驱动电路及液晶显示面板
CN108169969B (zh) * 2017-12-26 2020-09-18 深圳市华星光电技术有限公司 一种阵列基板及液晶显示面板
CN209343105U (zh) * 2018-12-04 2019-09-03 惠科股份有限公司 一种显示面板和显示装置
CN111381408B (zh) * 2018-12-29 2023-04-25 咸阳彩虹光电科技有限公司 一种像素阵列及其液晶面板
CN110930959A (zh) * 2019-11-28 2020-03-27 武汉华星光电半导体显示技术有限公司 像素驱动电路和液晶显示面板
CN113219744A (zh) * 2021-04-20 2021-08-06 北海惠科光电技术有限公司 显示面板、显示设备以及显示面板的驱动方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080136983A1 (en) * 2006-12-12 2008-06-12 Industrial Technology Research Institute Pixel structure of display device and method for driving the same
CN101308301A (zh) * 2007-05-17 2008-11-19 株式会社半导体能源研究所 液晶显示装置
US20090135322A1 (en) * 2007-11-26 2009-05-28 Samsung Electronics Co., Ltd Thin film transistor substrate, liquid crystal display device having the same and method of manufacturing the same
CN102915716A (zh) * 2012-08-03 2013-02-06 友达光电股份有限公司 像素电路、像素结构、可切换二维/三维显示装置、显示驱动方法
CN103353698A (zh) * 2013-07-19 2013-10-16 深圳市华星光电技术有限公司 一种阵列基板及液晶显示面板

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005258094A (ja) * 2004-03-11 2005-09-22 Sharp Corp 表示装置および電子情報機器
TWI330746B (en) * 2006-08-25 2010-09-21 Au Optronics Corp Liquid crystal display and operation method thereof
US7830346B2 (en) * 2007-07-12 2010-11-09 Au Optronics Corporation Liquid crystal display panel with color washout improvement by scanning line coupling and applications of same
TWI460517B (zh) * 2011-11-18 2014-11-11 Au Optronics Corp 顯示面板及其中畫素結構以及顯示面板中之驅動方法
CN102692770B (zh) * 2012-06-07 2015-02-18 昆山龙腾光电有限公司 液晶显示装置
TWI489175B (zh) * 2012-11-30 2015-06-21 Au Optronics Corp 顯示面板的陣列基板及其驅動方法
CN103278977B (zh) * 2013-05-31 2015-11-25 深圳市华星光电技术有限公司 液晶显示面板及其像素结构和驱动方法
US20150022510A1 (en) * 2013-07-19 2015-01-22 Shenzhen China Star Optoelectronics Technology Co., Ltd. Array substrate and liquid crystal panel with the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080136983A1 (en) * 2006-12-12 2008-06-12 Industrial Technology Research Institute Pixel structure of display device and method for driving the same
CN101308301A (zh) * 2007-05-17 2008-11-19 株式会社半导体能源研究所 液晶显示装置
US20090135322A1 (en) * 2007-11-26 2009-05-28 Samsung Electronics Co., Ltd Thin film transistor substrate, liquid crystal display device having the same and method of manufacturing the same
CN102915716A (zh) * 2012-08-03 2013-02-06 友达光电股份有限公司 像素电路、像素结构、可切换二维/三维显示装置、显示驱动方法
CN103353698A (zh) * 2013-07-19 2013-10-16 深圳市华星光电技术有限公司 一种阵列基板及液晶显示面板

Also Published As

Publication number Publication date
CN104360556B (zh) 2017-06-16
CN104360556A (zh) 2015-02-18
US20170140714A1 (en) 2017-05-18

Similar Documents

Publication Publication Date Title
WO2016078204A1 (zh) 一种液晶显示面板及阵列基板
WO2014190585A1 (zh) 液晶显示面板及其像素结构和驱动方法
WO2018072287A1 (zh) 一种像素结构及液晶显示面板
WO2016058183A1 (zh) 阵列基板及液晶显示面板
WO2015021660A1 (zh) 阵列基板及液晶显示装置
WO2018126510A1 (zh) 一种阵列基板及显示装置
WO2018058797A1 (zh) 一种coa 阵列基板及显示装置
US9213441B2 (en) In-cell touch panel and liquid crystal device
WO2016149957A1 (zh) 液晶显示装置、液晶显示器及其制作方法和暗点作业方法
WO2017092082A1 (zh) 阵列基板以及液晶显示装置
CN109491120A (zh) 显示面板和显示装置
WO2016000296A1 (zh) 低色偏液晶阵列基板及其驱动方法
WO2017197693A1 (zh) 3t像素结构及液晶显示装置
US9588382B2 (en) Pixel structure, manufacturing method of pixel structure, array substrate, display panel, and display device
WO2020224124A1 (zh) 像素补偿方法及液晶显示装置
WO2016127464A1 (zh) 一种阵列基板及液晶显示面板
WO2019015077A1 (zh) 一种阵列基板及其制造方法、液晶显示装置
WO2018120543A1 (zh) 像素结构的制造方法
WO2015006959A1 (zh) 显示面板及显示装置
CN108363248A (zh) 显示面板及其降低电容负载的方法
WO2016095242A1 (zh) 阵列基板、液晶显示面板及液晶显示面板的检测方法
WO2017059606A1 (zh) 一种液晶显示器及其制备方法
WO2019100416A1 (zh) 一种像素驱动电路及液晶显示面板
WO2017124605A1 (zh) 触摸面板以及其制造方法
WO2016026167A1 (zh) 一种液晶显示面板及阵列基板

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14437488

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 15861374

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 15861374

Country of ref document: EP

Kind code of ref document: A1