WO2018126510A1 - 一种阵列基板及显示装置 - Google Patents

一种阵列基板及显示装置 Download PDF

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Publication number
WO2018126510A1
WO2018126510A1 PCT/CN2017/073344 CN2017073344W WO2018126510A1 WO 2018126510 A1 WO2018126510 A1 WO 2018126510A1 CN 2017073344 W CN2017073344 W CN 2017073344W WO 2018126510 A1 WO2018126510 A1 WO 2018126510A1
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Prior art keywords
thin film
film transistor
pixel region
sub
capacitor
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PCT/CN2017/073344
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English (en)
French (fr)
Inventor
安立扬
Original Assignee
深圳市华星光电技术有限公司
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Priority to US15/513,590 priority Critical patent/US20180231851A1/en
Publication of WO2018126510A1 publication Critical patent/WO2018126510A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G09G3/3629—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals
    • G09G3/364—Control of matrices with row and column drivers using a passive matrix using liquid crystals having memory effects, e.g. ferroelectric liquid crystals with use of subpixels
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G02F1/134354—Subdivided pixels, e.g. for grey scale or redundancy the sub-pixels being capacitively coupled
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to an array substrate and a display device.
  • Liquid crystal display Liquid Crystal Display
  • LCD and other flat display devices are widely used in mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, desktop computers, etc. due to their high image quality, power saving, thin body and wide application range.
  • Various consumer electronic products have become the mainstream in display devices.
  • Most of the liquid crystal display devices on the market are backlight type liquid crystal displays, which include a liquid crystal display panel (TFT-LCD) and a backlight module (backlight) Module). LCD on the current mainstream market
  • TFT-LCD liquid crystal display panel
  • backlight backlight module
  • LCD liquid crystal display panel
  • the VA type liquid crystal display panel has a very high contrast ratio compared to other types of liquid crystal display panels, and has a very wide application in large-size display such as a television.
  • the VA type liquid crystal display panel adopts a vertically rotating liquid crystal
  • the difference in birefringence of the liquid crystal molecules is relatively large, resulting in color shift at a large viewing angle (color The shift problem is more serious, which makes the VA type liquid crystal display panel have a large difference in brightness from different angles, resulting in picture distortion.
  • the design shown in FIG. 2 is generally adopted, and the entire display unit is divided into a main-pixel (main pixel) 10 and a sub-pixel (sub-pixel) 20, which are respectively separated by two TFT devices. control.
  • the two TFTs are controlled by the same G-line (gate line).
  • the D-line (data line) charges the main-pixel and the sub-pixel, and the potential of the main-pixel remains as the signal given by the D-line.
  • the liquid crystal molecules have two alignment directions in the same gray scale, and can play the role of viewing angle compensation when viewed from a large viewing angle, so as to achieve the purpose of improving the large viewing angle.
  • the improvement effect of the design is limited, and there is still a large color shift phenomenon in the middle and low gray levels.
  • An object of the present invention is to provide an array substrate and a display device to solve the problem that the VA liquid crystal display panel adopts vertically rotating liquid crystal in the prior art, and the difference in birefringence of liquid crystal molecules is relatively large, resulting in color shift problem under a large viewing angle. More serious, the VA type liquid crystal display panel sees a large difference in brightness from different angles, causing a problem of picture distortion.
  • An array substrate comprising: a plurality of gate lines, a plurality of data lines, and a plurality of pixel units formed by crossing the plurality of gate lines and the plurality of data lines, each of the pixel units including a horizontal a main pixel area, a first sub-pixel area, and a second sub-pixel area arranged in sequence;
  • N be a positive integer, one of the pixel units being respectively connected to the gate lines of the Nth and N+1th lines, and when the Nth gate line is turned on, the data line is opposite to the main pixel area
  • the first sub-pixel region and the second sub-pixel region are charged.
  • the gate line of the (N+1)th column is turned on, the main pixel region, the first sub-pixel region, and the second Capacitive coupling may occur inside the sub-pixel region such that potentials of the main pixel region, the first sub-pixel region, and the second sub-pixel region are different from each other.
  • the main pixel region includes a first thin film transistor
  • the first sub-pixel region includes a second thin film transistor
  • the second sub-pixel region includes a third thin film transistor
  • the first thin film transistor the The second thin film transistor is connected to the gate of the third thin film transistor and is connected only to the Nth gate line.
  • the second sub-pixel region further includes a fourth thin film transistor, and the gate of the fourth thin film transistor is connected and only the N+1th gate line is connected.
  • the sources of the first thin film transistor, the second thin film transistor and the third thin film transistor are all connected to the same data line, and the drains of the first thin film transistors are respectively connected with the first a liquid crystal capacitor and a first storage capacitor, a drain of the second thin film transistor is respectively connected with a second liquid crystal capacitor and a second storage capacitor, and a drain of the third thin film transistor is respectively connected with a third liquid crystal capacitor and a third storage capacitance.
  • a second capacitor is disposed between a drain of the first thin film transistor and a drain of the second thin film transistor, and a drain of the fourth thin film transistor and a drain of the third thin film transistor A first capacitor is disposed therebetween, and a source of the fourth thin film transistor is connected to a drain of the second thin film transistor.
  • the data line is opposite to the first liquid crystal capacitor, the first storage capacitor, the second liquid crystal capacitor, the second storage capacitor, and the first The three liquid crystal capacitors, the third storage capacitor, the first capacitor, and the second capacitor are charged, and when the gate line of the (N+1)th column is turned on, the first capacitor and the second storage capacitor a capacitive coupling with the second liquid crystal capacitor, the second capacitor capacitively coupling with the first storage capacitor and the first liquid crystal capacitor, such that the main pixel region and the first sub-pixel region And the potentials of the second sub-pixel regions are different from each other.
  • the data line commonly connected to the first thin film transistor, the second thin film transistor and the third thin film transistor is located between the main pixel region and the first sub-pixel region.
  • one end of the first storage capacitor, the second storage capacitor and the third storage capacitor are connected to a common electrode.
  • one end of the first liquid crystal capacitor, the second liquid crystal capacitor and the third liquid crystal capacitor are grounded.
  • a display device includes an array substrate, the array substrate comprising:
  • each of the pixel units including a main pixel area sequentially arranged in a horizontal direction, a first sub-pixel region and a second sub-pixel region;
  • N be a positive integer, one of the pixel units being respectively connected to the gate lines of the Nth and N+1th lines, and when the Nth gate line is turned on, the data line is opposite to the main pixel area
  • the first sub-pixel region and the second sub-pixel region are charged.
  • the gate line of the (N+1)th column is turned on, the main pixel region, the first sub-pixel region, and the second Capacitive coupling may occur inside the sub-pixel region such that potentials of the main pixel region, the first sub-pixel region, and the second sub-pixel region are different from each other.
  • the main pixel region comprises a first thin film transistor
  • the first sub-pixel region comprises a second thin film transistor
  • the second sub-pixel region comprises a third thin film transistor
  • the first thin film transistor The second thin film transistor is connected to the gate of the third thin film transistor and only the Nth gate line is connected.
  • the second sub-pixel region further includes a fourth thin film transistor, and the gate of the fourth thin film transistor is connected and only the N+1th gate line is connected.
  • the sources of the first thin film transistor, the second thin film transistor and the third thin film transistor are all connected to the same data line, and the drains of the first thin film transistors are respectively connected to the first a liquid crystal capacitor and a first storage capacitor, a drain of the second thin film transistor is respectively connected with a second liquid crystal capacitor and a second storage capacitor, and a drain of the third thin film transistor is respectively connected with a third liquid crystal capacitor and a third Storage capacitor.
  • a second capacitor is disposed between a drain of the first thin film transistor and a drain of the second thin film transistor, a drain of the fourth thin film transistor and a drain of the third thin film transistor
  • a first capacitor is disposed between the source of the fourth thin film transistor and a drain of the second thin film transistor.
  • the data line is opposite to the first liquid crystal capacitor, the first storage capacitor, the second liquid crystal capacitor, the second storage capacitor, The third liquid crystal capacitor, the third storage capacitor, the first capacitor, and the second capacitor are charged, and when the gate line of the (N+1)th column is turned on, the first capacitor and the second storage a capacitive coupling between the capacitor and the second liquid crystal capacitor, the second capacitor capacitively coupling with the first storage capacitor and the first liquid crystal capacitor, such that the main pixel region and the first sub-pixel The potentials of the region and the second sub-pixel region are different from each other.
  • the data line in which the first thin film transistor, the second thin film transistor and the third thin film transistor are commonly connected is located between the main pixel region and the first sub-pixel region.
  • one end of the first storage capacitor, the second storage capacitor and the third storage capacitor are connected to a common electrode.
  • one end of the first liquid crystal capacitor, the second liquid crystal capacitor and the third liquid crystal capacitor are grounded.
  • An array substrate and a display device of the present invention divide a pixel unit into a main pixel region, a first sub-pixel region, and a second sub-pixel region, and cause the main pixel region and the
  • the potentials of the first sub-pixel region and the second sub-pixel region are different from each other, and the VA liquid crystal display panel adopts vertically rotating liquid crystal in the prior art, and the difference in birefringence of the liquid crystal molecules is relatively large, resulting in a large viewing angle.
  • the color shift problem under the above is more serious, which makes the VA type liquid crystal display panel have a large difference in brightness from different angles, causing a problem of picture distortion.
  • FIG. 1 is a schematic overall structural diagram of a pixel unit of an array substrate according to an embodiment of the invention.
  • FIG. 2 is a schematic view showing the overall structure of a pixel unit of an array substrate in the prior art.
  • the basic principle of the present invention is that by dividing each pixel unit into three portions insulated from each other, one portion is the main pixel region 100, and the remaining two portions are the first sub-pixel region 200 and the second sub-pixel region 300. Then, by inputting the same voltage to the main pixel region 100, the first sub-pixel region 200, and the second sub-pixel region 300, respectively, the voltages of the three mutually insulated pixel regions are different from each other by capacitive coupling. Further, the liquid crystal deflection angles of the respective pixel regions are different, thereby realizing color shift compensation for a large viewing angle of the liquid crystal display panel.
  • FIG. 1 is a schematic view showing the overall structure of a pixel unit of an array substrate according to an embodiment of the present invention.
  • an array substrate of the present invention includes:
  • each of the pixel units including the horizontal direction
  • N be a positive integer, one of the pixel units being respectively connected to the gate lines Gate of the Nth and N+1th strips, and when the Nth gate line Gate is turned on, the data line Data is The main pixel region 100, the first sub-pixel region 200, and the second sub-pixel region 300 are charged.
  • the gate line Gate of the N+1th column is turned on, the main pixel region 100, the first Capacitive coupling may occur in the interior of the sub-pixel region 200 and the second sub-pixel region 300 such that the potentials of the main pixel region 100, the first sub-pixel region 200, and the second sub-pixel region 300 are not mutually the same.
  • each of the pixel units is as follows:
  • the main pixel region 100 includes a first thin film transistor T1, the first sub-pixel region 200 includes a second thin film transistor T2, the second sub-pixel region 300 includes a third thin film transistor T3, and the first thin film transistor T1, the second thin film transistor T2 and the gate of the third thin film transistor T3 are both connected to each other and only the Nth gate line Gate is connected.
  • the second sub-pixel region 300 further includes a fourth thin film transistor T4 whose gate is connected and connected only to the N+1th gate line Gate.
  • the sources of the first thin film transistor T1, the second thin film transistor T2, and the third thin film transistor T3 are both connected to the same data line Data, and the first thin film transistor T1
  • the drain is connected to the first liquid crystal capacitor Clc1 and the first storage capacitor Cst1
  • the drain of the second thin film transistor T2 is respectively connected to the second liquid crystal capacitor Clc2 and the second storage capacitor Cst2, and the third thin film transistor T3
  • the drains are respectively connected with a third liquid crystal capacitor Clc3 and a third storage capacitor Cst3.
  • a second capacitor Cb is disposed between the drain of the first thin film transistor T1 and the drain of the second thin film transistor T2, and the drain of the fourth thin film transistor T4 and the third thin film transistor T3
  • a first capacitor Ca is disposed between the drains, and a source of the fourth thin film transistor T4 is connected to a drain of the second thin film transistor T2.
  • the data line Data in which the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 are commonly connected are located in the main pixel region 100 and the first Between the sub-pixel regions 200, preferably, the first storage capacitor Cst1, the second storage capacitor Cst2, and one end of the third storage capacitor Cst3 are connected to a common electrode, preferably the first liquid crystal capacitor Clc1. Both ends of the second liquid crystal capacitor Clc2 and the third liquid crystal capacitor Clc3 are grounded.
  • the data line Data is opposite to the first liquid crystal capacitor Cl1, the first storage capacitor Cst1, the second liquid crystal capacitor Clc2, and the second storage capacitor Cst2.
  • the third liquid crystal capacitor Clc3, the third storage capacitor Cst3, the first capacitor Ca, and the second capacitor Cb are charged while the one end capacitor plate of the first capacitor Ca is connected to the third thin film transistor T3 ( That is, the lower end plate) collects a part of the electric charge, and the capacitive plates at both ends of the second capacitance Cb gather a part of the electric charge.
  • the gate line Gate of the (N+1)th column When the gate line Gate of the (N+1)th column is turned on, the gate line Gate of the Nth column is turned off, and the first capacitor Ca is capacitively coupled with the second storage capacitor Cst2 and the second liquid crystal capacitor Clc2.
  • the effect is that the potential of the upper end plate of the first capacitor Ca is lower, and the potential of the upper end plate of the second liquid crystal capacitor Clc2 and the second storage capacitor Cst2 (connected to the drain of the second thin film transistor T2) is higher.
  • the charges of the upper end plates of the second liquid crystal capacitor Clc2 and the second storage capacitor Cst2 are transferred to the upper end plate of the first capacitor Ca, so that the overall potential of the first sub-pixel region 200 is lowered, and the second sub-pixel region 300 is made The overall potential rises.
  • the second capacitor Cb is capacitively coupled to the first storage capacitor Cst1 and the first liquid crystal capacitor Clc1, that is, a partial charge transfer of the upper storage plate Cst2 and the upper end plate of the second liquid crystal capacitor Clc2 After the first capacitor Ca, its potential drops, and then the partial charge of the second capacitor Cb is transferred to the second storage capacitor Cst2 and the second liquid crystal capacitor Clc2, causing the potential of the second capacitor Cb to drop. This in turn causes a drop in the potential of the main pixel region 100.
  • the potentials of the main pixel region 100, the first sub-pixel region 200, and the second sub-pixel region 300 are different from each other.
  • An array substrate of the present invention divides a pixel unit into a main pixel region 100, a first sub-pixel region 200, and a second sub-pixel region 300, and causes a capacitive coupling effect to cause the main pixel region 100 and the
  • the potentials of the first sub-pixel region 200 and the second sub-pixel region 300 are different from each other, and the VA liquid crystal display panel adopts vertically rotating liquid crystal in the prior art, and the difference in birefringence of the liquid crystal molecules is relatively large.
  • the color shift problem under the large viewing angle is relatively serious, which makes the VA type liquid crystal display panel have a large difference in brightness from different angles, causing a problem of picture distortion.
  • a display device of the present embodiment includes the array substrate according to the first embodiment.
  • the array substrate has been discussed in detail in the first embodiment, and the description thereof will not be repeated.
  • a display device of the present invention divides a pixel unit of an array substrate into a main pixel region 100, a first sub-pixel region 200, and a second sub-pixel region 300, and causes the main pixel by capacitive coupling.
  • the potentials of the region 100, the first sub-pixel region 200 and the second sub-pixel region 300 are different from each other, and the VA liquid crystal display panel adopts vertically rotating liquid crystal, and the liquid crystal molecules have birefringence.
  • the difference is relatively large, resulting in a serious color shift problem under a large viewing angle, which makes the VA type liquid crystal display panel have a large difference in brightness from different angles, causing a problem of picture distortion.

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Abstract

一种阵列基板及显示装置，阵列基板包括多条栅极线（Gate(n)）、多条数据线（Date(n)）及多个像素单元，一个像素单元分别与第N条和第N+1条栅极线（Gate(n+1)）连接，当第N条栅极线（Gate(n)）开启，数据线（Date(n)）对主像素区（100）、第一子像素区（200）及第二子像素区（300）进行充电，当第N+1条栅极线（Gate(n+1)）开启，主像素区（100）、第一子像素区（200）及第二子像素区（300）的内部可发生电容耦合作用，使得主像素区（100）、第一子像素区（200）及第二子像素区（300）的电位互不相同，因而改善了大视角下的显示效果。

Description

一种阵列基板及显示装置 技术领域
本发明涉及液晶显示领域，特别涉及一种阵列基板及显示装置。
背景技术
液晶显示器(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。现有市场上的液晶显示装置大部分为背光型液晶显示器，其包括液晶显示面板(TFT-LCD)及背光模组(backlight module)。就目前主流市场上的 LCD 显示面板而言，VA型液晶显示面板相比其他种类的液晶显示面板具有极高的对比度，在大尺寸显示，如电视等方面具有非常广的应用。但由于VA型液晶显示面板采用垂直转动的液晶，液晶分子双折射率的差异比较大，导致大视角下的色偏(color shift)问题比较严重，使得VA型液晶显示面板从不同角度看到的亮度差异较大，造成画面失真。
因为液晶显示的内在因素，VA显示器在不同位置观察到的图像始终有些差异。这导致正视情况下看起来正常的图片大视角观看时显示异常，这种异常主要体现在颜色上，也就是大视角色偏。为了改善VA显示器的大视角色偏，一般采取图2所示的设计，将整个显示单元分为main-pixel（主像素）10与sub-pixel（次像素）20，分别由两个TFT器件单独控制。两个TFT由同一条G-line（栅极线）控制，gate打开时D-line（数据线）对main-pixel与sub-pixel进行充电，main-pixel的电位保持为D-line给的信号。这样在同一灰阶下液晶分子有两种排列方向，在大视角观看时可以起到视角补偿的作用，以实现改善大视角的目的。但是该设计的改善效果受到限制，在中低灰阶依然存在较大色偏现象。
 技术问题
本发明的目的在于提供一种阵列基板及显示装置，以解决现有技术中，VA型液晶显示面板采用垂直转动的液晶，液晶分子双折射率的差异比较大，导致大视角下的色偏问题比较严重，使得VA型液晶显示面板从不同角度看到的亮度差异较大，造成画面失真的问题。
 技术解决方案
本发明的技术方案如下：
一种阵列基板，其包括：多条栅极线、多条数据线及由所述多条栅极线与所述多条数据线交叉形成的多个像素单元，每个所述像素单元包括水平方向依次排列的主像素区、第一子像素区及第二子像素区；
设N为正整数，一个所述像素单元分别与第N条和第N+1条所述栅极线连接，当第N条所述栅极线开启，所述数据线对所述主像素区、所述第一子像素区及所述第二子像素区进行充电，当第N+1条所述栅极线开启，所述主像素区、所述第一子像素区及所述第二子像素区的内部可发生电容耦合作用，使得所述主像素区、所述第一子像素区及所述第二子像素区的电位互不相同。
优选地，所述主像素区包括第一薄膜晶体管，所述第一子像素区包括第二薄膜晶体管，所述第二子像素区包括第三薄膜晶体管，且所述第一薄膜晶体管、所述第二薄膜晶体管与所述第三薄膜晶体管的栅极均连接且只连接第N条所述栅极线。
优选地，所述第二子像素区还包括第四薄膜晶体管，所述第四薄膜晶体管的栅极连接且只连接第N+1条所述栅极线。
优选地，所述第一薄膜晶体管、所述第二薄膜晶体管与所述第三薄膜晶体管的源极均与同一条所述数据线连接，所述第一薄膜晶体管的漏极分别连接有第一液晶电容与第一存储电容，所述第二薄膜晶体管的漏极分别连接有第二液晶电容与第二存储电容，所述第三薄膜晶体管的漏极分别连接有第三液晶电容与第三存储电容。
优选地，所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的漏极之间设有第二电容，所述第四薄膜晶体管的漏极与所述第三薄膜晶体管的漏极之间设有第一电容，所述第四薄膜晶体管的源极与所述第二薄膜晶体管的漏极连接。
优选地，当第N条所述栅极线开启，所述数据线对所述第一液晶电容、所述第一存储电容、所述第二液晶电容、所述第二存储电容、所述第三液晶电容、所述第三存储电容、所述第一电容及所述第二电容进行充电，当第N+1条所述栅极线开启，所述第一电容与所述第二存储电容和所述第二液晶电容发生电容耦合作用，所述第二电容与所述第一存储电容和所述第一液晶电容发生电容耦合作用，使得所述主像素区、所述第一子像素区及所述第二子像素区的电位互不相同。
优选地，所述第一薄膜晶体管、所述第二薄膜晶体管与所述第三薄膜晶体管共同连接的所述数据线位于所述主像素区与所述第一子像素区之间。
优选地，所述第一存储电容、所述第二存储电容与所述第三存储电容的一端均与公共电极连接。
优选地，所述第一液晶电容、所述第二液晶电容与所述第三液晶电容的一端均接地。
一种显示装置，其包括一阵列基板，该阵列基板包括：
多条栅极线、多条数据线及由所述多条栅极线与所述多条数据线交叉形成的多个像素单元，每个所述像素单元包括水平方向依次排列的主像素区、第一子像素区及第二子像素区；
设N为正整数，一个所述像素单元分别与第N条和第N+1条所述栅极线连接，当第N条所述栅极线开启，所述数据线对所述主像素区、所述第一子像素区及所述第二子像素区进行充电，当第N+1条所述栅极线开启，所述主像素区、所述第一子像素区及所述第二子像素区的内部可发生电容耦合作用，使得所述主像素区、所述第一子像素区及所述第二子像素区的电位互不相同。
优选地，其中所述主像素区包括第一薄膜晶体管，所述第一子像素区包括第二薄膜晶体管，所述第二子像素区包括第三薄膜晶体管，且所述第一薄膜晶体管、所述第二薄膜晶体管与所述第三薄膜晶体管的栅极均连接且只连接第N条所述栅极线。
优选地，其中所述第二子像素区还包括第四薄膜晶体管，所述第四薄膜晶体管的栅极连接且只连接第N+1条所述栅极线。
优选地，其中所述第一薄膜晶体管、所述第二薄膜晶体管与所述第三薄膜晶体管的源极均与同一条所述数据线连接，所述第一薄膜晶体管的漏极分别连接有第一液晶电容与第一存储电容，所述第二薄膜晶体管的漏极分别连接有第二液晶电容与第二存储电容，所述第三薄膜晶体管的漏极分别连接有第三液晶电容与第三存储电容。
优选地，其中所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的漏极之间设有第二电容，所述第四薄膜晶体管的漏极与所述第三薄膜晶体管的漏极之间设有第一电容，所述第四薄膜晶体管的源极与所述第二薄膜晶体管的漏极连接。
优选地，其中当第N条所述栅极线开启，所述数据线对所述第一液晶电容、所述第一存储电容、所述第二液晶电容、所述第二存储电容、所述第三液晶电容、所述第三存储电容、所述第一电容及所述第二电容进行充电，当第N+1条所述栅极线开启，所述第一电容与所述第二存储电容和所述第二液晶电容发生电容耦合作用，所述第二电容与所述第一存储电容和所述第一液晶电容发生电容耦合作用，使得所述主像素区、所述第一子像素区及所述第二子像素区的电位互不相同。
优选地，其中所述第一薄膜晶体管、所述第二薄膜晶体管与所述第三薄膜晶体管共同连接的所述数据线位于所述主像素区与所述第一子像素区之间。
优选地，其中所述第一存储电容、所述第二存储电容与所述第三存储电容的一端均与公共电极连接。
优选地，其中所述第一液晶电容、所述第二液晶电容与所述第三液晶电容的一端均接地。
 有益效果
本发明的有益效果：
本发明的一种阵列基板及显示装置，通过将一个像素单元分为主像素区、第一子像素区和第二子像素区，并通过发生电容耦合作用，使得所述主像素区、所述第一子像素区及所述第二子像素区的电位互不相同，解决了现有技术中，VA型液晶显示面板采用垂直转动的液晶，液晶分子双折射率的差异比较大，导致大视角下的色偏问题比较严重，使得VA型液晶显示面板从不同角度看到的亮度差异较大，造成画面失真的问题。
 附图说明
图1为本发明实施例的一种阵列基板的像素单元的整体结构示意图；
图2为现有技术的一种阵列基板的像素单元的整体结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
实施例一
本发明的基本原理在于，通过将每个像素单元分为彼此绝缘的三个部分，一个部分为主像素区100，剩余的两个部分为第一子像素区200和第二子像素区300，然后通过先对对该主像素区100、第一子像素区200和第二子像素区300分别输入相同的电压，在通过电容耦合作用使该三个彼此绝缘的像素区的电压互不相同，进而使得各个像素区的液晶偏转角度不同，从而实现对液晶显示面板的大视角的色偏补偿。
请参考图1，图1为本实施例的一种阵列基板的像素单元的整体结构示意图，从图1可以看到，本发明的一种阵列基板，其包括：
多条栅极线Gate、多条数据线Data及由所述多条栅极线Gate与所述多条数据线Data交叉形成的多个像素单元，每个所述像素单元包括水平方向依次排列的主像素区100、第一子像素区200及第二子像素区300。
设N为正整数，一个所述像素单元分别与第N条和第N+1条所述栅极线Gate连接，当第N条所述栅极线Gate开启，所述数据线Data对所述主像素区100、所述第一子像素区200及所述第二子像素区300进行充电，当第N+1条所述栅极线Gate开启，所述主像素区100、所述第一子像素区200及所述第二子像素区300的内部可发生电容耦合作用，使得所述主像素区100、所述第一子像素区200及所述第二子像素区300的电位互不相同。
其中，每个所述像素单元的整体结构如下所述：
所述主像素区100包括第一薄膜晶体管T1，所述第一子像素区200包括第二薄膜晶体管T2，所述第二子像素区300包括第三薄膜晶体管T3，且所述第一薄膜晶体管T1、所述第二薄膜晶体管T2与所述第三薄膜晶体管T3的栅极均连接且只连接第N条所述栅极线Gate。
另外，所述第二子像素区300还包括第四薄膜晶体管T4，所述第四薄膜晶体管T4的栅极连接且只连接第N+1条所述栅极线Gate。
在本实施例中，所述第一薄膜晶体管T1、所述第二薄膜晶体管T2与所述第三薄膜晶体管T3的源极均与同一条所述数据线Data连接，所述第一薄膜晶体管T1的漏极分别连接有第一液晶电容Clc1与第一存储电容Cst1，所述第二薄膜晶体管T2的漏极分别连接有第二液晶电容Clc2与第二存储电容Cst2，所述第三薄膜晶体管T3的漏极分别连接有第三液晶电容Clc3与第三存储电容Cst3。
另外，所述第一薄膜晶体管T1的漏极与所述第二薄膜晶体管T2的漏极之间设有第二电容Cb，所述第四薄膜晶体管T4的漏极与所述第三薄膜晶体管T3的漏极之间设有第一电容Ca，所述第四薄膜晶体管T4的源极与所述第二薄膜晶体管T2的漏极连接。
在本实施例中，优选所述第一薄膜晶体管T1、所述第二薄膜晶体管T2与所述第三薄膜晶体管T3共同连接的所述数据线Data位于所述主像素区100与所述第一子像素区200之间，优选所述第一存储电容Cst1、所述第二存储电容Cst2与所述第三存储电容Cst3的一端均与公共电极连接，优选所述第一液晶电容Clc1、所述第二液晶电容Clc2与所述第三液晶电容Clc3的一端均接地。
本发明的工作原理如下所述：
当第N条所述栅极线Gate开启，所述数据线Data对所述第一液晶电容Clc1、所述第一存储电容Cst1、所述第二液晶电容Clc2、所述第二存储电容Cst2、所述第三液晶电容Clc3、所述第三存储电容Cst3、所述第一电容Ca及所述第二电容Cb进行充电，同时第一电容Ca的与第三薄膜晶体管T3连接的一端电容板（即下端板）聚集了部分电荷，而第二电容Cb的两端电容板均聚集了部分电荷。
当第N+1条所述栅极线Gate开启，第N条所述栅极线Gate关闭，所述第一电容Ca与所述第二存储电容Cst2和所述第二液晶电容Clc2发生电容耦合作用，即此时所述第一电容Ca的上端板的电位较低，第二液晶电容Clc2和第二存储电容Cst2的上端板（与第二薄膜晶体管T2的漏极连接）的电位较高，第二液晶电容Clc2和第二存储电容Cst2的上端板的电荷会转移到所述第一电容Ca的上端板，使得第一子像素区200的总体电位下降，并使得第二子像素区300的总体电位上升。
所述第二电容Cb与所述第一存储电容Cst1和所述第一液晶电容Clc1发生电容耦合作用，即所述第二存储电容Cst2和所述第二液晶电容Clc2的上端板的部分电荷转移到第一电容Ca之后，其电位下降，这时第二电容Cb的部分电荷就会转移到所述第二存储电容Cst2和所述第二液晶电容Clc2上，导致第二电容Cb的电位下降，进而导致所述主像素区100的电位的下降。
总的来说，就是使得所述主像素区100、所述第一子像素区200及所述第二子像素区300的电位互不相同。
本发明的一种阵列基板，通过将一个像素单元分为主像素区100、第一子像素区200和第二子像素区300，并通过发生电容耦合作用，使得所述主像素区100、所述第一子像素区200及所述第二子像素区300的电位互不相同，解决了现有技术中，VA型液晶显示面板采用垂直转动的液晶，液晶分子双折射率的差异比较大，导致大视角下的色偏问题比较严重，使得VA型液晶显示面板从不同角度看到的亮度差异较大，造成画面失真的问题。
实施例二
本实施的一种显示装置，包括一实施例一所述的阵列基板，该阵列基板已经在实施例一中进行过了详细的论述，在此不再重复说明。
本发明的一种显示装置，通过将其阵列基板的一个像素单元分为主像素区100、第一子像素区200和第二子像素区300，并通过发生电容耦合作用，使得所述主像素区100、所述第一子像素区200及所述第二子像素区300的电位互不相同，解决了现有技术中，VA型液晶显示面板采用垂直转动的液晶，液晶分子双折射率的差异比较大，导致大视角下的色偏问题比较严重，使得VA型液晶显示面板从不同角度看到的亮度差异较大，造成画面失真的问题。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (18)

  1. 一种阵列基板，其包括：多条栅极线、多条数据线及由所述多条栅极线与所述多条数据线交叉形成的多个像素单元，每个所述像素单元包括水平方向依次排列的主像素区、第一子像素区及第二子像素区；
    设N为正整数，一个所述像素单元分别与第N条和第N+1条所述栅极线连接，当第N条所述栅极线开启，所述数据线对所述主像素区、所述第一子像素区及所述第二子像素区进行充电，当第N+1条所述栅极线开启，所述主像素区、所述第一子像素区及所述第二子像素区的内部可发生电容耦合作用，使得所述主像素区、所述第一子像素区及所述第二子像素区的电位互不相同。
  2. 根据权利要求1所述的阵列基板，其中所述主像素区包括第一薄膜晶体管，所述第一子像素区包括第二薄膜晶体管，所述第二子像素区包括第三薄膜晶体管，且所述第一薄膜晶体管、所述第二薄膜晶体管与所述第三薄膜晶体管的栅极均连接且只连接第N条所述栅极线。
  3. 根据权利要求2所述的阵列基板，其中所述第二子像素区还包括第四薄膜晶体管，所述第四薄膜晶体管的栅极连接且只连接第N+1条所述栅极线。
  4. 根据权利要求3所述的阵列基板，其中所述第一薄膜晶体管、所述第二薄膜晶体管与所述第三薄膜晶体管的源极均与同一条所述数据线连接，所述第一薄膜晶体管的漏极分别连接有第一液晶电容与第一存储电容，所述第二薄膜晶体管的漏极分别连接有第二液晶电容与第二存储电容，所述第三薄膜晶体管的漏极分别连接有第三液晶电容与第三存储电容。
  5. 根据权利要求3所述的阵列基板，其中所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的漏极之间设有第二电容，所述第四薄膜晶体管的漏极与所述第三薄膜晶体管的漏极之间设有第一电容，所述第四薄膜晶体管的源极与所述第二薄膜晶体管的漏极连接。
  6. 根据权利要求5所述的阵列基板，其中当第N条所述栅极线开启，所述数据线对所述第一液晶电容、所述第一存储电容、所述第二液晶电容、所述第二存储电容、所述第三液晶电容、所述第三存储电容、所述第一电容及所述第二电容进行充电，当第N+1条所述栅极线开启，所述第一电容与所述第二存储电容和所述第二液晶电容发生电容耦合作用，所述第二电容与所述第一存储电容和所述第一液晶电容发生电容耦合作用，使得所述主像素区、所述第一子像素区及所述第二子像素区的电位互不相同。
  7. 根据权利要求4所述的阵列基板，其中所述第一薄膜晶体管、所述第二薄膜晶体管与所述第三薄膜晶体管共同连接的所述数据线位于所述主像素区与所述第一子像素区之间。
  8. 根据权利要求4所述的阵列基板，其中所述第一存储电容、所述第二存储电容与所述第三存储电容的一端均与公共电极连接。
  9. 根据权利要求4所述的阵列基板，其中所述第一液晶电容、所述第二液晶电容与所述第三液晶电容的一端均接地。
  10. 一种显示装置，其包括一阵列基板，该阵列基板包括：
    多条栅极线、多条数据线及由所述多条栅极线与所述多条数据线交叉形成的多个像素单元，每个所述像素单元包括水平方向依次排列的主像素区、第一子像素区及第二子像素区；
    设N为正整数，一个所述像素单元分别与第N条和第N+1条所述栅极线连接，当第N条所述栅极线开启，所述数据线对所述主像素区、所述第一子像素区及所述第二子像素区进行充电，当第N+1条所述栅极线开启，所述主像素区、所述第一子像素区及所述第二子像素区的内部可发生电容耦合作用，使得所述主像素区、所述第一子像素区及所述第二子像素区的电位互不相同。
  11. 根据权利要求10所述显示装置，其中所述主像素区包括第一薄膜晶体管，所述第一子像素区包括第二薄膜晶体管，所述第二子像素区包括第三薄膜晶体管，且所述第一薄膜晶体管、所述第二薄膜晶体管与所述第三薄膜晶体管的栅极均连接且只连接第N条所述栅极线。
  12. 根据权利要求11所述显示装置，其中所述第二子像素区还包括第四薄膜晶体管，所述第四薄膜晶体管的栅极连接且只连接第N+1条所述栅极线。
  13. 根据权利要求12所述显示装置，其中所述第一薄膜晶体管、所述第二薄膜晶体管与所述第三薄膜晶体管的源极均与同一条所述数据线连接，所述第一薄膜晶体管的漏极分别连接有第一液晶电容与第一存储电容，所述第二薄膜晶体管的漏极分别连接有第二液晶电容与第二存储电容，所述第三薄膜晶体管的漏极分别连接有第三液晶电容与第三存储电容。
  14. 根据权利要求12所述显示装置，其中所述第一薄膜晶体管的漏极与所述第二薄膜晶体管的漏极之间设有第二电容，所述第四薄膜晶体管的漏极与所述第三薄膜晶体管的漏极之间设有第一电容，所述第四薄膜晶体管的源极与所述第二薄膜晶体管的漏极连接。
  15. 根据权利要求14所述显示装置，其中当第N条所述栅极线开启，所述数据线对所述第一液晶电容、所述第一存储电容、所述第二液晶电容、所述第二存储电容、所述第三液晶电容、所述第三存储电容、所述第一电容及所述第二电容进行充电，当第N+1条所述栅极线开启，所述第一电容与所述第二存储电容和所述第二液晶电容发生电容耦合作用，所述第二电容与所述第一存储电容和所述第一液晶电容发生电容耦合作用，使得所述主像素区、所述第一子像素区及所述第二子像素区的电位互不相同。
  16. 根据权利要求13所述显示装置，其中所述第一薄膜晶体管、所述第二薄膜晶体管与所述第三薄膜晶体管共同连接的所述数据线位于所述主像素区与所述第一子像素区之间。
  17. 根据权利要求13所述显示装置，其中所述第一存储电容、所述第二存储电容与所述第三存储电容的一端均与公共电极连接。
  18. 根据权利要求13所述显示装置，其中所述第一液晶电容、所述第二液晶电容与所述第三液晶电容的一端均接地。
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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102239581B1 (ko) * 2015-01-26 2021-04-14 삼성디스플레이 주식회사 표시 장치
CN107643639A (zh) * 2017-10-25 2018-01-30 深圳市华星光电技术有限公司 一种像素结构、阵列基板及显示面板
CN109119038A (zh) * 2018-09-03 2019-01-01 惠科股份有限公司 一种显示面板和显示装置
CN110660371B (zh) * 2019-09-30 2021-08-10 海信视像科技股份有限公司 液晶模组显示修正方法及设备
CN110738974B (zh) * 2019-10-28 2022-05-20 京东方科技集团股份有限公司 液晶像素电路、其驱动方法、显示面板及显示装置
CN113219747B (zh) * 2021-04-23 2022-11-08 成都中电熊猫显示科技有限公司 阵列基板、液晶显示面板及液晶显示器
CN114002884B (zh) * 2021-09-30 2022-10-21 惠科股份有限公司 阵列基板、显示面板及显示器

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1755470A (zh) * 2004-07-27 2006-04-05 三星电子株式会社 液晶显示板及薄膜晶体管阵列板
US20090009458A1 (en) * 2007-07-04 2009-01-08 Samsung Electronics Co., Ltd. Thin film transistor array panel and display appratus having the same
CN101706635A (zh) * 2009-11-02 2010-05-12 友达光电股份有限公司 像素阵列、聚合物稳定配向液晶显示面板以及光电装置
CN103323995A (zh) * 2013-06-21 2013-09-25 深圳市华星光电技术有限公司 液晶阵列基板及电子装置
CN104216187A (zh) * 2014-09-04 2014-12-17 深圳市华星光电技术有限公司 像素结构、液晶显示面板及其驱动方法
CN104360556A (zh) * 2014-11-21 2015-02-18 深圳市华星光电技术有限公司 一种液晶显示面板及阵列基板
CN105045009A (zh) * 2015-08-24 2015-11-11 深圳市华星光电技术有限公司 一种液晶显示面板及其阵列基板

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20080049514A (ko) * 2006-11-30 2008-06-04 엘지디스플레이 주식회사 수직정렬구조 반사투과형 액정표시장치 및 그 제조방법
US8542227B2 (en) * 2007-02-05 2013-09-24 Samsung Display Co., Ltd. Display apparatus and method for driving the same
CN101840119A (zh) * 2009-03-20 2010-09-22 瀚宇彩晶股份有限公司 像素结构及其驱动方法
TWI460517B (zh) * 2011-11-18 2014-11-11 Au Optronics Corp 顯示面板及其中畫素結構以及顯示面板中之驅動方法
WO2014077175A1 (ja) * 2012-11-16 2014-05-22 シャープ株式会社 駆動モジュール、表示パネル、表示装置、およびマルチディスプレイ装置
KR102197819B1 (ko) * 2014-08-14 2021-01-05 삼성디스플레이 주식회사 표시 패널 및 이를 포함하는 표시 장치

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1755470A (zh) * 2004-07-27 2006-04-05 三星电子株式会社 液晶显示板及薄膜晶体管阵列板
US20090009458A1 (en) * 2007-07-04 2009-01-08 Samsung Electronics Co., Ltd. Thin film transistor array panel and display appratus having the same
CN101706635A (zh) * 2009-11-02 2010-05-12 友达光电股份有限公司 像素阵列、聚合物稳定配向液晶显示面板以及光电装置
CN103323995A (zh) * 2013-06-21 2013-09-25 深圳市华星光电技术有限公司 液晶阵列基板及电子装置
CN104216187A (zh) * 2014-09-04 2014-12-17 深圳市华星光电技术有限公司 像素结构、液晶显示面板及其驱动方法
CN104360556A (zh) * 2014-11-21 2015-02-18 深圳市华星光电技术有限公司 一种液晶显示面板及阵列基板
CN105045009A (zh) * 2015-08-24 2015-11-11 深圳市华星光电技术有限公司 一种液晶显示面板及其阵列基板

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