WO2018126684A1 - 一种显示基板、显示装置及驱动方法 - Google Patents

一种显示基板、显示装置及驱动方法 Download PDF

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Publication number
WO2018126684A1
WO2018126684A1 PCT/CN2017/096712 CN2017096712W WO2018126684A1 WO 2018126684 A1 WO2018126684 A1 WO 2018126684A1 CN 2017096712 W CN2017096712 W CN 2017096712W WO 2018126684 A1 WO2018126684 A1 WO 2018126684A1
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Prior art keywords
common electrode
voltage
sub
line
control
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PCT/CN2017/096712
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English (en)
French (fr)
Inventor
高吉磊
蒋学兵
王庆浦
李君�
陈沫
赵剑
张扬
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京东方科技集团股份有限公司
合肥鑫晟光电科技有限公司
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Priority to US15/779,522 priority Critical patent/US10943551B2/en
Publication of WO2018126684A1 publication Critical patent/WO2018126684A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • the present disclosure relates to the field of display technologies, and in particular, to a display substrate, a display device, and a driving method.
  • TFT-LCD thin film transistor liquid crystal display
  • the thin film transistor liquid crystal display has small size and low power consumption. , no radiation, low manufacturing costs and so on.
  • the requirements for display are also increasing.
  • the design requirements inside the liquid crystal display panel (Panel) are becoming more and more demanding.
  • the voltage of the pixel electrode in different regions of the TFT array substrate may be different when the gate electrode (Gate) is turned off ( ⁇ VP), and the ⁇ VP of different regions may be different.
  • the same common voltage is input, the voltage difference between the pixel voltage and the common voltage in different regions is different, resulting in different gray scale differences and uneven display.
  • the present disclosure provides a display substrate, a display device, and a driving method for solving the difference in voltage between a pixel voltage and a common voltage in different regions of the display panel in the related art, resulting in different gray scale differences and uneven display.
  • the problem is a display substrate, a display device, and a driving method for solving the difference in voltage between a pixel voltage and a common voltage in different regions of the display panel in the related art, resulting in different gray scale differences and uneven display.
  • the present disclosure provides a display substrate, which is divided into a plurality of partitions, each partition including at least one sub-pixel unit, a common electrode voltage input line, a common electrode voltage control line, and at least a control thin film transistor, in the same partition, a gate electrode of the control thin film transistor is connected to the common electrode voltage control line, a source electrode is connected to the common electrode voltage input line, and a drain electrode and a common electrode of the sub-pixel unit connection.
  • each partition includes a row of sub-pixel units.
  • common electrodes of one row of sub-pixel units belonging to the same partition are separately disposed, and each sub-pixel unit corresponds to a control thin film transistor.
  • the display substrate further includes a gate line, and the common electrode voltage input line and the common electrode voltage control line are both parallel to the gate line and are disposed in the same layer and material.
  • the common electrode voltage input line and the common electrode voltage control line of the same row of sub-pixel units are located on the same side of the row of sub-pixel units, and the gate line is located on the other side of the row of sub-pixel units, the same side and the other side One side is the opposite side.
  • control thin film transistor is disposed in the same layer as the gate electrode of the switching thin film transistor in the sub-pixel unit, and the active layer is disposed in the same layer and the same material, and the source electrode and the drain electrode are disposed in the same material.
  • the switching thin film transistors of the odd row sub-pixel units are connected to the data lines of the first side of the corresponding sub-pixel unit, and the source electrodes of the switching thin film transistors of the odd row sub-pixel units are close to the data lines connected thereto, and the drain electrodes Along from the data line connected thereto, the switching thin film transistor of the even row sub-pixel unit is connected to the data line of the second side of the corresponding sub-pixel unit, and the source electrode of the switching thin film transistor of the sub-pixel unit of the odd row is close to the data line connected thereto.
  • the drain electrode is away from the data line connected thereto, the first side is the left side, the second side is the right side, or the first side is the right side and the second side is the left side.
  • multiple rows of sub-pixel units are included in each partition.
  • the common electrodes of the sub-pixel units of each partition are connected together.
  • the present disclosure also provides a display device including the above display substrate and a control module;
  • the control module is connected to the common electrode voltage control line and a common voltage input line for inputting a control voltage to the common electrode voltage control line in different partitions, and inputting a common voltage to the common electrode voltage input line,
  • the pressure difference between the voltage of the common electrode in the different partitions and the voltage of the pixel electrode is made the same.
  • control module inputs the same common voltage to the common electrode voltage input line in different partitions.
  • each of the partitions includes a row of sub-pixel units
  • the control module inputs a control voltage to a common electrode voltage control line in a partition corresponding to the odd row sub-pixel unit and a partition corresponding to the even-numbered row sub-pixel unit.
  • the control voltage input to the common electrode voltage control line is different such that the voltage difference between the voltage of the common electrode and the voltage of the pixel electrode in the different partitions is the same.
  • the common electrode voltage control lines of the odd row sub-pixel units are connected to each other and connected to The control module; the common electrode voltage control lines of the even row sub-pixel units are connected to each other and to the control module.
  • the common electrode voltage control lines of the odd row sub-pixel units are respectively connected to the control module; the common electrode voltage control lines of the even row sub-pixel units are respectively connected to the control module.
  • the present disclosure also provides a driving method of a display device for driving the above display device, the method comprising:
  • the step of inputting a control voltage to the common electrode voltage control line in different partitions, and inputting a common voltage to the common electrode voltage input line includes:
  • the common voltage input to the common electrode voltage input line in the different partitions is the same.
  • each of the partitions includes a row of sub-pixel units
  • the step of inputting a control voltage to the common electrode voltage control line in different partitions, and inputting a common voltage to the common electrode voltage input line includes:
  • the control voltage input to the common electrode voltage control line in the partition corresponding to the odd row sub-pixel unit is different from the control voltage input to the common electrode voltage control line in the partition corresponding to the even-numbered row sub-pixel unit, so that in different partitions
  • the voltage difference between the voltage of the common electrode and the voltage of the pixel electrode is the same.
  • the display substrate is divided into a plurality of partitions, and the common electrodes in each of the partitions are connected to the common electrode voltage input line through the control thin film transistor, and the voltage transmitted on the common electrode voltage input line must pass through the control film.
  • the transistor can enter the common electrode to solve the related art.
  • the display panel of the related art has different voltage difference between the pixel voltage and the common voltage of different partitions, resulting in different gray scale differences and showing unevenness.
  • FIG. 1 is a schematic structural view of an array substrate designed by using a Z-inversion direction in the related art
  • FIG. 2 is a schematic diagram showing the attenuation of the voltage of the pixel electrode of the array substrate in the related art when the gate electrode is turned off;
  • FIG. 3 is a schematic structural view of an array substrate according to at least one embodiment of the present disclosure.
  • Figure 4 is a cross-sectional view taken along line A-A' of the array substrate of Figure 3;
  • FIG. 5 is an equivalent circuit diagram of the array substrate of FIG. 3;
  • FIG. 6 is a schematic structural diagram of an array substrate according to at least one embodiment of the present disclosure.
  • FIG. 7 is a schematic structural view of an array substrate according to at least one embodiment of the present disclosure.
  • At least one embodiment of the present disclosure provides a display substrate, the display The substrate is divided into a plurality of partitions, each partition includes at least one sub-pixel unit, a common electrode voltage input line, a common electrode voltage control line, and at least one control thin film transistor (TFT).
  • the control thin film transistor The gate electrode is connected to the common electrode voltage control line, the source electrode is connected to the common electrode voltage input line, and the drain electrode is connected to the common electrode of the sub-pixel unit.
  • the gate electrode of the control thin film transistor is equivalent to a switch, and by inputting a voltage of a different magnitude to the gate electrode of the control thin film transistor, it is possible to control the degree of opening of the control thin film transistor, that is, control between the source electrode and the drain electrode of the thin film transistor.
  • the size of the current is equivalent to a switch, and by inputting a voltage of a different magnitude to the gate electrode of the control thin film transistor, it is possible to control the degree of opening of the control thin film transistor, that is, control between the source electrode and the drain electrode of the thin film transistor. The size of the current.
  • the voltage transmitted on the common electrode voltage input line must pass through the control thin film transistor to enter the common electrode, and thus at least one embodiment of the present disclosure, Controlling the magnitude of the current between the source electrode and the drain electrode of the control thin film transistor connected thereto by controlling the magnitude of the voltage input to the common electrode voltage control line, thereby controlling the magnitude of the voltage input to the common electrode by the common electrode voltage input line,
  • the display panel in the related art has different voltage difference between the pixel voltage and the common voltage of different partitions, resulting in different gray scale differences and uneven display.
  • the display substrate in at least one embodiment of the present disclosure is an array substrate, and of course, the display substrate is not a color film substrate.
  • the display substrate is used as an array substrate as an example.
  • FIG. 1 is a schematic structural diagram of an array substrate designed by using a Z-inversion direction in a related art, the array substrate including a gate line 101, a data line 102, and a pixel region defined by the gate line 101 and the data line 102.
  • each sub-pixel unit includes a pixel electrode 103 and a common electrode 104, each sub-pixel unit corresponding to a switching thin film transistor, and a gate electrode of the switching thin film transistor is connected to the gate line 101 (at least one implementation of the present disclosure)
  • the gate electrode is directly a part of the gate line 101
  • the source electrode 105 is connected to the data line 102
  • the drain electrode 106 is connected to the pixel electrode 103.
  • the switching thin film transistors of the sub-pixel units located in the first row and the third row are connected to the data lines on the right side of the corresponding sub-pixel unit, in the first row and the third row.
  • the source electrode of the switching thin film transistor of the sub-pixel unit (odd row) is close to the data line connected thereto, and the drain electrode is away from the data line connected thereto, and the switching thin film transistor of the sub-pixel unit of the second row (even row) is corresponding to The data lines on the left side of the sub-pixel unit are connected, and the source electrodes of the switching thin film transistors of the sub-pixel units in the first row and the third row (odd rows) are close to the data lines connected thereto, and the drain electrodes are away from the data lines connected thereto. Therefore, the opening direction of the switching thin film transistor corresponding to the odd row sub-pixel unit is opposite to the opening direction of the switching thin film transistor corresponding to the even row sub-pixel unit.
  • the opening direction of the switching thin film transistor corresponding to the odd row sub-pixel unit and the even row sub-pixel single The opening direction of the switching thin film transistor corresponding to the element is different, and the fluctuation in the precision range of the process is bound to cause the overlapping area and the even row sub-pixel of the gate electrode and the source electrode of the switching thin film transistor corresponding to the odd row sub-pixel unit.
  • the overlapping area of the gate electrode and the source electrode of the switching thin film transistor corresponding to the unit is different. According to the current process precision, the overlapping area of the two is about 5% difference, thereby causing the switching thin film transistor corresponding to the odd row sub-pixel unit.
  • the Cgs gate-source capacitance
  • Vg refers to the gate voltage Vgate
  • Vp refers to the pixel voltage Vpixel
  • Vsig.c refers to the data voltage of the data line, Vcom. It refers to the ideal common electrode voltage obtained according to the conventionally input data voltage without considering ⁇ vp
  • Vcom1 is the common electrode voltage considering ⁇ vp.
  • ⁇ VP is present for each frame of image.
  • ⁇ VP refers to the attenuation of the voltage of the pixel electrode when the gate electrode is closed
  • Cgs is the gate-source capacitance
  • Clc is the liquid crystal capacitor
  • Cst is the storage capacitor
  • ⁇ Vg is VGH (the opening voltage of the gate electrode) and VGL (the gate electrode) The difference in the off voltage).
  • At least one embodiment of the present disclosure provides an array substrate. Referring to FIG. 3, the array substrate is divided into a plurality of partitions 10, each of which includes a row of sub-pixel units, a common electrode voltage input line 3021, and a common electrode.
  • each sub-pixel unit includes a common electrode 303 and a pixel electrode 3081, and in the same partition 10, the gate electrode of the control thin film transistor 20 and the common electrode voltage control Line 3022 is connected (in at least one embodiment of the present disclosure, the gate electrode of control thin film transistor 20 is part of common electrode voltage control line 3022), and source electrode 3061 is connected to said common electrode voltage input line 3021
  • the drain electrode 3062 is connected to the common electrode 303 of the sub-pixel unit.
  • the common electrode 303 of each sub-pixel unit is separately disposed, and each sub-pixel unit corresponds to a control thin film transistor 20.
  • the common electrode voltage can be made by using a metal material.
  • the resulting common electrode voltage input line is quickly transmitted to the common electrode of each sub-pixel unit.
  • the common electrodes of the sub-pixel units in the same row can also be connected together.
  • the row of sub-pixel units can be connected to the common electrode voltage control line 3022 and the common electrode voltage input line 3021 through a control thin film transistor, thereby Save on the number of control thin film transistors.
  • the array substrate further includes: a gate line 3023, a data line 3063, and a switching thin film transistor 30 corresponding to each sub-pixel unit, and the common electrode voltage input line 3021 and the common electrode voltage control line 3022 are both connected to the gate
  • the lines 3023 are parallel and the same layer is provided with the same material, and can be formed by one patterning process, so that the number of masks can be increased and the production cost can be reduced.
  • the common electrode voltage input line 3021 and the common electrode voltage control line 3022 of the same row of sub-pixel units are located on the same side of the row of sub-pixel units, and the gate line 3023 is located in the row of sub-pixel units.
  • the same side and the other side are opposite sides to make the wiring on the array substrate clearer and simpler.
  • Figure 4 is a cross-sectional view taken along the line A-A' of the array substrate of Figure 3;
  • the structure of the array substrate of at least one embodiment of the present disclosure will be described below from the perspective of a cross-sectional view.
  • the array substrate of at least one embodiment of the present disclosure includes:
  • Substrate substrate 301 Substrate substrate 301;
  • the gate metal layer includes: a common electrode voltage input line 3021, a common electrode voltage control line 3022, a gate line 3023, and a gate electrode of the control thin film transistor 10 (in at least one embodiment of the present embodiment, a part of the common electrode voltage control line 3022) a gate electrode (not shown) of the switching thin film transistor, wherein the common electrode voltage input line 3021, the common electrode voltage control line 3022, the gate line 3023, the gate electrode of the control thin film transistor 10, and the gate electrode of the switching thin film transistor pass One patterning process is formed;
  • the common electrode 303, the common electrode 303 is in the same layer as the gate metal layer; the common electrode 303 is usually made of ITO;
  • the source and drain metal layers include: a data line 3063, a source electrode 3061 that controls the thin film transistor 10, and a drain electrode 3062 and a source electrode and a drain electrode (not shown) of the switching thin film transistor, wherein the data line 3063, the source electrode 3061 and the drain electrode 3062 of the control thin film transistor 10, and the source and drain electrodes of the switching thin film transistor pass One patterning process is formed;
  • the pixel electrode layer includes: a pixel electrode 3081 and a via connection portion 3082.
  • the via connection portion 3082 is disposed in the via hole penetrating the passivation layer 307, the source/drain metal layer, and the gate insulating layer 304 for connecting the control thin film transistor.
  • the source electrode 3061 and the common electrode voltage input line 3021 of 10, and the drain electrode 3062 and the common electrode 303 for connecting the control thin film transistor 10; the pixel electrode layer is usually made of ITO.
  • the control thin film transistor 20 is formed simultaneously with the switching thin film transistor 30 in the sub-pixel unit, that is, the gate electrode of the control thin film transistor 20 and the gate electrode of the switching thin film transistor 30 are the same layer.
  • the material arrangement controls the gate insulating layer of the thin film transistor 20 and the gate insulating layer of the switching thin film transistor 30 to be disposed in the same material, and controls the active layer of the thin film transistor 20 and the active layer of the switching thin film transistor 30 to be in the same material.
  • the source electrode and the drain electrode of the control thin film transistor 20 and the source electrode and the drain electrode of the switching thin film transistor 30 are disposed in the same material. Therefore, the number of masks can be increased without reducing the production cost when forming the control thin film transistor.
  • the voltage transmitted on the common electrode voltage input line 3021 must pass through the control thin film transistor 10 to enter the common electrode 303.
  • the voltage control line 3022 can be controlled to the common electrode.
  • the magnitude of the input voltage controls the magnitude of the current between the source electrode 3061 and the drain electrode 3062 of the control thin film transistor 10 connected thereto, thereby controlling the magnitude of the voltage input to the common electrode 303 by the common electrode voltage input line 3021.
  • FIG. 5 is an equivalent circuit diagram of the array substrate of FIG. 3, and FIG. 5 shows a common electrode voltage (Vcom) control circuit and data voltage corresponding to the Nth row sub-pixel unit and the N+1th row sub-pixel unit. )Control circuit.
  • Vcom common electrode voltage
  • the array substrate is divided into a plurality of partitions, each of which includes one row of sub-pixel units, such that the common electrodes of the odd-row sub-pixel units and the even-row sub-pixel units are arranged on the arrangement.
  • Separation which can be separately controlled, can input different voltages to the common electrode voltage input lines of odd-numbered rows and even-row row sub-pixel units as needed, or input the same to common electrode voltage input lines of odd-numbered rows and even-row rows of sub-pixel cells Voltage, and input different voltages to the common electrode voltage control lines of odd-numbered rows and even-row sub-pixel units to control input to odd-numbered rows and even-numbered rows
  • the voltages of the common electrodes of the sub-pixels are the same, and the display panel in the related art has different voltage differences between the pixel voltages of the odd-numbered rows and the even-numbered-row sub-pixel cells and the common voltage, resulting in a difference in gray scale display and poor display of light and dark stripes.
  • the problem is that the screen display is uniform and the picture quality is improved.
  • the direction of the source electrode to the drain electrode in the switching thin film transistor in the odd row sub-pixel unit is opposite to the direction from the source electrode to the drain electrode in the switching thin film transistor in the even row sub-pixel unit,
  • the array substrate of such a structure is more likely to cause a problem that the pixel voltages of the odd-numbered rows and the even-numbered-row sub-pixel cells are different from the voltage difference of the common voltage.
  • the above aspect of at least one embodiment of the present disclosure is also applicable to the source-to-drain electrode direction in the switching thin film transistor in the odd-line sub-pixel unit and the source electrode in the switching thin film transistor in the even-row sub-pixel unit.
  • the directions of the drain electrodes are the same, please refer to FIG. 6.
  • At least one embodiment of the present disclosure shown in FIG. 6 is different from at least one embodiment of the present disclosure shown in FIG. 3 only in the odd-numbered sub-pixel units.
  • the direction from the source electrode to the drain electrode in the switching thin film transistor is the same as the direction from the source electrode to the drain electrode in the switching thin film transistor in the even row sub-pixel unit.
  • each sub-area 10 includes a row of sub-pixel units.
  • each of the partitions 10 may further include a plurality of rows of sub-pixel units, please refer to FIG.
  • each partition 10 includes two rows of sub-pixel units, and common electrodes belonging to sub-pixel units in the same partition are connected together.
  • array substrate of the present disclosure may also adopt other partitioning modes, which will not be exemplified herein.
  • the common electrode voltage input line and the common electrode voltage control line are both parallel to the gate line and are disposed in the same layer, of course, the common electrode voltage input line and the The common electrode voltage control line may also be other arrangement manners.
  • the common electrode voltage input line may be disposed in the same material as the data line, but at the intersection with the data line, a bridge connection is required.
  • the array substrate in at least one embodiment of the present disclosure is an array substrate of an ADS mode.
  • the array substrate in the embodiment of the present disclosure may also be an array substrate of HADS or IPS mode.
  • At least one embodiment of the present disclosure further provides a display device including a display substrate and a control module, wherein the display substrate is the display substrate in any of the above embodiments, and the common electrode voltage on the control module and the display substrate a control line and a common voltage input line are connected for inputting a control voltage to the common electrode voltage control line in different partitions, and inputting a common voltage to the common electrode voltage input line such that voltages of common electrodes in different partitions The voltage difference between the voltage and the pixel electrode is the same.
  • the common voltage input by the control module to the common electrode voltage input line in different partitions is the same, so that it is not necessary to modify the common electrode voltage, as long as the voltage input to the common electrode voltage control line in the partition is controlled, It is convenient and flexible to control the size of the common electrode voltage input to different partitions.
  • each of the partitions includes a row of sub-pixel units, that is, the common electrodes of the odd row sub-pixel unit and the even row sub-pixel unit are separately controllable, and the control module is common to the partition corresponding to the odd row sub-pixel unit.
  • the control voltage input to the electrode voltage control line is different from the control voltage input to the common electrode voltage control line in the partition corresponding to the even-line sub-pixel unit, such that the voltage of the common electrode of the odd-row sub-pixel unit and the voltage of the pixel electrode The pressure difference between them is the same as the voltage difference between the voltage of the common electrode of the even-line sub-pixel unit and the voltage of the pixel electrode.
  • the common electrode voltage control lines of all odd row sub-pixel units may be connected to each other and to the control module, and the common electrode voltage control lines of all even-row sub-pixel units may be connected to each other and connected to Control module.
  • the common electrode voltage control lines of all odd-row sub-pixel units can also be respectively connected to the control module, and the common electrode voltage control lines of all even-row sub-pixel units can be respectively connected to the control module.
  • At least one embodiment of the present disclosure also provides a driving method of a display device for driving the above display device, the method comprising: inputting a control voltage to the common electrode voltage control line in different partitions, and to the public The electrode voltage input line inputs a common voltage such that the voltage difference between the voltage of the common electrode in the different sections and the voltage of the pixel electrode is the same.
  • the step of inputting a control voltage to the common electrode voltage control line in different partitions, and inputting a common voltage to the common electrode voltage input line includes: inputting the common electrode voltage input line in different partitions The input common voltage is the same.
  • each of the partitions includes a row of sub-pixel units; the control voltage is input to the common electrode voltage control line in different partitions, and the input to the common electrode voltage input line is common
  • the step of voltageing includes: a control voltage input to the common electrode voltage control line in the partition corresponding to the odd row sub-pixel unit is different from a control voltage input to the common electrode voltage control line in the partition corresponding to the even-numbered row sub-pixel unit.

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Abstract

一种显示基板、显示装置及驱动方法，该显示基板上划分为多个分区（10），每一分区（10）中包括至少一个亚像素单元、一公共电极电压输入线（3021）、一公共电极电压控制线（3022）和至少一个控制薄膜晶体管（20），同一分区（10）中，控制薄膜晶体管（20）的栅电极与公共电极电压控制线（3022）连接，源电极（3061）与公共电极电压输入线（3021）连接，漏电极（3062）与亚像素单元的公共电极（303）连接。

Description

一种显示基板、显示装置及驱动方法
相关申请的交叉引用
本申请主张在2017年1月3日在中国提交的中国专利申请号No.201710001965.6的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板、显示装置及驱动方法。
背景技术
随着生活质量的日益提升，平板显示器已经成为生活中不可或缺的一部分，目前平板显示器中的主流之一是薄膜晶体管液晶显示器(TFT-LCD)，薄膜晶体管液晶显示器具有体积小、功耗低、无辐射、制造成本低等优点。随着显示行业的发展和人民物质水平的提高，对显示的要求也越来越高。为了满足高标准的显示，对液晶显示面板(Panel)内部的设计要求也越来越苛刻。
目前TFT阵列基板中，由于设计或工艺等方面的影响，可能会造成TFT阵列基板不同区域的像素电极在栅电极(Gate)关闭时电压的衰减(ΔVP)不同，不同区域的ΔVP存在差异，使得在输入相同公共电压下，不同区域的像素电压与公共电压的压差不同，导致灰阶差异不同，显示不均一。
发明内容
有鉴于此，本公开提供一种显示基板、显示装置及驱动方法，用于解决相关技术中的显示面板中不同区域的像素电压与公共电压的压差不同，导致灰阶差异不同，显示不均一的问题。
为解决上述技术问题，本公开提供一种显示基板，所述显示基板划分为多个分区，每一分区中包括至少一个亚像素单元、一公共电极电压输入线、一公共电极电压控制线和至少一个控制薄膜晶体管，同一分区中，所述控制薄膜晶体管的栅电极与所述公共电极电压控制线连接，源电极与所述公共电极电压输入线连接，漏电极与所述亚像素单元的公共电极连接。
可选的，每一分区中包括一行亚像素单元。
可选的，属于同一分区中的一行亚像素单元的公共电极分开设置，每一亚像素单元对应一控制薄膜晶体管。
可选的，所述显示基板还包括栅线，所述公共电极电压输入线和所述公共电极电压控制线均与所述栅线平行且同层同材料设置。
可选的，同一行亚像素单元的公共电极电压输入线和公共电极电压控制线位于该行亚像素单元的同一侧，栅线位于该行亚像素单元的另一侧，所述同一侧和另一侧为相对的两侧。
可选的，所述控制薄膜晶体管与所述亚像素单元中的开关薄膜晶体管的栅电极同层同材料设置，有源层同层同材料设置，源电极和漏电极同层同材料设置。
可选的，，奇数行亚像素单元的开关薄膜晶体管均与对应的亚像素单元第一侧的数据线连接，奇数行亚像素单元的开关薄膜晶体管的源电极靠近与其连接的数据线，漏电极远离与其连接的数据线，偶数行亚像素单元的开关薄膜晶体管与对应的亚像素单元第二侧的数据线连接，奇数行的亚像素单元的开关薄膜晶体管的源电极靠近与其连接的数据线，而漏电极远离与其连接的数据线，第一侧为左侧，第二侧为右侧，或者，第一侧为右侧，第二侧为左侧。
可选的，每一分区中包括多行亚像素单元。
可选的，每一分区的亚像素单元的公共电极连接在一起。
本公开还提供一种显示装置，包括上述显示基板和控制模块；
所述控制模块与所述公共电极电压控制线和公共电压输入线连接，用于向不同分区中的所述公共电极电压控制线输入控制电压，以及向所述公共电极电压输入线输入公共电压，以使得不同分区中的公共电极的电压和像素电极的电压之间的压差相同。
可选的，所述控制模块向不同分区中的所述公共电极电压输入线输入的公共电压相同。
可选的，每一所述分区包括一行亚像素单元，所述控制模块向奇数行亚像素单元对应的分区中的公共电极电压控制线输入的控制电压与向偶数行亚像素单元对应的分区中的所述公共电极电压控制线输入的控制电压不同，以使得不同分区中的公共电极的电压和像素电极的电压之间的压差相同。
可选的，奇数行亚像素单元的公共电极电压控制线相互连接，并连接至 所述控制模块；偶数行亚像素单元的公共电极电压控制线相互连接，并连接至所述控制模块。
可选的，奇数行亚像素单元的公共电极电压控制线分别连接至所述控制模块；偶数行亚像素单元的公共电极电压控制线分别连接至所述控制模块。
本公开还提供一种显示装置的驱动方法，用于驱动上述显示装置，所述方法包括：
向不同分区中的所述公共电极电压控制线输入控制电压，以及向所述公共电极电压输入线输入公共电压，以使得不同分区中的公共电极的电压和像素电极的电压之间的压差相同。
可选的，所述向不同分区中的所述公共电极电压控制线输入控制电压，以及向所述公共电极电压输入线输入公共电压的步骤包括：
向不同分区中的所述公共电极电压输入线输入的公共电压相同。
可选的，每一所述分区包括一行亚像素单元；
所述向不同分区中的所述公共电极电压控制线输入控制电压，以及向所述公共电极电压输入线输入公共电压的步骤包括：
向奇数行亚像素单元对应的分区中的公共电极电压控制线输入的控制电压与向偶数行亚像素单元对应的分区中的所述公共电极电压控制线输入的控制电压不同，以使得不同分区中的公共电极的电压和像素电极的电压之间的压差相同。
本公开的上述技术方案的有益效果如下：
本公开的至少一个实施例中，显示基板划分为多个分区，每一分区中的公共电极均通过控制薄膜晶体管与公共电极电压输入线连接，公共电极电压输入线上传输的电压必须通过控制薄膜晶体管才能够进入公共电极解决相关技术中的显示面板因不同分区的像素电压与公共电压的压差不同，导致灰阶差异不同，显示不均一的问题。
附图说明
图1为相关技术中的采用Z-inversion方向设计的阵列基板的结构示意图；
图2为相关技术中的阵列基板的像素电极的电压在栅电极关闭时产生衰减的示意图；
图3为本公开的至少一个实施例的阵列基板的结构示意图；
图4为图3中的阵列基板的A-A’剖视图；
图5为图3中的阵列基板的等效电路图；
图6为本公开的至少一个实施例的阵列基板的结构示意图；
图7为本公开的至少一个实施例的阵列基板的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非另作定义，此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开专利申请说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”或者“一”等类似词语也不表示数量限制，而是表示存在至少一个。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也相应地改变。
为解决相关技术中的显示面板中不同区域的像素电压与公共电压的压差不同，导致灰阶差异不同，显示不均一的问题，本公开的至少一个实施例提供一种显示基板，所述显示基板划分为多个分区，每一分区中包括至少一个亚像素单元、一公共电极电压输入线、一公共电极电压控制线和至少一个控制薄膜晶体管(TFT)，同一分区中，所述控制薄膜晶体管的栅电极与所述公共电极电压控制线连接，源电极与所述公共电极电压输入线连接，漏电极与所述亚像素单元的公共电极连接。
其中，控制薄膜晶体管的栅电极相当于一个开关，通过向控制薄膜晶体管的栅电极输入大小不同的电压，可以控制控制薄膜晶体管的打开程度，即控制控制薄膜晶体管的源电极和漏电极之间的电流的大小。
由于本公开的至少一个实施例中，公共电极电压输入线上传输的电压必须通过控制薄膜晶体管才能够进入公共电极，因而利用上述控制薄膜晶体管的工作原理，本公开的至少一个实施例中，可以通过控制向公共电极电压控制线输入的电压的大小，控制与其连接的控制薄膜晶体管的源电极和漏电极之间的电流的大小，从而控制公共电极电压输入线输入至公共电极的电压的大小，以使得不同区域的像素电压与公共电压的压差相同，解决相关技术中的显示面板因不同分区的像素电压与公共电压的压差不同，导致灰阶差异不同，显示不均一的问题。
可选的，本公开的至少一个实施例中的显示基板为阵列基板，当然，也不排除该显示基板是彩膜基板的可能。以下实施例中，均以显示基板为阵列基板为例进行说明。
目前，大量阵列基板在设计方面采用Z-inversion方向设计，即，奇数行亚像素单元对应的开关薄膜晶体管的开口方向与偶数行亚像素单元对应的开关薄膜晶体管的开口方向相反，所谓开口方向是指开关薄膜晶体管中的源电极指向漏电极的方向。请参见图1，图1为相关技术中的采用Z-inversion方向设计的阵列基板的结构示意图，该阵列基板包括栅线101、数据线102和位于由栅线101和数据线102限定的像素区域中的亚像素单元，每一亚像素单元均包括像素电极103和公共电极104，每一亚像素单元对应一开关薄膜晶体管，开关薄膜晶体管的栅电极与栅线101连接(本公开的至少一个实施例中，栅电极直接是栅线101的一部分)，源电极105与数据线102连接，漏电极106与像素电极103连接。从图1中可以看出，位于第一行和第三行(奇数行)的亚像素单元的开关薄膜晶体管均与对应的亚像素单元右侧的数据线连接，位于第一行和第三行(奇数行)的亚像素单元的开关薄膜晶体管的源电极靠近与其连接的数据线，而漏电极远离与其连接的数据线，位于第二行(偶数行)亚像素单元的开关薄膜晶体管与对应的亚像素单元左侧的数据线连接，位于第一行和第三行(奇数行)的亚像素单元的开关薄膜晶体管的源电极靠近与其连接的数据线，而漏电极远离与其连接的数据线，从而使得奇数行亚像素单元对应的开关薄膜晶体管的开口方向与偶数行亚像素单元对应的开关薄膜晶体管的开口方向相反。
奇数行亚像素单元对应的开关薄膜晶体管的开口方向与偶数行亚像素单 元对应的开关薄膜晶体管的开口方向不同，再加上工艺上精度范围内的波动，势必会造成奇数行亚像素单元对应的开关薄膜晶体管的栅电极与源电极的交叠面积与偶数行亚像素单元对应的开关薄膜晶体管的栅电极与源电极的交叠面积不同，按照目前的工艺精度，两者的交叠面积约有5％的差异，从而造成奇数行亚像素单元对应的开关薄膜晶体管的Cgs(栅源电容)与偶数行亚像素单元对应的开关薄膜晶体管的Cgs不同。
像素电极的电压在栅电极关闭时会产生衰减ΔVP，请参考图2，图2中，Vg是指栅极电压Vgate，Vp是指像素电压Vpixel，Vsig.c是指数据线的数据电压，Vcom是指根据常规输入的数据电压，不考虑Δvp的情况下，得到的理想公共电极电压，Vcom1是考虑Δvp情况下的公共电极电压。从图2中可以看出，每一帧图像都存在ΔVP。
另外，请参考以下公式：
Figure PCTCN2017096712-appb-000001
其中，ΔVP是指像素电极的电压在栅电极关闭时产生的衰减，Cgs是栅源电容，Clc是液晶电容，Cst是存储电容，ΔVg是指VGH(栅电极的打开电压)和VGL(栅电极的关闭电压)的差值。
从上述公式可以看出，奇数行亚像素单元对应的开关薄膜晶体管的Cgs与偶数行亚像素单元对应的开关薄膜晶体管的Cgs不同时，会造成奇数行亚像素单元的ΔVP与偶数行亚像素单元的ΔVP不同，使得奇数行亚像素单元和偶数行亚像素单元在输入相同的公共电压的情况下，公共电极的电压与像素电极的电压之间的差值不同，从而导致灰阶显示差异，形成明暗相间条纹的显示不良。
为了解决相关技术中的奇数行亚像素单元与偶数行亚像素单元的公共电极的电压与像素电极的电压之间的差值不同，导致灰阶显示差异，形成明暗相间条纹的显示不良的问题，本公开的至少一个实施例提供一种阵列基板，请参考图3，该阵列基板划分为多个分区10，每一分区10中包括一行亚像素单元、一公共电极电压输入线3021、一公共电极电压控制线3022和多个控制薄膜晶体管20，其中，每一亚像素单元中包括公共电极303和像素电极3081，同一分区10中，所述控制薄膜晶体管20的栅电极与所述公共电极电压控制线3022连接(本公开的至少一个实施例中，控制薄膜晶体管20的栅电极是公共电极电压控制线3022的一部分)，源电极3061与所述公共电极电压输入线3021连 接，漏电极3062与所述亚像素单元的公共电极303连接。
本公开的至少一个实施例中，每一亚像素单元的公共电极303均分开设置，每一亚像素单元均对应一控制薄膜晶体管20，该种设置方式下，公共电极电压可以通过采用金属材料制成的公共电极电压输入线快速传输至每一亚像素单元的公共电极。当然，处于同一行的亚像素单元的公共电极也可以连接在一起，此时，该行亚像素单元可以通过一个控制薄膜晶体管与公共电极电压控制线3022和公共电极电压输入线3021连接，从而可节省控制薄膜晶体管的数量。
所述阵列基板还包括：栅线3023、数据线3063以及与每一亚像素单元对应的开关薄膜晶体管30，所述公共电极电压输入线3021和所述公共电极电压控制线3022均与所述栅线3023平行且同层同材料设置，可通过一次构图工艺形成，从而可以不增加mask数量，降低生产成本。
另外，本公开的至少一个实施例中，同一行亚像素单元的公共电极电压输入线3021和公共电极电压控制线3022位于该行亚像素单元的同一侧，栅线3023位于该行亚像素单元的另一侧，所述同一侧和另一侧为相对的两侧从而使得阵列基板上的布线更清晰简单。
图4是图3中的阵列基板的A-A’剖视图。
下面从剖视图的角度出发，对本公开的至少一个实施例的阵列基板的结构进行说明。本公开的至少一个实施例的阵列基板包括：
衬底基板301；
栅金属层，包括：公共电极电压输入线3021、公共电极电压控制线3022、栅线3023、控制薄膜晶体管10的栅电极(本的至少一个实施例中，为公共电极电压控制线3022的一部分)、开关薄膜晶体管的栅电极(图未示出)，其中，公共电极电压输入线3021、公共电极电压控制线3022、栅线3023、控制薄膜晶体管10的栅电极、开关薄膜晶体管的栅电极，通过一次构图工艺形成；
公共电极303，公共电极303与栅金属层同层；公共电极303通常采用ITO制成；
栅极绝缘层304；
有源层305；
源漏金属层，包括：数据线3063、控制薄膜晶体管10的源电极3061和 漏电极3062以及开关薄膜晶体管的源电极和漏电极(图未示出)，其中，数据线3063、控制薄膜晶体管10的源电极3061和漏电极3062以及开关薄膜晶体管的源电极和漏电极，通过一次构图工艺形成；
钝化层307；
像素电极层，包括：像素电极3081和过孔连接部3082，过孔连接部3082设置于贯穿钝化层307、源漏金属层和栅极绝缘层304的过孔中，用于连接控制薄膜晶体管10的源电极3061与公共电极电压输入线3021，以及用于连接控制薄膜晶体管10的漏电极3062与公共电极303；像素电极层通常采用ITO制成。
本公开的至少一个实施例中，所述控制薄膜晶体管20与所述亚像素单元中的开关薄膜晶体管30同时形成，即，控制薄膜晶体管20的栅电极和开关薄膜晶体管30的栅电极同层同材料设置，控制薄膜晶体管20的栅极绝缘层和开关薄膜晶体管30的栅极绝缘层同层同材料设置，控制薄膜晶体管20的有源层和开关薄膜晶体管30的有源层同层同材料设置，控制薄膜晶体管20的源电极和漏电极和开关薄膜晶体管30的源电极和漏电极同层同材料设置。从而使得形成控制薄膜晶体管时可以不增加mask数量，降低生产成本。
从图4中可以看出，公共电极电压输入线3021上传输的电压必须通过控制薄膜晶体管10才能够进入公共电极303，利用控制薄膜晶体管10的工作原理，可以通过控制向公共电极电压控制线3022输入的电压的大小，控制与其连接的控制薄膜晶体管10的源电极3061和漏电极3062之间的电流的大小，从而控制公共电极电压输入线3021输入至公共电极303的电压的大小。
图5为图3中的阵列基板的等效电路图，图5中示出了第N行亚像素单元和第N+1行亚像素单元对应的公共电极电压(Vcom)控制电路和数据电压(Data)控制电路。
本公开的至少一个实施例中，阵列基板划分为多个分区，每一分区中的包括一行亚像素单元，从而使得奇数行亚像素单元和偶数行亚像素单元的公共电极在排布上进行了分离，能够分开进行控制，可以根据需要向奇数行和偶数行亚像素单元的公共电极电压输入线输入不同的电压，或者，向奇数行和偶数行亚像素单元的公共电极电压输入线输入相同的电压，且向奇数行和偶数行亚像素单元的公共电极电压控制线输入不同的电压，以控制输入至奇数行和偶数行 亚像素的公共电极的电压相同，解决相关技术中的显示面板因奇数行和偶数行亚像素单元的像素电压与公共电压的压差不同，导致灰阶显示差异，形成明暗相间条纹的显示不良的问题，实现了画面显示均匀，提升了画面品质。
本公开的至少一个实施例中，奇数行亚像素单元中的开关薄膜晶体管中的源电极到漏电极的方向与偶数行亚像素单元中的开关薄膜晶体管中的源电极到漏电极的方向相反，该种结构的阵列基板更容易产生奇数行和偶数行亚像素单元的像素电压与公共电压的压差不同的问题。
当然，本公开的至少一个实施例的上述方案也适用于奇数行亚像素单元中的开关薄膜晶体管中的源电极到漏电极的方向与偶数行亚像素单元中的开关薄膜晶体管中的源电极到漏电极的方向相同的情况，请参考图6，图6所示的本公开的至少一个实施例与图3所示的本公开的至少一个实施例的区别仅在于：奇数行亚像素单元中的开关薄膜晶体管中的源电极到漏电极的方向与偶数行亚像素单元中的开关薄膜晶体管中的源电极到漏电极的方向相同。
本公开的至少一个实施例中，每一分区10中包括一行亚像素单元，当然，在本公开的至少一个实施例中，每一分区10还可以包括多行亚像素单元，请参考图7，图7所示的本公开的至少一个实施例中，每一分区10包括两行亚像素单元，属于同一分区中的亚像素单元的公共电极连接在一起。本公开的至少一个实施例中，同一分区10中，只需要一个公共电极电压输入线、一个公共电极电压控制线和一个控制薄膜晶体管即可控制两行亚像素单元的公共电极的输入，节省了公共电极电压输入线、公共电极电压控制线和控制薄膜晶体管的数量，且增加了阵列基板的开口率。
当然，本公开的阵列基板还可以采用其他分区方式，在此不再一一举例说明。
本公开的至少一个实施例中，所述公共电极电压输入线和所述公共电极电压控制线均与所述栅线平行且同层同材料设置，当然，所述公共电极电压输入线和所述公共电极电压控制线也可以是其他设置方式，例如所述公共电极电压输入线可以与数据线同层同材料设置，但是在与数据线的交叉处需要采用过桥的方式连接。
本公开的至少一个实施例中的阵列基板为ADS模式的阵列基板，当然，本公开实施例中的阵列基板也可以HADS、IPS模式的阵列基板。
本公开的至少一个实施例还提供一种显示装置，包括显示基板和控制模块，所述显示基板为上述任一实施例中的显示基板，所述控制模块与所述显示基板上的公共电极电压控制线和公共电压输入线连接，用于向不同分区中的所述公共电极电压控制线输入控制电压，以及向所述公共电极电压输入线输入公共电压，以使得不同分区中的公共电极的电压和像素电极的电压之间的压差相同。
可选的，所述控制模块向不同分区中的所述公共电极电压输入线输入的公共电压相同，从而无需修改公共电极电压，只要控制向分区中的公共电极电压控制线输入的电压的大小，便可控制输入至不同分区中的公共电极电压的大小，方便灵活。
可选的，每一所述分区包括一行亚像素单元，即奇数行亚像素单元和偶数行亚像素单元的公共电极可分开控制，所述控制模块向奇数行亚像素单元对应的分区中的公共电极电压控制线输入的控制电压与向偶数行亚像素单元对应的分区中的所述公共电极电压控制线输入的控制电压不同，以使得奇数行亚像素单元的公共电极的电压和像素电极的电压之间的压差与偶数行亚像素单元的公共电极的电压和像素电极的电压之间的压差相同。
本公开的至少一个实施例中，所有奇数行亚像素单元的公共电极电压控制线可相互连接，并连接至控制模块，所有偶数行亚像素单元的公共电极电压控制线可以相互连接，并连接至控制模块。当然，所有奇数行亚像素单元的公共电极电压控制线也可以分别连接至控制模块，所有偶数行亚像素单元的公共电极电压控制线可以分别连接至控制模块。
本公开的至少一个实施例还提供一种显示装置的驱动方法，用于驱动上述显示装置，所述方法包括：向不同分区中的所述公共电极电压控制线输入控制电压，以及向所述公共电极电压输入线输入公共电压，以使得不同分区中的公共电极的电压和像素电极的电压之间的压差相同。
可选的，所述向不同分区中的所述公共电极电压控制线输入控制电压，以及向所述公共电极电压输入线输入公共电压的步骤包括：向不同分区中的所述公共电极电压输入线输入的公共电压相同。
可选的，每一所述分区包括一行亚像素单元；所述向不同分区中的所述公共电极电压控制线输入控制电压，以及向所述公共电极电压输入线输入公共 电压的步骤包括：向奇数行亚像素单元对应的分区中的公共电极电压控制线输入的控制电压与向偶数行亚像素单元对应的分区中的所述公共电极电压控制线输入的控制电压不同。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (17)

  1. 一种显示基板，其中，所述显示基板划分为多个分区，每一分区中包括至少一个亚像素单元、一公共电极电压输入线、一公共电极电压控制线和至少一个控制薄膜晶体管，同一分区中，所述控制薄膜晶体管的栅电极与所述公共电极电压控制线连接，源电极与所述公共电极电压输入线连接，漏电极与所述亚像素单元的公共电极连接。
  2. 根据权利要求1所述的显示基板，其中，每一分区中包括一行亚像素单元。
  3. 根据权利要求2所述的显示基板，其中，属于同一分区中的一行亚像素单元的公共电极分开设置，每一亚像素单元对应一控制薄膜晶体管。
  4. 根据权利要求1所述的显示基板，还包括栅线，所述公共电极电压输入线和所述公共电极电压控制线均与所述栅线平行且同层同材料设置。
  5. 根据权利要求4所述的显示基板，其中，同一行亚像素单元的公共电极电压输入线和公共电极电压控制线位于该行亚像素单元的同一侧，栅线位于该行亚像素单元的另一侧，所述同一侧和另一侧为相对的两侧。
  6. 根据权利要求1所述的显示基板，其中，所述控制薄膜晶体管与所述亚像素单元中的开关薄膜晶体管的栅电极同层同材料设置，有源层同层同材料设置，源电极和漏电极同层同材料设置。
  7. 根据权利要求2-6任一项所述的显示基板，其中，奇数行亚像素单元的开关薄膜晶体管均与对应的亚像素单元第一侧的数据线连接，奇数行亚像素单元的开关薄膜晶体管的源电极靠近与其连接的数据线，漏电极远离与其连接的数据线，偶数行亚像素单元的开关薄膜晶体管与对应的亚像素单元第二侧的数据线连接，奇数行的亚像素单元的开关薄膜晶体管的源电极靠近与其连接的数据线，而漏电极远离与其连接的数据线，第一侧为左侧，第二侧为右侧，或者，第一侧为右侧，第二侧为左侧。
  8. 根据权利要求1所述的显示基板，其中，每一分区中包括多行亚像素单元。
  9. 根据权利要求8所述的显示基板，其中，每一分区的亚像素单元的公共电极连接在一起。
  10. 一种显示装置，包括如权利要求1-9任一项所述的显示基板和控制模块；
    所述控制模块与所述公共电极电压控制线和公共电压输入线连接，用于向不同分区中的所述公共电极电压控制线输入控制电压，以及向所述公共电极电压输入线输入公共电压，以使得不同分区中的公共电极的电压和像素电极的电压之间的压差相同。
  11. 根据权利要求10所述的显示装置，其中，所述控制模块向不同分区中的所述公共电极电压输入线输入的公共电压相同。
  12. 根据权利要求11所述的显示装置，其中，每一所述分区包括一行亚像素单元，所述控制模块向奇数行亚像素单元对应的分区中的公共电极电压控制线输入的控制电压与向偶数行亚像素单元对应的分区中的所述公共电极电压控制线输入的控制电压不同，以使得不同分区中的公共电极的电压和像素电极的电压之间的压差相同。
  13. 根据权利要求10所述的显示装置，其中，奇数行亚像素单元的公共电极电压控制线相互连接，并连接至所述控制模块；偶数行亚像素单元的公共电极电压控制线相互连接，并连接至所述控制模块。
  14. 根据权利要求10所述的显示装置，其中，奇数行亚像素单元的公共电极电压控制线分别连接至所述控制模块；偶数行亚像素单元的公共电极电压控制线分别连接至所述控制模块。
  15. 一种显示装置的驱动方法，用于驱动如权利要求10-14任一项所述的显示装置，所述方法包括：
    向不同分区中的所述公共电极电压控制线输入控制电压，以及向所述公共电极电压输入线输入公共电压，以使得不同分区中的公共电极的电压和像素电极的电压之间的压差相同。
  16. 根据权利要求15所述的显示装置的驱动方法，其中，所述向不同分区中的所述公共电极电压控制线输入控制电压，以及向所述公共电极电压输入线输入公共电压的步骤包括：
    向不同分区中的所述公共电极电压输入线输入的公共电压相同。
  17. 根据权利要求16所述的显示装置的驱动方法，其中，每一所述分区包括一行亚像素单元；
    所述向不同分区中的所述公共电极电压控制线输入控制电压，以及向所述公共电极电压输入线输入公共电压的步骤包括：
    向奇数行亚像素单元对应的分区中的公共电极电压控制线输入的控制电压与向偶数行亚像素单元对应的分区中的所述公共电极电压控制线输入的控制电压不同，以使得不同分区中的公共电极的电压和像素电极的电压之间的压差相同。
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