WO2017031793A1 - 一种液晶显示面板及其阵列基板 - Google Patents

一种液晶显示面板及其阵列基板 Download PDF

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Publication number
WO2017031793A1
WO2017031793A1 PCT/CN2015/089430 CN2015089430W WO2017031793A1 WO 2017031793 A1 WO2017031793 A1 WO 2017031793A1 CN 2015089430 W CN2015089430 W CN 2015089430W WO 2017031793 A1 WO2017031793 A1 WO 2017031793A1
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Prior art keywords
thin film
film transistor
nth
pixel unit
scan line
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PCT/CN2015/089430
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English (en)
French (fr)
Inventor
刘桓
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深圳市华星光电技术有限公司
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Priority to US14/783,818 priority Critical patent/US9857650B2/en
Publication of WO2017031793A1 publication Critical patent/WO2017031793A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present invention relates to the field of liquid crystal display technologies, and in particular, to a liquid crystal display panel and an array substrate thereof.
  • VA Vertical Alignment, vertical alignment
  • liquid crystal display generally divides the pixel into a main pixel area and a sub-pixel area, and the pixel voltage of the sub-pixel area is lower than the pixel voltage of the main pixel unit, so that the liquid crystal in the sub-pixel area is reversed and located at the main
  • the liquid crystals in the pixel area are reversed differently, thereby improving the bias of the large-view character.
  • the prior art In order to make the pixel voltage of the sub-pixel region lower than the pixel voltage of the main pixel unit, the prior art has a shared scan line disposed by each pixel, but the shared scan line occupies the aperture ratio of the pixel, thereby affecting the penetration of the liquid crystal display. rate.
  • the embodiment of the invention provides a liquid crystal display panel and an array substrate thereof, which can reduce the aperture ratio occupied by the shared scan line and improve the aperture ratio of the pixel.
  • the present invention provides an array substrate including a substrate, a plurality of scan lines, a plurality of data lines, and a plurality of shared scan lines.
  • the plurality of scan lines and the plurality of data lines are disposed on the substrate to form a plurality of pixel units.
  • Each of the pixel units includes a main pixel unit and a sub-pixel unit, and sub-pixel units of two adjacent pixel units are adjacently disposed, and two adjacent sub-pixel units share one shared scan line, and the shared scan line is used to simultaneously drive adjacent ones.
  • Two sub-pixel units wherein two adjacent pixel units include an Nth pixel unit and an N+1th pixel unit disposed adjacent to each other along a data line extending direction, and the Nth pixel unit includes an Nth main pixel a unit, an Nth sub-pixel unit, and an Nth sharing capacitor, the N+1th pixel unit includes an N+1th main pixel unit, an N+1th sub-pixel unit, and an N+1th sharing capacitor; the Nth The pixel unit is located between the Nth scan line and the Mth shared scan line, and the N+1th pixel unit is located between the Mth shared scan line and the N+1th scan line; the Nth pixel unit and the Between N+1 pixel units
  • the array substrate further includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, and a sixth thin film transistor.
  • the gate of the first thin film transistor is connected to the Nth scan line.
  • a source of the first thin film transistor is connected to the Nth data line, a drain of the first thin film transistor is connected to the Nth main pixel unit, a gate of the second thin film transistor is connected to the Nth scan line, and a second thin film
  • the source of the transistor is connected to the Nth data line, the drain of the second thin film transistor is connected to the Nth sub-pixel unit;
  • the gate of the third thin film transistor is connected to the Mth shared scan line, and the source of the third thin film transistor Connected to the Nth sub-pixel unit, the drain of the third thin film transistor is connected to the Nth shared capacitor;
  • the gate of the fourth thin film transistor is connected to the N+1th scan line, and the source and the Nth of the fourth thin film transistor are connected
  • the data lines are connected, the drain of the fourth thin film transistor is connected to the (N+1)th main pixel unit;
  • the gate of the fifth thin film transistor is connected to the (N+1)th scan line, and the source of the fifth thin film transistor Connected
  • the present invention also provides an array substrate comprising a substrate, a plurality of scan lines, a plurality of data lines, and a plurality of shared scan lines, wherein the plurality of scan lines and the plurality of data lines are disposed on the substrate to form a plurality of pixel units
  • Each pixel unit includes a main pixel unit and a sub-pixel unit, and sub-pixel units of two adjacent pixel units are adjacently disposed, and two adjacent sub-pixel units share one shared scan line, and the shared scan line is used to simultaneously drive adjacent Two sub-pixel units.
  • the adjacent two pixel units include an Nth pixel unit and an N+1th pixel unit disposed adjacent to each other along a data line extending direction, and the Nth pixel unit includes an Nth main pixel unit and an Nth sub-unit.
  • the pixel unit and the Nth sharing capacitor, the N+1th pixel unit includes an N+1th main pixel unit, an N+1th sub-pixel unit, and an N+1th sharing capacitor.
  • the Nth pixel unit is located between the Nth scan line and the Mth shared scan line, and the N+1th pixel unit is located between the Mth shared scan line and the (N+1)th scan line.
  • the array substrate further includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, and a sixth thin film transistor.
  • the gate of the first thin film transistor is connected to the Nth scan line.
  • a source of the first thin film transistor is connected to the Nth data line, a drain of the first thin film transistor is connected to the Nth main pixel unit, a gate of the second thin film transistor is connected to the Nth scan line, and a second thin film
  • the source of the transistor is connected to the Nth data line, the drain of the second thin film transistor is connected to the Nth sub-pixel unit;
  • the gate of the third thin film transistor is connected to the Mth shared scan line, and the source of the third thin film transistor Connected to the Nth sub-pixel unit, the drain of the third thin film transistor is connected to the Nth shared capacitor;
  • the gate of the fourth thin film transistor is connected to the N+1th scan line, and the source and the Nth of the fourth thin film transistor are connected
  • the data lines are connected, the drain of the fourth thin film transistor is connected to the (N+1)th main pixel unit;
  • the gate of the fifth thin film transistor is connected to the (N+1)th scan line, and the source of the fifth thin film transistor Connected
  • the Mth shared scan line is connected to the N+2th scan line.
  • the Nth scan line when the Nth scan line is turned on, the N+1th scan line and the N+2th scan line are turned off, the first thin film transistor and the second thin film transistor are turned on, and the Nth data line is the Nth main The pixel unit and the Nth sub-pixel unit are charged; when the N+1th scan line is turned on, the Nth scan line and the N+2th scan line are turned off, the fourth thin film transistor and the fifth thin film transistor are turned on, Nth The strip data lines charge the N+1th main pixel unit and the N+1th sub-pixel unit.
  • the N+2th scan line when the N+2th scan line is turned on, the N+1th scan line and the Nth scan line are turned off, the third thin film transistor and the sixth thin film transistor are turned on, and the Nth sub-pixel unit is shared with the Mth The capacitor is connected, and the N+1th sub-pixel unit is connected to the Mth shared capacitor to reduce the voltage of the Nth sub-pixel unit and the (N+1)th sub-pixel unit.
  • the pixel electrode of each pixel unit is ITO.
  • the present invention further provides a liquid crystal display panel, comprising an array substrate, the array substrate comprising a substrate, a plurality of scan lines, a plurality of data lines, and a plurality of shared scan lines, wherein the plurality of scan lines and the plurality of data lines are disposed on the substrate a plurality of pixel units, each of the pixel units includes a main pixel unit and a sub-pixel unit, the sub-pixel units of the adjacent two pixel units are adjacently disposed, and the adjacent two sub-pixel units share a shared scan line, and the shared scan The line is used to drive two adjacent sub-pixel units simultaneously.
  • the adjacent two pixel units include an Nth pixel unit and an N+1th pixel unit disposed adjacent to each other along a data line extending direction, and the Nth pixel unit includes an Nth main pixel unit and an Nth sub-unit.
  • the pixel unit and the Nth sharing capacitor, the N+1th pixel unit includes an N+1th main pixel unit, an N+1th sub-pixel unit, and an N+1th sharing capacitor.
  • the Nth pixel unit is located between the Nth scan line and the Mth shared scan line, and the N+1th pixel unit is located between the Mth shared scan line and the (N+1)th scan line.
  • the array substrate further includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, and a sixth thin film transistor.
  • the gate of the first thin film transistor is connected to the Nth scan line.
  • a source of the first thin film transistor is connected to the Nth data line, a drain of the first thin film transistor is connected to the Nth main pixel unit, a gate of the second thin film transistor is connected to the Nth scan line, and a second thin film
  • the source of the transistor is connected to the Nth data line, the drain of the second thin film transistor is connected to the Nth sub-pixel unit;
  • the gate of the third thin film transistor is connected to the Mth shared scan line, and the source of the third thin film transistor Connected to the Nth sub-pixel unit, the drain of the third thin film transistor is connected to the Nth shared capacitor;
  • the gate of the fourth thin film transistor is connected to the N+1th scan line, and the source and the Nth of the fourth thin film transistor are connected
  • the data lines are connected, the drain of the fourth thin film transistor is connected to the (N+1)th main pixel unit;
  • the gate of the fifth thin film transistor is connected to the (N+1)th scan line, and the source of the fifth thin film transistor Connected
  • the Mth shared scan line is connected to the N+2th scan line.
  • the Nth scan line when the Nth scan line is turned on, the N+1th scan line and the N+2th scan line are turned off, the first thin film transistor and the second thin film transistor are turned on, and the Nth data line is the Nth main The pixel unit and the Nth sub-pixel unit are charged; when the N+1th scan line is turned on, the Nth scan line and the N+2th scan line are turned off, the fourth thin film transistor and the fifth thin film transistor are turned on, Nth The strip data lines charge the N+1th main pixel unit and the N+1th sub-pixel unit.
  • the N+2th scan line when the N+2th scan line is turned on, the N+1th scan line and the Nth scan line are turned off, the third thin film transistor and the sixth thin film transistor are turned on, and the Nth sub-pixel unit is shared with the Mth The capacitor is connected, and the N+1th sub-pixel unit is connected to the Mth shared capacitor to reduce the voltage of the Nth sub-pixel unit and the (N+1)th sub-pixel unit.
  • the pixel electrode of each pixel unit is ITO.
  • the present invention is configured by setting a substrate, a plurality of scan lines, a plurality of data lines, and a plurality of shared scan lines, wherein the plurality of scan lines and the plurality of data lines are intersected on the substrate to form a plurality of pixel units, each of which includes a main pixel unit and a sub-pixel unit, wherein sub-pixel units of two adjacent pixel units are adjacently disposed, and two adjacent sub-pixel units share one shared scan line, and the shared scan line is used for Simultaneously driving two adjacent sub-pixel units can reduce the number of shared scan lines, thereby reducing the aperture ratio occupied by the shared scan lines and increasing the aperture ratio of the pixels.
  • FIG. 1 is a schematic structural view of an array substrate according to a first embodiment of the present invention
  • FIG. 2 is an equivalent circuit diagram of two adjacent pixel unit structures in FIG. 1;
  • FIG 3 is a schematic structural view of a liquid crystal panel according to a first embodiment of the present invention.
  • FIG. 1 is a schematic structural view of an array substrate according to a first embodiment of the present invention.
  • the array substrate 10 disclosed in this embodiment includes a substrate 11 , a plurality of scan lines 12 , a plurality of data lines 13 , and a plurality of shared scan lines 14 .
  • a plurality of scan lines 12 and a plurality of data lines 13 are disposed on the substrate 11 to form a plurality of pixel units 15; each of the pixel units 15 includes a main pixel unit and a sub-pixel unit, wherein adjacent two pixel units 15 The sub-pixel units are arranged adjacently. Two adjacent sub-pixel units share one shared scan line 14, and the shared scan line 14 is used to simultaneously drive two adjacent sub-pixel units.
  • the adjacent two pixel units 15 include an Nth pixel unit 151 and an N+1th pixel unit 152 which are adjacently disposed along the extending direction of the data line 13, that is, the Nth pixel unit 151 and the N+th One pixel unit 152 is a pixel unit of two adjacent rows.
  • the Nth pixel unit 151 includes an Nth main pixel unit 161, an Nth sub-pixel unit 171, and an Nth sharing capacitor 181
  • the N+1th pixel unit 152 includes an N+1th main pixel unit 162, a Nth +1 sub-pixel unit 172 and N+1th sharing capacitor 182; rotating the existing N+1th pixel unit 152 by 180°, so that the Nth sub-pixel unit 171 and the N+1th sub-pixel unit 172 Adjacent settings.
  • N is an integer greater than or equal to 1.
  • the Nth pixel unit 151 is located between the Nth scan line 12 and the Mth shared scan line 14, and the N+1th pixel unit 152 is located at the Mth shared scan line 14 and the (N+1)th scan line. Between 12.
  • the array substrate 10 further includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, and a sixth thin film transistor T6.
  • the gate of the first thin film transistor T1 is connected to the Nth scan line 12, the source of the first thin film transistor T1 is connected to the Nth data line 13, and the drain of the first thin film transistor T1 and the Nth main pixel unit 161 are connected.
  • the gate of the second thin film transistor T2 is connected to the Nth scan line 12, the source of the second thin film transistor T2 is connected to the Nth data line 13, and the drain of the second thin film transistor T2 and the Nth sub-pixel unit 171 is connected;
  • the gate of the third thin film transistor T3 is connected to the Mth shared scan line 14, the source of the third thin film transistor T3 is connected to the Nth sub-pixel unit 171, and the drain and the Nth of the third thin film transistor T3 are connected.
  • the sharing capacitor 181 is connected; the gate of the fourth thin film transistor T4 is connected to the N+1th scanning line 12, the source of the fourth thin film transistor T4 is connected to the Nth data line 13, and the drain of the fourth thin film transistor T4 is The N+1th main pixel unit 162 is connected; the gate of the fifth thin film transistor T5 is connected to the N+1th scan line 12, and the source of the fifth thin film transistor T5 is connected to the Nth data line 13, the fifth thin film
  • the drain of the transistor T5 is connected to the N+1th sub-pixel unit 172; the sixth thin film crystal
  • the gate of T6 is connected to the Mth shared scan line 14, the source of the sixth thin film transistor T6 is connected to the N+1th sub-pixel unit 172, and the drain of the sixth thin film transistor T6 and the (N+1)th shared capacitor 182 are connected. connection.
  • the Nth main pixel unit 161 is equivalent to the liquid crystal capacitor Clc1 and the storage capacitor Cst1, the Nth sub-pixel unit 171 is equivalent to the liquid crystal capacitor Clc2 and the storage capacitor Cst2, and the Nth shared capacitor 181 is the capacitor Cdown1;
  • One main pixel unit 162 is equivalent to the liquid crystal capacitor Clc3 and the storage capacitor Cst3, the N+1th sub-pixel unit 172 is equivalent to the liquid crystal capacitor Clc4 and the storage capacitor Cst4, and the N+1th shared capacitor 182 is the capacitor Cdown2.
  • Nth scan line 12 When the Nth scan line 12 is turned on, the first thin film transistor T1 and the second thin film transistor T2 are turned on, and the Nth data line 13 is charged by the Nth main pixel unit 161 and the Nth sub pixel unit 171, Nth The voltage of the main pixel unit 161 is equal to the voltage of the Nth sub-pixel unit 171, that is, the voltages of the liquid crystal capacitor Clc1 and the storage capacitor Cst1 are equal to the voltages of the liquid crystal capacitor Clc2 and the storage capacitor Cst2, respectively.
  • the pixel unit 172 performs charging.
  • the voltage of the N+1th main pixel unit 162 is equal to the voltage of the N+1th sub-pixel unit 172, that is, the voltages of the liquid crystal capacitor Clc3 and the storage capacitor Cst3 and the voltages of the liquid crystal capacitor Clc4 and the storage capacitor Cst4, respectively. equal.
  • the Mth shared scan line 14 When the Mth shared scan line 14 is turned on, that is, the Mth shared scan line 14 simultaneously drives the Nth sub-pixel unit 171 and the N+1th sub-pixel unit 172, the third thin film transistor T3 and the sixth thin film transistor T6 are turned on.
  • the Nth sub-pixel unit 171 is connected to the Nth shared capacitor 181 through the third thin film transistor T3.
  • the Nth shared capacitor 181 is used to share the voltage of the Nth sub-pixel unit 171 to make the voltage of the Nth sub-pixel unit 171.
  • the voltage of the Nth main pixel unit 161 is greater than the voltage of the Nth sub-pixel unit 171.
  • the liquid crystal reversal at the Nth main pixel unit 161 is different from the liquid crystal reversal at the Nth sub-pixel unit 171.
  • the N+1 sub-pixel units 172 are connected to the N+1th sharing capacitor 182 through the sixth thin film transistor T6, and the N+1th sharing capacitor 182 is used to share the voltage of the (N+1)th sub-pixel unit 172, so that the Nth The voltage of the +1 sub-pixel unit 172 is lowered, the voltage of the (N+1)th main pixel unit 162 is greater than the voltage of the (N+1)th sub-pixel unit 172, and the liquid crystal is reversed at the N+1th main pixel unit 162.
  • the liquid crystal located at the (N+1)th sub-pixel unit 172 is not inverted . Therefore, the array substrate 10 disclosed in the embodiment can improve the large-view character bias.
  • the Mth shared scan line 14 between the Nth pixel unit 151 and the N+1th pixel unit 152 is connected to the N+nth scan line 12, where n is an integer greater than or equal to 2, and M is greater than Or an integer equal to 1, and M and N satisfy the following relationship:
  • n is equal to 2, that is, the Mth shared scan line 14 is connected to the N+2th scan line 12.
  • the Nth scan line 12, the N+1th scan line 12, and the N+2 scan line 12 are sequentially turned on. After the Nth scan line 12 and the N+1th scan line 12 are turned off, the first The N+2 scan lines 12 are turned on, that is, the Mth shared scan line 14 is turned on, so that the Mth shared scan line 14 is charged and turned off after the Nth pixel unit 151 and the (N+1)th pixel unit 152 are charged and turned off. turn on.
  • each pixel unit 15 is ITO (Indium Tin Oxides).
  • the array substrate 10 disclosed in this embodiment is disposed adjacent to the N+1th sub-pixel unit 172 by the Nth sub-pixel unit 171, and the Nth sub-pixel unit 171 and the (N+1)th sub-pixel unit 172 share the Mth shared scan.
  • the line 14 and the Mth shared scan line 14 simultaneously drive the Nth sub-pixel unit 171 and the N+1th sub-pixel unit 172, thereby reducing the number of shared scan lines 14, thereby reducing the aperture ratio occupied by the shared scan line 14, and increasing the pixel.
  • the aperture ratio increases product penetration and product quality.
  • the present invention also provides a liquid crystal display panel which is described on the basis of the array substrate 10 disclosed in the first embodiment.
  • the liquid crystal display panel 30 disclosed in the present embodiment includes an array substrate 31, a color filter substrate 32, and a liquid crystal layer 33 disposed between the array substrate 31 and the color filter substrate 32, wherein the array substrate 31 and the color filter substrate 32 are provided.
  • the array substrate 31 is preferably the array substrate 10 described above, and details are not described herein again.
  • the present invention is disposed adjacent to the N+1th sub-pixel unit 172 by the Nth sub-pixel unit 171, and the Nth sub-pixel unit 171 and the (N+1)th sub-pixel unit 172 share the Mth shared scan line 14
  • the Mth shared scan line 14 simultaneously drives the Nth sub-pixel unit 171 and the N+1th sub-pixel unit 172, which can reduce the number of shared scan lines 14, thereby reducing the aperture ratio occupied by the shared scan line 14, and improving the opening of the pixel. Rate, improve product penetration and product quality.

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Abstract

一种液晶显示面板及其阵列基板(10)。该阵列基板(10)包括基板(11)、多条扫描线(12)、多条数据线(13)以及多条共享扫描线(14)，多条扫描线(12)和多条数据线(13)相交设置在基板(11)上，以形成多个像素单元(15)，每个像素单元(15)包括主像素单元和子像素单元，相邻的两个像素单元的子像素单元相邻设置，相邻的两个子像素单元共用一条共享扫描线(14)，共享扫描线(14)用于同时驱动相邻的两个子像素单元。通过以上方式，能够减少共享扫描线(14)的数量，进而减少共享扫描线(14)占用的开口率，提高像素的开口率。

Description

一种液晶显示面板及其阵列基板
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种液晶显示面板及其阵列基板。
【背景技术】
目前采用VA（Vertical Alignment，垂直配向）的液晶显示器通常将像素分为主像素区域和子像素区域，并且子像素区域的像素电压低于主像素单元的像素电压，以使位于子像素区域的液晶的倒向与位于主像素区域的液晶的倒向不同，进而改善大视角色偏。
为了使得子像素区域的像素电压低于主像素单元的像素电压，现有技术通过每个像素均设置有一条共享扫描线，但是共享扫描线会占用像素的开口率，进而影响液晶显示器的穿透率。
【发明内容】
本发明实施例提供了一种液晶显示面板及其阵列基板，能够减少共享扫描线占用的开口率，提高像素的开口率。
本发明提供一种阵列基板，其包括基板、多条扫描线、多条数据线以及多条共享扫描线，多条扫描线和多条数据线相交设置在基板上，以形成多个像素单元，每个像素单元包括主像素单元和子像素单元，相邻的两个像素单元的子像素单元相邻设置，相邻的两个子像素单元共用一条共享扫描线，共享扫描线用于同时驱动相邻的两个子像素单元；其中，相邻的两个像素单元包括沿着数据线延伸方向相邻设置的第N个像素单元和第N+1个像素单元，第N个像素单元包括第N个主像素单元、第N个子像素单元以及第N个分享电容，第N+1个像素单元包括第N+1个主像素单元、第N+1个子像素单元以及第N+1个分享电容；第N个像素单元位于第N条扫描线和第M条共享扫描线之间，第N+1个像素单元位于第M条共享扫描线和第N+1条扫描线之间；第N个像素单元和第N+1个像素单元之间的第M条共享扫描线与第N+n条的扫描线连接，其中n为大于或等于2的整数，M、N均为大于或等于1的整数，并且M=（N+1）/2。
其中，阵列基板还包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管以及第六薄膜晶体管，第一薄膜晶体管的栅极与第N条扫描线连接，第一薄膜晶体管的源极与第N条数据线连接，第一薄膜晶体管的漏极与第N个主像素单元连接；第二薄膜晶体管的栅极与第N条扫描线连接，第二薄膜晶体管的源极与第N条数据线连接，第二薄膜晶体管的漏极与第N个子像素单元连接；第三薄膜晶体管的栅极与第M条共享扫描线连接，第三薄膜晶体管的源极与第N个子像素单元连接，第三薄膜晶体管的漏极与第N个分享电容连接；第四薄膜晶体管的栅极与第N+1条扫描线连接，第四薄膜晶体管的源极与第N条数据线连接，第四薄膜晶体管的漏极与第N+1个主像素单元连接；第五薄膜晶体管的栅极与第N+1条扫描线连接，第五薄膜晶体管的源极与第N条数据线连接，第五薄膜晶体管的漏极与第N+1子像素单元连接；第六薄膜晶体管的栅极与第M条共享扫描线连接，第六薄膜晶体管的源极与第N+1个子像素单元连接，第六薄膜晶体管的漏极与第N+1个分享电容连接。
本发明还提供一种阵列基板，其包括基板、多条扫描线、多条数据线以及多条共享扫描线，多条扫描线和多条数据线相交设置在基板上，以形成多个像素单元，每个像素单元包括主像素单元和子像素单元，相邻的两个像素单元的子像素单元相邻设置，相邻的两个子像素单元共用一条共享扫描线，共享扫描线用于同时驱动相邻的两个子像素单元。
其中，相邻的两个像素单元包括沿着数据线延伸方向相邻设置的第N个像素单元和第N+1个像素单元，第N个像素单元包括第N个主像素单元、第N个子像素单元以及第N个分享电容，第N+1个像素单元包括第N+1个主像素单元、第N+1个子像素单元以及第N+1个分享电容。
其中，第N个像素单元位于第N条扫描线和第M条共享扫描线之间，第N+1个像素单元位于第M条共享扫描线和第N+1条扫描线之间。
其中，阵列基板还包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管以及第六薄膜晶体管，第一薄膜晶体管的栅极与第N条扫描线连接，第一薄膜晶体管的源极与第N条数据线连接，第一薄膜晶体管的漏极与第N个主像素单元连接；第二薄膜晶体管的栅极与第N条扫描线连接，第二薄膜晶体管的源极与第N条数据线连接，第二薄膜晶体管的漏极与第N个子像素单元连接；第三薄膜晶体管的栅极与第M条共享扫描线连接，第三薄膜晶体管的源极与第N个子像素单元连接，第三薄膜晶体管的漏极与第N个分享电容连接；第四薄膜晶体管的栅极与第N+1条扫描线连接，第四薄膜晶体管的源极与第N条数据线连接，第四薄膜晶体管的漏极与第N+1个主像素单元连接；第五薄膜晶体管的栅极与第N+1条扫描线连接，第五薄膜晶体管的源极与第N条数据线连接，第五薄膜晶体管的漏极与第N+1子像素单元连接；第六薄膜晶体管的栅极与第M条共享扫描线连接，第六薄膜晶体管的源极与第N+1个子像素单元连接，第六薄膜晶体管的漏极与第N+1个分享电容连接。
其中，第N个像素单元和第N+1个像素单元之间的第M条共享扫描线与第N+n条的扫描线连接，其中n为大于或等于2的整数，M、N均为大于或等于1的整数，并且M=（N+1）/2。
其中，第M条共享扫描线与第N+2条扫描线连接。
其中，当第N条扫描线开启，第N+1条扫描线和第N+2条扫描线关闭时，第一薄膜晶体管和第二薄膜晶体管导通，第N条数据线为第N个主像素单元和第N个子像素单元充电；当第N+1条扫描线开启，第N条扫描线和第N+2条扫描线关闭时，第四薄膜晶体管和第五薄膜晶体管导通，第N条数据线为第N+1个主像素单元和第N+1个子像素单元充电。
其中，当第N+2条扫描线开启，第N+1条扫描线和第N条扫描线关闭时，第三薄膜晶体管和第六薄膜晶体管导通，第N个子像素单元与第M个分享电容连接，第N+1个子像素单元与第M个分享电容连接，以降低第N个子像素单元和第N+1个子像素单元的电压。
其中，每个像素单元的像素电极为ITO。
本发明还提供一种液晶显示面板，其包括阵列基板，阵列基板包括基板、多条扫描线、多条数据线以及多条共享扫描线，多条扫描线和多条数据线相交设置在基板上，以形成多个像素单元，每个像素单元包括主像素单元和子像素单元，相邻的两个像素单元的子像素单元相邻设置，相邻的两个子像素单元共用一条共享扫描线，共享扫描线用于同时驱动相邻的两个子像素单元。
其中，相邻的两个像素单元包括沿着数据线延伸方向相邻设置的第N个像素单元和第N+1个像素单元，第N个像素单元包括第N个主像素单元、第N个子像素单元以及第N个分享电容，第N+1个像素单元包括第N+1个主像素单元、第N+1个子像素单元以及第N+1个分享电容。
其中，第N个像素单元位于第N条扫描线和第M条共享扫描线之间，第N+1个像素单元位于第M条共享扫描线和第N+1条扫描线之间。
其中，阵列基板还包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管以及第六薄膜晶体管，第一薄膜晶体管的栅极与第N条扫描线连接，第一薄膜晶体管的源极与第N条数据线连接，第一薄膜晶体管的漏极与第N个主像素单元连接；第二薄膜晶体管的栅极与第N条扫描线连接，第二薄膜晶体管的源极与第N条数据线连接，第二薄膜晶体管的漏极与第N个子像素单元连接；第三薄膜晶体管的栅极与第M条共享扫描线连接，第三薄膜晶体管的源极与第N个子像素单元连接，第三薄膜晶体管的漏极与第N个分享电容连接；第四薄膜晶体管的栅极与第N+1条扫描线连接，第四薄膜晶体管的源极与第N条数据线连接，第四薄膜晶体管的漏极与第N+1个主像素单元连接；第五薄膜晶体管的栅极与第N+1条扫描线连接，第五薄膜晶体管的源极与第N条数据线连接，第五薄膜晶体管的漏极与第N+1子像素单元连接；第六薄膜晶体管的栅极与第M条共享扫描线连接，第六薄膜晶体管的源极与第N+1个子像素单元连接，第六薄膜晶体管的漏极与第N+1个分享电容连接。
其中，第N个像素单元和第N+1个像素单元之间的第M条共享扫描线与第N+n条的扫描线连接，其中n为大于或等于2的整数，M、N均为大于或等于1的整数，并且M=（N+1）/2。
其中，第M条共享扫描线与第N+2条扫描线连接。
其中，当第N条扫描线开启，第N+1条扫描线和第N+2条扫描线关闭时，第一薄膜晶体管和第二薄膜晶体管导通，第N条数据线为第N个主像素单元和第N个子像素单元充电；当第N+1条扫描线开启，第N条扫描线和第N+2条扫描线关闭时，第四薄膜晶体管和第五薄膜晶体管导通，第N条数据线为第N+1个主像素单元和第N+1个子像素单元充电。
其中，当第N+2条扫描线开启，第N+1条扫描线和第N条扫描线关闭时，第三薄膜晶体管和第六薄膜晶体管导通，第N个子像素单元与第M个分享电容连接，第N+1个子像素单元与第M个分享电容连接，以降低第N个子像素单元和第N+1个子像素单元的电压。
其中，每个像素单元的像素电极为ITO。
通过上述方案，本发明的有益效果是：本发明通过设置基板、多条扫描线、多条数据线以及多条共享扫描线，多条扫描线和多条数据线相交设置在基板上，以形成多个像素单元，每个像素单元包括主像素单元和子像素单元，相邻的两个像素单元的子像素单元相邻设置，相邻的两个子像素单元共用一条共享扫描线，共享扫描线用于同时驱动相邻的两个子像素单元，能够减少共享扫描线的数量，进而减少共享扫描线占用的开口率，提高像素的开口率。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明第一实施例的阵列基板的结构示意图；
图2是图1中相邻的两个像素单元结构的等效电路图；
图3是本发明第一实施例的液晶面板的结构示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参见图1所示，图1是本发明第一实施例的阵列基板的结构示意图。如图1所示，本实施例所揭示的阵列基板10包括基板11、多条扫描线12、多条数据线13以及多条共享扫描线14。
多条扫描线12和多条数据线13相交设置在基板11上，以形成多个像素单元15；每个像素单元15均包括主像素单元和子像素单元，其中相邻的两个像素单元15的子像素单元相邻设置。相邻的两个子像素单元共用一条共享扫描线14，共享扫描线14用于同时驱动相邻的两个子像素单元。
优选地，相邻的两个像素单元15包括沿着数据线13延伸方向相邻设置的第N个像素单元151和第N+1个像素单元152，即第N个像素单元151和第N+1个像素单元152为相邻两行的像素单元。第N个像素单元151包括第N个主像素单元161、第N个子像素单元171以及第N个分享电容181，第N+1个像素单元152包括第N+1个主像素单元162、第N+1个子像素单元172以及第N+1个分享电容182；将现有的第N+1个像素单元152旋转180°，以使的第N个子像素单元171与第N+1个子像素单元172相邻设置。其中，N为大于或等于1的整数。
其中，第N个像素单元151位于第N条扫描线12和第M条共享扫描线14之间，第N+1个像素单元152位于第M条共享扫描线14和第N+1条扫描线12之间。阵列基板10还包括第一薄膜晶体管T1、第二薄膜晶体管T2第三薄膜晶体管T3、第四薄膜晶体管T4、第五薄膜晶体管T5以及第六薄膜晶体管T6。
第一薄膜晶体管T1的栅极与第N条扫描线12连接，第一薄膜晶体管T1的源极与第N条数据线13连接，第一薄膜晶体管T1的漏极与第N个主像素单元161连接；第二薄膜晶体管T2的栅极与第N条扫描线12连接，第二薄膜晶体管T2的源极与第N条数据线13连接，第二薄膜晶体管T2的漏极与第N个子像素单元171连接；第三薄膜晶体管T3的栅极与第M条共享扫描线14连接，第三薄膜晶体管T3的源极与第N个子像素单元171连接，第三薄膜晶体管T3的漏极与第N个分享电容181连接；第四薄膜晶体管T4的栅极与第N+1条扫描线12连接，第四薄膜晶体管T4的源极与第N条数据线13连接，第四薄膜晶体管T4的漏极与第N+1个主像素单元162连接；第五薄膜晶体管T5的栅极与第N+1条扫描线12连接，第五薄膜晶体管T5的源极与第N条数据线13连接，第五薄膜晶体管T5的漏极与第N+1子像素单元172连接；第六薄膜晶体管T6的栅极与第M条共享扫描线14连接，第六薄膜晶体管T6的源极与第N+1个子像素单元172连接，第六薄膜晶体管T6的漏极与第N+1个分享电容182连接。
请一并参见图2所示，本实施例所揭示的相邻的两个像素单元15结构的等效电路图。其中，第N个主像素单元161等效于液晶电容Clc1和存储电容Cst1，第N个子像素单元171等效于液晶电容Clc2和存储电容Cst2，第N个分享电容181为电容Cdown1；第N+1个主像素单元162等效于液晶电容Clc3和存储电容Cst3，第N+1子像素单元172等效于液晶电容Clc4和存储电容Cst4，第N+1个分享电容182为电容Cdown2。
当第N条扫描线12打开时，第一薄膜晶体管T1和第二薄膜晶体管T2导通，第N条数据线13为第N个主像素单元161和第N个子像素单元171进行充电，第N个主像素单元161的电压等于第N个子像素单元171的电压，即液晶电容Clc1和存储电容Cst1的电压分别与液晶电容Clc2和存储电容Cst2的电压相等。
当第N+1条扫描线12打开时，第四薄膜晶体管T4和第五薄膜晶体管T5导通，第N+1条数据线13为第N+1个主像素单元162和第N+1个子像素单元172进行充电，第N+1个主像素单元162的电压等于第N+1个子像素单元172的电压，即液晶电容Clc3和存储电容Cst3的电压分别与液晶电容Clc4和存储电容Cst4的电压相等。
当第M条共享扫描线14打开，即第M条共享扫描线14同时驱动第N个子像素单元171与第N+1个子像素单元172时，第三薄膜晶体管T3和第六薄膜晶体管T6导通，第N个子像素单元171通过第三薄膜晶体管T3与第N个分享电容181连接，第N个分享电容181用于分担第N个子像素单元171的电压，以使第N个子像素单元171的电压降低，第N个主像素单元161的电压大于第N个子像素单元171的电压，此时位于第N个主像素单元161的液晶倒向与位于第N个子像素单元171的液晶倒向不同；第N+1个子像素单元172通过第六薄膜晶体管T6与第N+1个分享电容182连接，第N+1个分享电容182用于分担第N+1个子像素单元172的电压，以使第N+1个子像素单元172的电压降低，第N+1个主像素单元162的电压大于第N+1个子像素单元172的电压，此时位于第N+1个主像素单元162的液晶倒向与位于第N+1个子像素单元172的液晶倒向不同。因此，本实施例所揭示的阵列基板10能够改善大视角色偏。
第N个像素单元151和第N+1个像素单元152之间的第M条共享扫描线14与第N+n条的扫描线12连接，其中n为大于或等于2的整数，M为大于或等于1的整数，并且M与N满足以下关系：
M=（N+1）/2
当N=1时，M=1，第1个像素单元151和第2个像素单元152之间的第1条共享扫描线14。
优选地，n等于2，即第M条共享扫描线14与第N+2条的扫描线12连接。其中，第N条扫描线12、第N+1条扫描线12以及第N+2条的扫描线12依次打开，在第N条扫描线12和第N+1条扫描线12关闭后，第N+2条扫描线12打开，即第M条共享扫描线14打开，以使第M条共享扫描线14在第N个像素单元151和第N+1个像素单元152充电完成并关闭后才打开。
值得注意的是，每个像素单元15的像素电极均为ITO（Indium Tin Oxides，纳米铟锡）。
本实施例所揭示的阵列基板10通过第N个子像素单元171与第N+1个子像素单元172相邻设置，第N个子像素单元171与第N+1个子像素单元172共用第M条共享扫描线14，第M条共享扫描线14同时驱动第N个子像素单元171与第N+1个子像素单元172，能够减少共享扫描线14的数量，进而减少共享扫描线14占用的开口率，提高像素的开口率，提升产品穿透率和产品品质。
本发明还提供一种液晶显示面板，其在第一实施例所揭示的阵列基板10的基础上进行描述。如图3所示，本实施所揭示的液晶显示面板30包括阵列基板31、彩膜基板32以及设置在阵列基板31和彩膜基板32之间液晶层33，其中阵列基板31和彩膜基板32相对设置，阵列基板31优选为上述的阵列基板10，在此不再赘述。
综上所述，本发明通过第N个子像素单元171与第N+1个子像素单元172相邻设置，第N个子像素单元171与第N+1个子像素单元172共用第M条共享扫描线14，第M条共享扫描线14同时驱动第N个子像素单元171与第N+1个子像素单元172，能够减少共享扫描线14的数量，进而减少共享扫描线14占用的开口率，提高像素的开口率，提升产品穿透率和产品品质。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，所述阵列基板包括基板、多条扫描线、多条数据线以及多条共享扫描线，所述多条扫描线和所述多条数据线相交设置在所述基板上，以形成多个像素单元，每个所述像素单元包括主像素单元和子像素单元，相邻的两个所述像素单元的子像素单元相邻设置，所述相邻的两个子像素单元共用一条所述共享扫描线，所述共享扫描线用于同时驱动所述相邻的两个子像素单元；
    其中，所述相邻的两个像素单元包括沿着所述数据线延伸方向相邻设置的第N个像素单元和第N+1个像素单元，所述第N个像素单元包括第N个主像素单元、第N个子像素单元以及第N个分享电容，所述第N+1个像素单元包括第N+1个主像素单元、第N+1个子像素单元以及第N+1个分享电容；
    所述第N个像素单元位于所述第N条扫描线和第M条共享扫描线之间，所述第N+1个像素单元位于所述第M条共享扫描线和所述第N+1条扫描线之间；
    所述第N个像素单元和所述第N+1个像素单元之间的所述第M条共享扫描线与第N+n条的扫描线连接，其中n为大于或等于2的整数，M、N均为大于或等于1的整数，并且M=（N+1）/2。
  2. 根据权利要求1所述的阵列基板，其中，所述阵列基板还包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管以及第六薄膜晶体管，所述第一薄膜晶体管的栅极与第N条扫描线连接，所述第一薄膜晶体管的源极与第N条数据线连接，所述第一薄膜晶体管的漏极与所述第N个主像素单元连接；所述第二薄膜晶体管的栅极与所述第N条扫描线连接，所述第二薄膜晶体管的源极与所述第N条数据线连接，所述第二薄膜晶体管的漏极与所述第N个子像素单元连接；所述第三薄膜晶体管的栅极与第M条共享扫描线连接，所述第三薄膜晶体管的源极与所述第N个子像素单元连接，所述第三薄膜晶体管的漏极与所述第N个分享电容连接；所述第四薄膜晶体管的栅极与第N+1条扫描线连接，所述第四薄膜晶体管的源极与第N条所述数据线连接，所述第四薄膜晶体管的漏极与所述第N+1个主像素单元连接；所述第五薄膜晶体管的栅极与所述第N+1条扫描线连接，所述第五薄膜晶体管的源极与所述第N条数据线连接，所述第五薄膜晶体管的漏极与所述第N+1子像素单元连接；所述第六薄膜晶体管的栅极与所述第M条共享扫描线连接，所述第六薄膜晶体管的源极与所述第N+1个子像素单元连接，所述第六薄膜晶体管的漏极与所述第N+1个分享电容连接。
  3. 一种阵列基板，其中，所述阵列基板包括基板、多条扫描线、多条数据线以及多条共享扫描线，所述多条扫描线和所述多条数据线相交设置在所述基板上，以形成多个像素单元，每个所述像素单元包括主像素单元和子像素单元，相邻的两个所述像素单元的子像素单元相邻设置，所述相邻的两个子像素单元共用一条所述共享扫描线，所述共享扫描线用于同时驱动所述相邻的两个子像素单元。
  4. 根据权利要求3所述的阵列基板，其中，所述相邻的两个像素单元包括沿着所述数据线延伸方向相邻设置的第N个像素单元和第N+1个像素单元，所述第N个像素单元包括第N个主像素单元、第N个子像素单元以及第N个分享电容，所述第N+1个像素单元包括第N+1个主像素单元、第N+1个子像素单元以及第N+1个分享电容。
  5. 根据权利要求4所述的阵列基板，其中，所述第N个像素单元位于所述第N条扫描线和第M条共享扫描线之间，所述第N+1个像素单元位于所述第M条共享扫描线和所述第N+1条扫描线之间。
  6. 根据权利要求4所述的阵列基板，其中，所述阵列基板还包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管以及第六薄膜晶体管，所述第一薄膜晶体管的栅极与第N条扫描线连接，所述第一薄膜晶体管的源极与第N条数据线连接，所述第一薄膜晶体管的漏极与所述第N个主像素单元连接；所述第二薄膜晶体管的栅极与所述第N条扫描线连接，所述第二薄膜晶体管的源极与所述第N条数据线连接，所述第二薄膜晶体管的漏极与所述第N个子像素单元连接；所述第三薄膜晶体管的栅极与第M条共享扫描线连接，所述第三薄膜晶体管的源极与所述第N个子像素单元连接，所述第三薄膜晶体管的漏极与所述第N个分享电容连接；所述第四薄膜晶体管的栅极与第N+1条扫描线连接，所述第四薄膜晶体管的源极与第N条所述数据线连接，所述第四薄膜晶体管的漏极与所述第N+1个主像素单元连接；所述第五薄膜晶体管的栅极与所述第N+1条扫描线连接，所述第五薄膜晶体管的源极与所述第N条数据线连接，所述第五薄膜晶体管的漏极与所述第N+1子像素单元连接；所述第六薄膜晶体管的栅极与所述第M条共享扫描线连接，所述第六薄膜晶体管的源极与所述第N+1个子像素单元连接，所述第六薄膜晶体管的漏极与所述第N+1个分享电容连接。
  7. 根据权利要求6所述的阵列基板，其中，所述第N个像素单元和所述第N+1个像素单元之间的所述第M条共享扫描线与第N+n条的扫描线连接，其中n为大于或等于2的整数，M、N均为大于或等于1的整数，并且M=（N+1）/2。
  8. 根据权利要求6所述的阵列基板，其中，所述第M条共享扫描线与第N+2条扫描线连接。
  9. 根据权利要求6所述的阵列基板，其中，当所述第N条扫描线开启，所述第N+1条扫描线和第N+2条扫描线关闭时，所述第一薄膜晶体管和第二薄膜晶体管导通，所述第N条数据线为所述第N个主像素单元和所述第N个子像素单元充电；当所述第N+1条扫描线开启，所述第N条扫描线和第N+2条扫描线关闭时，所述第四薄膜晶体管和第五薄膜晶体管导通，所述第N条数据线为所述第N+1个主像素单元和所述第N+1个子像素单元充电。
  10. 根据权利要求9所述的阵列基板，其中，当所述第N+2条扫描线开启，所述第N+1条扫描线和第N条扫描线关闭时，所述第三薄膜晶体管和第六薄膜晶体管导通，所述第N个子像素单元与所述第M个分享电容连接，所述第N+1个子像素单元与所述第M个分享电容连接，以降低所述第N个子像素单元和第N+1个子像素单元的电压。
  11. 根据权利要求3所述的阵列基板，其中，每个所述像素单元的像素电极为ITO。
  12. 一种液晶显示面板，其中，所述液晶显示面板包括阵列基板，所述阵列基板包括基板、多条扫描线、多条数据线以及多条共享扫描线，所述多条扫描线和所述多条数据线相交设置在所述基板上，以形成多个像素单元，每个所述像素单元包括主像素单元和子像素单元，相邻的两个所述像素单元的子像素单元相邻设置，所述相邻的两个子像素单元共用一条所述共享扫描线，所述共享扫描线用于同时驱动所述相邻的两个子像素单元。
  13. 根据权利要求12所述的液晶显示面板，其中，所述相邻的两个像素单元包括沿着所述数据线延伸方向相邻设置的第N个像素单元和第N+1个像素单元，所述第N个像素单元包括第N个主像素单元、第N个子像素单元以及第N个分享电容，所述第N+1个像素单元包括第N+1个主像素单元、第N+1个子像素单元以及第N+1个分享电容。
  14. 根据权利要求13所述的液晶显示面板，其中，所述第N个像素单元位于所述第N条扫描线和第M条共享扫描线之间，所述第N+1个像素单元位于所述第M条共享扫描线和所述第N+1条扫描线之间。
  15. 根据权利要求13所述的液晶显示面板，其中，所述阵列基板还包括第一薄膜晶体管、第二薄膜晶体管、第三薄膜晶体管、第四薄膜晶体管、第五薄膜晶体管以及第六薄膜晶体管，所述第一薄膜晶体管的栅极与第N条扫描线连接，所述第一薄膜晶体管的源极与第N条数据线连接，所述第一薄膜晶体管的漏极与所述第N个主像素单元连接；所述第二薄膜晶体管的栅极与所述第N条扫描线连接，所述第二薄膜晶体管的源极与所述第N条数据线连接，所述第二薄膜晶体管的漏极与所述第N个子像素单元连接；所述第三薄膜晶体管的栅极与第M条共享扫描线连接，所述第三薄膜晶体管的源极与所述第N个子像素单元连接，所述第三薄膜晶体管的漏极与所述第N个分享电容连接；所述第四薄膜晶体管的栅极与第N+1条扫描线连接，所述第四薄膜晶体管的源极与第N条所述数据线连接，所述第四薄膜晶体管的漏极与所述第N+1个主像素单元连接；所述第五薄膜晶体管的栅极与所述第N+1条扫描线连接，所述第五薄膜晶体管的源极与所述第N条数据线连接，所述第五薄膜晶体管的漏极与所述第N+1子像素单元连接；所述第六薄膜晶体管的栅极与所述第M条共享扫描线连接，所述第六薄膜晶体管的源极与所述第N+1个子像素单元连接，所述第六薄膜晶体管的漏极与所述第N+1个分享电容连接。
  16. 根据权利要求15所述的液晶显示面板，其中，所述第N个像素单元和所述第N+1个像素单元之间的所述第M条共享扫描线与第N+n条的扫描线连接，其中n为大于或等于2的整数，M、N均为大于或等于1的整数，并且M=（N+1）/2。
  17. 根据权利要求15所述的液晶显示面板，其中，所述第M条共享扫描线与第N+2条扫描线连接。
  18. 根据权利要求15所述的液晶显示面板，其中，当所述第N条扫描线开启，所述第N+1条扫描线和第N+2条扫描线关闭时，所述第一薄膜晶体管和第二薄膜晶体管导通，所述第N条数据线为所述第N个主像素单元和所述第N个子像素单元充电；当所述第N+1条扫描线开启，所述第N条扫描线和第N+2条扫描线关闭时，所述第四薄膜晶体管和第五薄膜晶体管导通，所述第N条数据线为所述第N+1个主像素单元和所述第N+1个子像素单元充电。
  19. 根据权利要求18所述的液晶显示面板，其中，当所述第N+2条扫描线开启，所述第N+1条扫描线和第N条扫描线关闭时，所述第三薄膜晶体管和第六薄膜晶体管导通，所述第N个子像素单元与所述第M个分享电容连接，所述第N+1个子像素单元与所述第M个分享电容连接，以降低所述第N个子像素单元和第N+1个子像素单元的电压。
  20. 根据权利要求12所述的液晶显示面板，其中，每个所述像素单元的像素电极为ITO。
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