WO2019015078A1 - 一种阵列基板以及显示面板 - Google Patents

一种阵列基板以及显示面板 Download PDF

Info

Publication number
WO2019015078A1
WO2019015078A1 PCT/CN2017/102542 CN2017102542W WO2019015078A1 WO 2019015078 A1 WO2019015078 A1 WO 2019015078A1 CN 2017102542 W CN2017102542 W CN 2017102542W WO 2019015078 A1 WO2019015078 A1 WO 2019015078A1
Authority
WO
WIPO (PCT)
Prior art keywords
shorting bar
pixels
sub
driving chip
pins
Prior art date
Application number
PCT/CN2017/102542
Other languages
English (en)
French (fr)
Inventor
甘启明
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/739,731 priority Critical patent/US10403648B2/en
Publication of WO2019015078A1 publication Critical patent/WO2019015078A1/zh

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3666—Control of matrices with row and column drivers using an active matrix with the matrix divided into sections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G02F1/13454—Drivers integrated on the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2003—Display of colours
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0823—Several active elements per pixel in active matrix panels used to establish symmetry in driving, e.g. with polarity inversion
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0224—Details of interlacing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2370/00—Aspects of data communication
    • G09G2370/08—Details of image data interface between the display device controller and the data line driver circuit

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a display panel.
  • the liquid crystal display panel has a layer of liquid crystal sandwiched between two glass substrates, the upper layer of glass is a color filter substrate, the lower layer of glass is an array substrate in which a thin film transistor is embedded, and the upper layer of the filter substrate corresponds to a position of the thin film transistor.
  • a color resistance is formed in which each pixel of the panel is composed of sub-pixels of three colors of red, green and blue.
  • a current is generated by a thin film transistor to cause an electric field change, causing liquid crystal molecules to deflect, a light and dark state of each sub-pixel can be determined, and a set of red, green, and blue sub-pixels can be mixed with a pixel display color, and all pixels are combined.
  • the image screen of the panel since adjacent sub-pixels are likely to cause flickering of the picture if they have the same polarity, the polarity of the sub-pixels on the panel is generally designed to minimize the flicker of the picture in a dot-reversed arrangement.
  • the signals of the odd-numbered data lines are fed from the upper side, and the signals of the even-numbered data lines are fed from the lower side, which makes the first and second lines,
  • the polarity of the signal outputted by the data lines of the 5th and 6th lines is positive, and the polarity of the signal output by the 3rd, 4th, and 7th data lines is negative, so this design cannot make any sub-pixels up and down.
  • the polarity between the adjacent sub-pixels is different, and since there is a new requirement: three sub-pixels in the same pixel must be driven by the same side of the driving chip, the existing array substrate structure obviously cannot meet the requirements.
  • the technical problem to be solved by the present invention is to provide an array substrate and a display panel, which can realize dot inversion of sub-pixel polarity under the requirement that three sub-pixels in the same pixel of any row are driven by the same side driving chip. Reduce the flicker of the picture.
  • an array substrate including:
  • the display area includes (m+1) data lines, n scan lines, and sub-pixels including n rows and m columns distributed in an array, wherein the sub-pixels of each row in the array are corresponding to one
  • the scan lines are connected, the sub-pixels of each column are alternately connected by two corresponding adjacent data lines in a parity row, and the sub-pixels of the same column are of the same color, and the data lines include the first strip.
  • the peripheral area includes at least one first driving chip on an upper side of the display area, at least one second driving chip on a lower side of the display area, and at least one third driving chip on one side of the display area
  • the first driving chip includes a plurality of first pins
  • the second driving chip includes a plurality of second pins
  • the third driving chip is connected to the scan lines to input gates to the sub-pixels Drive signal
  • the first driving chip and the second driving chip are connected to the data line in such a manner that the first pin of each adjacent 6a column and the second pin of each adjacent 6a column are alternately connected, so that any row Three of the sub-pixels in the same pixel are driven by the same side of the driving chip.
  • the signals of the adjacent first pins output different polarities
  • the signals of the adjacent second pins output different polarities, so that any of the sub-pixels are adjacent to the upper, lower, left and right sides thereof.
  • the polarity between sub-pixels is different, and a, n, and m are positive integers.
  • an array substrate including:
  • the display area includes a plurality of data lines crossing each other, a plurality of scan lines, and sub-pixels distributed in an array, wherein the sub-pixels of each row in the array are connected by a corresponding one of the scan lines, and each column is The sub-pixels are alternately connected by two corresponding adjacent data lines in a parity row, and the sub-pixels of the same column are the same color;
  • the peripheral area includes at least one first driving chip on an upper side of the display area and at least one second driving chip on a lower side of the display area, the first driving chip includes a plurality of first pins, The second driving chip includes a plurality of second pins;
  • the first driving chip and the second driving chip are connected to the data line in such a manner that the first pin of each adjacent 6a column and the second pin of each adjacent 6a column are alternately connected, so that any row Three of the sub-pixels in the same pixel are driven by the same side of the driving chip.
  • the signals of the adjacent first pins output different polarities
  • the signals of the adjacent second pins output different polarities, so that any of the sub-pixels are adjacent to the upper, lower, left and right sides thereof.
  • the polarity between sub-pixels is different, and a is a positive integer.
  • an array substrate including:
  • the display area includes a plurality of data lines crossing each other, a plurality of scan lines, and sub-pixels distributed in an array, wherein the sub-pixels of each row in the array are connected by a corresponding one of the scan lines, and each column is The sub-pixels are alternately connected by two corresponding adjacent data lines in a parity row, and the sub-pixels of the same column are the same color;
  • the peripheral region includes a first shorting bar region above the display region, a second shorting bar region below the display region, and a third shorting bar region at a side of the display region,
  • the first shorting bar area includes a first shorting bar, a second shorting bar, and a third shorting bar disposed laterally
  • the second shorting bar area includes a fourth shorting bar and a fifth shorting disposed laterally a rod, a sixth shorting bar, the third shorting bar area comprising a seventh shorting bar and an eighth shorting bar arranged vertically;
  • the first shorting bar area and the second shorting bar area are connected to the data line in such a manner as to alternately connect the data lines of each adjacent 6b column, so that three of the same pixels of any row are
  • the sub-pixels are connected by the shorting bar regions on the same side, the seventh shorting bars are connected to the scan lines of the odd rows, and the eighth shorting bars are connected to the scan lines of the even rows, wherein b is a positive integer.
  • the invention has the beneficial effects that the first driving chip and the second driving chip are respectively disposed on the upper and lower sides of the display area of the array substrate, and the first driving chip and the second driving chip are respectively arranged in the adjacent 6a column.
  • a pin is connected to the second pin of each adjacent 6a column alternately to connect the data line, so that three sub-pixels in the same pixel of any row are driven by the same side of the driving chip, and the adjacent first pin and The signal polarity of the output of the adjacent second pin is different, and the dot inversion of the polarity of the sub-pixel can be realized under the premise that the same pixel is driven by the same side driving chip, thereby reducing flicker of the picture.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic structural view of another embodiment of an array substrate of the present invention.
  • FIG. 3 is a schematic structural view of still another embodiment of the array substrate of the present invention.
  • FIG. 4 is a schematic structural view of an embodiment of a display panel of the present invention.
  • FIG. 1 is a schematic structural diagram of an embodiment of an array substrate according to the present invention.
  • the array substrate includes a display area 400 and a peripheral area 500.
  • the display area 400 includes a plurality of scan lines 420 crossing each other, a plurality of data lines 430, and sub-pixels 410 distributed in an array.
  • the sub-pixels 410 of each row in the array are connected by a corresponding scan line 420, and the sub-pixels of each column are alternately connected by odd-even rows of two corresponding adjacent data lines 430.
  • the array includes red, green, and blue.
  • the seed pixels are the same, and the sub-pixels 410 of the same column have the same color.
  • the pixels in the first column and the fourth column are red sub-pixels
  • the pixels in the second column and the fifth column are green sub-pixels
  • the pixels in the third column and the sixth column are blue.
  • the color sub-pixels, and so on are red sub-pixels, the pixels in the second column and the fifth column are green sub-pixels, and the pixels in the third column and the sixth column are blue.
  • the peripheral area 500 includes at least one first driving chip 510 located on the upper side of the display area 400 and at least one second driving chip 520 located on the lower side of the display area 400.
  • the first driving chip 510 includes a plurality of first pins 511
  • the second driver chip 520 includes a plurality of second pins 521.
  • the number of the first driving chip 510 and the second driving chip 520 is one. It can be understood that in other embodiments, the number of the first driving chip 510 and the second driving chip 520 can be determined by the designer according to the size, resolution, and size of the chip.
  • the first driving chip 510 and the second driving chip 520 are connected to the data line 430 by alternately connecting the first pin 511 of each adjacent 6a column with the second pin 521 of each adjacent 6a column.
  • the first driving chip 510 is The data line 430 is connected from the top to the bottom, and the second driving chip 520 is connected to the data line 430 from the bottom up, so that three sub-pixels 410 in the same pixel of any row are driven by the driving chip on the same side.
  • each adjacent 6a column of data lines 430 is connected to the first pin 511 of the first driving chip 510, or the second pin 521 of the second driving chip 520 is connected to the other.
  • each adjacent 6a column of data lines may be connected by adjacent pins of two or more adjacent first driving chips 510. Connected to adjacent pins of two or more adjacent second driving chips 520, that is, as long as three sub-pixels 410 in the same pixel satisfying any row are driven by the driving chip on the same side, It must be driven by the same driver chip.
  • the first pin 511 adjacent to the first driving chip 510 outputs a different polarity of the signal
  • the second pin 521 adjacent to the second chip 520 outputs a different polarity, that is, the adjacent first pin 511.
  • the signals output by the adjacent second pins 521 are outputted in a positive and negative alternating manner, as shown in FIG. 1, such that the polarity of any of the sub-pixels 410 is different from the sub-pixels 410 adjacent thereto. Thereby, the polarity point inversion of the sub-pixel 410 is realized, and the flicker of the picture is reduced.
  • a is a positive integer, for example: a can be 1, 2, 5, and the like.
  • the first driving chip and the second driving chip are respectively disposed on the upper and lower sides of the display area of the array substrate, and the first driving chip and the second driving chip are respectively disposed on the first pin of each adjacent 6a column.
  • the data lines are connected in such a manner that the second pins of the adjacent 6a columns are alternately connected, so that three sub-pixels in the same pixel of any row are driven by the driving chip on the same side, and the adjacent first pins and adjacent ones
  • the signal polarity of the two-pin output is different, and the dot inversion of the sub-pixel polarity can be realized under the premise that the same pixel is driven by the same side driving chip, thereby reducing the flicker of the picture.
  • the array includes n rows and m columns of sub-pixels, the scan lines are n, the data lines are (m+1), and the data lines include the first data line to the (m+1)th line.
  • a data line, wherein n and m are positive integers, for example, 5, 10, etc. may be taken.
  • the plurality of first pins 511 of the first driving chip 510 are respectively connected to the first to sixth data lines, and the plurality of second pins 521 of the second driving chip 520 are respectively connected.
  • the data lines of the seventh to the twelfth are sequentially looped so that the plurality of first pins 511 of the first driving chip 510 and the plurality of second pins 521 of the second driving chip 520 are connected to all (m+1) Data line.
  • the polarity of the signal output by the odd-numbered data line is positive, and the polarity of the signal output by the even-numbered data line is negative.
  • the polarity of the signal output by the data lines 430 of the first, third, and fifth columns is The polarity of the signal outputted by the data lines 430 of the second, fourth, and sixth columns is negative, so that the polarity between any of the sub-pixels 410 and the sub-pixels 410 adjacent to the upper, lower, left, and right sides thereof is different.
  • FIG. 2 is a schematic structural view of another embodiment of the array substrate of the present invention.
  • the peripheral substrate 500 further includes at least one third driving chip 530.
  • the third driving chip 530 is located at one side of the display region 400.
  • the third driving chip 530 is located.
  • the third driving chip 530 is provided with a plurality of third pins 531 connected to the scan lines 420 to input gate driving signals to the sub-pixels 410.
  • the number of the third driving chips 530 is one. In other embodiments, the designer can select an appropriate number of third drivers according to the size, resolution, and chip size of the display panel. Chip 530.
  • FIG. 3 is a schematic structural diagram of still another embodiment of an array substrate according to the present invention.
  • the array substrate includes a display area 600 and a peripheral area 700.
  • the display area 600 includes a plurality of data lines 630 crossing each other, a plurality of scan lines 620, and sub-pixels 610 distributed in an array.
  • the sub-pixels 610 of each row in the array are connected by a corresponding scan line 620, and the sub-pixels 610 of each column.
  • the two adjacent adjacent data lines 630 are alternately connected in odd and even rows, and the sub-pixels 610 of the same column are of the same color.
  • the peripheral area 700 includes a first shorting bar area 710 located above the display area 600, a second shorting bar area 720 located below the display area 600, and a third shorting bar area 730 located at the side of the display area 600, the first short
  • the bar area 710 includes a first shorting bar 711, a second shorting bar 712, and a third shorting bar 713 disposed laterally.
  • the second shorting bar area 720 includes a fourth shorting bar 721 disposed laterally, and a fifth short
  • the rod 722 and the sixth shorting bar 723 include a seventh shorting rod 731 and an eighth shorting rod 732 which are vertically disposed.
  • the first shorting bar area 710 and the second shorting bar area 720 are connected to each of the adjacent 6b column data lines 630 in such a manner that the three sub-pixels 610 of the same pixel of any row are on the same side.
  • the shorting bar area is connected, the seventh shorting bar 731 is connected to the odd-numbered scanning lines 620, and the eighth shorting bar 732 is connected to the even-numbered scanning lines 620, wherein b is a positive integer, specifically, b can be 1 , 2, 5, etc.
  • the first shorting bar region 710 further includes a first conductive pad 714, a second conductive pad 715, and a third conductive pad 716.
  • the first shorting bar 711 is connected to the first conductive pad 714.
  • the second shorting bar 712 is connected to the second conductive pad 715, and the third shorting bar 713 is connected to the third conductive pad 716.
  • the second shorting bar region 720 further includes a fourth conductive pad 724, a fifth conductive pad 725, and a sixth conductive pad 726.
  • the fourth shorting bar 721 is connected to the fourth conductive pad 724, and the fifth shorting bar 722 and the fifth The conductive pads 725 are connected, and the sixth shorting bars 723 are connected to the sixth conductive pads 726.
  • the third shorting bar region 730 further includes a seventh conductive pad 733 and an eighth conductive pad 734.
  • the seventh shorting bar 731 is connected to the seventh conductive pad 733, and the eighth shorting bar 732 is connected to the eighth conductive pad 734.
  • the sub-pixel 610 includes three sub-pixels of red, green and blue.
  • the gate drive signal is supplied to the scan lines 620 of the odd rows through the seventh shorting bar 731, the first shorting bar 711 and the fourth pass are passed.
  • the shorting bar 721 provides a signal to the data line 630, and the red pixels of the odd row are illuminated.
  • the red pixel that satisfies the condition is not lit, the red pixel is short-circuited or broken, if the second shorting is passed.
  • the bar 712 and the fifth shorting bar 722 provide signals to the data line 630, and the green pixels of the odd rows are illuminated.
  • the green pixel that satisfies the condition is not lit, the green pixel is short-circuited or broken.
  • the data line 630 is supplied with a signal by the third shorting bar 713 and the sixth shorting bar 723, and the blue pixels of the odd-numbered rows are illuminated. At this time, if the blue pixel that satisfies the condition is not lit, the blue pixel appears. Open or short circuit.
  • the gate drive signal is supplied to the scan lines 620 of the even rows through the eighth shorting bar 732, if the signal is supplied to the data line 630 through the first shorting bar 711 and the fourth shorting bar 721, the blue pixels of the even rows Is illuminated, at this time, if the blue pixel that satisfies the condition is not illuminated, the blue pixel is short-circuited or broken; if the second shorting bar 712 and the fifth shorting bar 722 provide signals to the data line 630, then The red pixel of the even row is lit.
  • the red pixel that satisfies the condition is not illuminated, the red pixel is broken or shorted; if the data line is given through the third shorting bar 713 and the sixth shorting bar 723 630 provides a signal, and the green pixels of the even rows are illuminated. At this time, if the green pixel that satisfies the condition is not lit, the green pixel is broken or shorted.
  • the signal in the case of dot screen detection, under the condition that the same pixel is connected by the same shorting bar area, the signal can be detected for each sub-pixel 610, and can be timely when a certain pixel is short-circuited or disconnected. Found that it also improves the quality of the test.
  • the first shorting bar area 710 further includes a ninth shorting bar 717 and a ninth conductive pad 718.
  • the ninth shorting bar 717 is connected to the ninth conductive pad 718
  • the second shorting bar area 720 further includes The ten shorting bar 727 and the tenth conductive pad 728, the tenth shorting bar 727 is connected to the tenth conductive pad 728
  • the third shorting bar area 730 further includes an eleventh shorting bar 735 and an eleventh conductive pad 736.
  • the eleventh shorting bar 735 is connected to the eleventh conductive pad 736
  • the ninth shorting bar 717, the tenth shorting bar 727, and the eleventh shorting bar 735 are respectively connected to a common electrode (not shown).
  • FIG. 4 is a schematic structural diagram of an embodiment of a display panel according to the present invention.
  • the display panel includes a first substrate 900 and a second substrate 800.
  • the first substrate 900 and the second substrate 800 are oppositely disposed.
  • the first substrate 900 is the array substrate in any of the above embodiments.
  • the above description and details are not described herein again.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

一种阵列基板以及显示面板，该基板包括：分别设于显示区（400）上、下侧的第一驱动芯片（510）及第二驱动芯片（520），第一驱动芯片（510）与第二驱动芯片（520）以每相邻6a列第一引脚（511）与每相邻6a列第二引脚（521）交替连接的方式连接数据线（430），使得任一行同一个像素中的三个子像素（410）由同一侧驱动芯片（510、520）驱动，相邻第一引脚（511）及相邻第二引脚（521）输出的信号极性不同。通过该基板，能够在满足同一像素由同一侧驱动芯片驱动的要求下，实现子像素（410）极性。

Description

一种阵列基板以及显示面板
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板以及显示面板。
【背景技术】
液晶显示面板为两片玻璃基板中间夹着一层液晶，上层的玻璃是一彩色滤光片基板，下层的玻璃则是镶嵌有薄膜晶体管的阵列基板，而上层滤光片基板对应薄膜晶体管的位置形成色阻，其中面板的每一像素分别由红绿蓝三种颜色的子像素组成。当电流通过薄膜晶体管产生电场变化，造成液晶分子偏转，可以决定每一子像素的明暗状态，而一组红绿蓝三种颜色的子像素可混合出一像素显示的色彩，并且所有像素共同构成了面板的影像画面。然而，由于相邻的子像素若具有相同的极性容易造成画面的闪烁，因此面板上的子像素极性一般会设计成按照点反转的排列方式来尽量减少画面的闪烁。
然而，由于目前面板的分辨率越来越高，相比较之下，相同尺寸的面板数据线也越来越多。当数据线越多时，将外部数据信号引入面板内的驱动芯片的数量也越来越多，而芯片的引脚有一定的数量限定，并且相邻的芯片之间也需要足够的制作空间，因此，在面板数据线越来越多的情况下，一般采用将数据线的信号从面板上下两侧交叉给入的方式。
但是目前这种交叉给入的方式，会使第奇数条数据线的信号由上侧给入，第偶数条数据线的信号由下侧给入，此时会使得第1条、第2条、第5条、第6条数据线输出的信号极性为正，第3条、第4条、第7条数据线输出的信号极性为负，因此这样的设计无法使得任一子像素与上下左右相邻的子像素之间的极性不同，且由于现在新增要求：同一像素中的三个子像素必须由同一侧的驱动芯片驱动，现有的阵列基板结构显然不能满足要求。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板以及显示面板，能够在满足任一行同一像素中的三个子像素由同一侧驱动芯片驱动的要求下，实现子像素极性的点反转，从而减少画面的闪烁。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包括：
显示区以及外围区；
所述显示区包括互相交叉的（m+1）条数据线、n条扫描线以及呈阵列分布的包括n行及m列的子像素，所述阵列中每一行的所述子像素由一条对应的所述扫描线连接，每一列的所述子像素由两条对应相邻的所述数据线按奇偶行交替连接，且同一列的所述子像素颜色相同，所述数据线包括第1条数据线至第（m+1）条数据线；
所述外围区包括位于所述显示区上侧的至少一个第一驱动芯片、位于所述显示区下侧的至少一个第二驱动芯片以及位于所述显示区一侧边的至少一个第三驱动芯片，所述第一驱动芯片包括多个第一引脚，所述第二驱动芯片包括多个第二引脚，所述第三驱动芯片连接所述扫描线，以对所述子像素输入栅极驱动信号；
所述第一驱动芯片与所述第二驱动芯片以每相邻6a列所述第一引脚与每相邻6a列所述第二引脚交替连接的方式连接所述数据线，使得任一行的同一个像素中的三个所述子像素由同一侧所述驱动芯片驱动，
其中，相邻的所述第一引脚输出的信号极性不同，相邻的所述第二引脚输出的信号极性不同，以使得任一所述子像素与其上下左右相邻的所述子像素之间的极性不同，a、n以及m为正整数。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括：
显示区以及外围区；
所述显示区包括互相交叉的多条数据线、多条扫描线以及呈阵列分布的子像素，所述阵列中每一行的所述子像素由一条对应的所述扫描线连接，每一列的所述子像素由两条对应相邻的所述数据线按奇偶行交替连接，且同一列的所述子像素颜色相同；
所述外围区包括位于所述显示区上侧的至少一个第一驱动芯片以及位于所述显示区下侧的至少一个第二驱动芯片，所述第一驱动芯片包括多个第一引脚，所述第二驱动芯片包括多个第二引脚；
所述第一驱动芯片与所述第二驱动芯片以每相邻6a列所述第一引脚与每相邻6a列所述第二引脚交替连接的方式连接所述数据线，使得任一行的同一个像素中的三个所述子像素由同一侧所述驱动芯片驱动，
其中，相邻的所述第一引脚输出的信号极性不同，相邻的所述第二引脚输出的信号极性不同，以使得任一所述子像素与其上下左右相邻的所述子像素之间的极性不同，a为正整数。
为解决上述问题，本发明采用的又一个技术方案是：提供一种阵列基板，包括：
显示区以及外围区；
所述显示区包括互相交叉的多条数据线、多条扫描线以及呈阵列分布的子像素，所述阵列中每一行的所述子像素由一条对应的所述扫描线连接，每一列的所述子像素由两条对应相邻的所述数据线按奇偶行交替连接，且同一列的所述子像素颜色相同；
所述外围区包括位于所述显示区上方的第一短接棒区域、位于所述显示区下方的第二短接棒区域以及位于所述显示区侧边的第三短接棒区域，所述第一短接棒区域包括横向设置的第一短接棒、第二短接棒、第三短接棒，所述第二短接棒区域包括横向设置的第四短接棒、第五短接棒、第六短接棒，所述第三短接棒区域包括竖向设置的第七短接棒、第八短接棒；
所述第一短接棒区域与所述第二短接棒区域以交替连接每相邻6b列所述数据线的方式连接所述数据线，使得任一行的同一个像素中的三个所述子像素由同一侧的所述短接棒区域连接，所述第七短接棒与奇数行的所述扫描线连接，所述第八短接棒与偶数行的所述扫描线连接，其中，b为正整数。
本发明的有益效果是：本发明通过将第一驱动芯片以及第二驱动芯片分别设置在阵列基板显示区的上下两侧，同时将第一驱动芯片与第二驱动芯片以每相邻6a列第一引脚与每相邻6a列第二引脚交替连接的方式连接数据线，使得任一行的同一个像素中的三个子像素由同一侧的驱动芯片驱动，且相邻的第一引脚及相邻的第二引脚输出的信号极性不同，能够在满足同一像素由同一侧驱动芯片驱动的前提下，实现子像素极性的点反转，减少画面的闪烁。
【附图说明】
图1是本发明阵列基板一实施例的结构示意图；
图2是本发明阵列基板另一实施例的结构示意图；
图3是本发明阵列基板再一实施例的结构示意图；
图4是本发明显示面板一实施例的结构示意图。
【具体实施方式】
请参阅图1，图1是本发明阵列基板一实施例的结构示意图，该阵列基板包括：显示区400以及外围区500。
显示区400包括互相交叉的多条扫描线420、多条数据线430以及呈阵列分布的子像素410。
阵列中每一行的子像素410由一条对应的扫描线420连接，每一列的子像素由两条对应相邻的数据线430按奇偶行交替连接，具体地，该阵列包括红、绿、蓝三种子像素，且同一列的子像素410颜色相同，例如第1列、第4列像素为红色子像素，第2列、第5列像素为绿色子像素，第3列、第6列像素为蓝色子像素，其余依次类推。
外围区500包括位于显示区400上侧的至少一个第一驱动芯片510以及位于显示区400下侧的至少一个第二驱动芯片520，第一驱动芯片510包括多个第一引脚511，,第二驱动芯片520包括多个第二引脚521。
在本实施例中，以第一驱动芯片510、第二驱动芯片520的数量均为1个进行说明。可以理解的是，在其他实施例中，第一驱动芯片510以及第二驱动芯片520的数量可由设计人员根据显示面板的尺寸、分辨率以及芯片的大小选择确定。
第一驱动芯片510与第二驱动芯片520以每相邻6a列第一引脚511与每相邻6a列第二引521脚交替连接的方式连接数据线430，其中，第一驱动芯片510是由上向下连接数据线430，第二驱动芯片520是由下向上连接数据线430，使得任一行的同一个像素中的三个子像素410由同一侧的驱动芯片驱动。
可以理解的是，在本实施例中，每相邻6a列数据线430连接一个第一驱动芯片510的第一引脚511，或连接一个第二驱动芯片520的第二引脚521，在其他实施例中，当第一驱动芯片510或第二驱动芯片520的数量不止一个时，每相邻6a列数据线可以是由相邻2个或多个第一驱动芯片510的相邻引脚连接的或相邻2个或多个第二驱动芯片520的相邻引脚连接的，即只要满足任一行的同一个像素中的三个子像素410是由同一侧的驱动芯片驱动即可，并不一定需要是由同一个驱动芯片驱动。
其中，第一驱动芯片510相邻的第一引脚511输出的信号极性不同，第二芯片520相邻的第二引脚521输出的信号极性不同，即相邻的第一引脚511以及相邻的第二引脚521输出的信号按照正负交替的方式进行输出信号，如图1所示，以使得任一子像素410与其上下左右相邻的子像素410之间的极性不同，从而实现子像素410的极性点反转，减少画面的闪烁。其中，a为正整数，例如：a可以为1、2、5等。
上述实施例中，通过将第一驱动芯片以及第二驱动芯片分别设置在阵列基板显示区的上下两侧，同时将第一驱动芯片与第二驱动芯片以每相邻6a列第一引脚与每相邻6a列第二引脚交替连接的方式连接数据线，使得任一行的同一个像素中的三个子像素由同一侧的驱动芯片驱动，且相邻的第一引脚及相邻的第二引脚输出的信号极性不同，能够在满足同一像素由同一侧驱动芯片驱动的前提下，实现子像素极性的点反转，减少画面的闪烁。
在本实施例中，该阵列包括n行及m列的子像素，扫描线为n条，数据线为（m+1）条，数据线包括第1条数据线至第（m+1）条数据线，其中，n、m均为正整数，例如，可以取5、10等。
可选地，当a取1时，第一驱动芯片510的多个第一引脚511分别连接第1条至第6条数据线，第二驱动芯片520的多个第二引脚521分别连接第7条至第12条数据线，并依次循环，以使第一驱动芯片510的多个第一引脚511以及第二驱动芯片520的多个第二引脚521连接所有（m+1）条数据线。
其中，第奇数列数据线输出的信号极性为正，第偶数列数据线输出的信号极性为负，具体地，第1、第3、第5列等数据线430输出的信号极性为正，第2、第4、第6列等数据线430输出的信号极性为负，从而使得任一子像素410与其上下左右相邻的子像素410之间的极性不同。
请参阅图2，图2是本发明阵列基板另一实施例的结构示意图。
在本实施例中的阵列基板除了上述结构外，外围区500还包括至少一个第三驱动芯片530，第三驱动芯片530位于显示区400的一侧边，可选地，第三驱动芯片530位于显示区400的左侧，第三驱动芯片530设有多个第三引脚531，分别连接扫描线420，以对子像素410输入栅极驱动信号。
可以理解的是，图2中以第三驱动芯片530的数量为1个进行说明，在其他实施例中，可由设计人员根据显示面板的尺寸、分辨率及芯片的大小选择合适数量的第三驱动芯片530。
请参阅图3，图3是本发明阵列基板再一实施例的结构示意图，该阵列基板包括：显示区600以及外围区700。
显示区600包括互相交叉的多条数据线630、多条扫描线620以及呈阵列分布的子像素610，阵列中每一行的子像素610由一条对应的扫描线620连接，每一列的子像素610由两条对应相邻的数据线630按奇偶行交替连接，且同一列的子像素610颜色相同。
外围区700包括位于显示区600上方的第一短接棒区域710、位于显示区600下方的第二短接棒区域720以及位于显示区600侧边的第三短接棒区域730，第一短接棒区域710包括横向设置的第一短接棒711、第二短接棒712、第三短接棒713，第二短接棒区域720包括横向设置的第四短接棒721、第五短接棒722、第六短接棒723，第三短接棒区域730包括竖向设置的第七短接棒731、第八短接棒732。
第一短接棒区域710与第二短接棒区域720以交替连接每相邻6b列数据线630的方式连接数据线630，使得任一行的同一个像素中的三个子像素610由同一侧的短接棒区域连接，第七短接棒731与奇数行的扫描线620连接，第八短接棒732与偶数行的扫描线620连接，其中，b为正整数，具体地，b可以为1、2、5等。
可选地，在本实施例中，第一短接棒区域710还包括第一导电垫714、第二导电垫715以及第三导电垫716，第一短接棒711与第一导电垫714连接、第二短接棒712与第二导电垫715连接、第三短接棒713与第三导电垫716连接。第二短接棒区域720还包括第四导电垫724、第五导电垫725以及第六导电垫726，第四短接棒721与第四导电垫724连接、第五短接棒722与第五导电垫725连接、第六短接棒723与第六导电垫726连接。第三短接棒区域730还包括第七导电垫733以及第八导电垫734，第七短接棒731与第七导电垫733连接、第八短接棒732与第八导电734连接。
在本实施例中，子像素610包括红绿蓝三种子像素，当通过第七短接棒731给奇数行的扫描线620提供栅极驱动信号时，若通过第一短接棒711以及第四短接棒721给数据线630提供信号，则奇数行的红像素被点亮，此时，如果满足条件的红像素未被点亮，则该红像素出现短路或断路，若通过第二短接棒712以及第五短接棒722给数据线630提供信号，则奇数行的绿像素被点亮，此时，如果满足条件的绿像素未被点亮，则该绿像素出现短路或断路，若通过第三短接棒713以及第六短接棒723给数据线630提供信号，则奇数行的蓝像素被点亮，此时，如果满足条件的蓝像素未被点亮，则该蓝像素出现断路或短路。
当通过第八短接棒732给偶数行的扫描线620提供栅极驱动信号时，若通过第一短接棒711以及第四短接棒721给数据线630提供信号，则偶数行的蓝像素被点亮，此时，如果满足条件的蓝像素未被点亮，则该蓝像素出现短路或断路；若通过第二短接棒712以及第五短接棒722给数据线630提供信号，则偶数行的红像素被点亮，此时，如果满足条件的红像素未被点亮，则该红像素出现断路或短路；若通过第三短接棒713以及第六短接棒723给数据线630提供信号，则偶数行的绿像素被点亮，此时，如果满足条件的绿像素未被点亮，则该绿像素出现断路或短路。
通过上述的实施方式，在点屏检测时，在满足同一像素由同一短接棒区域连接的条件下，可以对每一个子像素610提供信号进行检测，在某一像素出现短路或断路时能够及时发现，同时还能提高检测质量。
可选地，第一短接棒区域710还包括第九短接棒717以及第九导电垫718，第九短接棒717与第九导电垫718连接，第二短接棒区域720还包括第十短接棒727以及第十导电垫728，第十短接棒727与第十导电垫728连接，第三短接棒区域730还包括第十一短接棒735以及第十一导电垫736，第十一短接棒735与第十一导电垫736连接，第九短接棒717、第十短接棒727以及第十一短接棒735分别与公共电极（图未示）连接。
请参阅图4，图4是本发明显示面板一实施例的结构示意图，该显示面板包括：第一基板900以及第二基板800。
第一基板900以及第二基板800相对设置，具体地，第一基板900为上述任一项实施例中的阵列基板，具体结构可参见上述，在此不再赘述。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (11)

  1. 一种阵列基板，其中，包括：
    显示区以及外围区；
    所述显示区包括互相交叉的（m+1）条数据线、n条扫描线以及呈阵列分布的包括n行及m列的子像素，所述阵列中每一行的所述子像素由一条对应的所述扫描线连接，每一列的所述子像素由两条对应相邻的所述数据线按奇偶行交替连接，且同一列的所述子像素颜色相同，所述数据线包括第1条数据线至第（m+1）条数据线；
    所述外围区包括位于所述显示区上侧的至少一个第一驱动芯片、位于所述显示区下侧的至少一个第二驱动芯片以及位于所述显示区一侧边的至少一个第三驱动芯片，所述第一驱动芯片包括多个第一引脚，所述第二驱动芯片包括多个第二引脚，所述第三驱动芯片连接所述扫描线，以对所述子像素输入栅极驱动信号；
    所述第一驱动芯片与所述第二驱动芯片以每相邻6a列所述第一引脚与每相邻6a列所述第二引脚交替连接的方式连接所述数据线，使得任一行的同一个像素中的三个所述子像素由同一侧所述驱动芯片驱动，
    其中，相邻的所述第一引脚输出的信号极性不同，相邻的所述第二引脚输出的信号极性不同，以使得任一所述子像素与其上下左右相邻的所述子像素之间的极性不同，a、n以及m为正整数。
  2. 如权利要求1所述的阵列基板，其中，
    所述第一驱动芯片的所述多个第一引脚分别连接所述第1条至第6条数据线，所述第二驱动芯片的所述多个第二引脚分别连接第7条至第12条数据线，并依次循环，以使所述第一驱动芯片的所述多个第一引脚以及所述第二驱动芯片的所述多个第二引脚连接所有所述（m+1）条数据线。
  3. 如权利要求2所述的阵列基板，其中，
    第奇数列所述数据线输出的信号极性为正，第偶数列所述数据线输出的信号极性为负。
  4. 一种阵列基板，其中，包括：
    显示区以及外围区；
    所述显示区包括互相交叉的多条数据线、多条扫描线以及呈阵列分布的子像素，所述阵列中每一行的所述子像素由一条对应的所述扫描线连接，每一列的所述子像素由两条对应相邻的所述数据线按奇偶行交替连接，且同一列的所述子像素颜色相同；
    所述外围区包括位于所述显示区上侧的至少一个第一驱动芯片以及位于所述显示区下侧的至少一个第二驱动芯片，所述第一驱动芯片包括多个第一引脚，所述第二驱动芯片包括多个第二引脚；
    所述第一驱动芯片与所述第二驱动芯片以每相邻6a列所述第一引脚与每相邻6a列所述第二引脚交替连接的方式连接所述数据线，使得任一行的同一个像素中的三个所述子像素由同一侧所述驱动芯片驱动，
    其中，相邻的所述第一引脚输出的信号极性不同，相邻的所述第二引脚输出的信号极性不同，以使得任一所述子像素与其上下左右相邻的所述子像素之间的极性不同，a、n以及m为正整数。
  5. 如权利要求4所述的阵列基板，其中，
    所述阵列包括n行及m列的子像素，所述扫描线为n条，所述数据线为（m+1）条，所述数据线包括第1条数据线至第（m+1）条数据线，其中，所述n、m均为正整数。
  6. 如权利要求5所述的阵列基板，其中，
    所述第一驱动芯片的所述多个第一引脚分别连接所述第1条至第6条数据线，所述第二驱动芯片的所述多个第二引脚分别连接第7条至第12条数据线，并依次循环，以使所述第一驱动芯片的所述多个第一引脚以及所述第二驱动芯片的所述多个第二引脚连接所有所述（m+1）条数据线。
  7. 如权利要求6所述的阵列基板，其中，
    第奇数列所述数据线输出的信号极性为正，第偶数列所述数据线输出的信号极性为负。
  8. 如权利要求4所述的阵列基板，其中，
    所述外围区还包括至少一个第三驱动芯片，所述第三驱动芯片位于所述显示区的一侧边，所述第三驱动芯片连接所述扫描线，以对所述子像素输入栅极驱动信号。
  9. 一种阵列基板，其中，所述阵列基板包括：
    显示区以及外围区；
    所述显示区包括互相交叉的多条数据线、多条扫描线以及呈阵列分布的子像素，所述阵列中每一行的所述子像素由一条对应的所述扫描线连接，每一列的所述子像素由两条对应相邻的所述数据线按奇偶行交替连接，且同一列的所述子像素颜色相同；
    所述外围区包括位于所述显示区上方的第一短接棒区域、位于所述显示区下方的第二短接棒区域以及位于所述显示区侧边的第三短接棒区域，所述第一短接棒区域包括横向设置的第一短接棒、第二短接棒、第三短接棒，所述第二短接棒区域包括横向设置的第四短接棒、第五短接棒、第六短接棒，所述第三短接棒区域包括竖向设置的第七短接棒、第八短接棒；
    所述第一短接棒区域与所述第二短接棒区域以交替连接每相邻6b列所述数据线的方式连接所述数据线，使得任一行的同一个像素中的三个所述子像素由同一侧的所述短接棒区域连接，所述第七短接棒与奇数行的所述扫描线连接，所述第八短接棒与偶数行的所述扫描线连接，其中，b为正整数。
  10. 如权利要求9所述的阵列基板，其中，
    所述子像素包括红绿蓝三种子像素，当通过第七短接棒给奇数行的所述扫描线提供栅极驱动信号时，若通过第一短接棒以及所述第四短接棒给所述数据线提供信号，则奇数行的所述红像素被点亮，若通过第二短接棒以及所述第五短接棒给所述数据线提供信号，则奇数行的所述绿像素被点亮，若通过第三短接棒以及所述第六短接棒给所述数据线提供信号，则奇数行的所述蓝像素被点亮；
    当通过第八短接棒给偶数行的所述扫描线提供栅极驱动信号时，若通过第一短接棒以及所述第四短接棒给所述数据线提供信号，则偶数行的所述蓝像素被点亮，若通过第二短接棒以及所述第五短接棒给数据线提供信号，则偶数行的所述红像素被点亮，若通过第三短接棒以及所述第六短接棒给所述数据线提供信号，则偶数行的所述绿像素被点亮。
  11. 如权利要求9所述的阵列基板，其中，
    所述第一短接棒区域还包括第九短接棒，所述第二短接棒区域还包括第十短接棒，所述第三短接棒区域还包括第十一短接棒，所述第九短接棒、第十短接棒以及第十一短接棒分别与公共电极连接。
PCT/CN2017/102542 2017-07-18 2017-09-21 一种阵列基板以及显示面板 WO2019015078A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/739,731 US10403648B2 (en) 2017-07-18 2017-09-21 Array substrates with adjacent sub-pixels having opposite polarities

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710586052.5A CN107272290A (zh) 2017-07-18 2017-07-18 一种阵列基板以及显示面板
CN201710586052.5 2017-07-18

Publications (1)

Publication Number Publication Date
WO2019015078A1 true WO2019015078A1 (zh) 2019-01-24

Family

ID=60078898

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/102542 WO2019015078A1 (zh) 2017-07-18 2017-09-21 一种阵列基板以及显示面板

Country Status (3)

Country Link
US (1) US10403648B2 (zh)
CN (1) CN107272290A (zh)
WO (1) WO2019015078A1 (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107749282A (zh) 2017-11-03 2018-03-02 惠科股份有限公司 一种显示面板及显示装置
CN108364931B (zh) * 2018-02-28 2020-01-03 武汉华星光电技术有限公司 阵列基板、显示面板和移动终端
CN109637473B (zh) * 2018-12-12 2021-04-06 惠科股份有限公司 阵列基板、显示面板及显示装置
CN109599073B (zh) * 2019-01-09 2020-12-25 惠科股份有限公司 一种显示装置、驱动方法和显示器
CN110133883B (zh) * 2019-04-22 2024-05-07 北京集创北方科技股份有限公司 显示装置、显示系统及制造方法
CN111028762B (zh) * 2019-12-31 2022-09-30 厦门天马微电子有限公司 一种显示装置
CN111951691B (zh) * 2020-08-25 2022-07-19 上海天马微电子有限公司 显示面板及显示装置
TWI770633B (zh) * 2020-10-14 2022-07-11 友達光電股份有限公司 顯示裝置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101251660A (zh) * 2007-02-23 2008-08-27 三星电子株式会社 显示装置
US20100053487A1 (en) * 2008-09-04 2010-03-04 Hung-Chang Wu Lcd panel
CN104698637A (zh) * 2015-04-01 2015-06-10 上海天马微电子有限公司 阵列基板、测试方法、显示面板及显示装置
CN104714319A (zh) * 2014-12-23 2015-06-17 上海中航光电子有限公司 一种液晶显示面板及其显示装置
CN105353545A (zh) * 2015-12-03 2016-02-24 深圳市华星光电技术有限公司 液晶显示面板及其阵列基板电路
CN105676496A (zh) * 2016-04-21 2016-06-15 深圳市华星光电技术有限公司 液晶显示面板及液晶显示装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013020188A (ja) * 2011-07-13 2013-01-31 Panasonic Liquid Crystal Display Co Ltd 液晶表示装置
US20140184672A1 (en) * 2012-12-28 2014-07-03 Shenzhen China Star Optoelectronics Technology Co., Ltd. Liquid crystal panel and liquid display device with the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101251660A (zh) * 2007-02-23 2008-08-27 三星电子株式会社 显示装置
US20100053487A1 (en) * 2008-09-04 2010-03-04 Hung-Chang Wu Lcd panel
CN104714319A (zh) * 2014-12-23 2015-06-17 上海中航光电子有限公司 一种液晶显示面板及其显示装置
CN104698637A (zh) * 2015-04-01 2015-06-10 上海天马微电子有限公司 阵列基板、测试方法、显示面板及显示装置
CN105353545A (zh) * 2015-12-03 2016-02-24 深圳市华星光电技术有限公司 液晶显示面板及其阵列基板电路
CN105676496A (zh) * 2016-04-21 2016-06-15 深圳市华星光电技术有限公司 液晶显示面板及液晶显示装置

Also Published As

Publication number Publication date
CN107272290A (zh) 2017-10-20
US20190027496A1 (en) 2019-01-24
US10403648B2 (en) 2019-09-03

Similar Documents

Publication Publication Date Title
WO2019015078A1 (zh) 一种阵列基板以及显示面板
WO2017024644A1 (zh) 一种液晶显示面板及其驱动电路
CN104820325B (zh) 薄膜晶体管液晶显示器及阵列基板
US20150015623A1 (en) Display panel and display device
CN105182644B (zh) 薄膜晶体管阵列基板、显示面板及显示面板的检测方法
WO2016176914A1 (zh) 基板及其液晶显示装置
CN105702226A (zh) 一种显示面板的驱动方法、显示面板及显示装置
JP6373498B2 (ja) 配列基板及び液晶パネル及び液晶ディスプレイ
WO2017031790A1 (zh) 阵列基板及其驱动方法
WO2017092082A1 (zh) 阵列基板以及液晶显示装置
WO2016183922A1 (zh) 一种液晶显示面板及装置
WO2019119810A1 (zh) 显示面板的驱动方法、驱动装置及显示装置
WO2019015022A1 (zh) 一种goa显示面板及goa显示装置
JP6369925B2 (ja) 配列基板及び液晶パネル及び液晶ディスプレイ
WO2015010348A1 (zh) 一种阵列基板及液晶显示面板
WO2017015973A1 (zh) 一种阵列基板、显示面板以及显示装置
WO2019127767A1 (zh) 显示面板的驱动方法及显示装置
WO2020056839A1 (zh) 显示装置和液晶显示器
WO2017101161A1 (zh) 基于hsd结构的显示面板和显示装置
US20240105112A1 (en) Display substrate and display apparatus
WO2014153771A1 (zh) 阵列基板及液晶显示装置
WO2018152936A1 (zh) 一种阵列基板及显示面板
WO2023019629A1 (zh) 显示面板及移动终端
WO2014023010A1 (zh) 一种阵列基板及液晶显示面板
WO2017121016A1 (zh) 显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17918099

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17918099

Country of ref document: EP

Kind code of ref document: A1