WO2014153771A1 - 阵列基板及液晶显示装置 - Google Patents

阵列基板及液晶显示装置 Download PDF

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Publication number
WO2014153771A1
WO2014153771A1 PCT/CN2013/073442 CN2013073442W WO2014153771A1 WO 2014153771 A1 WO2014153771 A1 WO 2014153771A1 CN 2013073442 W CN2013073442 W CN 2013073442W WO 2014153771 A1 WO2014153771 A1 WO 2014153771A1
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WIPO (PCT)
Prior art keywords
scan
line
scan line
pixel unit
data
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PCT/CN2013/073442
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English (en)
French (fr)
Inventor
罗时勲
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深圳市华星光电技术有限公司
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Priority to US13/878,758 priority Critical patent/US9389475B2/en
Publication of WO2014153771A1 publication Critical patent/WO2014153771A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to an array substrate, and to a liquid crystal display device including an array substrate.
  • FIG. 1 it is a partial schematic diagram of a circuit structure of an array substrate in the prior art.
  • the array substrate has a plurality of pixel units 11, each of which includes a pixel electrode 101 and a thin film transistor 102.
  • the scan lines G01 and G02 of the array substrate are simultaneously turned on and off, and the data lines D01 and D02 are arranged on both sides of one column of pixel units 11, and the two scan lines G01 and G02 pass through the thin film transistors 102 and two of the two pixel units 11, respectively.
  • the data lines D01 and D02 are connected, and when the two scanning lines G01 and G02 are simultaneously turned on, the charging time of the pixel electrode 101 can be lengthened.
  • the effective charging time becomes 1/4 baking
  • at least three scanning lines are required to be simultaneously turned on, and when at least three data lines are arranged around one column of pixel units, if the data lines are still arranged in a straight line, crossover of the pixel electrodes may occur. In this case, it is easy to interfere with the pixel electrodes of the plurality of pixel units.
  • a primary object of the present invention is to provide an array substrate and a liquid crystal display device capable of avoiding the technical problem of interference between a data line and a pixel electrode when at least three scanning lines are turned on.
  • a technical solution adopted by the present invention is to provide an array substrate including a plurality of pixel units arranged in a matrix form in a row direction and a column direction, each pixel unit including a pixel electrode and a a thin film transistor, a drain of the thin film transistor is connected to the pixel electrode, the array substrate further includes a plurality of scan line groups and a plurality of data line groups disposed in an insulated intersection, each scan line group including three scan lines extending in a row direction, and each The scan lines are connected to the gates of the thin film transistors in the corresponding row of pixel units, and each scan line in each scan line group simultaneously receives the scan signals to control the rows of pixel units corresponding to the scan lines in the scan line group.
  • the thin film transistors are simultaneously turned on and off, and each of the data line groups respectively includes a data line corresponding to the number of scan lines in the scan line group, and the source of the thin film transistor in each pixel unit of the same column is connected to a corresponding one of the same data line group.
  • a data line one of the three scan lines and the second one of the third scan line Extending and arranging on both sides of each pixel unit of the same column, wherein the data lines of the second scan lines of the corresponding three scan lines in each data line group pass through the corresponding pixel unit and adjacent pixels in the column direction
  • the cells are bent from one side of the corresponding pixel unit to the other side so that the thin film transistors in each pixel unit are connected to the most adjacent data lines and the data lines do not interfere with each other.
  • the data line corresponding to the second scan line of the three scan lines includes at least a first portion, a second portion, and a third portion that are sequentially connected, wherein the first portion and the third portion respectively extend in the column direction and are located corresponding thereto
  • the second portion extends in the row direction and is located between the corresponding pixel unit and the adjacent pixel unit in the column direction, thereby connecting the adjacent ends of the first portion and the third portion.
  • the first scan line, the second scan line, and the third scan line are shorted, and receive the scan signal.
  • the first scan line, the second scan line, and the third scan line each receive one scan signal.
  • Each scan line group further includes a fourth scan line disposed adjacent to the third scan line in the column direction, the fourth scan line receives the scan signal, and the data line corresponding to the fourth scan line extends in the column direction.
  • the data line corresponding to the third scan line is bent and extended before extending to the pixel unit corresponding to the fourth scan line in the column direction, and the data line corresponding to the third scan line is not extended with the second The data lines corresponding to the scan lines intersect.
  • an array substrate including a plurality of pixel units arranged in a matrix in a row direction and a column direction, each pixel unit including a pixel electrode and a thin film transistor, a drain of the thin film transistor is connected to the pixel electrode, the array substrate further includes a plurality of scan line groups and a plurality of data line groups, and each scan line group includes at least three scan lines extending in a row direction. And each scan line is connected to a gate of a thin film transistor in a corresponding row of pixel units, and each scan line in each scan line group simultaneously receives a scan signal to control each row of pixel units corresponding to each scan line in the scan line group.
  • each data line group respectively includes a data line corresponding to the number of scan lines in the scan line group, and the source of the thin film transistor in each pixel unit of the same column is connected in the same data line group.
  • Corresponding to a data line wherein at least part of the data lines in each data line group pass through the corresponding pixel list It means between adjacent pixels in the column direction and is bent to extend from its corresponding pixel unit side to the other side, so that the thin film transistor in each pixel cell connected to the most adjacent data lines.
  • At least a portion of the data lines includes at least a first portion, a second portion, and a third portion that are sequentially connected, wherein the first portion and the third portion respectively extend in the column direction and are located on opposite sides of the corresponding pixel unit, the second portion Extending in the row direction and between the corresponding pixel unit and the adjacent pixel unit in the column direction, thereby connecting the adjacent ends of the first portion and the third portion.
  • the number of scan lines of each scan line group is three, and the two data lines corresponding to the first scan line and the third scan line of the three scan lines extend in the column direction and are disposed on both sides of each pixel unit in the same column.
  • the data lines corresponding to the second scan lines of the three scan lines are bent and extended so that the data lines do not interfere with each other corresponding to the pixel unit.
  • the first scan line, the second scan line, and the third scan line are shorted, and receive the scan signal.
  • the first scan line, the second scan line, and the third scan line each receive one scan signal.
  • Each scan line group further includes a fourth scan line disposed adjacent to the third scan line in the column direction, the fourth scan line receives the scan signal, and the data line corresponding to the fourth scan line extends in the column direction.
  • the data line corresponding to the third scan line is bent and extended before extending to the pixel unit corresponding to the fourth scan line in the column direction, and the data line corresponding to the third scan line is not extended with the second The data lines corresponding to the scan lines intersect.
  • a liquid crystal display device including an array substrate including a plurality of pixel units arranged in a matrix form in a row direction and a column direction, each The pixel unit includes a pixel electrode and a thin film transistor.
  • the drain of the thin film transistor is connected to the pixel electrode, and the array substrate further includes a plurality of scan line groups and a plurality of data line groups, and each scan line group includes At least three scan lines extending in a direction, and each scan line is connected to a gate of a thin film transistor in a corresponding row of pixel units, and each scan line in each scan line group simultaneously receives a scan signal to control each of the scan line groups
  • the thin film transistors in each row of pixel units corresponding to the scan lines are simultaneously turned on and off, and each data line group includes a data line corresponding to the number of scan lines in the scan line group, and a source of the thin film transistor in each pixel unit of the same column.
  • each of the data line groups A portion of the data line is bent from the corresponding pixel unit and the adjacent pixel unit in the column direction from the corresponding pixel unit side to the other side, so that the thin film transistor in each pixel unit is the most Adjacent data lines are connected.
  • At least a portion of the data lines includes at least a first portion, a second portion, and a third portion that are sequentially connected, wherein the first portion and the third portion respectively extend in the column direction and are located on opposite sides of the corresponding pixel unit, the second portion Extending in the row direction and between the corresponding pixel unit and the adjacent pixel unit in the column direction, thereby connecting the adjacent ends of the first portion and the third portion.
  • the number of scan lines of each scan line group is three, and the two data lines corresponding to the first scan line and the third scan line of the three scan lines extend in the column direction and are disposed on both sides of each pixel unit in the same column.
  • the data lines corresponding to the second scan lines of the three scan lines are bent and extended so that the data lines do not interfere with each other corresponding to the pixel unit.
  • the first scan line, the second scan line, and the third scan line are shorted, and receive the scan signal.
  • the first scan line, the second scan line, and the third scan line each receive one scan signal.
  • Each scan line group further includes a fourth scan line disposed adjacent to the third scan line in the column direction, the fourth scan line receives the scan signal, and the data line corresponding to the fourth scan line extends in the column direction.
  • the data line corresponding to the third scan line is bent and extended before extending to the pixel unit corresponding to the fourth scan line in the column direction, and the data line corresponding to the third scan line is not extended with the second The data lines corresponding to the scan lines intersect.
  • the array substrate and the liquid crystal display device of the present invention have at least a portion of the data lines corresponding to each column of pixel units passing between the corresponding pixel unit and the adjacent pixel unit in the column direction.
  • the corresponding pixel unit is bent to extend to the other side, so that the thin film transistor in each pixel unit is connected to the most adjacent data line, so that each data line does not interfere with the pixel electrode of the pixel unit, and the opening can be realized.
  • FIG. 1 is a partial schematic view showing the circuit structure of an array substrate in the prior art
  • FIG. 2 is a partial schematic view showing the circuit structure of the first embodiment of the array substrate of the present invention.
  • FIG. 3 is a partial schematic view showing a circuit structure of a second embodiment of the array substrate of the present invention.
  • FIG. 4 is a partial schematic view showing the circuit structure of a third embodiment of the array substrate of the present invention.
  • Fig. 5 is a partial schematic view showing the circuit structure of a fourth embodiment of the array substrate of the present invention.
  • FIG. 2 is a partial schematic view showing the circuit structure of the first embodiment of the array substrate of the present invention.
  • the array substrate includes a plurality of pixel units 21 arranged in a matrix in a row direction and a column direction.
  • Each of the pixel units 21 includes a pixel electrode 201 and a thin film transistor 202.
  • the pixel electrode 201 can be turned on and off by the thin film transistor 202. Charging.
  • the array substrate further includes a plurality of scan line groups GS1 and a plurality of data line groups DS1 that are insulated and disposed in cross.
  • Each of the scanning line groups GS1 includes three scanning lines G1, G2, and G3 extending in the row direction.
  • Each of the data line groups DS1 includes three data lines D1, D2, and D3 corresponding to the number of scanning lines in the scanning line group GS1, respectively.
  • the pixel electrode 201 of each pixel unit 21 is electrically connected to the scan line and the data line corresponding to the pixel unit 21 through the thin film transistor 202.
  • the drain of the thin film transistor 202 is connected to the pixel electrode 201, and each of the scan lines G1, G2, and G3 is connected to the gate of the thin film transistor 202 in the corresponding row of pixel units 21, and the thin film in each pixel unit 21 of the same column.
  • the source of transistor 202 is coupled to corresponding data lines D1, D2, and D3 in the same data line group DS1.
  • Each of the scan lines G1, G2, and G3 in each scan line group GS1 simultaneously receives a scan signal to control the thin film transistor 202 in each row of pixel units 21 corresponding to each of the scan lines G1, G2, and G3 in the scan line group GS1. Turning on and off, that is, the pixel electrodes 201 in the pixel units 21 of the respective rows are simultaneously charged.
  • the first scanning line G1, the second scanning line G2, and the third scanning line G3 are short-circuited, and receive a scanning signal.
  • the first scan line G1, the second scan line G2, and the third scan line G3 each receive one scan signal.
  • each scan line G1, G2, and G3 are respectively connected to three outputs of the control chip. Port, the control chip controls three output ports to simultaneously output the scan signal.
  • the data line D2 in each data line group DS1 is bent from the corresponding pixel unit 21 and the adjacent pixel unit 21 in the column direction from the corresponding pixel unit 21 side thereof to the other side to
  • the thin film transistor 202 in each pixel unit 21 is connected to the most adjacent data lines D1, D2, and D3.
  • the first three columns of pixel units 21 in the first three rows are taken as an example, and the two data lines D1 and D3 corresponding to the first scanning line G1 and the third scanning line G3 extend in the column direction and are arranged in the first column.
  • the pixel unit 21 of the first row is connected to the most adjacent data line D1
  • the pixel unit 21 of the second row is connected to the most adjacent data line D2.
  • the pixel unit 21 of the third row will be the closest to the data line D2 instead of the data line D3, but the pixel unit 21 of the third row should be connected to the data line D3. Therefore, the data line D2 corresponding to the second scanning line G2 is bent and extended, and after the data line D2 is bent and extended, the one side of the pixel unit 21 of the second row is bent and extended to the other side, and the third line is The data lines immediately adjacent to the pixel unit 21 become the data line D3, so that the data lines D1, D2, and D3 do not cross the pixel electrode 201 and do not interfere with the pixel unit 21 corresponding thereto.
  • the data line D2 includes at least the first portion d1, the second portion d2, and the third portion d3 which are sequentially connected.
  • the first portion d1 and the third portion d3 respectively extend in the column direction and are located on the right and left sides of the corresponding pixel unit 21 thereof.
  • the second portion d2 extends in the row direction and is located between the corresponding pixel unit 21 and the adjacent pixel unit 21 in the column direction, thereby connecting the adjacent ends of the first portion d1 and the third portion d3.
  • the second portion d2 may be located between the pixel unit 21 of the first row and the pixel unit 21 of the second row, or may be located between the pixel unit 21 of the second row and the pixel unit 21 of the third row.
  • FIG. 3 is a partial schematic view showing the circuit structure of the second embodiment of the array substrate of the present invention.
  • the second embodiment shown in FIG. 3 is similar to the first embodiment shown in FIG. 2, and therefore the same components as those in FIG. 2 are denoted by the same reference numerals and the description thereof will not be repeated.
  • the second embodiment of FIG. 3 is different from the first embodiment of FIG. 2 in that the data line D3 corresponding to the first scanning line G1 is on the right side of the pixel unit 21 of the first row and the pixel unit 21 of the first row.
  • the data line D1 corresponding to the third scanning line G3 is electrically connected to the pixel unit 21 of the third row on the left side of the pixel unit 21 of the third row.
  • the first portion d1 and the third portion d3 of the data line D2 corresponding to the second scanning line G2 respectively extend in the column direction and are respectively located on the left and right sides of the corresponding pixel unit 21, and the second portion d2 is connected to the first portion d1.
  • the data lines D1, D2, and D3 in the data line group DS1 correspond to the pixel units 21 of different rows, and the direction in which the data lines D2 are bent and extended is different.
  • the array substrate is also included in the protection scope of the present invention.
  • FIG. 4 is a partial schematic view showing the circuit structure of the third embodiment of the array substrate of the present invention.
  • the third embodiment shown in FIG. 4 is similar to the first embodiment shown in FIG. 2, and therefore the same components as those in FIG. 2 are denoted by the same reference numerals and the description thereof will not be repeated.
  • the third embodiment of FIG. 4 is different from the first embodiment of FIG. 2 in that the scan line group GS1 further includes a fourth scan line G4 disposed adjacent to the third scan line G3 in the column direction, and the fourth scan The data line corresponding to the line G4 is the data line D4.
  • the fourth scanning line G4 is connected to the gate of the thin film transistor 202 of the corresponding row of pixel units 21, and the data line D4 corresponding to the fourth scanning line G4 is connected to the source of the B-transistor 202 of the column of pixel units 21, and the thin film transistor 202 is The drain is connected to the pixel electrode 201.
  • the scanning lines G1, G2, G3, and G4 simultaneously receive the scanning signals to control the thin film transistors 202 in the respective rows of pixel units 21 corresponding to the scanning lines G1, G2, G3, and G4 in the scanning line group GS1 to be simultaneously turned on and off.
  • the data line D4 corresponding to the fourth scanning line G4 extends in the column direction, and is not bent in the middle. Similar to the data line D2 corresponding to the second scanning line G2, the data line D3 corresponding to the third scanning line G3 is bent and extended before extending to the pixel unit 21 corresponding to the fourth scanning line G4 in the column direction, that is, from The pixel unit 21 of the third row and the adjacent pixel unit 21 in the column direction are bent from the side of the corresponding pixel unit 21 to the other side. In the present embodiment, the data line D2 is bent and extended from the pixel unit 21 of the second row and the pixel unit 21 of the third row, and the data line D3 is from the pixel unit 21 of the third row and the pixel unit 21 of the fourth row.
  • the bend extends between.
  • the data line D2 is bent and stretched from between the pixel unit 21 of the first row and the pixel unit 21 of the second row
  • the data line D3 is from the pixel unit 21 of the second row and the pixel unit 21 of the third row.
  • the bend extends between.
  • the data line D2 is bent and stretched from between the pixel unit 21 of the first row and the pixel unit 21 of the second row
  • the data line D3 is bent from between the pixel unit 21 of the third row and the pixel unit 21 of the fourth row.
  • FIG. 5 is a partial schematic view showing the circuit structure of the fourth embodiment of the array substrate of the present invention.
  • the fourth embodiment shown in FIG. 5 is similar to the third embodiment shown in FIG. 4, and therefore the same components as those in FIG. 4 are denoted by the same reference numerals and the description thereof will not be repeated.
  • the fourth embodiment of FIG. 5 is different from the third embodiment of FIG. 4 in that the pixel units 21 corresponding to the respective data lines D1, D2, D3, and D4 of the data line group DS1 are different.
  • the data line D4 extends from the right side of the pixel unit 21 of the first column in the column direction, and on the right side with the first scanning line G1 and the first row
  • the pixel unit 21 is electrically connected.
  • the data line D1 extends from the left side of the pixel unit of the first column in the column direction, and is electrically connected to the fourth scanning line G4 and the pixel unit 21 of the fourth row on the left side.
  • the data line D2 extends from the left side in the column direction, and is bent from the left side of the pixel unit 21 of the third row to the pixel unit 21 of the fourth row from the left side of the pixel unit 21 of the third row to the right side, and is bent. It is electrically connected to the third scanning line G3 and the pixel unit 21 of the third row.
  • the data line D3 also extends from the left side in the column direction, and is bent from the left side of the pixel unit 21 of the third row to the pixel unit 21 of the second row from the left side of the pixel unit 21 of the second row to the right side, at the bend
  • the folding time is electrically connected to the second scanning line G2 and the pixel unit 21 of the second row.
  • the position when the data line D2 and the data line D3 are bent and extended also has various options including between the pixel unit 21 of the first row and the pixel unit 21 of the second row, and the second row. Between the pixel unit 21 and the pixel unit 21 of the third row, and between the pixel unit 21 of the third row and the pixel unit 21 of the fourth row.
  • the position when the data line D2 and the data line D3 are bent and extended depends on the actual situation, and the present invention does not limit this.
  • the data lines D1, D2, D3, and D4 in the data line group DS1 correspond to the pixel units 21 of different rows, and the data lines D2 and D3 are bent and extended.
  • the direction of the time is different, however, those skilled in the art can easily obtain the array substrate in which the third embodiment and the fourth embodiment are combined and combined according to the present invention and common knowledge in the art, and therefore, the array substrate is also included in the protection of the present invention.
  • the scan line group GS1 includes only three or four scan lines that simultaneously receive scan signals, but the present invention does not limit the number of scan lines included in the scan line group GS1, that is, scan lines.
  • the scanning line group GS1 of the present invention may include at least three scanning lines extending in the row direction, correspondingly,
  • the data line group DS1 also includes at least three data lines.
  • the fourth scanning line G4 when the fourth scanning line G4 is added, the data line D3 is bent and extended, and when the scanning line is further added to the third embodiment, the data line D4 is performed. The bending is extended, and so on, as long as there is sufficient space on the array substrate, in theory, the number of scanning lines included in the scanning line group GS1 can be increased indefinitely.
  • the present invention also provides a liquid crystal display device including the array substrate of the foregoing embodiment.
  • a liquid crystal display device including the array substrate of the foregoing embodiment.
  • the scan line group when the scan line group is included in at least three scan lines, at least part of the data lines are bent from the pixel unit side by the position between adjacent pixel units on the same column.
  • the folding extends to the other side, so that the thin film transistor in each pixel unit is connected with the most adjacent data line, which can avoid interference between the data line and the pixel electrode, and improve the charging time, so that the resolution can reach 4000 ⁇ 2000 and above.

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Abstract

一种阵列基板及液晶显示装置。扫描线组（GS1）包括至少三条扫描线（G1，G2，G3），通过使每一列像素单元对应的数据线中至少部分数据线（D2）经其所对应的像素单元和列方向上的相邻像素单元之间从其所对应的像素单元一侧弯折延伸至另一侧，使得每一像素单元中的薄膜晶体管与最相邻的数据线连接。该阵列基板及液晶显示装置能够避免各数据线与像素单元的像素电极之间的干涉，同时通过开启至少三条扫描线提升了充电时间。

Description

阵列基板及液晶显示装置
【技术领域】
本发明涉及液晶显示领域，特别是涉及一种阵列基板，还涉及一种包括阵列基板的液晶显示装置。
【背景技术】
近年来，配备TFT-LCD（Thin Film Transistor-Liquid Crystal Display，薄膜晶体管液晶显示器）的设备已经能够支持FHD（Full High Definition，全高清）显示，其分辨率可以达到1920×1080，部分满足更高需求的设备，比如强调3D显示效果的设备，已经支持QFHD（Quad Full High Definition，四全高清）显示，其分辨率可以达到3840×2160或者4000×2000，能够在一个屏幕上显示4个FHD图像。
但是，QFHD相对于FHD而言，在采用的驱动频率为60Hz或120Hz时，像素电极的有效充电时间将变为1/2焙或1/4焙。有效充电时间变为1/2焙，可以通过同时开启阵列基板上两条扫描线并相应增加数据线的数目来应对。例如，参阅图1，是现有技术一种阵列基板的电路结构局部示意图。阵列基板上具有多个像素单元11，每个像素单元11包括像素电极101和薄膜晶体管102。阵列基板的扫描线G01和G02同时开启和关闭，而一列像素单元11的两侧各配置数据线D01和D02，两条扫描线G01和G02分别通过两个像素单元11的薄膜晶体管102与两条数据线D01和D02连接，在两条扫描线G01和G02同时开启时，可以延长像素电极101的充电时间。
但是，有效充电时间变为1/4焙时，需要至少三条扫描线同时开启，而在一列像素单元周围配置至少三条数据线时，各数据线如果仍然以直线配置，则可能出现跨越像素电极的情况，从而容易与多个像素单元的像素电极产生干涉。
【发明内容】
本发明的主要目的是提供一种阵列基板及液晶显示装置，能够在开启至少三条扫描线时避免数据线与像素电极干涉的技术问题。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，阵列基板包括沿行方向和列方向以矩阵形式排列的多个像素单元，每一像素单元包括一像素电极以及一薄膜晶体管，薄膜晶体管的漏极与像素电极连接，阵列基板进一步包括绝缘交叉设置的多个扫描线组以及多个数据线组，每一扫描线组包括沿行方向延伸的三条扫描线，且每条扫描线连接对应的一行像素单元中的薄膜晶体管的栅极，每一扫描线组中的各扫描线同时接收扫描信号，以控制扫描线组中的各扫描线所对应的各行像素单元中的薄膜晶体管同时打开和关闭，每一数据线组分别包括与扫描线组中的扫描线数量对应的数据线，同一列的各像素单元中的薄膜晶体管的源极连接同一数据线组中的对应一数据线，三条扫描线中第一条扫描线和第三条扫描线对应的两条数据线沿列方向延伸并配置于同一列的各像素单元两侧，其中每一数据线组中的对应三条扫描线中第二条扫描线的数据线经其所对应的像素单元与列方向上的相邻像素单元之间从其所对应的像素单元一侧弯折延伸至另一侧，以使每一像素单元中的薄膜晶体管与最相邻的数据线连接且各数据线互不干涉其所对应的像素单元，对应三条扫描线中第二条扫描线的数据线至少包括顺次连接的第一部分、第二部分和第三部分，其中第一部分和第三部分分别沿列方向延伸并位于其所对应的像素单元的两侧，第二部分沿行方向延伸并位于其所对应的像素单元与列方向上的相邻像素单元之间，进而连接第一部分和第三部分的相邻端。
其中，第一条扫描线、第二条扫描线和第三条扫描线短接，并接收扫描信号。
其中，第一条扫描线、第二条扫描线和第三条扫描线各接收一路扫描信号。
其中，每一扫描线组还包括沿列方向相邻第三条扫描线设置的第四条扫描线，第四条扫描线接收扫描信号，且第四条扫描线对应的数据线沿列方向延伸，第三条扫描线对应的数据线在沿列方向延伸至第四条扫描线对应的像素单元之前进行弯折延伸，且第三条扫描线对应的数据线进行弯折延伸时不与第二条扫描线对应的数据线交叉。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，阵列基板包括沿行方向和列方向以矩阵形式排列的多个像素单元，每一像素单元包括一像素电极以及一薄膜晶体管，薄膜晶体管的漏极与像素电极连接，阵列基板进一步包括绝缘交叉设置的多个扫描线组以及多个数据线组，每一扫描线组包括沿行方向延伸的至少三条扫描线，且每条扫描线连接对应的一行像素单元中的薄膜晶体管的栅极，每一扫描线组中的各扫描线同时接收扫描信号，以控制扫描线组中的各扫描线所对应的各行像素单元中的薄膜晶体管同时打开和关闭，每一数据线组分别包括与扫描线组中的扫描线数量对应的数据线，同一列的各像素单元中的薄膜晶体管的源极连接同一数据线组中的对应一数据线，其中每一数据线组中的至少部分数据线经其所对应的像素单元与列方向上的相邻像素单元之间从其所对应的像素单元一侧弯折延伸至另一侧，以使每一像素单元中的薄膜晶体管与最相邻的数据线连接。
其中，至少部分数据线至少包括顺次连接的第一部分、第二部分和第三部分，其中第一部分和第三部分分别沿列方向延伸并位于其所对应的像素单元的两侧，第二部分沿行方向延伸并位于其所对应的像素单元与列方向上的相邻像素单元之间，进而连接第一部分和第三部分的相邻端。
其中，每一扫描线组扫描线的数量为三条，三条扫描线中第一条扫描线和第三条扫描线对应的两条数据线沿列方向延伸并配置于同一列的各像素单元两侧，三条扫描线中第二条扫描线对应的数据线进行弯折延伸，以使得各数据线互不干涉其所对应的像素单元。
其中，第一条扫描线、第二条扫描线和第三条扫描线短接，并接收扫描信号。
其中，第一条扫描线、第二条扫描线和第三条扫描线各接收一路扫描信号。
其中，每一扫描线组还包括沿列方向相邻第三条扫描线设置的第四条扫描线，第四条扫描线接收扫描信号，且第四条扫描线对应的数据线沿列方向延伸，第三条扫描线对应的数据线在沿列方向延伸至第四条扫描线对应的像素单元之前进行弯折延伸，且第三条扫描线对应的数据线进行弯折延伸时不与第二条扫描线对应的数据线交叉。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示装置，液晶显示装置包括阵列基板，阵列基板包括沿行方向和列方向以矩阵形式排列的多个像素单元，每一像素单元包括一像素电极以及一薄膜晶体管，薄膜晶体管的漏极与像素电极连接，阵列基板进一步包括绝缘交叉设置的多个扫描线组以及多个数据线组，每一扫描线组包括沿行方向延伸的至少三条扫描线，且每条扫描线连接对应的一行像素单元中的薄膜晶体管的栅极，每一扫描线组中的各扫描线同时接收扫描信号，以控制扫描线组中的各扫描线所对应的各行像素单元中的薄膜晶体管同时打开和关闭，每一数据线组分别包括与扫描线组中的扫描线数量对应的数据线，同一列的各像素单元中的薄膜晶体管的源极连接同一数据线组中的对应一数据线，其中每一数据线组中的至少部分数据线经其所对应的像素单元与列方向上的相邻像素单元之间从其所对应的像素单元一侧弯折延伸至另一侧，以使每一像素单元中的薄膜晶体管与最相邻的数据线连接。
其中，至少部分数据线至少包括顺次连接的第一部分、第二部分和第三部分，其中第一部分和第三部分分别沿列方向延伸并位于其所对应的像素单元的两侧，第二部分沿行方向延伸并位于其所对应的像素单元与列方向上的相邻像素单元之间，进而连接第一部分和第三部分的相邻端。
其中，每一扫描线组扫描线的数量为三条，三条扫描线中第一条扫描线和第三条扫描线对应的两条数据线沿列方向延伸并配置于同一列的各像素单元两侧，三条扫描线中第二条扫描线对应的数据线进行弯折延伸，以使得各数据线互不干涉其所对应的像素单元。
其中，第一条扫描线、第二条扫描线和第三条扫描线短接，并接收扫描信号。
其中，第一条扫描线、第二条扫描线和第三条扫描线各接收一路扫描信号。
其中，每一扫描线组还包括沿列方向相邻第三条扫描线设置的第四条扫描线，第四条扫描线接收扫描信号，且第四条扫描线对应的数据线沿列方向延伸，第三条扫描线对应的数据线在沿列方向延伸至第四条扫描线对应的像素单元之前进行弯折延伸，且第三条扫描线对应的数据线进行弯折延伸时不与第二条扫描线对应的数据线交叉。
综上所述，本发明的阵列基板及液晶显示装置通过使每一列像素单元对应的数据线中至少部分数据线经其所对应的像素单元与列方向上的相邻像素单元之间从其所对应的像素单元一侧弯折延伸至另一侧，使得每一像素单元中的薄膜晶体管与最相邻的数据线连接，达到各数据线不与像素单元的像素电极干涉的目的，能够实现开启至少三条扫描线来提升充电时间。
上述说明仅是本发明技术方案的概述，为了能够更清楚了解本发明的技术手段，而可依照说明书的内容予以实施，并且为了让本发明的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。
【附图说明】
图1是现有技术一种阵列基板的电路结构局部示意图；
图2是本发明阵列基板第一实施方式的电路结构局部示意图；
图3是本发明阵列基板第二实施方式的电路结构局部示意图；
图4是本发明阵列基板第三实施方式的电路结构局部示意图；
图5是本发明阵列基板第四实施方式的电路结构局部示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，均属于本发明保护的范围。
参阅图2，是本发明阵列基板第一实施方式的电路结构局部示意图。
阵列基板包括沿行方向和列方向以矩阵方式排列的多个像素单元21，每一像素单元21包括一像素电极201以及一薄膜晶体管202，通过薄膜晶体管202的开启和关闭，可以向像素电极201充电。
阵列基板进一步包括绝缘交叉设置的多个扫描线组GS1以及多个数据线组DS1。每一扫描线组GS1包括沿行方向延伸的三条扫描线G1、G2和G3。每一数据线组DS1分别包括与扫描线组GS1中的扫描线数量对应的三条数据线D1、D2和D3。
每一像素单元21中像素电极201通过薄膜晶体管202与该像素单元21对应的扫描线和数据线电性连接。具体地，薄膜晶体管202的漏极与像素电极201连接，每条扫描线G1、G2和G3连接对应的一行像素单元21中的薄膜晶体管202的栅极，同一列的各像素单元21中的薄膜晶体管202的源极连接同一数据线组DS1中的对应的数据线D1、D2和D3。
每一扫描线组GS1中的各扫描线G1、G2、G3同时接收扫描信号，以控制扫描线组GS1中的各扫描线G1、G2、G3所对应的各行像素单元21中的薄膜晶体管202同时打开和关闭，即各行像素单元21中的像素电极201同时充电。在本实施方式中，第一条扫描线G1、第二条扫描线G2和第三条扫描线G3短接，并接收扫描信号。在其他实施方式中，第一条扫描线G1、第二条扫描线G2和第三条扫描线G3各接收一路扫描信号，比如，各扫描线G1、G2、G3分别连接控制芯片的三个输出端口，由控制芯片控制三个输出端口同时输出扫描信号。
每一数据线组DS1中的数据线D2经其所对应的像素单元21与列方向上的相邻像素单元21之间从其所对应的像素单元21一侧弯折延伸至另一侧，以使每一像素单元21中的薄膜晶体管202与最相邻的数据线D1、D2和D3连接。具体地，以前三行的第一列三个像素单元21为例，第一条扫描线G1和第三条扫描线G3对应的两条数据线D1和D3沿列方向延伸并配置于第一列的各像素单元21的两侧，第一行的像素单元21与最相邻的数据线D1连接，第二行的像素单元21与最相邻的数据线D2连接。如果数据线D2不进行弯折延伸，那么第三行的像素单元21将会与数据线D2最相邻，而不是数据线D3，但是，第三行的像素单元21应该与数据线D3连接。因此，第二条扫描线G2对应的数据线D2进行弯折延伸，数据线D2弯折延伸后，从第二行的像素单元21的一侧弯折延伸至另一侧，则第三行的像素单元21最相邻的数据线就变成数据线D3，从而使得各数据线D1、D2、D3不会跨越像素电极201，互不干涉其所对应的像素单元21。
在本实施方式中，数据线D2至少包括顺次连接的第一部分d1、第二部分d2和第三部分d3。第一部分d1和第三部分d3分别沿列方向延伸并位于其所对应的像素单元21的右侧和左侧。第二部分d2沿行方向延伸并位于其所对应的像素单元21与列方向上的相邻像素单元21之间，进而连接第一部分d1和第三部分d3的相邻端。第二部分d2可以位于第一行的像素单元21与第二行的像素单元21之间，也可以位于第二行的像素单元21和第三行的像素单元21之间。
参阅图3，是本发明阵列基板第二实施方式的电路结构局部示意图。图3所示的第二实施方式与图2所示的第一实施方式相似，因此与图2相同的元件以相同的标号表示，且不再重复赘述。
图3的第二实施方式与图2的第一实施方式不同之处在于，第一条扫描线G1对应的数据线D3在第一行的像素单元21的右侧与第一行的像素单元21电性连接，而第三条扫描线G3对应的数据线D1在第三行的像素单元21的左侧与第三行的像素单元21电性连接。第二条扫描线G2对应的数据线D2的第一部分d1和第三部分d3分别沿列方向延伸并分别位于其所对应的像素单元21的左侧和右侧，第二部分d2连接第一部分d1和第三部分d3的相邻端。
应当理解的是，本发明的第一实施方式和第二实施方式中，数据线组DS1中数据线D1、D2、D3对应不同行的像素单元21，且数据线D2弯折延伸时的方向不同，但是，本领域技术人员容易根据本发明以及本领域公知常识得出将第一实施方式和第二实施方式混合组合的阵列基板，因此，该阵列基板同样包括在本发明的保护范围之内。
参阅图4，是本发明阵列基板第三实施方式的电路结构局部示意图。图4所示的第三实施方式与图2所示的第一实施方式相似，因此与图2相同的元件以相同的标号表示，且不再重复赘述。图4的第三实施方式与图2的第一实施方式不同之处在于，扫描线组GS1还包括沿列方向相邻第三条扫描线G3设置的第四条扫描线G4，第四条扫描线G4对应的数据线为数据线D4。
第四条扫描线G4连接对应的一行像素单元21的薄膜晶体管202的栅极，第四条扫描线G4对应的数据线D4连接一列像素单元21的波密晶体管202的源极，薄膜晶体管202的漏极连接像素电极201。各扫描线G1、G2、G3、G4同时接收扫描信号，以控制扫描线组GS1中的各扫描线G1、G2、G3、G4所对应的各行像素单元21中的薄膜晶体管202同时打开和关闭。
第四条扫描线G4对应的数据线D4沿列方向延伸，中途不进行弯折。与第二条扫描线G2对应的数据线D2类似，第三条扫描线G3对应的数据线D3在沿列方向延伸至第四条扫描线G4对应的像素单元21之前进行弯折延伸，即从第三行的像素单元21与列方向上的相邻像素单元21之间从其所对应的像素单元21一侧弯折延伸至另一侧。在本实施方式中，数据线D2从第二行的像素单元21与第三行的像素单元21之间弯折延伸，数据线D3从第三行的像素单元21和第四行的像素单元21之间弯折延伸。在其它实施方式中，数据线D2从第一行的像素单元21与第二行的像素单元21之间弯折延伸，数据线D3从第二行的像素单元21与第三行的像素单元21之间弯折延伸。或者，数据线D2从第一行的像素单元21与第二行的像素单元21之间弯折延伸，数据线D3从第三行的像素单元21和第四行的像素单元21之间弯折延伸。
参阅图5，是本发明阵列基板第四实施方式的电路结构局部示意图
图5所示的第四实施方式与图4所示的第三实施方式相似，因此与图4相同的元件以相同的标号表示，且不再重复赘述。图5的第四施方式与图4的第三实施方式不同之处在于，数据线组DS1的各数据线D1、D2、D3、D4对应的像素单元21不同。
以前四行第一列的四个像素单元21为例，数据线D4从第一列的像素单元21的右侧沿列方向延伸，并在右侧与第一条扫描线G1和第一行的像素单元21电性连接。数据线D1从第一列的像素单元的左侧沿列方向延伸，并在左侧与第四条扫描线G4和第四行的像素单元21电性连接。数据线D2从左侧沿列方向延伸，并经第三行的像素单元21与第四行的像素单元21之间从第三行的像素单元21左侧弯折延伸至右侧，在弯折时与第三条扫描线G3和第三行的像素单元21电性连接。数据线D3也从左侧沿列方向延伸，并经第三行的像素单元21与第二行的像素单元21之间从第二行的像素单元21左侧弯折延伸至右侧，在弯折时与第二条扫描线G2和第二行的像素单元21电性连接。
与第二实施方式类似，数据线D2和数据线D3弯折延伸时的位置同样具有多种选择，这些选择包括第一行的像素单元21与第二行的像素单元21之间、第二行的像素单元21与第三行的像素单元21之间、以及第三行的像素单元21与第四行的像素单元21之间。数据线D2与数据线D3弯折延伸时的位置视实际情况而定，本发明对此不作限定。
应当理解的是，本发明的第三实施方式和第四实施方式中，数据线组DS1中数据线D1、D2、D3、D4对应不同行的像素单元21，且数据线D2、D3弯折延伸时的方向不同，但是，本领域技术人员容易根据本发明以及本领域公知常识得出将第三实施方式和第四实施方式混合组合的阵列基板，因此，该阵列基板同样包括在本发明的保护范围之内。
此外，在本发明的所有实施方式中，扫描线组GS1只包括三条或四条同时接收扫描信号的扫描线，但是，本发明并不限定扫描线组GS1包含的扫描线的数量，即，扫描线组GS1包括四条以上同时接收扫描线号的扫描线时，仍然可以通过本发明的实施方式得以实现，换言之，本发明的扫描线组GS1可以包括沿行方向延伸的至少三条扫描线，相应的，数据线组DS1也包括至少三条数据线。例如，第三实施方式相对于第一实施方式而言，增加第四条扫描线G4时，数据线D3进行弯折延伸，而在第三实施方式上再增加一条扫描线时，数据线D4进行弯折延伸，以此类推，只要阵列基板上具有足够的空间，理论上，扫描线组GS1包括的扫描线的数量可以无限增加。
本发明还提出一种液晶显示装置，该液晶显示装置包括前述实施方式的阵列基板，液晶显示装置的其它结构请参照现有技术，此处不再赘述。
通过上述方式，本发明的阵列基板及液晶显示装置中，扫描线组在包括在设置至少三条扫描线时，至少部分数据线利用同一列上相邻像素单元之间的位置从像素单元一侧弯折延伸至另一侧，使每一像素单元中的薄膜晶体管与最相邻的数据线连接，能够避免数据线与像素电极干涉，提升充电时间，使分辨率可以达到4000×2000及以上。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (16)

  1. 一种阵列基板，所述阵列基板包括沿行方向和列方向以矩阵形式排列的多个像素单元，每一所述像素单元包括一像素电极以及一薄膜晶体管，所述薄膜晶体管的漏极与所述像素电极连接，其中，阵列基板进一步包括绝缘交叉设置的多个扫描线组以及多个数据线组，每一所述扫描线组包括沿所述行方向延伸的三条扫描线，且每条扫描线连接对应的一行所述像素单元中的所述薄膜晶体管的栅极，每一所述扫描线组中的各扫描线同时接收扫描信号，以控制所述扫描线组中的各扫描线所对应的各行所述像素单元中的所述薄膜晶体管同时打开和关闭，每一所述数据线组分别包括与所述扫描线组中的扫描线数量对应的数据线，同一列的各所述像素单元中的所述薄膜晶体管的源极连接同一所述数据线组中的对应一所述数据线，所述三条扫描线中第一条扫描线和第三条扫描线对应的两条数据线沿所述列方向延伸并配置于同一列的各所述像素单元两侧，其中每一所述数据线组中的对应所述三条扫描线中第二条扫描线的数据线经其所对应的像素单元与所述列方向上的相邻像素单元之间从其所对应的像素单元一侧弯折延伸至另一侧，以使每一所述像素单元中的所述薄膜晶体管与最相邻的所述数据线连接且各所述数据线互不干涉其所对应的像素单元，所述对应所述三条扫描线中第二条扫描线的数据线至少包括顺次连接的第一部分、第二部分和第三部分，其中所述第一部分和所述第三部分分别沿所述列方向延伸并位于其所对应的像素单元的两侧，所述第二部分沿所述行方向延伸并位于其所对应的像素单元与所述列方向上的相邻像素单元之间，进而连接所述第一部分和所述第三部分的相邻端。
  2. 根据权利要求1所述的阵列基板，其中，所述第一条扫描线、第二条扫描线和第三条扫描线短接，并接收所述扫描信号。
  3. 根据权利要求1所述的阵列基板，其中，所述第一条扫描线、第二条扫描线和第三条扫描线各接收一路所述扫描信号。
  4. 根据权利要求1所述的阵列基板，其中，每一所述扫描线组还包括沿所述列方向相邻所述第三条扫描线设置的第四条扫描线，所述第四条扫描线接收所述扫描信号，且所述第四条扫描线对应的数据线沿所述列方向延伸，所述第三条扫描线对应的数据线在沿所述列方向延伸至所述第四条扫描线对应的像素单元之前进行所述弯折延伸，且所述第三条扫描线对应的数据线进行所述弯折延伸时不与所述第二条扫描线对应的数据线交叉。
  5. 一种阵列基板，所述阵列基板包括沿行方向和列方向以矩阵形式排列的多个像素单元，每一所述像素单元包括一像素电极以及一薄膜晶体管，所述薄膜晶体管的漏极与所述像素电极连接，其中，阵列基板进一步包括绝缘交叉设置的多个扫描线组以及多个数据线组，每一所述扫描线组包括沿所述行方向延伸的至少三条扫描线，且每条扫描线连接对应的一行所述像素单元中的所述薄膜晶体管的栅极，每一所述扫描线组中的各扫描线同时接收扫描信号，以控制所述扫描线组中的各扫描线所对应的各行所述像素单元中的所述薄膜晶体管同时打开和关闭，每一所述数据线组分别包括与所述扫描线组中的扫描线数量对应的数据线，同一列的各所述像素单元中的所述薄膜晶体管的源极连接同一所述数据线组中的对应一所述数据线，其中每一所述数据线组中的至少部分所述数据线经其所对应的像素单元与所述列方向上的相邻像素单元之间从其所对应的像素单元一侧弯折延伸至另一侧，以使每一所述像素单元中的所述薄膜晶体管与最相邻的所述数据线连接。
  6. 根据权利要求5所述的阵列基板，其中，所述至少部分数据线至少包括顺次连接的第一部分、第二部分和第三部分，其中所述第一部分和所述第三部分分别沿所述列方向延伸并位于其所对应的像素单元的两侧，所述第二部分沿所述行方向延伸并位于其所对应的像素单元与所述列方向上的相邻像素单元之间，进而连接所述第一部分和所述第三部分的相邻端。
  7. 根据权利要求5所述的阵列基板，其中，每一所述扫描线组扫描线的数量为三条，所述三条扫描线中第一条扫描线和第三条扫描线对应的两条数据线沿所述列方向延伸并配置于同一列的各所述像素单元两侧，所述三条扫描线中第二条扫描线对应的所述数据线进行所述弯折延伸，以使得各所述数据线互不干涉其所对应的像素单元。
  8. 根据权利要求7所述的阵列基板，其中，所述第一条扫描线、第二条扫描线和第三条扫描线短接，并接收所述扫描信号。
  9. 根据权利要求7所述的阵列基板，其中，所述第一条扫描线、第二条扫描线和第三条扫描线各接收一路所述扫描信号。
  10. 根据权利要求7所述的阵列基板，其中，每一所述扫描线组还包括沿所述列方向相邻所述第三条扫描线设置的第四条扫描线，所述第四条扫描线接收所述扫描信号，且所述第四条扫描线对应的数据线沿所述列方向延伸，所述第三条扫描线对应的数据线在沿所述列方向延伸至所述第四条扫描线对应的像素单元之前进行所述弯折延伸，且所述第三条扫描线对应的数据线进行所述弯折延伸时不与所述第二条扫描线对应的数据线交叉。
  11. 一种液晶显示装置，其中，所述液晶显示装置包括阵列基板，所述阵列基板包括沿行方向和列方向以矩阵形式排列的多个像素单元，每一所述像素单元包括一像素电极以及一薄膜晶体管，所述薄膜晶体管的漏极与所述像素电极连接，阵列基板进一步包括绝缘交叉设置的多个扫描线组以及多个数据线组，每一所述扫描线组包括沿所述行方向延伸的至少三条扫描线，且每条扫描线连接对应的一行所述像素单元中的所述薄膜晶体管的栅极，每一所述扫描线组中的各扫描线同时接收扫描信号，以控制所述扫描线组中的各扫描线所对应的各行所述像素单元中的所述薄膜晶体管同时打开和关闭，每一所述数据线组分别包括与所述扫描线组中的扫描线数量对应的数据线，同一列的各所述像素单元中的所述薄膜晶体管的源极连接同一所述数据线组中的对应一所述数据线，其中每一所述数据线组中的至少部分所述数据线经其所对应的像素单元与所述列方向上的相邻像素单元之间从其所对应的像素单元一侧弯折延伸至另一侧，以使每一所述像素单元中的所述薄膜晶体管与最相邻的所述数据线连接。
  12. 根据权利要求11所述的液晶显示装置，其中，所述至少部分数据线至少包括顺次连接的第一部分、第二部分和第三部分，其中所述第一部分和所述第三部分分别沿所述列方向延伸并位于其所对应的像素单元的两侧，所述第二部分沿所述行方向延伸并位于其所对应的像素单元与所述列方向上的相邻像素单元之间，进而连接所述第一部分和所述第三部分的相邻端。
  13. 根据权利要求11所述的液晶显示装置，其中，每一所述扫描线组扫描线的数量为三条，所述三条扫描线中第一条扫描线和第三条扫描线对应的两条数据线沿所述列方向延伸并配置于同一列的各所述像素单元两侧，所述三条扫描线中第二条扫描线对应的所述数据线进行所述弯折延伸，以使得各所述数据线互不干涉其所对应的像素单元。
  14. 根据权利要求13所述的液晶显示装置，其中，所述第一条扫描线、第二条扫描线和第三条扫描线短接，并接收所述扫描信号。
  15. 根据权利要求13所述的液晶显示装置，其中，所述第一条扫描线、第二条扫描线和第三条扫描线各接收一路所述扫描信号。
  16. 根据权利要求13所述的液晶显示装置，其中，每一所述扫描线组还包括沿所述列方向相邻所述第三条扫描线设置的第四条扫描线，所述第四条扫描线接收所述扫描信号，且所述第四条扫描线对应的数据线沿所述列方向延伸，所述第三条扫描线对应的数据线在沿所述列方向延伸至所述第四条扫描线对应的像素单元之前进行所述弯折延伸，且所述第三条扫描线对应的数据线进行所述弯折延伸时不与所述第二条扫描线对应的数据线交叉。
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