WO2014187010A1 - 一种阵列基板及液晶显示面板 - Google Patents

一种阵列基板及液晶显示面板 Download PDF

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Publication number
WO2014187010A1
WO2014187010A1 PCT/CN2013/078205 CN2013078205W WO2014187010A1 WO 2014187010 A1 WO2014187010 A1 WO 2014187010A1 CN 2013078205 W CN2013078205 W CN 2013078205W WO 2014187010 A1 WO2014187010 A1 WO 2014187010A1
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Prior art keywords
switching element
pixel electrode
scan line
pixel
thin film
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PCT/CN2013/078205
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English (en)
French (fr)
Inventor
薛景峰
许哲豪
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深圳市华星光电技术有限公司
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Priority to US13/985,661 priority Critical patent/US20140347261A1/en
Publication of WO2014187010A1 publication Critical patent/WO2014187010A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a liquid crystal display panel.
  • FPR 3D Flexible Patterned Retarder 3 Dimensions, polarized three-dimensional display
  • the 3D display technology mainly adds a polarizing plate to the display screen to separate the image signal into a left eye image signal and a right eye image signal, respectively, to the left and right eyes of the viewer, so that the viewer's left eye and right eye are made.
  • the eye receives two sets of pictures, and then the stereoscopic image is synthesized through the brain, thereby obtaining a stereoscopic display viewing effect.
  • adjacent pixels of the display panel correspond to the left and right eyes of the viewer, respectively, to generate a left eye image signal and a right eye image signal, respectively.
  • the left and right eye images are prone to crosstalk, that is, the image that should be sent to the right eye is viewed by the left eye, causing the 3D images to overlap, affecting the stereoscopic display effect.
  • the BM Black
  • Matrix, black matrix masks the way to reduce crosstalk.
  • a BM region 103 is added between the left-eye pixel 101 and the right-eye pixel 102 to block the crosstalk signal, thereby enabling reduction of binocular signal crosstalk in the 3D display mode.
  • the BM area 103 is added, the area cannot be displayed in the 2D display mode, the aperture ratio in the 2D display mode is greatly reduced, and the brightness in the 2D display mode is greatly reduced.
  • 1G2D In the prior art, the above problem is usually solved by using 1G2D.
  • one pixel is divided into a pixel area 201 and a pixel area 202, a pixel area 201 is driven by a data line Data_N1, and a pixel area 202 is driven by a data line Data_N2.
  • the corresponding data signals are input to the two data lines Data_N1 and Data_N2 to make the pixel area 201 and the pixel area 202 are normally displayed, thereby improving the aperture ratio of the 2D display and passing in the 3D display mode.
  • the data line Data_N2 controls the pixel area to display a black picture to achieve the effect of the BM to mask the crosstalk signal, thereby causing a black matrix between the two pixels, solving the 3D crosstalk problem.
  • each pixel needs two data lines to be driven, and one more data line is added, so that the number of data driving chips is correspondingly increased, which is disadvantageous to cost reduction.
  • the increased data lines also cause the aperture ratio to decrease. .
  • the technical problem to be solved by the present invention is to provide an array substrate and a liquid crystal display panel, which can improve the aperture ratio in the 2D display mode and reduce the crosstalk of the two-eye signals in the 3D display mode, and reduce the number of data driving chips required. In turn, the cost is reduced.
  • the present invention adopts a technical solution to provide an array substrate including a plurality of first scan lines (30), a plurality of second scan lines (40), and a plurality of data lines (50).
  • Each pixel unit (70) includes a first pixel electrode (701), a second pixel electrode (702), a first switching element (703), a second switching element (704), and a third switching element (705), first
  • the pixel electrode (701) and the second pixel electrode (702) are arranged in a column direction, and each of the switching elements includes a control end, an input end, and an output end, a control end (7031) of the first switching element (703) and a second switch
  • the control terminals (7041) of the component (704) are both connected to the first scan line (30),
  • the output end (7053) of the third switching element (705) is connected to the common electrode (60); all the second scan lines (40) are electrically connected to each other at the periphery of the array substrate, the first scan line (30) and the second scan line (40), the first switching element (703), the second switching element (704), and the third switching element (705) are both located between the first pixel electrode (701) and the second pixel electrode (702);
  • the third switching element (705) is controlled to be turned off by the second scan line (40), and a scan signal is input to the first scan line (30) to drive the first switching element (703) and the second switching element ( 704)
  • Conduction, data line (50) passes first The off element (703) and the second switching element (704) respectively input data signals to the first pixel electrode (701) and the second pixel electrode (702) such that the first pixel electrode (701) and the second pixel electrode (702) The image corresponding to the 2D picture is displayed.
  • the third switching element (705) is controlled to be turned on by the second scan line (40), and the scan signal is input to the first scan line (30) to drive the first switch.
  • the element (703) and the second switching element (704) are turned on, and the data line (50) passes through the first switching element (703) and the second switching element (704) to the first pixel electrode (701) and the second pixel electrode, respectively.
  • (702) inputting a data signal such that among the first pixel electrode (701) and the second pixel electrode (702), the pixel electrode connected to the input end of the third switching element (705) displays a black screen, and the other pixel electrode displays Corresponds to the image of the 3D picture.
  • the first switching element (703), the second switching element (704), and the third switching element (705) are thin film transistors, respectively a first thin film transistor, a second thin film transistor, and a third thin film transistor, and the switching element
  • the control end corresponds to the gate of the thin film transistor
  • the input end of the switching element corresponds to the source of the thin film transistor
  • the output end of the switching element corresponds to the drain of the thin film transistor.
  • an array substrate including a plurality of first scan lines (30), a plurality of second scan lines (40), and a plurality of data lines (50).
  • Each pixel unit (70) includes a first pixel electrode (701), a second pixel electrode (702), a first switching element (703), a second switching element (704), and a third switching element (705),
  • a pixel electrode (701) and a second pixel electrode (702) are arranged in a column direction, each switching element includes a control end, an input end, and an output end, a control end (7031) and a second end of the first switching element (703)
  • the control terminals (7041) of the switching element (704) are both connected to the first scan line (30).
  • the output end (7053) of the third switching element (705) is connected to the common electrode (60); wherein, in the 2D display mode, the third switching element (705) is controlled to be turned off by the second scan line (40), for the first
  • the scan line (30) inputs a scan signal to drive the first switching element (703) and the second switching element (704) to be turned on, and the data line (50) passes through the first switching element (703) and the second switching element (704), respectively Inputting a data signal to the first pixel electrode (701) and the second pixel electrode (702) such that both the first pixel electrode (701) and the second pixel electrode (702) display an image corresponding to the 2D picture, in the 3D display mode Through the second scan line (40)
  • the third switching element (705) is turned on, and a scan signal is input to the first scan line (30) to drive the first switching element (703) and the second switching element (704) to be turned on, and the data line (50) passes through the first The switching element (703) and the
  • the second scan lines (40) are electrically connected to each other at the periphery of the array substrate.
  • the first scan line (30), the second scan line (40), the first switching element (703), the second switching element (704), and the third switching element (705) are all located at the first pixel electrode (701). And between the second pixel electrode (702).
  • the first switching element (703), the second switching element (704), and the third switching element (705) are thin film transistors, respectively a first thin film transistor, a second thin film transistor, and a third thin film transistor, and the switching element
  • the control end corresponds to the gate of the thin film transistor
  • the input end of the switching element corresponds to the source of the thin film transistor
  • the output end of the switching element corresponds to the drain of the thin film transistor.
  • a liquid crystal display panel including an array substrate (801), a color filter substrate (802), and an array substrate (801) and a color filter substrate ( a liquid crystal layer (803) between 802);
  • the array substrate (801) includes a plurality of first scan lines (30), a plurality of second scan lines (40), a plurality of data lines (50), and a common electrode (60) And a plurality of rows and columns of pixel units (70), each of the pixel units (70) corresponding to a first scan line (30), a second scan line (40) and a data line (50); each pixel unit ( 70) comprising a first pixel electrode (701), a second pixel electrode (702), a first switching element (703), a second switching element (704), and a third switching element (705), the first pixel electrode (701) And the second pixel electrodes (702) are arranged in the column direction, each of the switching elements includes a control end, an input
  • An output terminal (7053) of the three switching element (705) is connected to the common electrode (60); wherein, in the 2D display mode, the third switching element (705) is controlled to be turned off by the second scan line (40), for the first scan
  • the line (30) inputs a scan signal to drive the first switching element (703) and the second switching element (704) to be turned on, and the data line (50) is respectively passed through the first switching element (703) and the second switching element (704)
  • First pixel electrode (701) and second pixel electrode (70 2) inputting a data signal such that both the first pixel electrode (701) and the second pixel electrode (702) display an image corresponding to the 2D picture, and in the 3D display mode, the third switching element is controlled by the second scan line (40) (705) conducting, inputting a scan signal to the first scan line (30) to drive the first switching element (703) and the second switching element (704) to be turned on, and the data line (50) passing through the first switching element (703) And a second
  • the second scan lines (40) are electrically connected to each other at the periphery of the array substrate.
  • the first scan line (30), the second scan line (40), the first switching element (703), the second switching element (704), and the third switching element (705) are all located at the first pixel electrode (701). And between the second pixel electrode (702).
  • the first switching element (703), the second switching element (704), and the third switching element (705) are thin film transistors, respectively a first thin film transistor, a second thin film transistor, and a third thin film transistor, and the switching element
  • the control end corresponds to the gate of the thin film transistor
  • the input end of the switching element corresponds to the source of the thin film transistor
  • the output end of the switching element corresponds to the drain of the thin film transistor.
  • each pixel unit (70) corresponds to a first scan line (30), a second scan line (40) and a data line (50), as compared with
  • one data line is reduced, and the number of data driving chips can be reduced, and the added second scanning line (40) increases the number of scanning driving chips accordingly, but the price of the scanning driving chip is compared with Data-driven chips are cheaper, so they can reduce production costs to a certain extent.
  • the circuit for driving the scan lines is simpler than the circuit for driving the data lines, and the complexity of the drive circuit can be reduced.
  • the third switching element (705) is controlled to be turned off by the second scan line (40), and the pixel unit is enabled by the combination of the first scan line (30) and the data line (50).
  • the first pixel electrode (701) and the second pixel electrode (702) both normally display a 2D picture, thereby being able to increase the aperture ratio of the 2D display mode, in the 3D display mode, at the first scan line (30) and the data line ( 50) driving the first pixel electrode (701) and the second pixel electrode (702) to work together, and controlling the third switching element (705) to be turned on by the second scan line (40), so that the third switching element is turned on
  • the pixel electrode connected to the input end of (40) is electrically connected to the common electrode (60) such that the voltage difference between the pixel electrode and the common electrode (60) connected to the input end of the third switching element (705) is zero.
  • the pixel electrode connected to the input end of the third switching element (705) is displayed in a black screen, the other pixel electrode is displayed in a normal display 3D picture, and the first pixel electrode (701) and the second pixel electrode (702) are arranged in the column direction.
  • the pixel electrodes displaying the 3D picture in the two pixel units adjacent in the column direction are spaced apart by the pixel electrodes of the display black screen, whereby the 3D binocular signal crosstalk can be reduced.
  • FIG. 1 is a schematic structural view of an array substrate in the prior art
  • FIG. 2 is a schematic structural view of another array substrate in the prior art
  • Figure 3 is an equivalent circuit diagram of the pixel structure of Figure 2;
  • FIG. 4 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • FIG. 5 is an equivalent circuit diagram of a pixel unit of the array substrate of FIG. 4;
  • FIG. 6 is a view showing a display effect of a pixel unit of the array substrate of FIG. 4 in a 3D display mode
  • Fig. 7 is a side view showing an embodiment of a liquid crystal display panel of the present invention.
  • the array substrate includes a plurality of first scan lines 30, a plurality of second scan lines 40, a plurality of data lines 50, a common electrode 60, and a plurality of rows and columns.
  • Pixel unit 70 in an embodiment of the array substrate of the present invention, the array substrate includes a plurality of first scan lines 30, a plurality of second scan lines 40, a plurality of data lines 50, a common electrode 60, and a plurality of rows and columns.
  • Each of the pixel units 70 corresponds to a first scan line 30, a second scan line 40, and a data line 50 to drive the pixel unit 70 to operate through the first scan line 30, the second scan line 40, and the data line 50.
  • the pixel unit 70 includes a first pixel electrode 701, a second pixel electrode 702, a first switching element 703, a second switching element 704, and a third switching element 705.
  • the first pixel electrode 701 and the second pixel electrode 702 are arranged in the column direction, that is, the first pixel electrode 701 in one pixel unit 70 is adjacent to the second pixel electrode 702 in the adjacent previous pixel unit 70, and one pixel unit 70
  • the second pixel electrode 702 is adjacent to the first pixel electrode 701 of the adjacent next pixel unit 70.
  • the first to third switching elements 703, 704, and 705 each include a control terminal, an input terminal, and an output terminal, wherein the control terminal 7031 of the first switching component 703 and the control terminal 7041 of the second switching component 704 are both connected to the first scan line.
  • 30 is connected to control the conduction and disconnection of the first switching element 703 and the second switching element 704 through the first scanning line 30, and the input terminal 7032 of the first switching element 703 and the input terminal 7042 of the second switching element 704 are both
  • the data line 50 is connected to input a data signal through the data line 50.
  • the output end 7033 of the first switching element 703 is connected to the first pixel electrode 701, and the output end 7043 of the second switching element 704 is connected to the second pixel electrode 702.
  • the control terminal 7051 of the third switching element 705 is connected to the second scan line 40 to control the on and off of the third switching element 705 through the second scan line 40, and the input terminal 7052 and the second pixel of the third switching element 705
  • the electrode 702 is connected, and the output end 7053 of the third switching element 705 is connected to the common electrode 60.
  • all the second scan lines 40 are electrically connected to each other at the periphery of the array substrate, that is, at the periphery of the display area corresponding to the array substrate.
  • the first scan line 30, the second scan line 40, and the first to third switching elements 703, 704, and 705 are each disposed between the first pixel electrode 701 and the second pixel electrode 702.
  • the aperture ratio in the 2D display mode can be improved, the binocular signal crosstalk in the 3D display mode can be reduced, and the number required for the data driving chip can be reduced, thereby reducing the production cost.
  • a low level signal is input to all the second scan lines 40, and the low level signal may be about -6V to control the third switching element 705 to be turned off by the second scan line 40, thereby The second pixel electrode 702 and the common electrode 60 are made disconnected.
  • a scan signal is input to the first scan line 30 row by row to drive the first switching element 703 and the second switching element 704 to be turned on, and the data line 50 passes through the first switching element 703 and the second switching element 704 to the first pixel electrode, respectively.
  • the 701 and the second pixel electrode 702 input a data signal required to display the 2D picture, thereby driving the first pixel electrode 701 and the second pixel electrode to display an image corresponding to the 2D picture. Therefore, in the 2D display mode, all the pixel units 70 normally display images corresponding to the 2D screen, and the aperture ratio in the 2D display mode is improved.
  • the adjacent two rows of pixel units 70 respectively display the left eye image and the right eye image corresponding to the 3D picture, and respectively transmit the left eye image and the right eye image to the left and right eyes of the viewer, and watch through
  • the brain of the person synthesizes the left eye image and the right eye image to make the viewer feel the stereoscopic display effect.
  • a high level signal is input to all the second scan lines 40, and the high level signal may be about 27V ⁇ 33V, for example, a high level signal of 29V is input to the second scan line 40 to control the third switching element 705 to be turned on. Thereby, the second pixel electrode 702 and the common electrode 60 are turned on.
  • the scan signal is input to the first scan line 30 row by row to drive the first switching element 703 and the second switching element 704 to be turned on, and the data line 50 passes through the first switching element 703 and the second switching element 704 to the first pixel electrode 701, respectively.
  • the second pixel electrode 702 inputs a data signal required to display a 3D picture.
  • the third switching element 705 is turned on, the second pixel electrode 702 and the common electrode 60 are turned on, so that the potentials of the second pixel electrode 702 and the common electrode 60 are the same, that is, the second pixel electrode 702 and the common electrode 60
  • the voltage difference is zero.
  • the liquid crystal display panel realizes the display principle by causing a liquid crystal display panel to be normally displayed by causing a certain voltage difference between the pixel electrode in the array substrate and the common electrode in the color filter substrate, and When the voltage difference between the pixel electrode in the array substrate and the common electrode in the color filter substrate is zero, the liquid crystal display panel cannot display an image normally, and the display screen is a black screen.
  • the common electrode in the color filter substrate and the common electrode 60 in the array substrate are input with the same voltage signal. Therefore, when the voltage difference between the second pixel electrode 702 and the common electrode 60 of the array substrate is zero, The voltage difference between the two-pixel electrode 702 and the common electrode in the color filter substrate is also zero. Referring to FIG.
  • the second pixel electrode 702 displays a black image
  • the first pixel electrode 701 inputs a data signal at the data line 50.
  • the image corresponding to the 3D picture is normally displayed. Therefore, in the adjacent two rows of pixel units 70 corresponding to the display left eye image and the right eye image, the first pixel electrode 701 of one row of pixel units 70 displays the left eye image corresponding to the 3D picture, and the second pixel electrode 702 is due to the array
  • the common electrode 60 of the substrate is turned on to display a black screen
  • the first pixel electrode of the other row of the pixel unit 70 displays the right eye image corresponding to the 3D picture
  • the second pixel electrode 702 displays the black image, so that the left eye image is displayed in the row of pixel units 70.
  • the second pixel electrode 702 displaying the black screen can block the left eye image from entering the right eye of the viewer, and the right eye image enters the left eye of the viewer, effectively reducing the binocular image signal crosstalk.
  • the first switching element 703, the second switching element 704, and the third switching element 705 are thin film transistors, which are a first thin film transistor, a second thin film transistor, and a third thin film transistor, respectively.
  • the control end of the switching element corresponds to the gate of the thin film transistor
  • the input end of the switching element corresponds to the source of the thin film transistor
  • the output end of the switching element corresponds to the drain of the thin film transistor.
  • the three switching elements 703, 704, and 705 may also be three-terminal control switches such as a triode or a Darlington tube, and are not limited herein.
  • the third switching element 705 is controlled to be turned off by the second scan line 40 in the 2D display mode, so that the second pixel electrode 702 and the common electrode 60 of the array substrate are not turned on, thereby inputting a display 2D picture on the data line 50.
  • both the first pixel electrode 701 and the second pixel electrode 702 can normally display an image corresponding to the 2D picture, thereby effectively increasing the aperture ratio in the 2D display mode.
  • the third switching element 705 is controlled to be turned on by the second scan line 40 in the 3D display mode, so that the second pixel electrode 702 and the common electrode 60 of the array substrate are turned on, thereby inputting a data signal required for displaying a 3D picture on the data line 50.
  • the first pixel electrode 701 normally displays an image corresponding to the 3D picture
  • the second pixel electrode 702 displays a black picture such that the first pixel electrode 701 displaying the left eye image and the first image displaying the right eye image in the adjacent two rows of pixel units 70
  • the pixel electrodes 701 have a black area equivalent to a black matrix, which can effectively prevent crosstalk of both eyes.
  • each pixel unit 70 is driven by using one first scan line 30, one second scan line 40, and one data line 50, thereby reducing the usage of the data lines, thereby reducing the use of the data driving chip.
  • the amount of the second scan line 40 added increases the usage of the scan driver chip accordingly.
  • the price of the scan driver chip is cheaper than that of the data drive chip, which is advantageous for reducing the production cost and driving the scan.
  • the drive circuit of the line is simpler than the drive circuit for driving the data line, and can also reduce the complexity of the drive circuit.
  • the length of the data line is longer than the scan line, and the use of the data line can be reduced to a certain extent to increase the aperture ratio.
  • the input end of the third switching element may also be connected to the first pixel electrode, so that when the third switching element is turned on by the second scan line in the 3D display mode, the first pixel electrode Electrically conducting with the common electrode such that the voltage difference between the first pixel electrode and the common electrode is zero, so that the first pixel electrode displays a black image when the data line inputs a data signal required for displaying the 3D picture, and the second pixel electrode
  • the image corresponding to the 3D picture is normally displayed, and the first pixel electrode displaying the black picture is equivalent to the black matrix, and the double-eye signal crosstalk in the 3D display mode can also be reduced.
  • the liquid crystal display panel includes an array substrate 801, a color filter substrate 802, and a liquid crystal layer 803 between the array substrate 801 and the color filter substrate 802, wherein the array substrate 801 is the array substrate according to any of the above embodiments.

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Abstract

一种阵列基板及液晶显示面板，在阵列基板中，每个像素单元（70）对应一条第一扫描线（30）、一条第二扫描线（40）以及一条数据线（50），通过第一扫描线（30）控制第一开关元件（703）和第二开关元件（704）导通和断开，数据线（50）分别通过第一开关元件（703）和第二开关元件（704）与第一像素电极（701）和第二像素电极（702）连接，通过第二扫描线（40）控制第三开关元件（705）的导通和断开，第三开关元件（705）的输入端与任一像素电极连接，第三开关元件（705）的输出端与公共电极（60）连接。通过这种方式，能够提高2D显示模式下的开口率和减小3D显示模式下的双眼信号串扰的同时，减少数据驱动芯片所需的数量，进而降低成本。

Description

一种阵列基板及液晶显示面板
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板及液晶显示面板。
【背景技术】
FPR 3D（Film-type Patterned Retarder 3 Dimensions，偏光式三维显示）显示面板具有色彩损失小、可视角度大和闪烁感小等优点，是目前3D显示器发展的主流方向。FPR 3D显示技术主要是通过在显示屏幕上增加一偏光板，以将图像信号分离为左眼图像信号和右眼图像信号分别送至观看者的左眼和右眼，使得观看者的左眼和右眼接收两组画面，再经过大脑合成立体影像，进而获得立体显示观看效果。
FPR 3D显示技术中，显示面板的相邻两行像素分别对应观看者的左眼和右眼，以分别产生左眼图像信号和右眼图像信号。在3D显示模式下，当观看者处于较大视角观看时，容易出现左右眼图像相互串扰的现象，即本应该送到右眼的图像被左眼观看到了，造成3D影像重叠，影响立体显示效果。为了防止左右眼接收到的信号相互串扰，如图1所示，相邻两行像素间采取BM（Black Matrix，黑矩阵）遮蔽的方式降低串扰。在左眼像素101和右眼像素102之间增加BM区域103，用以阻挡串扰信号，从而能够降低3D显示模式下的双眼信号串扰。但是，由于增加了BM区域103，在2D显示模式下该区域不能显示，大大降低了2D显示模式下的开口率，导致2D显示模式下的亮度大大降低。
现有技术中，通常是采用1G2D的方式解决上述问题。参阅图2和图3，1G2D的技术方案中，将一个像素划分为像素区一201和像素区二202，像素区一201使用数据线Data_N1驱动，像素区二202使用数据线Data_N2驱动。在2D显示模式下对两条数据线Data_N1和Data_N2均输入相应的数据信号以使得像素区一201和像素区二202都正常显示，由此能够提高2D显示的开口率，在3D显示模式下通过数据线Data_N2控制像素区一显示黑画面以达到BM的效果，以遮蔽串扰信号，由此使得两个像素间存在黑色矩阵，解决了3D串扰问题。
但是，采用上述方案，每个像素需要两条数据线驱动，增加多了一条数据线，使得数据驱动芯片的数量也相应增加，不利于成本降低，其次，增加的数据线也会导致开口率降低。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及液晶显示面板，能够提高2D显示模式下的开口率和减小3D显示模式下的双眼信号串扰的同时，减少数据驱动芯片所需的数量，进而降低成本。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包括多条第一扫描线（30）、多条第二扫描线（40）、多条数据线（50）、公共电极（60）以及多个行列排列的像素单元（70），每个像素单元（70）对应一条第一扫描线（30）、一条第二扫描线（40）以及一条数据线（50）；每个像素单元（70）包括第一像素电极（701）、第二像素电极（702）、第一开关元件（703）、第二开关元件（704）以及第三开关元件（705），第一像素电极（701）和第二像素电极（702）沿列方向排列，每个开关元件均包括控制端、输入端以及输出端，第一开关元件（703）的控制端（7031）和第二开关元件（704）的控制端（7041）均与第一扫描线（30）连接，第一开关元件（703）的输入端（7032）和第二开关元件（704）的输入端（7042）均与数据线（50）连接，第一开关元件（703）的输出端（7033）与第一像素电极（701）连接，第二开关元件（704）的输出端（7043）与第二像素电极（702）连接，第三开关元件（705）的控制端（7051）与第二扫描线（40）连接，第三开关元件（705）的输入端（7052）连接第一像素电极（701）和第二像素电极（702）中的一个，第三开关元件（705）的输出端（7053）连接公共电极（60）；所有第二扫描线（40）在阵列基板的周边相互电性连接，第一扫描线（30）、第二扫描线（40）、第一开关元件（703）、第二开关元件（704）以及第三开关元件（705）均位于第一像素电极（701）和第二像素电极（702）之间；其中，在2D显示模式下，通过第二扫描线（40）控制第三开关元件（705）断开，对第一扫描线（30）输入扫描信号以驱动第一开关元件（703）和第二开关元件（704）导通，数据线（50）通过第一开关元件（703）和第二开关元件（704）分别对第一像素电极（701）和第二像素电极（702）输入数据信号，以使第一像素电极（701）和第二像素电极（702）均显示对应2D画面的图像，在3D显示模式下，通过第二扫描线（40）控制第三开关元件（705）导通，对第一扫描线（30）输入扫描信号以驱动第一开关元件（703）和第二开关元件（704）导通，数据线（50）通过第一开关元件（703）和第二开关元件（704）分别对第一像素电极（701）和第二像素电极（702）输入数据信号，以使得第一像素电极（701）和第二像素电极（702）中，与第三开关元件（705）的输入端连接的像素电极显示黑画面，另一像素电极显示对应3D画面的图像。
其中，第一开关元件（703）、第二开关元件（704）以及第三开关元件（705）均为薄膜晶体管，分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，开关元件的控制端对应薄膜晶体管的栅极，开关元件的输入端对应薄膜晶体管的源极，开关元件的输出端对应薄膜晶体管的漏极。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括多条第一扫描线（30）、多条第二扫描线（40）、多条数据线（50）、公共电极（60）以及多个行列排列的像素单元（70），每个像素单元（70）对应一条第一扫描线（30）、一条第二扫描线（40）以及一条数据线（50）；每个像素单元（70）包括第一像素电极（701）、第二像素电极（702）、第一开关元件（703）、第二开关元件（704）以及第三开关元件（705），第一像素电极（701）和第二像素电极（702）沿列方向排列，每个开关元件均包括控制端、输入端以及输出端，第一开关元件（703）的控制端（7031）和第二开关元件（704）的控制端（7041）均与第一扫描线（30）连接，第一开关元件（703）的输入端（7032）和第二开关元件（704）的输入端（7042）均与数据线（50）连接，第一开关元件（703）的输出端（7033）与第一像素电极（701）连接，第二开关元件（704）的输出端（7043）与第二像素电极（702）连接，第三开关元件（705）的控制端（7051）与第二扫描线（40）连接，第三开关元件（705）的输入端（7052）连接第一像素电极（701）和第二像素电极（702）中的一个，第三开关元件（705）的输出端（7053）连接公共电极（60）；其中，在2D显示模式下，通过第二扫描线（40）控制第三开关元件（705）断开，对第一扫描线（30）输入扫描信号以驱动第一开关元件（703）和第二开关元件（704）导通，数据线（50）通过第一开关元件（703）和第二开关元件（704）分别对第一像素电极（701）和第二像素电极（702）输入数据信号，以使第一像素电极（701）和第二像素电极（702）均显示对应2D画面的图像，在3D显示模式下，通过第二扫描线（40）控制第三开关元件（705）导通，对第一扫描线（30）输入扫描信号以驱动第一开关元件（703）和第二开关元件（704）导通，数据线（50）通过第一开关元件（703）和第二开关元件（704）分别对第一像素电极（701）和第二像素电极（702）输入数据信号，以使得第一像素电极（701）和第二像素电极（702）中，与第三开关元件（705）的输入端连接的像素电极显示黑画面，另一像素电极显示对应3D画面的图像。
其中，所有第二扫描线（40）在阵列基板的周边相互电性连接。
其中，第一扫描线（30）、第二扫描线（40）、第一开关元件（703）、第二开关元件（704）以及第三开关元件（705）均位于第一像素电极（701）和第二像素电极（702）之间。
其中，第一开关元件（703）、第二开关元件（704）以及第三开关元件（705）均为薄膜晶体管，分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，开关元件的控制端对应薄膜晶体管的栅极，开关元件的输入端对应薄膜晶体管的源极，开关元件的输出端对应薄膜晶体管的漏极。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板，包括阵列基板（801）、彩色滤光基板（802）以及位于阵列基板（801）和彩色滤光基板（802）之间的液晶层（803）；阵列基板（801）包括多条第一扫描线（30）、多条第二扫描线（40）、多条数据线（50）、公共电极（60）以及多个行列排列的像素单元（70），每个像素单元（70）对应一条第一扫描线（30）、一条第二扫描线（40）以及一条数据线（50）；每个像素单元（70）包括第一像素电极（701）、第二像素电极（702）、第一开关元件（703）、第二开关元件（704）以及第三开关元件（705），第一像素电极（701）和第二像素电极（702）沿列方向排列，每个开关元件均包括控制端、输入端以及输出端，第一开关元件（703）的控制端（7031）和第二开关元件（704）的控制端（7041）均与第一扫描线（30）连接，第一开关元件（703）的输入端（7032）和第二开关元件（704）的输入端（7042）均与数据线（50）连接，第一开关元件（703）的输出端（7033）与第一像素电极（701）连接，第二开关元件（704）的输出端（7043）与第二像素电极（702）连接，第三开关元件（705）的控制端（7051）与第二扫描线（40）连接，第三开关元件（705）的输入端（7052）连接第一像素电极（701）和第二像素电极（702）中的一个，第三开关元件（705）的输出端（7053）连接公共电极（60）；其中，在2D显示模式下，通过第二扫描线（40）控制第三开关元件（705）断开，对第一扫描线（30）输入扫描信号以驱动第一开关元件（703）和第二开关元件（704）导通，数据线（50）通过第一开关元件（703）和第二开关元件（704）分别对第一像素电极（701）和第二像素电极（702）输入数据信号，以使第一像素电极（701）和第二像素电极（702）均显示对应2D画面的图像，在3D显示模式下，通过第二扫描线（40）控制第三开关元件（705）导通，对第一扫描线（30）输入扫描信号以驱动第一开关元件（703）和第二开关元件（704）导通，数据线（50）通过第一开关元件（703）和第二开关元件（704）分别对第一像素电极（701）和第二像素电极（702）输入数据信号，以使得第一像素电极（701）和第二像素电极（702）中，与第三开关元件（705）的输入端连接的像素电极显示黑画面，另一像素电极显示对应3D画面的图像。
其中，所有第二扫描线（40）在阵列基板的周边相互电性连接。
其中，第一扫描线（30）、第二扫描线（40）、第一开关元件（703）、第二开关元件（704）以及第三开关元件（705）均位于第一像素电极（701）和第二像素电极（702）之间。
其中，第一开关元件（703）、第二开关元件（704）以及第三开关元件（705）均为薄膜晶体管，分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，开关元件的控制端对应薄膜晶体管的栅极，开关元件的输入端对应薄膜晶体管的源极，开关元件的输出端对应薄膜晶体管的漏极。
本发明的有益效果是：本发明的阵列基板中，每个像素单元（70）对应一条第一扫描线（30）、一条第二扫描线（40）以及一条数据线（50），相较于现有技术而言，减少了一条数据线，能够减少数据驱动芯片的数量，而所增加的第二扫描线（40）虽然会相应增加扫描驱动芯片的数量，然而扫描驱动芯片的价格相较于数据驱动芯片的价格更为便宜，因此能够在一定程度上降低生产成本，此外驱动扫描线的电路比驱动数据线的电路更为简单，也能够降低驱动电路的复杂性。此外，在2D显示模式下，通过第二扫描线（40）控制第三开关元件（705）断开，在第一扫描线（30）和数据线（50）的共同作用下使像素单元中的第一像素电极（701）和第二像素电极（702）均正常显示2D画面，由此能够提高2D显示模式的开口率，在3D显示模式下，在第一扫描线（30）和数据线（50）的共同作用下驱动第一像素电极（701）和第二像素电极（702）工作，而通过第二扫描线（40）控制第三开关元件（705）导通，使得与第三开关元件（40）的输入端连接的像素电极和公共电极（60）电性连接，从而使得与第三开关元件（705）的输入端连接的像素电极和公共电极（60）的压差为零，进而使得与第三开关元件（705）的输入端连接的像素电极显示黑画面，另一像素电极显示正常显示3D画面，而第一像素电极（701）和第二像素电极（702）沿列方向排列，由此使得沿列方向相邻的两个像素单元中显示3D画面的像素电极被该显示黑画面的像素电极所间隔，由此能够降低3D双眼信号串扰。
【附图说明】
图1是现有技术中一种阵列基板的结构示意图；
图2是现有技术中另一种阵列基板的结构示意图；
图3是图2中像素结构的等效电路图；
图4是本发明阵列基板一实施方式的结构示意图；
图5是图4中阵列基板的像素单元的等效电路图；
图6是图4中阵列基板的像素单元在3D显示模式下的显示效果图；
图7是本发明液晶显示面板一实施方式的侧视图。
【具体实施方式】
下面将结合附图和实施方式对本发明进行详细说明。
参阅图4和图5，本发明阵列基板的一实施方式中，阵列基板包括多条第一扫描线30、多条第二扫描线40、多条数据线50、公共电极60以及多个行列排列的像素单元70。
其中，每个像素单元70对应一条第一扫描线30、一条第二扫描线40以及一条数据线50，以通过第一扫描线30、第二扫描线40以及数据线50驱动像素单元70工作。像素单元70包括第一像素电极701、第二像素电极702、第一开关元件703、第二开关元件704以及第三开关元件705。第一像素电极701和第二像素电极702沿列方向排列，即一像素单元70中的第一像素电极701与相邻上一像素单元70中的第二像素电极702相邻，一像素单元70中的第二像素电极702与相邻下一像素单元70中的第一像素电极701相邻。第一至第三开关元件703、704、705均包括控制端、输入端以及输出端，其中，第一开关元件703的控制端7031和第二开关元件704的控制端7041均与第一扫描线30连接，以通过第一扫描线30控制第一开关元件703和第二开关元件704的导通和断开，第一开关元件703的输入端7032和第二开关元件704的输入端7042均与数据线50连接，以通过数据线50输入数据信号，第一开关元件703的输出端7033与第一像素电极701连接，第二开关元件704的输出端7043与第二像素电极702连接。第三开关元件705的控制端7051与第二扫描线40连接，以通过第二扫描线40控制第三开关元件705的导通和断开，第三开关元件705的输入端7052与第二像素电极702连接，第三开关元件705的输出端7053与公共电极60连接。
进一步地，在阵列基板的周边，即在阵列基板对应的显示区域的外围，所有第二扫描线40相互电性连接在一起。第一扫描线30、第二扫描线40以及第一至第三开关元件703、704、705均设置于第一像素电极701和第二像素电极702之间。
通过本实施方式的阵列基板，能够提高2D显示模式下的开口率，减小3D显示模式下的双眼信号串扰，同时能够减少数据驱动芯片所需的数量，进而降低生产成本。
具体地，在2D显示模式下，对所有第二扫描线40输入低电平信号，该低电平信号可以是-6V左右，以通过第二扫描线40控制第三开关元件705断开，从而使得第二像素电极702和公共电极60不连通。然后逐行对第一扫描线30输入扫描信号，以驱动第一开关元件703和第二开关元件704导通，数据线50分别通过第一开关元件703和第二开关元件704向第一像素电极701和第二像素电极702输入显示2D画面所需的数据信号，进而驱动第一像素电极701和第二像素电极显示对应2D画面的图像。从而在2D显示模式下，所有的像素单元70均正常显示对应2D画面的图像，提高了2D显示模式下的开口率。
在3D显示模式下，相邻两行像素单元70分别显示对应3D画面的左眼图像和右眼图像，将左眼图像和右眼图像分别传送至观看者的左眼和右眼，并通过观看者的大脑对左眼图像和右眼图像进行合成以使观看者感受到立体显示效果。对所有第二扫描线40输入高电平信号，该高电平信号可以是27V~33V左右，例如对第二扫描线40输入29V的高电平信号，以控制第三开关元件705导通，从而使得第二像素电极702和公共电极60导通。逐行对第一扫描线30输入扫描信号，以驱动第一开关元件703和第二开关元件704导通，数据线50分别通过第一开关元件703和第二开关元件704对第一像素电极701和第二像素电极702输入显示3D画面所需的数据信号。但是，由于第三开关元件705导通，使得第二像素电极702和公共电极60导通，从而使得第二像素电极702和公共电极60的电位相同，即第二像素电极702和公共电极60的电压差为零。在液晶显示技术中，液晶显示面板实现显示的原理是通过使阵列基板中的像素电极和彩色滤光基板中的公共电极之间存在一定的电压差，从而使液晶显示面板能够正常显示，而当阵列基板中的像素电极和彩色滤光基板中的公共电极之间的电压差为零时，液晶显示面板无法正常显示图像，显示画面为黑画面。而彩色滤光基板中的公共电极和阵列基板中的公共电极60所输入的电压信号相同，因此，当第二像素电极702与阵列基板的公共电极60之间的电压差为零时，使得第二像素电极702和彩色滤光基板中的公共电极之间的电压差也为零，参阅图6，从而使得第二像素电极702显示黑画面，第一像素电极701则在数据线50输入数据信号时正常显示对应3D画面的图像。因此，在对应显示左眼图像和右眼图像的相邻两行像素单元70中，其中一行像素单元70的第一像素电极701显示对应3D画面的左眼图像，第二像素电极702由于与阵列基板的公共电极60导通而显示黑画面，另一行像素单元70的第一像素电极显示对应3D画面的右眼图像，第二像素电极702显示黑画面，使得一行像素单元70中显示左眼图像的第一像素电极701和相邻另一行像素单元70中显示右眼图像的第一像素电极701之间存在一黑色区域，即显示黑画面的第二像素电极702，等效于黑色矩阵，从而通过显示黑画面的第二像素电极702能够阻挡左眼图像进入观看者的右眼，右眼图像进入观看者的左眼，有效降低双眼图像信号串扰。
本实施方式中，第一开关元件703、第二开关元件704以及第三开关元件705均为薄膜晶体管，分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管。其中，开关元件的控制端对应为薄膜晶体管的栅极，开关元件的输入端对应为薄膜晶体管的源极，开关元件的输出端对应为薄膜晶体管的漏极。在其他实施方式中，三个开关元件703、704、705也可以是三极管、达林顿管等三端式控制开关，此处不进行限制。
通过上述方式，在2D显示模式下通过第二扫描线40控制第三开关元件705断开，使得第二像素电极702和阵列基板的公共电极60不导通，从而在数据线50输入显示2D画面所需的数据信号时第一像素电极701和第二像素电极702均能正常显示对应2D画面的图像，有效提高2D显示模式下的开口率。在3D显示模式下通过第二扫描线40控制第三开关元件705导通，使得第二像素电极702和阵列基板的公共电极60导通，从而在数据线50输入显示3D画面所需的数据信号时第一像素电极701正常显示对应3D画面的图像，第二像素电极702显示黑画面，使得相邻两行像素单元70中显示左眼图像的第一像素电极701和显示右眼图像的第一像素电极701之间具有等效于黑色矩阵的黑色区域，能够有效防止双眼信号串扰。
此外，本实施方式中，每个像素单元70对应使用一条第一扫描线30、一条第二扫描线40和一条数据线50驱动，减少了数据线的使用量，从而减少了数据驱动芯片的使用量，而所增加的一条第二扫描线40虽然会相应增加扫描驱动芯片的使用量，然而扫描驱动芯片的价格相较于数据驱动芯片的价格更为便宜，有利于降低生产成本，且驱动扫描线的驱动电路相较于驱动数据线的驱动电路更为简单，也能够降低驱动电路的复杂性。并且，数据线的长度比扫描线更长，减少数据线的使用量在一定程度上也能够提高开口率。
当然，在其他的实施方式中，第三开关元件的输入端也可以连接第一像素电极，从而在3D显示模式下时通过第二扫描线控制第三开关元件的导通时，第一像素电极与公共电极电性导通，使得第一像素电极和公共电极之间的电压差为零，从而在数据线输入显示3D画面所需的数据信号时第一像素电极显示黑画面，第二像素电极正常显示对应3D画面的图像，而显示黑画面的第一像素电极等效于黑色矩阵，同样能够减小3D显示模式下的双眼信号串扰。
参阅图7，本发明液晶显示面板的一实施方式中，液晶显示面板包括阵列基板801、彩色滤光基板802以及位于阵列基板801和彩色滤光基板802之间的液晶层803，其中，阵列基板801为上述任一实施方式中的阵列基板。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (10)

  1. 一种阵列基板，其中，包括多条第一扫描线（30）、多条第二扫描线（40）、多条数据线（50）、公共电极（60）以及多个行列排列的像素单元（70），每个所述像素单元（70）对应一条第一扫描线（30）、一条第二扫描线（40）以及一条数据线（50）；
    每个所述像素单元（70）包括第一像素电极（701）、第二像素电极（702）、第一开关元件（703）、第二开关元件（704）以及第三开关元件（705），所述第一像素电极（701）和第二像素电极（702）沿列方向排列，每个所述开关元件均包括控制端、输入端以及输出端，所述第一开关元件（703）的控制端（7031）和第二开关元件（704）的控制端（7041）均与所述第一扫描线（30）连接，所述第一开关元件（703）的输入端（7032）和第二开关元件（704）的输入端（7042）均与所述数据线（50）连接，所述第一开关元件（703）的输出端（7033）与所述第一像素电极（701）连接，所述第二开关元件（704）的输出端（7043）与所述第二像素电极（702）连接，所述第三开关元件（705）的控制端（7051）与所述第二扫描线（40）连接，所述第三开关元件（705）的输入端（7052）连接所述第一像素电极（701）和第二像素电极（702）中的一个，所述第三开关元件（705）的输出端（7053）连接所述公共电极（60）；
    所有所述第二扫描线（40）在所述阵列基板的周边相互电性连接，所述第一扫描线（30）、第二扫描线（40）、第一开关元件（703）、第二开关元件（704）以及第三开关元件（705）均位于所述第一像素电极（701）和第二像素电极（702）之间；
    其中，在2D显示模式下，通过所述第二扫描线（40）控制第三开关元件（705）断开，对所述第一扫描线（30）输入扫描信号以驱动所述第一开关元件（703）和第二开关元件（704）导通，所述数据线（50）通过所述第一开关元件（703）和第二开关元件（704）分别对所述第一像素电极（701）和第二像素电极（702）输入数据信号，以使所述第一像素电极（701）和第二像素电极（702）均显示对应2D画面的图像，在3D显示模式下，通过所述第二扫描线（40）控制第三开关元件（705）导通，对所述第一扫描线（30）输入扫描信号以驱动所述第一开关元件（703）和第二开关元件（704）导通，所述数据线（50）通过所述第一开关元件（703）和第二开关元件（704）分别对所述第一像素电极（701）和第二像素电极（702）输入数据信号，以使得第一像素电极（701）和第二像素电极（702）中，与所述第三开关元件（705）的输入端连接的像素电极显示黑画面，另一像素电极显示对应3D画面的图像。
  2. 根据权利要求1所述的阵列基板，其中，
    所述第一开关元件（703）、第二开关元件（704）以及第三开关元件（705）均为薄膜晶体管，分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述开关元件的控制端对应所述薄膜晶体管的栅极，所述开关元件的输入端对应所述薄膜晶体管的源极，所述开关元件的输出端对应所述薄膜晶体管的漏极。
  3. 一种阵列基板，其中，包括多条第一扫描线（30）、多条第二扫描线（40）、多条数据线（50）、公共电极（60）以及多个行列排列的像素单元（70），每个所述像素单元（70）对应一条第一扫描线（30）、一条第二扫描线（40）以及一条数据线（50）；
    每个所述像素单元（70）包括第一像素电极（701）、第二像素电极（702）、第一开关元件（703）、第二开关元件（704）以及第三开关元件（705），所述第一像素电极（701）和第二像素电极（702）沿列方向排列，每个所述开关元件均包括控制端、输入端以及输出端，所述第一开关元件（703）的控制端（7031）和第二开关元件（704）的控制端（7041）均与所述第一扫描线（30）连接，所述第一开关元件（703）的输入端（7032）和第二开关元件（704）的输入端（7042）均与所述数据线（50）连接，所述第一开关元件（703）的输出端（7033）与所述第一像素电极（701）连接，所述第二开关元件（704）的输出端（7043）与所述第二像素电极（702）连接，所述第三开关元件（705）的控制端（7051）与所述第二扫描线（40）连接，所述第三开关元件（705）的输入端（7052）连接所述第一像素电极（701）和第二像素电极（702）中的一个，所述第三开关元件（705）的输出端（7053）连接所述公共电极（60）；
    其中，在2D显示模式下，通过所述第二扫描线（40）控制第三开关元件（705）断开，对所述第一扫描线（30）输入扫描信号以驱动所述第一开关元件（703）和第二开关元件（704）导通，所述数据线（50）通过所述第一开关元件（703）和第二开关元件（704）分别对所述第一像素电极（701）和第二像素电极（702）输入数据信号，以使所述第一像素电极（701）和第二像素电极（702）均显示对应2D画面的图像，在3D显示模式下，通过所述第二扫描线（40）控制第三开关元件（705）导通，对所述第一扫描线（30）输入扫描信号以驱动所述第一开关元件（703）和第二开关元件（704）导通，所述数据线（50）通过所述第一开关元件（703）和第二开关元件（704）分别对所述第一像素电极（701）和第二像素电极（702）输入数据信号，以使得第一像素电极（701）和第二像素电极（702）中，与所述第三开关元件（705）的输入端连接的像素电极显示黑画面，另一像素电极显示对应3D画面的图像。
  4. 根据权利要求3所述的阵列基板，其中，
    所有所述第二扫描线（40）在所述阵列基板的周边相互电性连接。
  5. 根据权利要求3所述的阵列基板，其中，
    所述第一扫描线（30）、第二扫描线（40）、第一开关元件（703）、第二开关元件（704）以及第三开关元件（705）均位于所述第一像素电极（701）和第二像素电极（702）之间。
  6. 根据权利要求3所述的阵列基板，其中，
    所述第一开关元件（703）、第二开关元件（704）以及第三开关元件（705）均为薄膜晶体管，分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述开关元件的控制端对应所述薄膜晶体管的栅极，所述开关元件的输入端对应所述薄膜晶体管的源极，所述开关元件的输出端对应所述薄膜晶体管的漏极。
  7. 一种液晶显示面板，其中，包括阵列基板（801）、彩色滤光基板（802）以及位于阵列基板（801）和彩色滤光基板（802）之间的液晶层（803）；
    所述阵列基板（801）包括多条第一扫描线（30）、多条第二扫描线（40）、多条数据线（50）、公共电极（60）以及多个行列排列的像素单元（70），每个所述像素单元（70）对应一条第一扫描线（30）、一条第二扫描线（40）以及一条数据线（50）；
    每个所述像素单元（70）包括第一像素电极（701）、第二像素电极（702）、第一开关元件（703）、第二开关元件（704）以及第三开关元件（705），所述第一像素电极（701）和第二像素电极（702）沿列方向排列，每个所述开关元件均包括控制端、输入端以及输出端，所述第一开关元件（703）的控制端（7031）和第二开关元件（704）的控制端（7041）均与所述第一扫描线（30）连接，所述第一开关元件（703）的输入端（7032）和第二开关元件（704）的输入端（7042）均与所述数据线（50）连接，所述第一开关元件（703）的输出端（7033）与所述第一像素电极（701）连接，所述第二开关元件（704）的输出端（7043）与所述第二像素电极（702）连接，所述第三开关元件（705）的控制端（7051）与所述第二扫描线（40）连接，所述第三开关元件（705）的输入端（7052）连接所述第一像素电极（701）和第二像素电极（702）中的一个，所述第三开关元件（705）的输出端（7053）连接所述公共电极（60）；
    其中，在2D显示模式下，通过所述第二扫描线（40）控制第三开关元件（705）断开，对所述第一扫描线（30）输入扫描信号以驱动所述第一开关元件（703）和第二开关元件（704）导通，所述数据线（50）通过所述第一开关元件（703）和第二开关元件（704）分别对所述第一像素电极（701）和第二像素电极（702）输入数据信号，以使所述第一像素电极（701）和第二像素电极（702）均显示对应2D画面的图像，在3D显示模式下，通过所述第二扫描线（40）控制第三开关元件（705）导通，对所述第一扫描线（30）输入扫描信号以驱动所述第一开关元件（703）和第二开关元件（704）导通，所述数据线（50）通过所述第一开关元件（703）和第二开关元件（704）分别对所述第一像素电极（701）和第二像素电极（702）输入数据信号，以使得第一像素电极（701）和第二像素电极（702）中，与所述第三开关元件（705）的输入端连接的像素电极显示黑画面，另一像素电极显示对应3D画面的图像。
  8. 根据权利要求7所述的液晶显示面板，其中，
    所有所述第二扫描线（40）在所述阵列基板的周边相互电性连接。
  9. 根据权利要求7所述的液晶显示面板，其中，
    所述第一扫描线（30）、第二扫描线（40）、第一开关元件（703）、第二开关元件（704）以及第三开关元件（705）均位于所述第一像素电极（701）和第二像素电极（702）之间。
  10. 根据权利要求7所述的液晶显示面板，其中，
    所述第一开关元件（703）、第二开关元件（704）以及第三开关元件（705）均为薄膜晶体管，分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述开关元件的控制端对应所述薄膜晶体管的栅极，所述开关元件的输入端对应所述薄膜晶体管的源极，所述开关元件的输出端对应所述薄膜晶体管的漏极。
PCT/CN2013/078205 2013-05-24 2013-06-27 一种阵列基板及液晶显示面板 WO2014187010A1 (zh)

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CN103472644B (zh) * 2013-09-25 2015-11-25 深圳市华星光电技术有限公司 一种阵列基板及液晶显示面板
KR102052317B1 (ko) * 2013-11-26 2019-12-05 엘지디스플레이 주식회사 유기발광표시장치 및 그 구동 방법
CN103728752B (zh) * 2013-12-30 2016-03-30 深圳市华星光电技术有限公司 改善显示3d影像发生闪烁的液晶显示器
CN105572980A (zh) * 2015-12-18 2016-05-11 武汉华星光电技术有限公司 液晶面板及其像素结构
CN106782390A (zh) * 2016-12-30 2017-05-31 深圳市华星光电技术有限公司 用于驱动显示面板的方法、显示面板及装置
CN107301847B (zh) * 2017-06-29 2018-08-28 惠科股份有限公司 一种显示面板的驱动方法、驱动装置及显示装置
CN107144994B (zh) * 2017-06-29 2018-10-23 惠科股份有限公司 一种显示面板的驱动方法、驱动装置及显示装置
CN107589610B (zh) * 2017-09-29 2020-07-14 上海天马微电子有限公司 液晶显示面板与显示装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102156370A (zh) * 2010-11-22 2011-08-17 友达光电股份有限公司 像素阵列基板以及显示面板
CN102193260A (zh) * 2010-03-17 2011-09-21 乐金显示有限公司 图像显示装置
CN102385201A (zh) * 2011-04-13 2012-03-21 友达光电股份有限公司 画素数组、画素结构及画素结构的驱动方法
CN102650781A (zh) * 2011-10-18 2012-08-29 京东方科技集团股份有限公司 用于立体显示的像素结构及其控制方法
CN103076702A (zh) * 2011-10-26 2013-05-01 乐金显示有限公司 立体图像显示器

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100983716B1 (ko) * 2006-06-30 2010-09-24 엘지디스플레이 주식회사 액정표시장치 및 그 제조방법
JP5657286B2 (ja) * 2010-06-25 2015-01-21 株式会社ジャパンディスプレイ 液晶表示装置
TWI450007B (zh) * 2011-09-15 2014-08-21 Au Optronics Corp 畫素結構
CN203275841U (zh) * 2013-05-24 2013-11-06 深圳市华星光电技术有限公司 一种阵列基板及液晶显示面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102193260A (zh) * 2010-03-17 2011-09-21 乐金显示有限公司 图像显示装置
CN102156370A (zh) * 2010-11-22 2011-08-17 友达光电股份有限公司 像素阵列基板以及显示面板
CN102385201A (zh) * 2011-04-13 2012-03-21 友达光电股份有限公司 画素数组、画素结构及画素结构的驱动方法
CN102650781A (zh) * 2011-10-18 2012-08-29 京东方科技集团股份有限公司 用于立体显示的像素结构及其控制方法
CN103076702A (zh) * 2011-10-26 2013-05-01 乐金显示有限公司 立体图像显示器

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