WO2015006995A1 - 一种阵列基板及液晶显示面板 - Google Patents

一种阵列基板及液晶显示面板 Download PDF

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Publication number
WO2015006995A1
WO2015006995A1 PCT/CN2013/080075 CN2013080075W WO2015006995A1 WO 2015006995 A1 WO2015006995 A1 WO 2015006995A1 CN 2013080075 W CN2013080075 W CN 2013080075W WO 2015006995 A1 WO2015006995 A1 WO 2015006995A1
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Prior art keywords
pixel electrode
switch
pixel
scan line
scan
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PCT/CN2013/080075
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English (en)
French (fr)
Inventor
姚晓慧
陈政鸿
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/232,270 priority Critical patent/US9218777B2/en
Priority to JP2016526397A priority patent/JP6127212B2/ja
Priority to KR1020167004366A priority patent/KR101764549B1/ko
Priority to RU2016105105A priority patent/RU2621884C1/ru
Priority to GB1522576.6A priority patent/GB2529979B/en
Publication of WO2015006995A1 publication Critical patent/WO2015006995A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a liquid crystal display panel.
  • VA Vertical Alignment, vertical alignment type liquid crystal display panel has the advantages of fast response speed and high contrast, and is the mainstream development direction of liquid crystal display panels.
  • the alignment of the liquid crystal molecules is not the same, so that the effective refractive index of the liquid crystal molecules is also different, thereby causing a change in the transmitted light intensity, which is manifested by a decrease in light transmission capability at oblique viewing angles.
  • the color of the viewing angle and the positive viewing direction are inconsistent, and chromatic aberration occurs, so color distortion is observed at a large viewing angle.
  • one pixel is divided into a main pixel region and a sub-pixel region, and each pixel is divided into four domains (domains, which refer to microscopic regions in which the directors of the liquid crystal molecules are substantially the same).
  • domains which refer to microscopic regions in which the directors of the liquid crystal molecules are substantially the same.
  • each pixel is divided into 8 domains, and the voltages of the main pixel region and the sub-pixel region are controlled to be different, so that the liquid crystal molecules in the two pixel regions are arranged differently, thereby improving color distortion at a large viewing angle to achieve LCS. (Low Color Shift, low color cast) effect.
  • liquid crystal displays are compatible with 2D and 3D display functions.
  • 3D FPR Flexible-type Patterned In the Retarder (polarized) stereoscopic display technology
  • two adjacent rows of pixels respectively correspond to the left and right eyes of the viewer to respectively generate a left eye image corresponding to the left eye and a right eye image corresponding to the right eye, and the left and right eyes of the viewer
  • the left and right eye images are synthesized by the brain to make the viewer feel the stereoscopic display effect.
  • the left eye image and the right eye image are prone to crosstalk, which causes the viewer to see overlapping images, which affects the viewing effect.
  • an additional blackout area BM is usually added between adjacent two pixels (Black) Matrix, black matrix) masks the way the crosstalk signal is blocked to reduce crosstalk between the two eyes.
  • Black Matrix, black matrix
  • the technical solution of dividing one pixel into a main pixel region and a sub-pixel region can simultaneously solve the aperture ratio in the 2D display mode and the binocular signal crosstalk problem in the 3D display mode, that is, control the main pixel in the 2D display mode.
  • the area and the sub-pixel area both normally display the 2D image, and in the 3D display mode, the main pixel area displays a black picture equivalent to BM for reducing the binocular signal crosstalk, so that the sub-pixel area normally displays the 3D image.
  • the technical problem to be solved by the present invention is to provide an array substrate and a liquid crystal display panel, which can reduce the color difference in a large viewing angle of the 2D and 3D display modes, and can improve the aperture ratio in the 2D display mode and reduce the 3D display mode. Binocular signal crosstalk.
  • the present invention adopts a technical solution to provide an array substrate including a plurality of first scan lines arranged in a plurality of rows, a plurality of second scan lines arranged in a plurality of rows, a plurality of data lines, and a plurality of branches.
  • each pixel unit includes a first pixel electrode, a second pixel electrode, a third pixel electrode, a first switch, a second switch, and a third switch, each of the pixel units further includes a control circuit, wherein the first pixel electrode is connected to the first scan line and the data line corresponding to the pixel unit through the first switch, The second pixel electrode is connected to the first scan line corresponding to the pixel unit and the first switch through the second switch, and the third pixel electrode is connected to the second scan line and the second pixel electrode corresponding to the pixel unit through the third switch, and is controlled.
  • the circuit is respectively connected to the first scan line and the second pixel electrode corresponding to the pixel unit, and the control circuit inputs the scan signal on the first scan line Acting on the second pixel electrode to change the voltage of the second pixel electrode, and controlling the voltage difference between the second pixel electrode and the common electrode to be non-zero; in the 2D display mode, the first scan line inputs the scan signal to control the a switch and a second switch are turned on, the first pixel electrode receives the data signal from the data line through the first switch to be in a state of displaying an image corresponding to the 2D picture, and the second pixel electrode is sequentially received through the first switch and the second switch The data signal of the data line is in a state of displaying an image corresponding to the 2D picture, the control circuit acts on the second pixel electrode such that the voltage of the second pixel electrode changes for the first time, and then the first scan line controls the first switch and the second switch Disconnected, the second scan line inputs a scan signal to control the third switch to be turned on, so
  • the control circuit includes a fourth switch and a charge sharing capacitor
  • the fourth switch includes a control end, a first end and a second end, and the control end of the fourth switch is connected to the first scan line corresponding to the pixel unit, and the fourth switch
  • the first end is connected to the second pixel electrode corresponding to the pixel unit
  • the second end of the fourth switch is connected to one end of the charge sharing capacitor
  • the charge sharing capacitor is connected to the common electrode
  • the fourth switch is turned on when the scan signal is input to the first scan line. So that the second pixel electrode and the charge sharing capacitor are electrically connected, the voltage of the second pixel electrode is changed for the first time by the charge sharing capacitor, and the fourth switch controls between the second pixel electrode and the common electrode during the time when it is turned on. The voltage difference is not zero.
  • the fourth switch is a thin film transistor, the control end of the fourth switch corresponds to the gate of the thin film transistor, the first end of the fourth switch corresponds to the source of the thin film transistor, and the second end of the fourth switch corresponds to the thin film transistor
  • the drain, the aspect ratio of the thin film transistor is smaller than the first set value, so that the voltage difference between the second pixel electrode and the common electrode is controlled to be non-zero during the time during which it is turned on.
  • the array substrate further includes a switch unit and a short circuit in a peripheral area of the array substrate;
  • the switch unit includes a plurality of controlled switches, and the controlled switch includes a control end, an input end, and an output end, and the input end of each controlled switch is connected to one line.
  • a first scan line corresponding to the pixel unit the output end is connected to a second scan line corresponding to the row of pixel units adjacent to the row of pixel units, and the control ends of all the controlled switches are connected with the short-circuit line; in the 2D display mode,
  • the short-circuit line inputs a control signal to control the conduction of all the controlled switches.
  • the scan signal When the scan signal is input to the first scan line corresponding to the row of pixel units, the scan signal is simultaneously input to the second end connected to the output of the controlled switch through the controlled switch.
  • the short-circuit line In the scan line, to control the corresponding third switch to be turned on, in the 3D display mode, the short-circuit line inputs a control signal to control all controlled switches to open to control all third switches to open.
  • an array substrate including a plurality of first scan lines, a plurality of second scan lines, a plurality of data lines, a plurality of pixel units, and an input.
  • a common electrode of a common voltage each pixel unit corresponding to a first scan line, a second scan line, and a data line;
  • each pixel unit includes a first pixel electrode, a second pixel electrode, a third pixel electrode, and a first switch a second switch and a third switch, each of the pixel units further includes a control circuit, the first pixel electrode is connected to the first scan line and the data line corresponding to the pixel unit through the first switch, and the second pixel electrode is passed through the second switch Connected to the first scan line and the first switch corresponding to the pixel unit, the third pixel electrode is connected to the second scan line and the second pixel electrode corresponding to the pixel unit through the third switch, and the control circuit is respectively connected to the corresponding pixel
  • the control circuit acts on the second pixel electrode when the scan signal is input to the first scan line to change a voltage of the two pixel electrode, and controlling a voltage difference between the second pixel electrode and the common electrode is not zero; in the 2D display mode, the first scan line inputs a scan signal to control the first switch and the second switch to be turned on, a pixel electrode receives a data signal from the data line through the first switch to be in a state of displaying an image corresponding to the 2D picture, and the second pixel electrode sequentially receives the data signal from the data line through the first switch and the second switch to be in a display corresponding to 2D
  • the control circuit acts on the second pixel electrode such that the voltage of the second pixel electrode changes for the first time, then the first scan line controls the first switch and the second switch to be turned off, and the second scan line inputs the scan signal To control the third switch to be turned on, so that the second pixel electrode and the third
  • the data signal is in a state of displaying an image corresponding to the 3D picture
  • the control circuit acts on the second pixel electrode to change the voltage of the second pixel electrode such that the voltage difference between the first pixel electrode and the second pixel electrode is not zero
  • the third pixel electrode is in a state of displaying an image corresponding to the black screen under the action of the third switch being turned off.
  • the control circuit includes a fourth switch and a charge sharing capacitor
  • the fourth switch includes a control end, a first end and a second end, and the control end of the fourth switch is connected to the first scan line corresponding to the pixel unit, and the fourth switch
  • the first end is connected to the second pixel electrode corresponding to the pixel unit
  • the second end of the fourth switch is connected to one end of the charge sharing capacitor
  • the charge sharing capacitor is connected to the common electrode
  • the fourth switch is turned on when the scan signal is input to the first scan line. So that the second pixel electrode and the charge sharing capacitor are electrically connected, the voltage of the second pixel electrode is changed for the first time by the charge sharing capacitor, and the fourth switch controls between the second pixel electrode and the common electrode during the time when it is turned on. The voltage difference is not zero.
  • the fourth switch is a thin film transistor, the control end of the fourth switch corresponds to the gate of the thin film transistor, the first end of the fourth switch corresponds to the source of the thin film transistor, and the second end of the fourth switch corresponds to the thin film transistor
  • the drain, the aspect ratio of the thin film transistor is smaller than the first set value, so that the voltage difference between the second pixel electrode and the common electrode is controlled to be non-zero during the time during which it is turned on.
  • the plurality of pixel units are arranged in a row, and the plurality of first scan lines and the second scan lines are also arranged in a row, and in the 2D display mode, while scanning the first scan line corresponding to the row of pixel units, The second scan line corresponding to the pixel unit of the previous row that is adjacent to the pixel unit is scanned.
  • the array substrate further includes a switch unit and a short circuit in a peripheral area of the array substrate;
  • the switch unit includes a plurality of controlled switches, and the controlled switch includes a control end, an input end, and an output end, and the input end of each controlled switch is connected to one line.
  • a first scan line corresponding to the pixel unit the output end is connected to a second scan line corresponding to the row of pixel units adjacent to the row of pixel units, and the control ends of all the controlled switches are connected with the short-circuit line; in the 2D display mode,
  • the short-circuit line inputs a control signal to control the conduction of all the controlled switches.
  • the scan signal When the scan signal is input to the first scan line corresponding to the row of pixel units, the scan signal is simultaneously input to the second end connected to the output of the controlled switch through the controlled switch.
  • the short-circuit line In the scan line, to control the corresponding third switch to be turned on, in the 3D display mode, the short-circuit line inputs a control signal to control all controlled switches to open to control all third switches to open.
  • the area of the region where the third pixel electrode is located is smaller than the area of the region where the first pixel electrode and the second pixel electrode are located.
  • the third switch controls the voltage difference between the second pixel electrode and the third pixel electrode to be non-zero during the time when the second switch is turned on, so that The voltage difference between the first pixel electrode, the second pixel electrode, and the third pixel electrode is not zero.
  • the third switch is a thin film transistor, the gate of the thin film transistor is connected to the second scan line, the source of the thin film transistor is connected to the second pixel electrode, the drain of the thin film transistor is connected to the third pixel electrode, and the width of the thin film transistor is wide.
  • the ratio is less than the second set value such that the voltage difference between the second pixel electrode and the third pixel electrode is controlled to be non-zero during the time during which it is turned on.
  • a liquid crystal display panel including an array substrate, a color filter substrate, and a liquid crystal layer between the array substrates, the array substrate including a plurality of first scan lines a plurality of second scan lines, a plurality of data lines, a plurality of pixel units, and a common electrode for inputting a common voltage, each of the pixel units corresponding to one first scan line, one second scan line, and one data line; each The pixel unit includes a first pixel electrode, a second pixel electrode, a third pixel electrode, a first switch, a second switch, and a third switch, each of the pixel units further includes a control circuit, and the first pixel electrode passes through the first switch and corresponds to The first scan line of the pixel unit is connected to the data line, the second pixel electrode is connected to the first scan line corresponding to the pixel unit and the first switch through the second switch, and the third pixel electrode passes through the third switch and the corresponding
  • the second scan line is connected to the second pixel electrode, and the control circuit is respectively connected to the first scan line and the second image corresponding to the pixel unit An electrode, the control circuit acts on the second pixel electrode when the scan signal is input to the first scan line to change the voltage of the second pixel electrode, and controls the voltage difference between the second pixel electrode and the common electrode to be non-zero; in 2D display
  • the first scan line inputs a scan signal to control the first switch and the second switch to be turned on, and the first pixel electrode receives the data signal from the data line through the first switch to be in a state of displaying an image corresponding to the 2D picture
  • second The pixel electrode sequentially receives the data signal from the data line through the first switch and the second switch to be in a state of displaying an image corresponding to the 2D picture, and the control circuit acts on the second pixel electrode to cause the voltage of the second pixel electrode to change for the first time, Then, the first scan line controls the first switch and the second switch to be turned off,
  • the control circuit includes a fourth switch and a charge sharing capacitor
  • the fourth switch includes a control end, a first end and a second end, and the control end of the fourth switch is connected to the first scan line corresponding to the pixel unit, and the fourth switch
  • the first end is connected to the second pixel electrode corresponding to the pixel unit
  • the second end of the fourth switch is connected to one end of the charge sharing capacitor
  • the charge sharing capacitor is connected to the common electrode
  • the fourth switch is turned on when the scan signal is input to the first scan line. So that the second pixel electrode and the charge sharing capacitor are electrically connected, the voltage of the second pixel electrode is changed for the first time by the charge sharing capacitor, and the fourth switch controls between the second pixel electrode and the common electrode during the time when it is turned on. The voltage difference is not zero.
  • the fourth switch is a thin film transistor, the control end of the fourth switch corresponds to the gate of the thin film transistor, the first end of the fourth switch corresponds to the source of the thin film transistor, and the second end of the fourth switch corresponds to the thin film transistor
  • the drain, the aspect ratio of the thin film transistor is smaller than the first set value, so that the voltage difference between the second pixel electrode and the common electrode is controlled to be non-zero during the time during which it is turned on.
  • the plurality of pixel units are arranged in a row, and the plurality of first scan lines and the second scan lines are also arranged in a row, and in the 2D display mode, while scanning the first scan line corresponding to the row of pixel units, The second scan line corresponding to the pixel unit of the previous row that is adjacent to the pixel unit is scanned.
  • the array substrate further includes a switch unit and a short circuit in a peripheral area of the array substrate;
  • the switch unit includes a plurality of controlled switches, and the controlled switch includes a control end, an input end, and an output end, and the input end of each controlled switch is connected to one line.
  • a first scan line corresponding to the pixel unit the output end is connected to a second scan line corresponding to the row of pixel units adjacent to the row of pixel units, and the control ends of all the controlled switches are connected with the short-circuit line; in the 2D display mode,
  • the short-circuit line inputs a control signal to control the conduction of all the controlled switches.
  • the scan signal When the scan signal is input to the first scan line corresponding to the row of pixel units, the scan signal is simultaneously input to the second end connected to the output of the controlled switch through the controlled switch.
  • the short-circuit line In the scan line, to control the corresponding third switch to be turned on, in the 3D display mode, the short-circuit line inputs a control signal to control all controlled switches to open to control all third switches to open.
  • the area of the region where the third pixel electrode is located is smaller than the area of the region where the first pixel electrode and the second pixel electrode are located.
  • the third switch controls the voltage difference between the second pixel electrode and the third pixel electrode to be non-zero during the time when the second switch is turned on, so that The voltage difference between the first pixel electrode, the second pixel electrode, and the third pixel electrode is not zero.
  • the third switch is a thin film transistor, the gate of the thin film transistor is connected to the second scan line, the source of the thin film transistor is connected to the second pixel electrode, the drain of the thin film transistor is connected to the third pixel electrode, and the width of the thin film transistor is wide.
  • the ratio is less than the second set value such that the voltage difference between the second pixel electrode and the third pixel electrode is controlled to be non-zero during the time during which it is turned on.
  • each pixel unit includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, and a control circuit acts on the second pixel.
  • the third pixel electrode is connected to the second pixel electrode through the third switch.
  • the control circuit acts on the second pixel electrode such that the voltage of the second pixel electrode changes for the first time, so that the voltages of the first pixel electrode and the second pixel electrode are different, The color difference at a large viewing angle can be reduced, and after the first scan line stops inputting the scan signal, the third switch is turned on to electrically connect the second pixel electrode and the third pixel electrode, and the third pixel electrode receives from the first
  • the data signal of the two-pixel electrode is in a state of displaying an image corresponding to the 2D picture, thereby causing the first to third pixel electrodes to be in a state of displaying an image corresponding to the 2D picture in the 2D display mode, and the aperture ratio can be improved, and
  • the voltage of the two pixel electrode is changed a second time through the third pixel electrode, so that at least two of the three pixel electrodes The voltages are different, and the voltage difference between the second pixel electrode and the first pixel electrode is
  • the first pixel electrode receives the data signal from the data line through the first switch
  • the second pixel electrode sequentially receives the data signal from the data line through the first switch and the second switch to display the corresponding 3D picture.
  • the state of the image, the control circuit acts on the second pixel electrode to change the voltage of the second pixel electrode such that the voltages of the first pixel electrode and the second pixel electrode are different, the color difference at a large viewing angle can be reduced
  • the 3D display mode The state in which the third pixel electrode is controlled to display an image corresponding to a black screen is controlled downward, whereby the binocular signal crosstalk can be reduced.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic structural view of a pixel unit of FIG. 1;
  • FIG. 3 is a structural equivalent circuit diagram of the pixel unit of FIG. 1;
  • FIG. 4 is a schematic diagram showing a display effect of a third pixel electrode of the pixel unit of FIG. 1 in a 3D display mode
  • FIG. 5 is a structural equivalent circuit diagram of a pixel unit in another embodiment of the array substrate of the present invention.
  • FIG. 6 is a schematic structural view of an embodiment of a liquid crystal display panel of the present invention.
  • the array substrate includes a plurality of first scan lines 11 , a plurality of second scan lines 12 , a plurality of data lines 13 , a plurality of pixel units 14 , and a common voltage for inputting The common electrode 15.
  • a plurality of pixel units 14 are arranged in an array, and each of the pixel units 14 is connected to a first scan line 11, a second scan line 12, and a data line 13.
  • each pixel unit 14 includes a first pixel electrode M1, a second pixel electrode M2, a third pixel electrode M3, and a first pixel electrode M1 and a second pixel electrode M2, respectively.
  • Each switch includes a control terminal, an input terminal, and an output terminal.
  • the control end of the first switch T1 and the control end of the second switch T2 are electrically connected to the first scan line 11 corresponding to the pixel unit 14, and the input end of the first switch T1 and the data line 13 corresponding to the pixel unit 14 Electrically connected, the output end of the first switch T1 is electrically connected to the first pixel electrode M1, and the input end of the second switch T2 is electrically connected to the first pixel electrode M1, that is, the input end of the second switch T2 is first The output end of the switch T1 is electrically connected, and the output end of the second switch T2 is electrically connected to the second pixel electrode M2.
  • the control end of the third switch T3 is electrically connected to the second scan line 12 corresponding to the pixel unit 14, the input end of the third switch T3 is electrically connected to the second pixel electrode M2, and the output end of the third switch T3 is connected to the third The pixel electrode M3 is electrically connected.
  • the first switch T1, the second switch T2, and the third switch T3 of the present embodiment are all thin film transistors, wherein the control ends of the three switches T1, T2, and T3 correspond to the gate of the thin film transistor, and the input end corresponds to the thin film transistor.
  • the source corresponds to the output of the thin film transistor.
  • the three switches may also be switching elements such as a triode or a Darlington tube.
  • Each of the pixel units 14 further includes a control circuit 16 respectively connected to the first scan line 11 and the second pixel electrode M2 corresponding to the pixel unit 14, and the control circuit 16 is input when the scan signal is input to the first scan line 11. Acting on the second pixel electrode M2 to change the voltage of the second pixel electrode M2, and controlling the voltage difference between the second pixel electrode M2 and the common electrode 15 to be not zero.
  • the control circuit 16 of the present embodiment includes a fourth switch T4 and a charge sharing capacitor Ca.
  • the fourth switch T4 includes a control terminal, an input terminal, and an output terminal.
  • the control end of the fourth switch T4 is electrically connected to the first scan line 11, the first end of the fourth switch T4 is electrically connected to the second pixel electrode M2, and the second end of the fourth switch T4 is connected to the charge sharing capacitor Ca. One end is connected, and the other end of the charge sharing capacitor Ca is electrically connected to the common electrode 15.
  • the fourth switch T4 is a thin film transistor, the control end of the fourth switch T4 corresponds to the gate of the thin film transistor, the first end of the fourth switch T4 corresponds to the source of the thin film transistor, and the second end of the fourth switch T4 corresponds to It is the drain of the thin film transistor.
  • the fourth switch T4 When the first scan line 11 inputs the scan signal, the fourth switch T4 is turned on, so that the second pixel electrode M2 and the charge sharing capacitor Ca are electrically connected, and the second pixel electrode M2 is electrically shared with the charge sharing capacitor Ca. The voltage thereof is changed, and the fourth switch T4 controls the voltage difference between the second pixel electrode M2 and the common electrode 15 not to be zero during the period in which it is turned on to ensure that the second pixel electrode M2 is in a state of normally displaying an image.
  • the color difference observed at a large viewing angle in the 2D and 3D display modes can be reduced, and the aperture ratio in the 2D display mode can be improved, and the binocular signal crosstalk in the 3D display mode can be reduced.
  • the present embodiment scans the first scan line 11 and the second scan line 12 in a progressive scan manner.
  • the common electrode 15 inputs a common voltage.
  • the positive polarity ie, the data signal is greater than the common voltage
  • the first scan line 11 inputs a high level scan signal to control the first switch T1 and the second switch T2 to be turned on
  • the data line 13 inputs the data signal
  • One pixel electrode M1 receives the data signal from the data line 13 through the first switch T1 and is in a state of displaying an image corresponding to the 2D picture
  • the second pixel electrode M2 sequentially receives the data signal through the first switch T1 and the second switch T2 to be displayed.
  • the voltage of the second pixel electrode M2 is slightly lower than the voltage of the first pixel electrode M1 by the impedance of the first switch T1 and the second switch T2, so that the first pixel electrode M1 and There is a certain voltage difference between the second pixel electrodes M2.
  • the fourth switch T4 also receives the scan signal and is turned on, so that the second pixel electrode M2 and the charge sharing capacitor Ca are electrically connected.
  • the voltage of the second pixel electrode M2 is changed by the charge sharing capacitor Ca for the first time, that is, the second pixel electrode M2 is discharged by the charge sharing capacitor Ca, so that the voltage of the second pixel electrode M2 is further lowered, thereby making the first pixel electrode M1 and the first pixel electrode The voltage difference between the two pixel electrodes M2 increases.
  • the first scan line 11 stops inputting the scan signal of the high level to turn off the first switch T1, the second switch T2 and the fourth switch T4, and the second scan line 12 inputs the high voltage.
  • the flat scan signal is controlled to be turned on by the third switch T3.
  • the second pixel electrode M2 and the third pixel electrode M3 are electrically connected through the third switch T3, and the third pixel electrode M3 receives the data signal from the second pixel electrode M2. Then, it is in the state of displaying the image corresponding to the 2D screen.
  • the three pixel electrodes M1, M2, and M3 are all in a state of displaying an image corresponding to the 2D screen, whereby the aperture ratio of the 2D display mode can be improved.
  • the voltage of the second pixel electrode M2 is changed a second time through the third pixel electrode M3, that is, the voltage of the second pixel electrode M2 passes through the liquid crystal capacitor Clc3 when the third switch T3 is turned on (by the third pixel electrode M3 and the other
  • the charge sharing between the liquid crystal molecules sandwiched between the common electrodes of a substrate changes the second time.
  • the partial charge of the second pixel electrode M2 is transferred to the third pixel electrode M3 such that the voltage of the second pixel electrode M2 is once again reduced until the voltage of the second pixel electrode M2 and the voltage of the third pixel electrode M3 are the same. At this time, there is a certain voltage difference between the first pixel electrode M1 and the second pixel electrode M2 and the third pixel electrode M3, respectively.
  • the first scan line 11 inputs a high level scan signal to control the first switch T1 and the second switch T2 to be turned on
  • the data line 13 inputs the data signal
  • first The pixel electrode M1 receives the data signal from the data line 13 through the first switch T1 and is in a state of displaying an image corresponding to the 2D picture
  • the second pixel electrode M2 sequentially receives the data signal through the first switch T1 and the second switch T2 to be in display corresponding
  • the state of the image of the 2D picture at which time the voltage of the second pixel electrode M2 is slightly lower than the voltage of the first pixel electrode M1 due to the influence of the impedance of the first switch T1 and the second switch T2, so that the first pixel electrode M1 and the first There is a certain voltage difference between the two pixel electrodes M2.
  • the fourth switch T4 When the scan signal of the high level is input to the first scan line 11, the fourth switch T4 also receives the scan signal and is turned on, so that the second pixel electrode M2 and the charge sharing capacitor Ca are electrically connected.
  • the voltage of the second pixel electrode M2 is changed by the charge sharing capacitor Ca for the first time, that is, the second pixel electrode M2 is charged by the charge sharing capacitor Ca, so that the voltage of the second pixel electrode M2 is increased for the first time, so that the second pixel electrode M2 There is a certain voltage difference between the first pixel electrode M1 and the first pixel electrode M1.
  • the first scan line 11 stops inputting the scan signal of the high level to turn off the first switch T1, the second switch T2 and the fourth switch T4, and the second scan line 12 inputs the high voltage.
  • the flat scan signal is controlled to be turned on by the third switch T3, and the second pixel electrode M2 and the third pixel electrode M3 are electrically connected through the third switch T3.
  • the third pixel electrode M3 retains the positive polarity voltage at the previous time frame, the partial charge of the third pixel electrode M3 is transferred to the second pixel electrode M2 when the third switch T3 is turned on, so that the second pixel electrode M2 The voltage is increased again until the voltage of the second pixel electrode M2 and the voltage of the third pixel electrode M3 are the same, since the voltage of the first pixel electrode M1 remains unchanged, so that the first pixel electrode M1 and the second pixel electrode M2 and the third, respectively There is a certain voltage difference between the pixel electrodes M3.
  • the voltage of the second pixel electrode M2 is firstly applied by the fourth switch T4 and the charge sharing capacitor Ca. Sub-lower (or increased), in the time frame of scanning the second scan line 12, the voltage of the second pixel electrode M2 is again lowered (or increased) by the charge sharing of the third pixel electrode M3, and the voltage of the second pixel electrode M2 The reduction (or increase) is experienced twice, thereby reducing the voltage difference between the second pixel electrode M2 and the common electrode 15 while also causing a voltage difference between the second pixel electrode M2 and the first pixel electrode M1 ( That is, the voltage difference between the third pixel electrode M3 and the first pixel electrode M1 is further increased, whereby color distortion of a large viewing angle can be further improved.
  • the fourth switch T4 causes a voltage difference between the second pixel electrode M2 and the common electrode 15 to be reduced when turned on, but in order to enable the second pixel electrode M2 to be in a state of normally displaying an image, the fourth switch T4 is The voltage difference between the second pixel electrode M2 and the common electrode 15 is controlled to be non-zero during the on-time, that is, the voltage of the second pixel electrode M2 is not lowered (or increased) to the common electrode by the action of the fourth switch T4. 15 voltage.
  • the time when the fourth switch T4 is turned on is the time when the first scan line 11 inputs the scan signal, and when the positive polarity is reversed, the control of the fourth switch T4 causes the fourth switch T4 to be turned on.
  • the inner second pixel electrode M2 releases only a part of the charge to the charge sharing capacitor Ca, and the voltage of the second pixel electrode M2 decreases but does not decrease to the same voltage as the common electrode 15; when the negative polarity is reversed, the fourth switch T4 is passed.
  • the control function is such that the charge sharing capacitor Ca transfers only a partial charge to the second pixel electrode M2 during the time when the fourth switch T4 is turned on, so that the voltage of the second pixel electrode M2 increases but does not increase to the same as the common electrode 15.
  • the voltage thereby causing a certain voltage difference between the second pixel electrode M2 and the common electrode 15 to ensure that the second pixel electrode M2 is in a state of normally displaying an image.
  • the charge transfer speed between the second pixel electrode M2 and the charge sharing capacitor Ca can be controlled by controlling the current passing capability of the fourth switch T4 when turned on, the current passing capability means that the fourth switch T4 is turned on.
  • the magnitude of the current allowed to flow, for example, the current passing ability of the fourth switch T4 when turned on is small, so that the charge transfer speed between the second pixel electrode M2 and the charge sharing capacitor Ca is slow, so that the fourth switch There is still a certain voltage difference between the second pixel electrode M2 and the common electrode 15 during the time when T4 is turned on.
  • the fourth switch T4 of the present embodiment is a thin film transistor.
  • the magnitude of the current that the thin film transistor can pass when it is turned on is related to the aspect ratio of the thin film transistor, and the smaller the aspect ratio is, the current that the thin film transistor can flow when turned on.
  • the smaller the current the smaller the current passing capability.
  • the larger the aspect ratio of the thin film transistor the larger the current that can flow when it is turned on, and the greater the current passing capability. Therefore, by controlling the aspect ratio of the fourth switch T4 such that the aspect ratio is smaller than the first set value, the current passing capability of the fourth switch T4 when turned on is less than a certain value, so that the fourth switch T4 is guided.
  • the charge transfer speed between the second pixel electrode M2 and the charge sharing capacitor Ca is also controlled to be less than a certain value to ensure the voltage difference between the second pixel electrode M2 and the common electrode 15 during the time when the fourth switch T4 is turned on. Not zero.
  • the first set value may be selected according to an actual situation, and the voltage difference between the second pixel electrode M2 and the common electrode 15 is not zero, and the second pixel can be made again during the time when the fourth switch T4 is turned on.
  • the first set value allows for a variety of choices, such as 0.3, or other ratios.
  • the current passing capability of the fourth switch when the fourth switch is turned on can also be controlled by controlling the magnitude of the gate voltage of the fourth switch.
  • the fourth switch may be a triode or the like, and is not limited thereto.
  • the first scan line 11 and the second scan line 12 corresponding to the row of pixel units 14 After the scanning of the first scan line 11 and the second scan line 12 corresponding to the row of pixel units 14 is completed, the first scan line 11 and the second scan line 12 corresponding to the next row of pixel units are scanned, and so on.
  • the third pixel electrode M3 is first turned off by using the black screen signal, that is, the data line 13 inputs a data signal indicating the corresponding black image to the first pixel electrode M1 and the second pixel electrode M2, and controls the third.
  • the switch T3 is turned on so that the third pixel electrode M3 is in a state of displaying an image corresponding to a black screen.
  • the first scan line 11 inputs a scan signal of a high level to control the first switch T1 and the second switch T2 to be turned on
  • the data line 13 inputs a data signal
  • the first pixel electrode M1 passes the first switch.
  • the second pixel electrode M2 sequentially receives the data signal through the first switch T1 and the second switch T2 to be in a state of displaying an image corresponding to the 3D picture.
  • the voltage of the second pixel electrode M2 is slightly lower than the voltage of the first pixel electrode M1 due to the influence of the impedances of the first switch T1 and the second switch T2, so that the first pixel electrode M1 and the second pixel electrode M2 exist between A certain voltage difference.
  • the fourth switch T4 is also in an on state when the scan signal is input to the first scan line 11, so that the second pixel electrode M2 and the charge sharing capacitor Ca are electrically connected, and the second pixel electrode M2 passes the charge between the charge sharing capacitor Ca and the charge sharing capacitor Ca. Sharing, the voltage is changed, that is, when the positive polarity is reversed, the second pixel electrode M2 discharges the charge sharing capacitor Ca to lower its voltage, and when the negative polarity is reversed, the second pixel electrode M2 is charged by the charge sharing capacitor Ca to make it The voltage is increased, whereby the voltage of the second pixel electrode M2 and the voltage of the first pixel electrode M1 are different, and there is a certain voltage difference therebetween, whereby color distortion in the 3D display mode can be improved.
  • the fourth switch T4 controls the voltage difference between the second pixel electrode M2 and the common electrode 15 to be non-zero during the time during which it is turned on to ensure that the second pixel electrode M2 is in a state of normally displaying an image corresponding to the 3D picture.
  • the second scan line 12 is turned off, that is, the scan signal is not input to the second scan line 12 to control the third switch T3 to be in an off state, so that the third pixel electrode M3 remains in the display corresponding black. The state of the image of the screen.
  • the first pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 are sequentially arranged in the column direction, and the adjacent two rows of pixel units 14 respectively display a left eye image and a right eye image corresponding to the 3D picture.
  • the third pixel electrode M3 is in a state of displaying an image corresponding to a black screen by the disconnection of the third switch T3, which is in a state of displaying an image of the image corresponding to the black screen.
  • the pixel electrode M3 is a light-shielding region (equivalent to a black matrix, Black Matrix, BM), such that pixel pixels of the adjacent two rows of pixel units 14 corresponding to the left eye image (the second pixel electrode and the third pixel electrode of the row of pixel units) and the pixel electrode corresponding to the image of the right eye are displayed ( There is a light blocking region between the second pixel electrode and the third pixel electrode in the other row of pixel units, and the crosstalk signal of the left eye image and the right eye image is blocked by the light blocking region, thereby reducing the binocular signal crosstalk in the 3D display mode. .
  • BM black matrix
  • the third pixel electrode M3 is mainly used to form a light-shielding region in the 3D display mode to reduce the crosstalk of the 3D signal, and thus the area of the region where the third pixel electrode M3 is located is smaller than the area of the first pixel electrode M1 and the second pixel electrode M2.
  • the area can also be designed according to the actual shading needs to occupy the area of the third pixel electrode M3 to minimize the 3D binocular signal crosstalk phenomenon.
  • the aperture ratio in the 2D display mode can be improved, the color distortion in the 2D and 3D display modes can be effectively improved, the color shifting effect is better, and the binocular signal in the 3D display mode can be reduced.
  • Crosstalk the aperture ratio in the 2D display mode
  • the three pixel electrodes may also be arranged in the row direction, in which case the adjacent two columns of pixel units are respectively in a state of displaying a left eye image and a right eye image corresponding to the 3D picture.
  • the third pixel electrode in the state in which the image corresponding to the black screen is displayed, the binocular signal crosstalk in the 3D display mode can be reduced.
  • the third pixel electrode in the 3D display mode, can also be in a state of displaying a black screen by inserting black, and the blanking time at the first scan line (Blanking) Time) Insert black.
  • the first pixel electrode and the second pixel electrode are in a state of displaying an image corresponding to the 3D picture, and the third pixel electrode is still in a state of displaying an image corresponding to the black screen, and in the next scan.
  • the first pixel electrode, the second pixel electrode, and the third pixel electrode are all in a state in which the image corresponding to the black image is displayed in the time frame, and then the first pixel electrode and the second pixel electrode are restored to the image in the 3D picture.
  • a state in which the third pixel electrode remains in a state in which an image corresponding to the 3D picture is displayed that is, a state in which the first pixel electrode and the second pixel electrode are alternately displayed in an image displaying the 3D picture and a state in which the image corresponding to the black picture is displayed, and
  • the third pixel electrode always maintains a state in which an image corresponding to the 3D picture is displayed.
  • control circuit can also be implemented by using a voltage dividing resistor and a switching component, so that the second pixel electrode is connected to the voltage dividing resistor through the trigger switch, and when the first scan line input scan signal triggers the switching element to be turned on,
  • the voltage of the second pixel electrode is changed by a voltage dividing resistor, and changing the magnitude of the voltage dividing resistor can change the degree of voltage change of the second pixel electrode.
  • the control circuit can also be implemented using only one voltage dividing resistor, so that the second pixel electrode is directly connected to the voltage dividing resistor to change the voltage of the second pixel electrode through the voltage dividing resistor.
  • the third switch T3 is a conventional thin film transistor, and the voltage of the second pixel electrode M2 is finally the same as the voltage of the third pixel electrode M3 when the third switch T3 is turned on, thereby making the second pixel electrode M2 has a certain voltage difference between the third pixel electrode M2 and the first pixel electrode M1 to achieve a low color shift effect.
  • a third switch may also be designed, such that the voltage between the second pixel electrode and the third pixel electrode is different by the action of the third switch, so that the first pixel electrode, the second pixel electrode, and the first pixel electrode There is a certain voltage difference between the two pixel electrodes.
  • the third switch controls the voltage difference between the second pixel electrode and the third pixel electrode to be non-zero during the time when the third switch is turned on, so that The discharge balance state is not achieved between the second pixel electrode and the third pixel electrode during the time when the third switch is turned on, that is, the voltage of the second pixel electrode and the voltage of the third pixel electrode are different, thereby making the first pixel
  • the voltages between the electrodes, the second pixel electrode, and the third pixel electrode are all different, whereby the color difference of the large viewing angle in the 2D display mode can be further reduced, and the low color shift effect can be improved.
  • the third switch of the present embodiment is a thin film transistor having a specific aspect ratio, and the third switch can be controlled to control the second pixel electrode and the third pixel electrode in its conduction by controlling the aspect ratio of the third switch.
  • the voltage difference between them is not zero, that is, the current passing capability of the third switch when conducting is controlled by controlling the aspect ratio of the third switch.
  • the larger the aspect ratio of the third switch the greater the current passing capability of the third switch when conducting, the faster the charge transfer speed between the second pixel electrode and the third pixel electrode, and the width and length of the third switch.
  • the smaller the ratio the smaller the current passing capability of the third switch when turned on, and the slower the charge transfer speed between the second pixel electrode and the third pixel electrode.
  • the charge transfer speed between the second pixel electrode and the third pixel electrode may be controlled to be slow, and further By making the aspect ratio of the third switch smaller than the second set value, for example, the second set value may be 0.2, such that between the second pixel electrode and the third pixel electrode during the time that the third switch is turned on The voltage difference is not zero, so that the voltage difference between the two pixel electrodes is not zero, and a better low color shift effect can be obtained.
  • the current passing capability of the third switch when conducting is controlled by controlling the magnitude of the gate voltage of the third switch (ie, the magnitude of the scan signal input by the second scan line).
  • the three switches control the voltage difference between the second pixel electrode and the third pixel electrode to be non-zero during the time during which it is turned on.
  • the first and second scan lines are scanned line by line in the 2D display mode.
  • the first corresponding to different pixel units may also be scanned simultaneously.
  • Scan line and second scan line are shown simultaneously.
  • the first scan line (only three are shown in the figure, including the first scan line 51_1, 51_2, 51_3) and the second scan line (only three are shown in the figure, including the second scan line 52_1, 52_2, 52_3) along The direction of the line extends.
  • the adjacent first row of pixel cells A1 and the second row of pixel cells A2 are taken as an example for scanning, while scanning the first scan line 51_2 corresponding to the second row of pixel cells A2,
  • the second row of scan lines 52_1 corresponding to the first row of pixel cells A1 of the first row adjacent to the pixel row A2 of the second row are scanned.
  • the array substrate of the present embodiment further includes a switch unit 55 and a short-circuit line 56 located in a peripheral region of the array substrate.
  • the switch unit 55 includes a plurality of controlled switches (including controlled switches T5_1, T5_2).
  • the controlled switch includes a control terminal, an input terminal, and an output terminal.
  • the control switch T5_1 between the first row of pixel units A1 and the second row of pixel units A2 is described.
  • the input end of the controlled switch T5_1 is connected to the first scan line 51_2 corresponding to the second row of pixel units A2, and the controlled switch T5_1
  • the output end is connected to the second scan line 52_1 corresponding to the pixel unit A1 of the first row, and the control ends of all the controlled switches are connected to the short-circuit line 56.
  • the controlled switch T5_1 is a thin film transistor, and the control end of the controlled switch T5_1 corresponds to the gate of the thin film transistor, the input end of the controlled switch T5 corresponds to the source of the thin film transistor, and the output end of the controlled switch T5_1 corresponds to the thin film. The drain of the transistor.
  • the short-circuit line 56 inputs a high level control signal to control all of the controlled switches to turn on, and then scans the first scan line line by line.
  • the first scan line 51_1 corresponding to the first row of pixel units A1 inputs a scan signal to control the first switch T1 and the second switch T2 in the first row of pixel units A1 to be turned on
  • the data line 53 inputs a data signal to make the first
  • the first pixel electrode M1 and the second pixel electrode M2 in the row pixel unit A1 are in a state of displaying an image corresponding to a 2D picture.
  • the fourth switch T4 is turned on when the scan signal is input by the first scan line 51_1, so that the second pixel electrode M2 and the charge sharing capacitor Ca are electrically connected, and the second pixel electrode M2 is caused by charge sharing with the charge sharing capacitor Ca.
  • the voltage is changed for the first time, so that there is a certain voltage difference between the first pixel electrode M1 and the second pixel electrode M2, whereby the color difference at a large viewing angle in the 2D display mode can be improved, and the display quality is improved.
  • the first scan line 51_2 corresponding to the pixel unit A2 of the second row inputs a scan signal to control the first switch T1 in the pixel unit A2 of the second row.
  • the second switch T2 and the fourth switch T4 are turned on.
  • the controlled switch T5_1 since the controlled switch T5_1 is in an on state, the scan signal input by the first scan line 51_2 corresponding to the second row of pixel units A2 is input through the controlled switch T5_1.
  • the voltage difference between the first pixel electrode and the first pixel electrode is further increased, and the low color shift effect can be further improved.
  • the first scan line 51_2 corresponding to the second row of pixel units A2 is scanned, and at the same time, the second row is controlled by the controlled switch T5_2.
  • the second scan line 52_2 corresponding to the pixel unit A2 is also scanned at the same time.
  • the short-circuit line 56 inputs a control signal to control all of the controlled switches to be in an off state, and inputs a scan signal to the first scan line 51_1 to control the first switch T1 and the second switch in the first row of pixel units A1.
  • T2 is turned on, and the data line 53 inputs a data signal such that the first pixel electrode M1 and the second pixel electrode M2 in the first row of pixel units A1 are in a state of displaying an image corresponding to the 3D picture.
  • the fourth switch T4 is turned on when the scan signal is input by the first scan line 51_1, so that the voltage of the second pixel electrode M2 is changed for the first time, so that the voltages of the first pixel electrode M1 and the second pixel electrode M2 are different, so that the two There is a certain voltage difference between them, thereby improving the color difference of the large viewing angle in the 3D display mode and improving the display quality.
  • a scan signal is input to the first scan line 51_2 corresponding to the second row of pixel units A2 to control the first switch T1 in the second row of pixel units A2.
  • the second switch T2 and the fourth switch T4 are turned on, and since the controlled switch T5_1 is in the off state, the scan signal input by the first scan line 51_2 corresponding to the second row of pixel units A2 does not enter the first row of pixel units A1.
  • a third switch T3 to control the third switch T3 to be in an off state, so that the third pixel electrode M3 in the first row of pixel units A1 is kept in a state of displaying an image corresponding to a black screen, by which the black screen is displayed
  • the third pixel electrode M3 of the state of the image can reduce the binocular signal crosstalk in the 3D display mode.
  • the switching unit 55 and the short-circuit line 55 of the present embodiment only one scanning driving chip is required to apply a control signal to the short-circuit line 56 to control the conduction or the closing of the controlled switch in the switching unit 55, thereby correspondingly controlling the third switch T3. Turning on or off not only enables low color shift and higher aperture ratio in 2D display mode, but also low color shift and low crosstalk in 3D display mode, while reducing the number of scan driving chips and reducing cost.
  • the scan time of each scan line helps to perform high update frequency operations.
  • the simultaneous scanning of the first scan line and the second scan line corresponding to different rows of pixel units may be implemented without using the above-described switch unit 55 and the short-circuit line 55, but each scan line is included (including The first scan line and the second scan line are independent of each other, and each scan line is connected to one scan drive chip to individually control scanning of one scan line, thereby simultaneously inputting a scan signal to a first scan line corresponding to one row of pixel units The scan signal is also input to the second scan line corresponding to the pixel unit of the previous row. In this manner, the scan of the two scan lines can also be performed simultaneously.
  • the liquid crystal display panel includes an array substrate 601 , a color filter substrate 602 , and a liquid crystal layer 603 between the array substrate 601 and the color filter substrate 602 .
  • the array substrate 601 is the array substrate in each of the above embodiments.

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  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

提供了一种阵列基板及液晶显示面板，阵列基板中，每个像素单元（14）包括第一像素电极（Ml）、第二像素电极（M2）以及第三像素电极（M3），还包括一作用于第二像素电极（M2）的控制电路（16），通过控制电路（16）改变第二像素电极（M2）的电压，并且第三像素电极（M3）通过一第三开关（T3）连接第二像素电极（M2），在2D显示模式下使三个像素电极均处于显示对应2D画面的图像的状态，在3D显示模式下使第三像素电极（M3）处于显示对应黑画面的图像的状态，而第一像素电极（Ml）和第二像素电极（M2）处于显示对应3D画面的图像的状态。通过上述方式，能够改善2D和3D显示模式下的颜色失真。

Description

一种阵列基板及液晶显示面板
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板及液晶显示面板。
【背景技术】
VA（Vertical Alignment，垂直对齐）型液晶显示面板具有响应速度快、对比度高等优点，是目前液晶显示面板的主流发展方向。但是，在不同的视角下，液晶分子的排列指向并不相同，使得液晶分子的有效折射率也不相同，由此会引起透射光强的变化，具体表现为斜视角下透光能力降低，斜视角方向和正视角方向所表现的颜色不一致，发生色差，因此在大视角下会观察到颜色失真。为了改善大视角下的颜色失真，在像素设计中，将一个像素分为主像素区和子像素区，每个像素区分为4个domain（畴，指液晶分子的指向矢基本相同的微小区域），由此每个像素分为8个domain，通过控制主像素区和子像素区的电压不相同，以使得两个像素区中的液晶分子排列不相同，进而改善大视角下的颜色失真，以达到LCS（Low Color Shift，低色偏）的效果。
此外，随着液晶显示技术的发展，大部分液晶显示器已兼容2D和3D显示功能。在3D FPR（Film-type Patterned Retarder，偏光式）立体显示技术中，相邻两行像素分别对应观看者的左眼和右眼，以分别产生对应左眼的左眼图像和对应右眼的右眼图像，观看者的左右眼分别接收到相应的左眼图像和右眼图像后，通过大脑对左右眼图像进行合成以使得观看者感受到立体显示效果。而左眼图像和右眼图像容易发生串扰，会导致观看者看到重叠的影像，影响了观看效果。为了避免双眼图像信号发生串扰，通常在相邻两像素之间增加额外的遮光区域BM（Black Matrix，黑色矩阵）遮蔽的方式来阻挡发生串扰的信号，以降低双眼信号串扰。然而，采用此种方式会导致2D显示模式下的开口率大大降低，降低了2D显示模式下的显示亮度。
上述LCS设计中，将一个像素分为主像素区和次像素区的技术方案能够同时解决2D显示模式下的开口率和3D显示模式下的双眼信号串扰问题，即在2D显示模式下控制主像素区和次像素区均正常显示2D图像，而在3D显示模式下使主像素区显示黑画面以等效于BM，用于降低双眼信号串扰，使次像素区正常显示3D图像。然而，在3D显示模式下，由于主像素区显示黑画面，即在3D显示模式下只有一个次像素区正常显示3D图像，而无法达到LCS效果，在大视角下仍然会观察到颜色失真。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及液晶显示面板，能够减小2D和3D显示模式大视角下的颜色差异，同时能够提高2D显示模式下的开口率，降低3D显示模式下的双眼信号串扰。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包括多条分行排列的第一扫描线、多条分行排列的第二扫描线、多条数据线、多个分行排列的像素单元以及用于输入公共电压的公共电极，每个像素单元对应一条第一扫描线、一条第二扫描线以及一条数据线；每个像素单元包括第一像素电极、第二像素电极、第三像素电极、第一开关、第二开关以及第三开关，每个像素单元还包括一控制电路，第一像素电极通过第一开关与对应本像素单元的第一扫描线和数据线连接，第二像素电极通过第二开关与对应本像素单元的第一扫描线和第一开关连接，第三像素电极通过第三开关与对应本像素单元的第二扫描线和第二像素电极连接，控制电路分别连接对应本像素单元的第一扫描线和第二像素电极，控制电路在第一扫描线输入扫描信号时作用于第二像素电极，以改变第二像素电极的电压，并控制第二像素电极和公共电极之间的电压差不为零；在2D显示模式下，第一扫描线输入扫描信号以控制第一开关和第二开关导通，第一像素电极通过第一开关接收来自数据线的数据信号以处于显示对应2D画面的图像的状态，第二像素电极依次通过第一开关和第二开关接收来自数据线的数据信号以处于显示对应2D画面的图像的状态，控制电路作用于第二像素电极以使得第二像素电极的电压第一次改变，随后第一扫描线控制第一开关和第二开关断开，第二扫描线输入扫描信号以控制第三开关导通，以使得第二像素电极和第三像素电极电性连接，第三像素电极接收来自第二像素电极的数据信号以处于显示对应2D画面的图像的状态，使得第一次改变后的第二像素电极的电压通过第三像素电极进行第二次改变，第三开关在其导通的时间内控制第二像素电极和第三像素电极之间的电压差不为零，以使得第一像素电极、第二像素电极和第三像素电极两两之间的电压差均不为零，其中，在对一行像素单元所对应的第一扫描线进行扫描的同时，对与一行像素单元相邻且最近被扫描的上一行像素单元所对应的第二扫描线进行扫描；在3D显示模式下，第二扫描线控制第三开关断开，第一扫描线输入扫描信号以控制第一开关和第二开关导通，第一像素电极通过第一开关接收来自数据线的数据信号以处于显示对应3D画面的的状态，第二像素电极依次通过第一开关和第二开关接收来自数据线的数据信号以处于显示对应3D画面的图像的状态，控制电路作用于第二像素电极以改变第二像素电极的电压，以使得第一像素电极和第二像素电极之间的电压差不为零，第三像素电极在第三开关断开的作用下处于显示对应黑画面的图像的状态。
其中，控制电路包括第四开关和一电荷分享电容，第四开关包括控制端、第一端和第二端，第四开关的控制端连接对应本像素单元的第一扫描线，第四开关的第一端连接对应本像素单元的第二像素电极，第四开关的第二端连接电荷分享电容的的一端，电荷分享电容连接公共电极，在第一扫描线输入扫描信号时第四开关导通，以使得第二像素电极和电荷分享电容电性连接，第二像素电极的电压通过电荷分享电容第一次改变，第四开关在其导通的时间内控制第二像素电极和公共电极之间的电压差不为零。
其中，第四开关为一薄膜晶体管，第四开关的控制端对应为薄膜晶体管的栅极，第四开关的第一端对应为薄膜晶体管的源极，第四开关的第二端对应为薄膜晶体管的漏极，薄膜晶体管的宽长比小于第一设定值，以使得在其导通的时间内控制第二像素电极和公共电极之间的电压差不为零。
其中，阵列基板还包括位于阵列基板外围区域的开关单元和短路线；开关单元包括多个受控开关，受控开关包括控制端、输入端以及输出端，每个受控开关的输入端连接一行像素单元所对应的第一扫描线，输出端连接与一行像素单元相邻的上一行像素单元所对应的第二扫描线，所有受控开关的控制端与短路线连接；在2D显示模式下，短路线输入控制信号以控制所有受控开关导通，在一行像素单元所对应的第一扫描线输入扫描信号时，扫描信号通过受控开关同时输入至与受控开关的输出端连接的第二扫描线中，以控制相应的第三开关导通，在3D显示模式下，短路线输入控制信号以控制所有受控开关断开，以控制所有第三开关断开。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括多条第一扫描线、多条第二扫描线、多条数据线、多个像素单元以及用于输入公共电压的公共电极，每个像素单元对应一条第一扫描线、一条第二扫描线以及一条数据线；每个像素单元包括第一像素电极、第二像素电极、第三像素电极、第一开关、第二开关以及第三开关，每个像素单元还包括一控制电路，第一像素电极通过第一开关与对应本像素单元的第一扫描线和数据线连接，第二像素电极通过第二开关与对应本像素单元的第一扫描线和第一开关连接，第三像素电极通过第三开关与对应本像素单元的第二扫描线和第二像素电极连接，控制电路分别连接对应本像素单元的第一扫描线和第二像素电极，控制电路在第一扫描线输入扫描信号时作用于第二像素电极，以改变第二像素电极的电压，并控制第二像素电极和公共电极之间的电压差不为零；在2D显示模式下，第一扫描线输入扫描信号以控制第一开关和第二开关导通，第一像素电极通过第一开关接收来自数据线的数据信号以处于显示对应2D画面的图像的状态，第二像素电极依次通过第一开关和第二开关接收来自数据线的数据信号以处于显示对应2D画面的图像的状态，控制电路作用于第二像素电极以使得第二像素电极的电压第一次改变，随后第一扫描线控制第一开关和第二开关断开，第二扫描线输入扫描信号以控制第三开关导通，以使得第二像素电极和第三像素电极电性连接，第三像素电极接收来自第二像素电极的数据信号以处于显示对应2D画面的图像的状态，使得第一次改变后的第二像素电极的电压通过第三像素电极进行第二次改变，进而使得第一像素电极、第二像素电极和第三像素电极中的至少两个之间的电压差不为零；在3D显示模式下，第二扫描线控制第三开关断开，第一扫描线输入扫描信号以控制第一开关和第二开关导通，第一像素电极通过第一开关接收来自数据线的数据信号以处于显示对应3D画面的的状态，第二像素电极依次通过第一开关和第二开关接收来自数据线的数据信号以处于显示对应3D画面的图像的状态，控制电路作用于第二像素电极以改变第二像素电极的电压，以使得第一像素电极和第二像素电极之间的电压差不为零，第三像素电极在第三开关断开的作用下处于显示对应黑画面的图像的状态。
其中，控制电路包括第四开关和一电荷分享电容，第四开关包括控制端、第一端和第二端，第四开关的控制端连接对应本像素单元的第一扫描线，第四开关的第一端连接对应本像素单元的第二像素电极，第四开关的第二端连接电荷分享电容的的一端，电荷分享电容连接公共电极，在第一扫描线输入扫描信号时第四开关导通，以使得第二像素电极和电荷分享电容电性连接，第二像素电极的电压通过电荷分享电容第一次改变，第四开关在其导通的时间内控制第二像素电极和公共电极之间的电压差不为零。
其中，第四开关为一薄膜晶体管，第四开关的控制端对应为薄膜晶体管的栅极，第四开关的第一端对应为薄膜晶体管的源极，第四开关的第二端对应为薄膜晶体管的漏极，薄膜晶体管的宽长比小于第一设定值，以使得在其导通的时间内控制第二像素电极和公共电极之间的电压差不为零。
其中，多个像素单元分行排列，多条第一扫描线和第二扫描线也分行排列，在2D显示模式下，在对一行像素单元所对应的第一扫描线进行扫描的同时，对与一行像素单元相邻且最近被扫描的上一行像素单元所对应的第二扫描线进行扫描。
其中，阵列基板还包括位于阵列基板外围区域的开关单元和短路线；开关单元包括多个受控开关，受控开关包括控制端、输入端以及输出端，每个受控开关的输入端连接一行像素单元所对应的第一扫描线，输出端连接与一行像素单元相邻的上一行像素单元所对应的第二扫描线，所有受控开关的控制端与短路线连接；在2D显示模式下，短路线输入控制信号以控制所有受控开关导通，在一行像素单元所对应的第一扫描线输入扫描信号时，扫描信号通过受控开关同时输入至与受控开关的输出端连接的第二扫描线中，以控制相应的第三开关导通，在3D显示模式下，短路线输入控制信号以控制所有受控开关断开，以控制所有第三开关断开。
其中，第三像素电极所在区域的面积小于第一像素电极和第二像素电极所在区域的面积。
其中，在第二扫描线输入扫描信号以控制第三开关导通时，第三开关在其导通的时间内控制第二像素电极和第三像素电极之间的电压差不为零，以使得第一像素电极、第二像素电极和第三像素电极两两之间的电压差均不为零。
其中，第三开关为薄膜晶体管，薄膜晶体管的栅极与第二扫描线连接，薄膜晶体管的源极与第二像素电极连接，薄膜晶体管的漏极与第三像素电极连接，薄膜晶体管的宽长比小于第二设定值，以使得在其导通的时间内控制第二像素电极和第三像素电极之间的电压差不为零。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板，包括阵列基板、彩色滤光基板以及位于阵列基板之间的液晶层，阵列基板包括多条第一扫描线、多条第二扫描线、多条数据线、多个像素单元以及用于输入公共电压的公共电极，每个像素单元对应一条第一扫描线、一条第二扫描线以及一条数据线；每个像素单元包括第一像素电极、第二像素电极、第三像素电极、第一开关、第二开关以及第三开关，每个像素单元还包括一控制电路，第一像素电极通过第一开关与对应本像素单元的第一扫描线和数据线连接，第二像素电极通过第二开关与对应本像素单元的第一扫描线和第一开关连接，第三像素电极通过第三开关与对应本像素单元的第二扫描线和第二像素电极连接，控制电路分别连接对应本像素单元的第一扫描线和第二像素电极，控制电路在第一扫描线输入扫描信号时作用于第二像素电极，以改变第二像素电极的电压，并控制第二像素电极和公共电极之间的电压差不为零；在2D显示模式下，第一扫描线输入扫描信号以控制第一开关和第二开关导通，第一像素电极通过第一开关接收来自数据线的数据信号以处于显示对应2D画面的图像的状态，第二像素电极依次通过第一开关和第二开关接收来自数据线的数据信号以处于显示对应2D画面的图像的状态，控制电路作用于第二像素电极以使得第二像素电极的电压第一次改变，随后第一扫描线控制第一开关和第二开关断开，第二扫描线输入扫描信号以控制第三开关导通，以使得第二像素电极和第三像素电极电性连接，第三像素电极接收来自第二像素电极的数据信号以处于显示对应2D画面的图像的状态，使得第一次改变后的第二像素电极的电压通过第三像素电极进行第二次改变，进而使得第一像素电极、第二像素电极和第三像素电极中的至少两个之间的电压差不为零；在3D显示模式下，第二扫描线控制第三开关断开，第一扫描线输入扫描信号以控制第一开关和第二开关导通，第一像素电极通过第一开关接收来自数据线的数据信号以处于显示对应3D画面的的状态，第二像素电极依次通过第一开关和第二开关接收来自数据线的数据信号以处于显示对应3D画面的图像的状态，控制电路作用于第二像素电极以改变第二像素电极的电压，以使得第一像素电极和第二像素电极之间的电压差不为零，第三像素电极在第三开关断开的作用下处于显示对应黑画面的图像的状态。
其中，控制电路包括第四开关和一电荷分享电容，第四开关包括控制端、第一端和第二端，第四开关的控制端连接对应本像素单元的第一扫描线，第四开关的第一端连接对应本像素单元的第二像素电极，第四开关的第二端连接电荷分享电容的的一端，电荷分享电容连接公共电极，在第一扫描线输入扫描信号时第四开关导通，以使得第二像素电极和电荷分享电容电性连接，第二像素电极的电压通过电荷分享电容第一次改变，第四开关在其导通的时间内控制第二像素电极和公共电极之间的电压差不为零。
其中，第四开关为一薄膜晶体管，第四开关的控制端对应为薄膜晶体管的栅极，第四开关的第一端对应为薄膜晶体管的源极，第四开关的第二端对应为薄膜晶体管的漏极，薄膜晶体管的宽长比小于第一设定值，以使得在其导通的时间内控制第二像素电极和公共电极之间的电压差不为零。
其中，多个像素单元分行排列，多条第一扫描线和第二扫描线也分行排列，在2D显示模式下，在对一行像素单元所对应的第一扫描线进行扫描的同时，对与一行像素单元相邻且最近被扫描的上一行像素单元所对应的第二扫描线进行扫描。
其中，阵列基板还包括位于阵列基板外围区域的开关单元和短路线；开关单元包括多个受控开关，受控开关包括控制端、输入端以及输出端，每个受控开关的输入端连接一行像素单元所对应的第一扫描线，输出端连接与一行像素单元相邻的上一行像素单元所对应的第二扫描线，所有受控开关的控制端与短路线连接；在2D显示模式下，短路线输入控制信号以控制所有受控开关导通，在一行像素单元所对应的第一扫描线输入扫描信号时，扫描信号通过受控开关同时输入至与受控开关的输出端连接的第二扫描线中，以控制相应的第三开关导通，在3D显示模式下，短路线输入控制信号以控制所有受控开关断开，以控制所有第三开关断开。
其中，第三像素电极所在区域的面积小于第一像素电极和第二像素电极所在区域的面积。
其中，在第二扫描线输入扫描信号以控制第三开关导通时，第三开关在其导通的时间内控制第二像素电极和第三像素电极之间的电压差不为零，以使得第一像素电极、第二像素电极和第三像素电极两两之间的电压差均不为零。
其中，第三开关为薄膜晶体管，薄膜晶体管的栅极与第二扫描线连接，薄膜晶体管的源极与第二像素电极连接，薄膜晶体管的漏极与第三像素电极连接，薄膜晶体管的宽长比小于第二设定值，以使得在其导通的时间内控制第二像素电极和第三像素电极之间的电压差不为零。
本发明的有益效果是：区别于现有技术的情况，本发明的阵列基板中，每个像素单元包括第一像素电极、第二像素电极以及第三像素电极，一控制电路作用于第二像素电极，第三像素电极通过第三开关与第二像素电极连接。在2D显示模式下第一扫描线输入扫描信号时，第一像素电极通过第一开关接收来自数据线的数据信号，第二像素电极依次通过第一开关和第二开关接收收来自数据线的数据信号，以处于显示对应2D画面的图像的状态，控制电路作用于第二像素电极以使得第二像素电极的电压第一次改变，从而使得第一像素电极和第二像素电极的电压不相同，能够减小大视角下的颜色差异，并且在第一扫描线停止输入扫描信号后，使第三开关导通以使得第二像素电极和第三像素电极电性连接，第三像素电极接收来自第二像素电极的数据信号以处于显示对应2D画面的图像的状态，由此使得在2D显示模式下第一至第三像素电极均处于显示对应2D画面的图像的状态，能够提高开口率，此外第二像素电极的电压通过第三像素电极进行第二次改变，使得三个像素电极中的至少两个的电压不相同，同时也使得第二像素电极和第一像素电极之间的电压差异增大，能够进一步减小大视角下的颜色差异，减小色彩失真。在3D显示模式下，第一像素电极通过第一开关接收来自数据线的数据信号，第二像素电极依次通过第一开关和第二开关接收来自数据线的数据信号，以处于显示对应3D画面的图像的状态，控制电路作用于第二像素电极以改变第二像素电极的电压，使得第一像素电极和第二像素电极的电压不相同，能够减小大视角下的颜色差异，并且3D显示模式下控制第三像素电极处于显示对应黑画面的图像的状态，由此能够降低双眼信号串扰。
【附图说明】
图1是本发明阵列基板一实施方式的结构示意图；
图2是图1中一个像素单元的结构示意图；
图3是图1中像素单元的结构等效电路图；
图4是图1中像素单元的第三像素电极在3D显示模式下的显示效果示意图；
图5是本发明阵列基板另一实施方式中，像素单元的结构等效电路图；
图6是本发明液晶显示面板一实施方式的结构示意图。
【具体实施方式】
下面将结合实施方式和附图对本发明进行详细说明。
参阅图1，本发明阵列基板的一实施方式中，阵列基板包括多条第一扫描线11、多条第二扫描线12、多条数据线13、多个像素单元14以及用于输入公共电压的公共电极15。多个像素单元14呈阵列排列，每个像素单元14与一条第一扫描线11、一条第二扫描线12以及一条数据线13连接。
其中，结合图2和图3，每个像素单元14包括第一像素电极M1、第二像素电极M2、第三像素电极M3，以及分别作用于第一像素电极M1、第二像素电极M2以及第三像素电极M3的第一开关T1、第二开关T2和第三开关T3。每个开关均包括控制端、输入端以及输出端。其中，第一开关T1的控制端和第二开关T2的控制端与对应本像素单元14的第一扫描线11电性连接，第一开关T1的输入端与对应本像素单元14的数据线13电性连接，第一开关T1的输出端与第一像素电极M1电性连接，第二开关T2的输入端与第一像素电极M1电性连接，也即第二开关T2的输入端与第一开关T1的输出端电性连接，第二开关T2的输出端与第二像素电极M2电性连接。第三开关T3的控制端与对应本像素单元14的第二扫描线12电性连接，第三开关T3的输入端与第二像素电极M2电性连接，第三开关T3的输出端与第三像素电极M3电性连接。
本实施方式的第一开关T1、第二开关T2以及第三开关T3均为薄膜晶体管，其中，三个开关T1、T2、T3的控制端对应为薄膜晶体管的栅极，输入端对应为薄膜晶体管的源极，输出端对应为薄膜晶体管的漏极。当然，在其他实施方式中，三个开关也可以是三极管、达林顿管等开关元件。
每个像素单元14还包括一控制电路16，控制电路16分别与对应本像素单元14的第一扫描线11和第二像素电极M2连接，在第一扫描线11输入扫描信号的时候控制电路16作用于第二像素电极M2，以改变第二像素电极M2的电压，并控制第二像素电极M2和公共电极15之间的电压差不为零。具体地，本实施方式的控制电路16包括第四开关T4和电荷分享电容Ca。第四开关T4包括控制端、输入端和输出端。其中，第四开关T4的控制端与第一扫描线11电性连接，第四开关T4的第一端与第二像素电极M2电性连接，第四开关T4的第二端电荷分享电容Ca的一端连接，电荷分享电容Ca的另一端与公共电极15电性连接。其中，第四开关T4为薄膜晶体管，第四开关T4的控制端对应为薄膜晶体管的栅极，第四开关T4的第一端对应为薄膜晶体管的源极，第四开关T4的第二端对应为薄膜晶体管的漏极。当第一扫描线11输入扫描信号时第四开关T4导通，从而使得第二像素电极M2和电荷分享电容Ca电性连接，第二像素电极M2通过与电荷分享电容Ca之间的电荷分享而使得其电压改变，并且第四开关T4在其导通的时间内控制第二像素电极M2和公共电极15之间的电压差不为零，以保证第二像素电极M2处于正常显示图像的状态。
通过本实施方式的阵列基板，能够降低2D和3D显示模式下大视角观察到的颜色差异，同时能够提高2D显示模式下的开口率，降低3D显示模式下的双眼信号串扰。
具体地，在2D显示模式下，本实施方式采用逐行扫描的方式对第一扫描线11和第二扫描线12进行扫描。公共电极15输入公共电压。在正极性（即数据信号大于公共电压）反转驱动时，第一扫描线11输入高电平的扫描信号以控制第一开关T1和第二开关T2导通，数据线13输入数据信号，第一像素电极M1通过第一开关T1接收来自数据线13的数据信号而处于显示对应2D画面的图像的状态，第二像素电极M2依次通过第一开关T1和第二开关T2接收数据信号而处于显示对应2D画面的图像的状态，此时第二像素电极M2的电压因受第一开关T1和第二开关T2的阻抗影响而略低于第一像素电极M1的电压，使得第一像素电极M1和第二像素电极M2之间存在一定的电压差异。在第一扫描线11输入高电平的扫描信号时，第四开关T4也同时接收该扫描信号而导通，从而使得第二像素电极M2和电荷分享电容Ca电性连接。第二像素电极M2的电压通过电荷分享电容Ca第一次改变，即第二像素电极M2通过电荷分享电容Ca放电，使得第二像素电极M2的电压进一步降低，从而使得第一像素电极M1和第二像素电极M2之间的电压差异增大。
完成第一扫描线11的扫描后，第一扫描线11停止输入高电平的扫描信号以使得第一开关T1、第二开关T2和第四开关T4断开，第二扫描线12输入高电平的扫描信号以控制第三开关T3导通，此时第二像素电极M2和第三像素电极M3通过第三开关T3电性连接，第三像素电极M3接收来自第二像素电极M2的数据信号后处于显示对应2D画面的图像的状态。因此，在2D显示模式下，三个像素电极M1、M2、M3均处于显示对应2D画面的图像的状态，由此能够提高2D显示模式的开口率。而第二像素电极M2的电压通过第三像素电极M3进行第二次改变，即在第三开关T3导通时第二像素电极M2的电压通过与液晶电容Clc3（由第三像素电极M3和另一基板的公共电极之间夹有液晶分子而造成的等效电容）之间的电荷分享而第二次改变。具体为，第二像素电极M2的部分电荷转移至第三像素电极M3中，使得第二像素电极M2的电压再一次被降低，直至第二像素电极M2的电压和第三像素电极M3的电压相同，此时第一像素电极M1分别与第二像素电极M2和第三像素电极M3之间存在一定的电压差异。
在负极性（即数据信号小于公共电压）反转时，第一扫描线11输入高电平的扫描信号以控制第一开关T1和第二开关T2导通，数据线13输入数据信号，第一像素电极M1通过第一开关T1接收来自数据线13的数据信号而处于显示对应2D画面的图像的状态，第二像素电极M2依次通过第一开关T1和第二开关T2接收数据信号而处于显示对应2D画面的图像的状态，此时第二像素电极M2的电压因受第一开关T1和第二开关T2的阻抗影响而略低于第一像素电极M1的电压，使得第一像素电极M1和第二像素电极M2之间存在一定的电压差异。在第一扫描线11输入高电平的扫描信号时，第四开关T4也同时接收该扫描信号而导通，从而使得第二像素电极M2和电荷分享电容Ca电性连接。第二像素电极M2的电压通过电荷分享电容Ca第一次改变，即第二像素电极M2通过电荷分享电容Ca充电，使得第二像素电极M2的电压第一次增加，从而使得第二像素电极M2和第一像素电极M1之间存在一定的电压差。
完成第一扫描线11的扫描后，第一扫描线11停止输入高电平的扫描信号以使得第一开关T1、第二开关T2和第四开关T4断开，第二扫描线12输入高电平的扫描信号以控制第三开关T3导通，此时第二像素电极M2和第三像素电极M3通过第三开关T3电性连接。由于第三像素电极M3保留着前一时帧时的正极性电压，因此在第三开关T3导通时第三像素电极M3的部分电荷转移至第二像素电极M2中，使得第二像素电极M2的电压再次增加，直至第二像素电极M2的电压和第三像素电极M3的电压相同，由于第一像素电极M1的电压保持不变而使得第一像素电极M1分别与第二像素电极M2和第三像素电极M3之间存在一定的电压差异。
因此，在正极性反转（或负极性反转）期间，在扫描第一扫描线11的时帧里，第二像素电极M2的电压在第四开关T4和电荷分享电容Ca的作用下第一次降低（或增加），在扫描第二扫描线12的时帧里，第二像素电极M2的电压通过第三像素电极M3的电荷分享而再次降低（或增加），第二像素电极M2的电压经历了两次的降低（或增加），从而使得第二像素电极M2和公共电极15之间的电压差异减小，同时也使得第二像素电极M2和第一像素电极M1之间的电压差异（也即第三像素电极M3和第一像素电极M1的电压差异）进一步增大，由此能够进一步改善大视角的颜色失真。
此外，第四开关T4在导通时使得第二像素电极M2和公共电极15之间的电压差异减小，然而为了使第二像素电极M2能够处于正常显示图像的状态，第四开关T4在其导通的时间内控制第二像素电极M2和公共电极15之间的电压差不为零，即通过第四开关T4的作用使得第二像素电极M2的电压不会降低（或增加）至公共电极15的电压。具体地，第四开关T4导通的时间即为第一扫描线11输入扫描信号的时间，在正极性反转时，通过第四开关T4的控制作用，使得在第四开关T4导通的时间内第二像素电极M2对电荷分享电容Ca只释放部分的电荷，第二像素电极M2的电压降低但不会降低至与公共电极15相同的电压；在负极性反转时，通过第四开关T4的控制作用，使得在第四开关T4导通的时间内电荷分享电容Ca对第二像素电极M2只转移部分电荷，使得第二像素电极M2的电压增加但不会增加至与公共电极15相同的电压，由此使得第二像素电极M2和公共电极15之间仍然存在一定的电压差，以保证第二像素电极M2处于正常显示图像的状态。进一步地，可通过控制第四开关T4在导通时的电流通过能力来控制第二像素电极M2和电荷分享电容Ca之间的电荷转移速度，该电流通过能力指第四开关T4在导通时允许流过的电流大小，例如使第四开关T4在导通时的电流通过能力较小，以使得第二像素电极M2和电荷分享电容Ca之间的电荷转移速度较慢，从而在第四开关T4导通的时间内使得第二像素电极M2和公共电极15之间仍然存在一定的电压差。本实施方式的第四开关T4为薄膜晶体管，薄膜晶体管在导通时能通过的电流的大小与薄膜晶体管的宽长比有关，宽长比越小，薄膜晶体管在导通时能流过的电流越小，其电流通过能力也就越小，薄膜晶体管的宽长比越大，其在导通时能流过的电流越大，电流通过能力也就越大。因此，通过控制第四开关T4的宽长比，使其宽长比小于第一设定值，使得第四开关T4在导通时的电流通过能力小于一定值，从而使得第四开关T4在导通时控制第二像素电极M2和电荷分享电容Ca之间的电荷转移速度也小于一定值，以保证在第四开关T4导通的时间内第二像素电极M2和公共电极15之间的电压差不为零。该第一设定值可根据实际情况进行选择，在保证在第四开关T4导通的时间内第二像素电极M2和公共电极15之间的电压差不为零、且又能够使得第二像素电极M2和电荷分享电容Ca之间电荷共享（若第一设定值过小，则有可能导致第四开关T4能通过的电流为零而使得第二像素电极M2的电压无法改变）的条件下，该第一设定值允许有多种选择，例如可以是0.3，或者其他比值。
当然，在其他实施方式中，也可以通过控制第四开关的栅极电压的大小来控制第四开关在导通时的电流通过能力，栅极电压越大其电流通过能力越大，反之越小。并且，第四开关也可以是三极管等，对此不进行限定。
在完成一行像素单元14所对应的第一扫描线11和第二扫描线12的扫描后，对下一行像素单元对应的第一扫描线11和第二扫描线12进行扫描，以此类推。
在3D显示模式下，结合图4，首先利用黑画面信号关闭第三像素电极M3，即数据线13对第一像素电极M1和第二像素电极M2输入显示对应黑画面的数据信号，控制第三开关T3导通使得第三像素电极M3处于显示对应黑画面的图像的状态。关闭第三像素电极M3后，第一扫描线11输入高电平的扫描信号以控制第一开关T1和第二开关T2导通，数据线13输入数据信号，第一像素电极M1通过第一开关T1接收数据信号以处于显示对应3D画面的图像的状态，，第二像素电极M2依次通过第一开关T1、第二开关T2接收数据信号以处于显示对应3D画面的图像的状态。此时第二像素电极M2的电压因受第一开关T1和第二开关T2的阻抗影响而略低于第一像素电极M1的电压，使得第一像素电极M1和第二像素电极M2之间存在一定的电压差异。第四开关T4在第一扫描线11输入扫描信号时也处于导通状态，使得第二像素电极M2和电荷分享电容Ca电性连接，第二像素电极M2通过与电荷分享电容Ca之间的电荷分享而使得其电压发生改变，即正极性反转时第二像素电极M2对电荷分享电容Ca放电而使得其电压降低，负极性反转时第二像素电极M2通过电荷分享电容Ca充电而使得其电压增加，由此使得第二像素电极M2的电压和第一像素电极M1的电压不相同，两者之间具有一定的电压差异，由此能够改善3D显示模式下的颜色失真。第四开关T4在其导通的时间内控制第二像素电极M2和公共电极15之间的电压差不为零，以保证第二像素电极M2处于正常显示对应3D画面的图像的状态。此外，在3D显示模式下，关闭第二扫描线12，即不对第二扫描线12输入扫描信号，以控制第三开关T3处于断开的状态，从而使得第三像素电极M3保持处于显示对应黑画面的图像的状态。
本实施方式中，第一像素电极M1、第二像素电极M2以及第三像素电极M3沿列方向依次排列，相邻两行像素单元14分别显示对应3D画面的左眼图像和右眼图像。在3D显示模式下，如图4所示，通过第三开关T3的断开作用使得第三像素电极M3处于显示对应黑画面的图像的状态，该处于显示对应黑画面的图像的状态的第三像素电极M3为遮光区域（等效于黑矩阵，Black Matrix，BM），从而使得相邻两行像素单元14中，对应显示左眼图像的像素电极（一行像素单元中的第二像素电极和第三像素电极）和对应显示右眼图像的像素电极（另一行像素单元中的第二像素电极和第三像素电极）之间存在一遮光区域，通过该遮光区域阻挡左眼图像和右眼图像的串扰信号，从而能够降低3D显示模式下的双眼信号串扰。此外，第三像素电极M3主要用于在3D显示模式下形成遮光区域以降低3D信号串扰，因此第三像素电极M3所在区域的面积均小于第一像素电极M1和第二像素电极M2所在区域的面积，当然也可根据实际的遮光需要设计第三像素电极M3所占的面积，以尽可能减少3D双眼信号串扰现象。
通过本实施方式的阵列基板，能够提高2D显示模式下的开口率，有效改善2D和3D显示模式下的颜色失真，具有较好的低色偏效果，同时也能降低3D显示模式下的双眼信号串扰。
在备选实施方式中，三个像素电极也可以沿行方向排列，此时相邻两列像素单元分别处于显示对应3D画面的左眼图像和右眼图像的状态。通过处于显示对应黑画面的图像的状态的第三像素电极，能够减少3D显示模式下的双眼信号串扰。此外，在3D显示模式时，也可以利用插黑的方式使第三像素电极处于显示黑画面的状态，并且在第一扫描线的消隐时间（Blanking time）进行插黑。进一步而言，在一个扫描时帧里使第一像素电极和第二像素电极处于显示对应3D画面的图像的状态，而第三像素电极仍然处于显示对应黑画面的图像的状态，而在下一个扫描时帧里使第一像素电极、第二像素电极、以及第三像素电极均处于显示对应黑画面的图像的状态，之后第一像素电极和第二像素电极又恢复到处于显示3D画面的图像的状态，而第三像素电极仍然保持处于显示对应3D画面的图像的状态，即第一像素电极和第二像素电极交替处于显示3D画面的图像的状态和处于显示对应黑画面的图像的状态，而第三像素电极一直保持着显示对应3D画面的图像的状态。通过上述插黑方式，能够防止第二像素电极由于漏电而出现漏光。
在其他实施方式中，控制电路也可以使用一分压电阻和一开关元件实现，使第二像素电极通过触发开关与分压电阻连接，在第一扫描线输入扫描信号触发开关元件导通时，第二像素电极的电压通过分压电阻而改变，改变分压电阻的大小可以改变第二像素电极的电压改变的程度。采用此种方式同样能够改变第二像素电极的电压而使得第一像素电极和第二像素电极之间具有一定的电压差，从而达到低色偏的效果。此外，控制电路也可以仅使用一分压电阻实现，使第二像素电极直接与分压电阻连接，以通过分压电阻改变第二像素电极的电压。
在上述实施方式中，第三开关T3为常规性的薄膜晶体管，第三开关T3在导通时第二像素电极M2的电压最终与第三像素电极M3的电压相同，由此使得第二像素电极M2、第三像素电极M2与第一像素电极M1之间具有一定的电压差，以达到低色偏的效果。在备选实施方式中，也可以设计第三开关，通过第三开关的作用使得第二像素电极和第三像素电极之间的电压不相同，从而使得第一像素电极、第二像素电极以及第三像素电极两两之间存在一定电压差异。具体地，在第二扫描线输入扫描信号以控制第三开关导通时，第三开关在其导通的时间内控制第二像素电极和第三像素电极之间的电压差不为零，使得在第三开关导通的时间内不会使得第二像素电极和第三像素电极之间达到放电平衡状态，即第二像素电极的电压和第三像素电极的电压不相同，从而使得第一像素电极、第二像素电极以及第三像素电极两两之间的电压均不相同，由此能够进一步减小2D显示模式下大视角的颜色差异，提高低色偏效果。
进一步地，本实施方式的第三开关为具有特定宽长比的薄膜晶体管，可通过控制第三开关的宽长比来控制第三开关在其导通内控制第二像素电极和第三像素电极之间的电压差不为零，即通过控制第三开关的宽长比来控制第三开关在导通时的电流通过能力。第三开关的宽长比越大，第三开关在导通时的电流通过能力越大，第二像素电极和第三像素电极之间的电荷转移速度也越快，而第三开关的宽长比越小，第三开关在导通时的电流通过能力越小，第二像素电极和第三像素电极之间的电荷转移速度也越慢。为了保证在第三开关导通的时间内使得第二像素电极的电压和第三像素电极的电压不相同，可控制第二像素电极和第三像素电极之间的电荷转移速度较慢，进一步可通过使得第三开关的宽长比小于第二设定值，例如该第二设定值可以为0.2，以使得在第三开关导通的时间内第二像素电极和第三像素电极之间的电压差不为零，从而使得三个像素电极两两之间的电压差均不为零，进而能够获得更好的低色偏效果。在其他实施方式中，也可以通过控制第三开关的栅极电压的大小（即第二扫描线所输入的扫描信号的大小）来控制第三开关在导通时的电流通过能力，以使得第三开关在其导通的时间内控制第二像素电极和第三像素电极之间的电压差不为零。
在上述各实施方式中，在2D显示模式下逐行对第一、第二扫描线进行扫描，参阅图5，本发明阵列基板另一实施方式中，也可以同时扫描对应不同像素单元的第一扫描线和第二扫描线。第一扫描线（图中仅示出3条，包括第一扫描线51_1、51_2、51_3）和第二扫描线（图中仅示出3条，包括第二扫描线52_1、52_2、52_3）沿行方向延伸。在2D显示模式下，以相邻的第一行像素单元A1和第二行像素单元A2为例进行说明，在对第二行像素单元A2所对应的第一扫描线51_2扫描的同时，对与第二行像素单元A2相邻的上一行最近被扫描的第一行像素单元A1所对应的第二扫描线52_1进行扫描。
具体地，本实施方式的阵列基板还包括位于阵列基板外围区域的开关单元55和一条短路线56。开关单元55包括多个受控开关（包括受控开关T5_1、T5_2）。受控开关包括控制端、输入端和输出端。以第一行像素单元A1和第二行像素单元A2之间的受控开关T5_1进行说明，受控开关T5_1的输入端连接第二行像素单元A2对应的第一扫描线51_2，受控开关T5_1的输出端连接第一行像素单元A1对应的第二扫描线52_1，所有受控开关的控制端均与短路线56连接。其中，受控开关T5_1为薄膜晶体管，受控开关T5_1的控制端对应为薄膜晶体管的栅极，受控开关T5的输入端对应为薄膜晶体管的源极，受控开关T5_1的输出端对应为薄膜晶体管的漏极。
在2D显示模式下，短路线56输入高电平的控制信号以控制所有受控开关导通，然后逐行扫描第一扫描线。首先第一行像素单元A1对应的第一扫描线51_1输入扫描信号以控制第一行像素单元A1中的第一开关T1和第二开关T2导通，数据线53输入数据信号，以使得第一行像素单元A1中的第一像素电极M1和第二像素电极M2处于显示对应2D画面的图像的状态。第四开关T4在第一扫描线51_1输入扫描信号时导通，使得第二像素电极M2和电荷分享电容Ca电性连接，第二像素电极M2通过与电荷分享电容Ca之间的电荷分享而使得其电压第一次改变，从而使得第一像素电极M1和第二像素电极M2之间存在一定的电压差异，由此能够改善2D显示模式下大视角下的颜色差异，提高显示品质。
完成第一行像素单元A1对应的第一扫描线51_1的扫描之后，第二行像素单元A2所对应的第一扫描线51_2输入扫描信号以控制第二行像素单元A2中的第一开关T1、第二开关T2和第四开关T4导通，与此同时，由于受控开关T5_1为导通状态，第二行像素单元A2对应的第一扫描线51_2所输入的扫描信号通过受控开关T5_1输入至第一行像素单元A1所对应的第二扫描线52_1中，以控制第一行像素单元A1中的第三开关T3导通，从而使得第一行像素单元A1中的第二像素电极M2和第三像素电极M3电性连接，由此使得第一行像素单元A1中的第三像素电极M3处于显示对应2D画面的图像的状态，能够提高2D显示模式下的开口率，并且第一行像素单元A1中的第二像素电极M2通过与第三像素电极M3之间的电荷分享而使得其电压第二次改变，进而使得第一行像素单元A1中的第二像素电极M2和第三像素电极M3与第一像素电极之间的电压差异进一步增大，能够进一步提高低色偏效果，具体的原理可参考上述实施方式，此处不进行一一赘述。在完成第二行像素单元A2所对应的第一扫描线51_2的扫描后，对下一行像素单元A3所对应的第一扫描线51_3进行扫描，与此同时，通过受控开关T5_2使得第二行像素单元A2所对应的第二扫描线52_2也同时进行扫描。
在3D显示模式下，短路线56输入控制信号以控制所有受控开关处于断开状态，对第一扫描线51_1输入扫描信号以控制第一行像素单元A1中的第一开关T1和第二开关T2导通，数据线53输入数据信号，以使得第一行像素单元A1中的第一像素电极M1和第二像素电极M2处于显示对应3D画面的图像的状态。第四开关T4在第一扫描线51_1输入扫描信号时导通，使得第二像素电极M2的电压第一次改变，使得第一像素电极M1和第二像素电极M2的电压不相同，从而两者之间具有一定的电压差异，由此能够改善3D显示模式下大视角的颜色差异，提高显示品质。
完成第一行像素单元A1对应的第一扫描线51_1的扫描之后，对第二行像素单元A2对应的第一扫描线51_2输入扫描信号以控制第二行像素单元A2中的第一开关T1、第二开关T2和第四开关T4导通，而由于受控开关T5_1处于断开状态，因此第二行像素单元A2对应的第一扫描线51_2输入的扫描信号不会进入第一行像素单元A1中的第三开关T3，以控制第三开关T3处于断开状态，从而使得第一行像素单元A1中的第三像素电极M3保持处于显示对应黑画面的图像的状态，通过该处于显示黑画面的图像的状态的第三像素电极M3能够降低3D显示模式下的双眼信号串扰。完成第二行像素单元A2对应的第一扫描线51_2的扫描后，以相同方式对剩余的第一扫描线进行扫描，而在3D显示模式下开关单元55中的所有受控开关始终为断开状态，以使得第二扫描线为关闭状态。。
通过本实施方式的开关单元55和短路线55，仅需一个扫描驱动芯片对短路线56施加控制信号以控制开关单元55中的受控开关的导通或关闭，从而相应控制第三开关T3导通或断开，不仅能够实现2D显示模式下的低色偏和较高开口率，以及3D显示模式下的低色偏和低串扰，同时能够减少扫描驱动芯片的数量，降低成本。并且，在同一扫描时帧里同时对两条扫描线（如第一行像素单元A1对应的第二扫描线52_1和第二行像素单元A2对应的第一扫描线51_2）进行扫描，从而相应延长了每一条扫描线的扫描时间，有助于进行高更新频率的操作。
此外，在其他实施方式中，也可以不采用上述的开关单元55和短路线55实现对应不同行像素单元的第一扫描线和第二扫描线的同时扫描，而是使各条扫描线（包括第一扫描线和第二扫描线）相互独立，每条扫描线连接一个扫描驱动芯片以单独控制一条扫描线的扫描，由此在对一行像素单元对应的第一扫描线输入扫描信号时，同时也对上一行像素单元对应的第二扫描线输入扫描信号，采用这种方式同样能够实现同时对两条扫描线进行扫描。
参阅图6，本发明液晶显示面板的一实施方式中，液晶显示面板包括阵列基板601、彩色滤光基板602以及位于阵列基板601和彩色滤光基板602之间的液晶层603。其中，阵列基板601为上述各实施方式中的阵列基板。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (20)

  1. 一种阵列基板，其中，包括多条分行排列的第一扫描线、多条分行排列的第二扫描线、多条数据线、多个分行排列的像素单元以及用于输入公共电压的公共电极，每个所述像素单元对应一条第一扫描线、一条第二扫描线以及一条数据线；
    每个所述像素单元包括第一像素电极、第二像素电极、第三像素电极、第一开关、第二开关以及第三开关，每个所述像素单元还包括一控制电路，所述第一像素电极通过所述第一开关与对应本像素单元的所述第一扫描线和所述数据线连接，所述第二像素电极通过所述第二开关与对应本像素单元的所述第一扫描线和所述第一开关连接，所述第三像素电极通过所述第三开关与对应本像素单元的所述第二扫描线和所述第二像素电极连接，所述控制电路分别连接对应本像素单元的所述第一扫描线和所述第二像素电极，所述控制电路在所述第一扫描线输入扫描信号时作用于所述第二像素电极，以改变所述第二像素电极的电压，并控制所述第二像素电极和所述公共电极之间的电压差不为零；
    在2D显示模式下，所述第一扫描线输入扫描信号以控制所述第一开关和第二开关导通，所述第一像素电极通过第一开关接收来自所述数据线的数据信号以处于显示对应2D画面的图像的状态，所述第二像素电极依次通过所述第一开关和第二开关接收来自所述数据线的数据信号以处于显示对应2D画面的图像的状态，所述控制电路作用于所述第二像素电极以使得所述第二像素电极的电压第一次改变，随后所述第一扫描线控制所述第一开关和第二开关断开，所述第二扫描线输入扫描信号以控制所述第三开关导通，以使得所述第二像素电极和所述第三像素电极电性连接，所述第三像素电极接收来自所述第二像素电极的数据信号以处于显示对应2D画面的图像的状态，使得第一次改变后的所述第二像素电极的电压通过所述第三像素电极进行第二次改变，所述第三开关在其导通的时间内控制所述第二像素电极和第三像素电极之间的电压差不为零，以使得所述第一像素电极、第二像素电极和第三像素电极两两之间的电压差均不为零，其中，在对一行所述像素单元所对应的第一扫描线进行扫描的同时，对与所述一行像素单元相邻且最近被扫描的上一行像素单元所对应的第二扫描线进行扫描；
    在3D显示模式下，所述第二扫描线控制所述第三开关断开，所述第一扫描线输入扫描信号以控制所述第一开关和第二开关导通，所述第一像素电极通过所述第一开关接收来自所述数据线的数据信号以处于显示对应3D画面的的状态，所述第二像素电极依次通过所述第一开关和第二开关接收来自所述数据线的数据信号以处于显示对应3D画面的图像的状态，所述控制电路作用于所述第二像素电极以改变所述第二像素电极的电压，以使得所述第一像素电极和第二像素电极之间的电压差不为零，所述第三像素电极在第三开关断开的作用下处于显示对应黑画面的图像的状态。
  2. 根据权利要求1所述的阵列基板，其中，
    所述控制电路包括第四开关和一电荷分享电容，所述第四开关包括控制端、第一端和第二端，所述第四开关的控制端连接对应本像素单元的所述第一扫描线，所述第四开关的第一端连接对应本像素单元的所述第二像素电极，所述第四开关的第二端连接所述电荷分享电容的的一端，所述电荷分享电容连接所述公共电极，在所述第一扫描线输入扫描信号时所述第四开关导通，以使得所述第二像素电极和所述电荷分享电容电性连接，所述第二像素电极的电压通过所述电荷分享电容第一次改变，所述第四开关在其导通的时间内控制所述第二像素电极和公共电极之间的电压差不为零。
  3. 根据权利要求2所述的阵列基板，其中，
    所述第四开关为一薄膜晶体管，所述第四开关的控制端对应为薄膜晶体管的栅极，所述第四开关的第一端对应为薄膜晶体管的源极，所述第四开关的第二端对应为薄膜晶体管的漏极，所述薄膜晶体管的宽长比小于第一设定值，以使得在其导通的时间内控制所述第二像素电极和公共电极之间的电压差不为零。
  4. 根据权利要求1所述的阵列基板，其中，
    所述阵列基板还包括位于阵列基板外围区域的开关单元和短路线；
    所述开关单元包括多个受控开关，所述受控开关包括控制端、输入端以及输出端，每个所述受控开关的输入端连接一行所述像素单元所对应的第一扫描线，输出端连接与所述一行像素单元相邻的上一行像素单元所对应的第二扫描线，所有所述受控开关的控制端与所述短路线连接；
    在2D显示模式下，所述短路线输入控制信号以控制所有所述受控开关导通，在一行所述像素单元所对应的第一扫描线输入扫描信号时，所述扫描信号通过所述受控开关同时输入至与所述受控开关的输出端连接的第二扫描线中，以控制相应的第三开关导通，在3D显示模式下，所述短路线输入控制信号以控制所有所述受控开关断开，以控制所有所述第三开关断开。
  5. 一种阵列基板，其中，包括多条第一扫描线、多条第二扫描线、多条数据线、多个像素单元以及用于输入公共电压的公共电极，每个所述像素单元对应一条第一扫描线、一条第二扫描线以及一条数据线；
    每个所述像素单元包括第一像素电极、第二像素电极、第三像素电极、第一开关、第二开关以及第三开关，每个所述像素单元还包括一控制电路，所述第一像素电极通过所述第一开关与对应本像素单元的所述第一扫描线和所述数据线连接，所述第二像素电极通过所述第二开关与对应本像素单元的所述第一扫描线和所述第一开关连接，所述第三像素电极通过所述第三开关与对应本像素单元的所述第二扫描线和所述第二像素电极连接，所述控制电路分别连接对应本像素单元的所述第一扫描线和所述第二像素电极，所述控制电路在所述第一扫描线输入扫描信号时作用于所述第二像素电极，以改变所述第二像素电极的电压，并控制所述第二像素电极和所述公共电极之间的电压差不为零；
    在2D显示模式下，所述第一扫描线输入扫描信号以控制所述第一开关和第二开关导通，所述第一像素电极通过第一开关接收来自所述数据线的数据信号以处于显示对应2D画面的图像的状态，所述第二像素电极依次通过所述第一开关和第二开关接收来自所述数据线的数据信号以处于显示对应2D画面的图像的状态，所述控制电路作用于所述第二像素电极以使得所述第二像素电极的电压第一次改变，随后所述第一扫描线控制所述第一开关和第二开关断开，所述第二扫描线输入扫描信号以控制所述第三开关导通，以使得所述第二像素电极和所述第三像素电极电性连接，所述第三像素电极接收来自所述第二像素电极的数据信号以处于显示对应2D画面的图像的状态，使得第一次改变后的所述第二像素电极的电压通过所述第三像素电极进行第二次改变，进而使得所述第一像素电极、第二像素电极和第三像素电极中的至少两个之间的电压差不为零；
    在3D显示模式下，所述第二扫描线控制所述第三开关断开，所述第一扫描线输入扫描信号以控制所述第一开关和第二开关导通，所述第一像素电极通过所述第一开关接收来自所述数据线的数据信号以处于显示对应3D画面的的状态，所述第二像素电极依次通过所述第一开关和第二开关接收来自所述数据线的数据信号以处于显示对应3D画面的图像的状态，所述控制电路作用于所述第二像素电极以改变所述第二像素电极的电压，以使得所述第一像素电极和第二像素电极之间的电压差不为零，所述第三像素电极在第三开关断开的作用下处于显示对应黑画面的图像的状态。
  6. 根据权利要求5所述的阵列基板，其中，
    所述控制电路包括第四开关和一电荷分享电容，所述第四开关包括控制端、第一端和第二端，所述第四开关的控制端连接对应本像素单元的所述第一扫描线，所述第四开关的第一端连接对应本像素单元的所述第二像素电极，所述第四开关的第二端连接所述电荷分享电容的的一端，所述电荷分享电容连接所述公共电极，在所述第一扫描线输入扫描信号时所述第四开关导通，以使得所述第二像素电极和所述电荷分享电容电性连接，所述第二像素电极的电压通过所述电荷分享电容第一次改变，所述第四开关在其导通的时间内控制所述第二像素电极和公共电极之间的电压差不为零。
  7. 根据权利要求6所述的阵列基板，其中，
    所述第四开关为一薄膜晶体管，所述第四开关的控制端对应为薄膜晶体管的栅极，所述第四开关的第一端对应为薄膜晶体管的源极，所述第四开关的第二端对应为薄膜晶体管的漏极，所述薄膜晶体管的宽长比小于第一设定值，以使得在其导通的时间内控制所述第二像素电极和公共电极之间的电压差不为零。
  8. 根据权利要求5所述的阵列基板，其中，
    多个所述像素单元分行排列，多条所述第一扫描线和第二扫描线也分行排列，在2D显示模式下，在对一行所述像素单元所对应的第一扫描线进行扫描的同时，对与所述一行像素单元相邻且最近被扫描的上一行像素单元所对应的第二扫描线进行扫描。
  9. 根据权利要求8所述的阵列基板，其中，
    所述阵列基板还包括位于阵列基板外围区域的开关单元和短路线；
    所述开关单元包括多个受控开关，所述受控开关包括控制端、输入端以及输出端，每个所述受控开关的输入端连接一行所述像素单元所对应的第一扫描线，输出端连接与所述一行像素单元相邻的上一行像素单元所对应的第二扫描线，所有所述受控开关的控制端与所述短路线连接；
    在2D显示模式下，所述短路线输入控制信号以控制所有所述受控开关导通，在一行所述像素单元所对应的第一扫描线输入扫描信号时，所述扫描信号通过所述受控开关同时输入至与所述受控开关的输出端连接的第二扫描线中，以控制相应的第三开关导通，在3D显示模式下，所述短路线输入控制信号以控制所有所述受控开关断开，以控制所有所述第三开关断开。
  10. 根据权利要求5所述的阵列基板，其中，
    所述第三像素电极所在区域的面积小于所述第一像素电极和第二像素电极所在区域的面积。
  11. 根据权利要求5所述的阵列基板，其中，
    在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第三开关在其导通的时间内控制所述第二像素电极和第三像素电极之间的电压差不为零，以使得所述第一像素电极、第二像素电极和第三像素电极两两之间的电压差均不为零。
  12. 根据权利要求11所述的阵列基板，其中，
    所述第三开关为薄膜晶体管，所述薄膜晶体管的栅极与所述第二扫描线连接，所述薄膜晶体管的源极与所述第二像素电极连接，所述薄膜晶体管的漏极与所述第三像素电极连接，所述薄膜晶体管的宽长比小于第二设定值，以使得在其导通的时间内控制所述第二像素电极和第三像素电极之间的电压差不为零。
  13. 一种液晶显示面板，其中，包括阵列基板、彩色滤光基板以及位于所述阵列基板之间的液晶层，所述阵列基板包括多条第一扫描线、多条第二扫描线、多条数据线、多个像素单元以及用于输入公共电压的公共电极，每个所述像素单元对应一条第一扫描线、一条第二扫描线以及一条数据线；
    每个所述像素单元包括第一像素电极、第二像素电极、第三像素电极、第一开关、第二开关以及第三开关，每个所述像素单元还包括一控制电路，所述第一像素电极通过所述第一开关与对应本像素单元的所述第一扫描线和所述数据线连接，所述第二像素电极通过所述第二开关与对应本像素单元的所述第一扫描线和所述第一开关连接，所述第三像素电极通过所述第三开关与对应本像素单元的所述第二扫描线和所述第二像素电极连接，所述控制电路分别连接对应本像素单元的所述第一扫描线和所述第二像素电极，所述控制电路在所述第一扫描线输入扫描信号时作用于所述第二像素电极，以改变所述第二像素电极的电压，并控制所述第二像素电极和所述公共电极之间的电压差不为零；
    在2D显示模式下，所述第一扫描线输入扫描信号以控制所述第一开关和第二开关导通，所述第一像素电极通过第一开关接收来自所述数据线的数据信号以处于显示对应2D画面的图像的状态，所述第二像素电极依次通过所述第一开关和第二开关接收来自所述数据线的数据信号以处于显示对应2D画面的图像的状态，所述控制电路作用于所述第二像素电极以使得所述第二像素电极的电压第一次改变，随后所述第一扫描线控制所述第一开关和第二开关断开，所述第二扫描线输入扫描信号以控制所述第三开关导通，以使得所述第二像素电极和所述第三像素电极电性连接，所述第三像素电极接收来自所述第二像素电极的数据信号以处于显示对应2D画面的图像的状态，使得第一次改变后的所述第二像素电极的电压通过所述第三像素电极进行第二次改变，进而使得所述第一像素电极、第二像素电极和第三像素电极中的至少两个之间的电压差不为零；
    在3D显示模式下，所述第二扫描线控制所述第三开关断开，所述第一扫描线输入扫描信号以控制所述第一开关和第二开关导通，所述第一像素电极通过所述第一开关接收来自所述数据线的数据信号以处于显示对应3D画面的的状态，所述第二像素电极依次通过所述第一开关和第二开关接收来自所述数据线的数据信号以处于显示对应3D画面的图像的状态，所述控制电路作用于所述第二像素电极以改变所述第二像素电极的电压，以使得所述第一像素电极和第二像素电极之间的电压差不为零，所述第三像素电极在第三开关断开的作用下处于显示对应黑画面的图像的状态。
  14. 根据权利要求13所述的液晶显示面板，其中，
    所述控制电路包括第四开关和一电荷分享电容，所述第四开关包括控制端、第一端和第二端，所述第四开关的控制端连接对应本像素单元的所述第一扫描线，所述第四开关的第一端连接对应本像素单元的所述第二像素电极，所述第四开关的第二端连接所述电荷分享电容的的一端，所述电荷分享电容连接所述公共电极，在所述第一扫描线输入扫描信号时所述第四开关导通，以使得所述第二像素电极和所述电荷分享电容电性连接，所述第二像素电极的电压通过所述电荷分享电容第一次改变，所述第四开关在其导通的时间内控制所述第二像素电极和公共电极之间的电压差不为零。
  15. 根据权利要求14所述的液晶显示面板，其中，
    所述第四开关为一薄膜晶体管，所述第四开关的控制端对应为薄膜晶体管的栅极，所述第四开关的第一端对应为薄膜晶体管的源极，所述第四开关的第二端对应为薄膜晶体管的漏极，所述薄膜晶体管的宽长比小于第一设定值，以使得在其导通的时间内控制所述第二像素电极和公共电极之间的电压差不为零。
  16. 根据权利要求13所述的液晶显示面板，其中，
    多个所述像素单元分行排列，多条所述第一扫描线和第二扫描线也分行排列，在2D显示模式下，在对一行所述像素单元所对应的第一扫描线进行扫描的同时，对与所述一行像素单元相邻且最近被扫描的上一行像素单元所对应的第二扫描线进行扫描。
  17. 根据权利要求16所述的液晶显示面板，其中，
    所述阵列基板还包括位于阵列基板外围区域的开关单元和短路线；
    所述开关单元包括多个受控开关，所述受控开关包括控制端、输入端以及输出端，每个所述受控开关的输入端连接一行所述像素单元所对应的第一扫描线，输出端连接与所述一行像素单元相邻的上一行像素单元所对应的第二扫描线，所有所述受控开关的控制端与所述短路线连接；
    在2D显示模式下，所述短路线输入控制信号以控制所有所述受控开关导通，在一行所述像素单元所对应的第一扫描线输入扫描信号时，所述扫描信号通过所述受控开关同时输入至与所述受控开关的输出端连接的第二扫描线中，以控制相应的第三开关导通，在3D显示模式下，所述短路线输入控制信号以控制所有所述受控开关断开，以控制所有所述第三开关断开。
  18. 根据权利要求13所述的液晶显示面板，其中，
    所述第三像素电极所在区域的面积小于所述第一像素电极和第二像素电极所在区域的面积。
  19. 根据权利要求13所述的液晶显示面板，其中，
    在所述第二扫描线输入扫描信号以控制所述第三开关导通时，所述第三开关在其导通的时间内控制所述第二像素电极和第三像素电极之间的电压差不为零，以使得所述第一像素电极、第二像素电极和第三像素电极两两之间的电压差均不为零。
  20. 根据权利要求19所述的液晶显示面板，其中，
    所述第三开关为薄膜晶体管，所述薄膜晶体管的栅极与所述第二扫描线连接，所述薄膜晶体管的源极与所述第二像素电极连接，所述薄膜晶体管的漏极与所述第三像素电极连接，所述薄膜晶体管的宽长比小于第二设定值，以使得在其导通的时间内控制所述第二像素电极和第三像素电极之间的电压差不为零。
PCT/CN2013/080075 2013-07-19 2013-07-25 一种阵列基板及液晶显示面板 WO2015006995A1 (zh)

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