WO2016058183A1 - 阵列基板及液晶显示面板 - Google Patents

阵列基板及液晶显示面板 Download PDF

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Publication number
WO2016058183A1
WO2016058183A1 PCT/CN2014/088840 CN2014088840W WO2016058183A1 WO 2016058183 A1 WO2016058183 A1 WO 2016058183A1 CN 2014088840 W CN2014088840 W CN 2014088840W WO 2016058183 A1 WO2016058183 A1 WO 2016058183A1
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WIPO (PCT)
Prior art keywords
pixel electrode
switch tube
pixel
scan line
driving circuit
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PCT/CN2014/088840
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English (en)
French (fr)
Inventor
黄世帅
Original Assignee
深圳市华星光电技术有限公司
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Priority to US14/426,144 priority Critical patent/US9897833B2/en
Publication of WO2016058183A1 publication Critical patent/WO2016058183A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to an array substrate and a liquid crystal display panel.
  • LCD panel usually has color shift (color The problem of shift) is that the color shift of the large-sized liquid crystal display panel is particularly serious, and the larger the viewing angle, the more obvious the color shift.
  • the liquid crystal display panel In order to improve the viewing angle and reduce the color shift, the liquid crystal display panel generally does Low color. Shift (low color shift) design.
  • one pixel unit 10 is generally divided into two parts, a main pixel electrode 101 and a sub-pixel electrode 102.
  • the thin film transistor Q1 is connected to the main pixel electrode 101, and the thin film transistor Q2 is connected to the sub-pixel electrode 102.
  • the scan line G1 inputs a scan signal to control the thin film transistors Q1 and Q2 to be turned on
  • the data line D1 inputs a display signal to the main pixel electrode 101 and the sub-pixel electrode 102.
  • a shared capacitor Cb is also disposed in the pixel structure.
  • the shared capacitor Cb is connected to the thin film transistor Q3 through the thin film transistor Q3 and the sub-pixel electrode 102, and the scan line G2 is connected to control the turn-on and turn-off of the thin film transistor Q3.
  • the main pixel electrode 101 and the sub-pixel electrode 102 are charged (i.e., input display signals) on the data line D1, the main pixel electrode 101 and the sub-pixel electrode 102 have the same potential.
  • the thin film transistor Q3 is turned on, at which time the shared capacitor Cb is in communication with the sub-pixel electrode 102, and the partial charge of the sub-pixel electrode 102 is released into the shared capacitor Cb, thereby causing the main pixel electrode 101 and the sub-pixel electrode 102 to have a potential difference.
  • the purpose of reducing the color shift can be achieved.
  • the shared capacitor Cb is formed using the common electrode layer 103 and the same metal layer 104 as the drain of the thin film transistor Q3, and the common electrode layer 103 is usually It is located in the light-transmitting region where the pixel electrode for light-transmitting display is located, and therefore the shared capacitor Cb occupies a portion of the pixel electrode region, resulting in a decrease in the aperture ratio.
  • the technical problem to be solved by the present invention is to provide an array substrate and a liquid crystal display panel, which can increase the aperture ratio.
  • a technical solution adopted by the present invention is to provide an array substrate including a pixel unit and a driving circuit and a control circuit corresponding to the pixel unit, the pixel unit including a first pixel electrode and a second a pixel electrode; the first pixel electrode and the second pixel electrode are both fishbone electrodes; the driving circuit includes a first switch tube, a second switch tube, a data line, and a first scan line; The scan line is configured to control the turn-on and turn-off of the first switch tube and the second switch tube, and when the first switch tube and the second switch tube are turned on, the data line is used to respectively pass the The first switch tube and the second switch tube input display signals to the first pixel electrode and the second pixel electrode; the control circuit includes a second scan line, a third switch tube and a capacitor element, the capacitor The component is located in a vertical projection area of the opaque region, the second scan line is configured to control conduction and deactivation of the third switch tube, and the capacitive element passes
  • the first switch tube, the second switch tube, and the third switch tube are all thin film transistors, and the capacitor element includes a first plate and a second plate, forming a metal layer and forming the first plate
  • the metal layer of the drain of the third switch tube is the same metal layer
  • the second plate is a metal layer forming the first scan line.
  • the first pixel electrode and the second pixel electrode are sequentially arranged along the data line direction, and the control circuit and a portion of the driving circuit are located between the first pixel electrode and the second pixel electrode .
  • an array substrate including a pixel unit and a driving circuit and a control circuit corresponding to the pixel unit, the pixel unit including a first pixel electrode and a a second pixel electrode; the driving circuit is connected to the first pixel electrode and the second pixel electrode to input display signals to the first pixel electrode and the second pixel electrode; the control circuit and the first One of a pixel electrode and the second pixel electrode are connected to control a predetermined voltage difference between the first pixel electrode and the second pixel electrode; the control circuit is located in a vertical projection area of the opaque region Inside.
  • the driving circuit includes a first switching transistor, a second switching transistor, a data line, and a first scan line; the first scan line is configured to control conduction and deactivation of the first switch tube and the second switch tube When the first switch tube and the second switch tube are turned on, the data line is used to pass the first switch tube and the second switch tube to the first pixel electrode and the The second pixel electrode inputs a display signal; the control circuit includes a second scan line, a third switch tube and a capacitor element, the capacitor element is located in a vertical projection area of the opaque region, and the second scan line is used for controlling The third switch tube is turned on and off, and the capacitive element is connected to the second pixel electrode through the third switch tube to change the second pixel electrode when the third switch tube is turned on The voltage, in turn, causes a predetermined voltage difference between the first pixel electrode and the second pixel electrode.
  • the first switch tube, the second switch tube, and the third switch tube are all thin film transistors, and the capacitor element includes a first plate and a second plate, forming a metal layer and forming the first plate
  • the metal layer of the drain of the third switch tube is the same metal layer
  • the second plate is a metal layer forming the first scan line.
  • the first pixel electrode and the second pixel electrode are sequentially arranged along the data line direction, and the control circuit and a portion of the driving circuit are located between the first pixel electrode and the second pixel electrode .
  • the driving circuit includes a first switching transistor, a second switching transistor, a data line, and a first scan line; the first scan line is configured to control conduction and deactivation of the first switch tube and the second switch tube When the first switch tube and the second switch tube are turned on, the data line is used to pass the first switch tube and the second switch tube to the first pixel electrode and the a second pixel electrode input display signal; the control circuit includes a third switch tube and a capacitive element, the capacitive element being located in a vertical projection area of the opaque region between adjacent two pixel units, the third switch The tube is connected to the first scan line in the driving circuit corresponding to the adjacent one of the next pixel units to be turned on and off under the action of the first scan line in the driving circuit corresponding to the adjacent next pixel unit. The capacitive element is connected to the second pixel electrode through the third switching tube to change a voltage of the second pixel electrode when the third switching tube is turned on, thereby causing the first pixel electrode and the Second pixel electrode There is a
  • the first pixel electrode and the second pixel electrode are sequentially arranged along a direction of the first scan line, and the control circuit and a portion of the driving circuit are located between two adjacent pixel units.
  • a liquid crystal display panel including an array substrate, a color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate.
  • the color filter substrate includes an opaque region
  • the array substrate includes a pixel unit and a driving circuit and a control circuit corresponding to the pixel unit
  • the pixel unit includes a first pixel electrode and a second pixel electrode;
  • a driving circuit connected to the first pixel electrode and the second pixel electrode to input display signals to the first pixel electrode and the second pixel electrode;
  • the control circuit and the first pixel electrode and the One of the second pixel electrodes is connected to control a predetermined voltage difference between the first pixel electrode and the second pixel electrode; the control circuit is located in a vertical projection area of the opaque region.
  • the driving circuit includes a first switching transistor, a second switching transistor, a data line, and a first scan line; the first scan line is configured to control conduction and deactivation of the first switch tube and the second switch tube When the first switch tube and the second switch tube are turned on, the data line is used to pass the first switch tube and the second switch tube to the first pixel electrode and the The second pixel electrode inputs a display signal; the control circuit includes a second scan line, a third switch tube and a capacitor element, the capacitor element is located in a vertical projection area of the opaque region, and the second scan line is used for controlling The third switch tube is turned on and off, and the capacitive element is connected to the second pixel electrode through the third switch tube to change the second pixel electrode when the third switch tube is turned on The voltage, in turn, causes a predetermined voltage difference between the first pixel electrode and the second pixel electrode.
  • the first switch tube, the second switch tube, and the third switch tube are all thin film transistors, and the capacitor element includes a first plate and a second plate, forming a metal layer and forming the first plate
  • the metal layer of the drain of the third switch tube is the same metal layer
  • the second plate is a metal layer forming the first scan line.
  • the first pixel electrode and the second pixel electrode are sequentially arranged along the data line direction, and the control circuit and a portion of the driving circuit are located between the first pixel electrode and the second pixel electrode .
  • the driving circuit includes a first switching transistor, a second switching transistor, a data line, and a first scan line; the first scan line is configured to control conduction and deactivation of the first switch tube and the second switch tube When the first switch tube and the second switch tube are turned on, the data line is used to pass the first switch tube and the second switch tube to the first pixel electrode and the a second pixel electrode input display signal; the control circuit includes a third switch tube and a capacitive element, the capacitive element being located in a vertical projection area of the opaque region between adjacent two pixel units, the third switch The tube is connected to the first scan line in the driving circuit corresponding to the adjacent one of the next pixel units to be turned on and off under the action of the first scan line in the driving circuit corresponding to the adjacent next pixel unit. The capacitive element is connected to the second pixel electrode through the third switching tube to change a voltage of the second pixel electrode when the third switching tube is turned on, thereby causing the first pixel electrode and the Second pixel electrode There is a
  • the first pixel electrode and the second pixel electrode are sequentially arranged along a direction of the first scan line, and the control circuit and a portion of the driving circuit are located between two adjacent pixel units.
  • the invention has the beneficial effects that, in the case of the prior art, in the array substrate of the present invention, a predetermined voltage difference is formed between the first pixel electrode and the second pixel electrode by the action of the control circuit, thereby reducing the color shift.
  • the effect is that the control circuit is located in the vertical projection area of the opaque area, and does not need to occupy the area where the pixel electrode is located, thereby making it possible to increase the aperture ratio.
  • FIG. 1 is a schematic diagram of a pixel structure of a liquid crystal display panel in the prior art
  • FIG. 2 is an equivalent circuit diagram of the pixel structure shown in FIG. 1;
  • FIG. 3 is a schematic structural view of an embodiment of a liquid crystal display panel of the present invention.
  • FIG. 4 is a schematic structural view of an embodiment of the array substrate shown in FIG. 3;
  • FIG. 5 is a schematic structural view of another embodiment of the array substrate shown in FIG. 3.
  • FIG. 5 is a schematic structural view of another embodiment of the array substrate shown in FIG. 3.
  • the liquid crystal display panel includes an array substrate 31 , a color filter substrate 32 , and a liquid crystal layer 33 between the array substrate 31 and the color filter base 32 .
  • the color filter substrate 32 includes an opaque region 321 which is a region where the black matrix (BM) is located.
  • the array substrate 31 includes a vertical projection region 311 of the opaque region 321 on the array substrate 31.
  • FIG. 4 is a schematic structural diagram of an embodiment of the array substrate 31 shown in FIG. 3.
  • the array substrate 31 includes a plurality of pixel units 41, a plurality of driving circuits 42, and a plurality of control circuits 43, each corresponding to each pixel unit 41.
  • a drive circuit 42 and a control circuit 43. 4 shows only one pixel structure composed of one pixel unit 41 and its corresponding drive circuit 42 and control circuit 43.
  • the pixel unit 41 includes a first pixel electrode 411 and a second pixel electrode 422.
  • the first pixel electrode 411 and the second pixel electrode 422 serve as light-transmissive areas of the array substrate 31 for realizing display of a picture.
  • the first pixel electrode 411 and the second pixel electrode 412 are both fishbone electrodes
  • the first pixel electrode 411 has four domains in which the electrode strips are arranged in different directions
  • the second pixel electrode 412 also has The electrode strips are arranged in four domains with different directions, whereby the entire pixel unit 41 is divided into eight electrode regions, so that the liquid crystal molecules in the liquid crystal layer 33 have a plurality of different alignment directions, thereby improving the viewing angle and improving the large viewing angle.
  • the color shift underneath the first pixel electrode and the second pixel electrode may also be electrodes of other shapes, such as a monolithic strip-shaped electrode.
  • the driving circuit 42 is connected to the first pixel electrode 411 and the second pixel electrode 422, respectively, to input display signals to the first pixel electrode 411 and the second pixel electrode 412.
  • the driving circuit 42 includes a first thin film transistor 421, a second thin film transistor 422, a data line 423, and a first scan line 424.
  • the data line 423 extends in the vertical direction and is located between the two pixel units 41.
  • the first scan line 424 extends in the horizontal direction, and both the vertical direction and the horizontal direction are described in the view shown in FIG. Based on other views, it can also be expressed in other ways.
  • the first scan line 424 is electrically connected to the gate of the first thin film transistor 421 and the gate of the second thin film transistor 422, respectively, to control the on and off of the first thin film transistor 421 and the second thin film transistor 422; the data line 423 respectively.
  • the source of the first thin film transistor 421 and the source of the second thin film transistor 422 are electrically connected; the drain of the first thin film transistor 421 is electrically connected to the first pixel electrode 411, and the drain and the second pixel of the second thin film transistor 422 are connected.
  • the electrodes 412 are electrically connected.
  • the first thin film transistor 421 and the second thin film transistor 422 are respectively a first switch tube and a second switch tube of the drive circuit 42.
  • other switch tubes such as a Darlington tube and a triode tube may also be used. instead.
  • the control circuit 43 is located in the vertical projection area 311 of the opaque region 321 and includes a second scan line 431, a third thin film transistor 432, and a capacitive element 433.
  • the second scan line 431 is electrically connected to the gate of the third thin film transistor 432 for controlling the on and off of the third thin film transistor 432.
  • the source of the third thin film transistor 432 is electrically connected to the second pixel electrode, and the third film is electrically connected.
  • the drain of the transistor 432 is electrically connected to one end of the capacitive element 433, and the other end of the capacitive element 433 is electrically connected to the common electrode 44 on the array substrate 31.
  • the third thin film transistor 432 is a third switching transistor of the control circuit 43.
  • the third thin film transistor 432 may be replaced by a switching tube such as a Darlington or a triode.
  • the first scan line 424 inputs a scan signal to control the first thin film transistor 421 and the second thin film transistor 422 to be turned on, and then the data line 423 passes through the first The thin film transistor 421 and the second thin film transistor 422 input display signals required for display into the first pixel electrode 411 and the second pixel electrode 412, at which time the charges of the first pixel electrode 411 and the second pixel electrode 412 are the same. Thereafter, the input of the scan signal to the first scan line 424 is stopped to turn off the first thin film transistor 421 and the second thin film transistor 422, and the scan signal is input to the second scan line 431 to control the third thin film transistor 432 to be turned on.
  • the second pixel electrode 412 is electrically connected to the capacitive element 433 such that a partial charge of the second pixel electrode 412 flows into the capacitive element 433, so that the charge of the second pixel electrode 412 occurs.
  • the change has a voltage difference from the first pixel electrode 411, thereby facilitating the improvement of the color shift condition and achieving a low color shift effect of the display screen.
  • control circuit 43 may be connected to the first pixel electrode 411 to change the charge of the first pixel electrode 411, that is, the source of the third thin film transistor may be connected to the first pixel electrode 411, so that When the third thin film transistor 432 is turned on, the first pixel electrode 411 and the capacitive element 433 are turned on to change the charge of the first pixel electrode 411, thereby causing a voltage difference between the first pixel electrode 411 and the second pixel electrode 412.
  • the size of the capacitive element 433 can be set according to the actual display requirement to control the magnitude of the charge flowing into the capacitive element 433, so that the preset voltage difference between the first pixel electrode 411 and the second pixel electrode 412 can be controlled.
  • the capacitive element 433 as a charge sharing capacitor is located in the vertical projection region 311 on the array substrate 31 of the opaque region 321 .
  • the first pixel electrode 411 and the second pixel electrode 412 are sequentially arranged along the extending direction of the data line 423, and the vertical projection area 311 of the opaque region 321 of the color filter substrate 32 on the array substrate 31 includes the first A region between the pixel electrode 411 and the second pixel electrode 412 and a region between the two pixel units 43.
  • the first scan line 424, the first thin film transistor 421, and the second thin film transistor 422 in the control circuit 43 and the drive circuit 42 of the present embodiment are located in comparison with the conventional method of disposing the shared capacitor in the pixel transparent region.
  • the vertical projection area 311 of the opaque area 321 is disposed between the first pixel electrode 411 and the second pixel electrode 412, thereby causing the control circuit 43 including the capacitive element 433 and some of the components of the drive circuit 42 not to
  • the capacitive element 433 includes a first plate 4331 and a second plate 4332.
  • the first plate 4331 is electrically connected to the drain of the third thin film transistor 432, and the second plate 4332 It is electrically connected to the common electrode 44 of the array substrate 31.
  • the metal layer forming the first plate 4331 and the metal layer forming the drain of the third thin film transistor 432 are the same metal layer, that is, in the photolithography process for forming the third thin film transistor 432, the first plate 4331 and the first The drain of the three thin film transistor 432 is formed by etching on the same metal layer.
  • the second plate 4332 is a metal layer forming the first scan line 424, that is, the capacitor element 433 is formed by the metal layer where the drain of the third thin film transistor 432 is located and the metal layer where the first scan line 424 is located, and the third thin film transistor is formed.
  • the position of the first scanning line 432 and the first scanning line 424 corresponds to the position of the black matrix of the color filter substrate 32, that is, within the vertical projection area 311 of the opaque area 321 .
  • the shared capacitor in the prior art needs to occupy a certain transparent region, and the existing In contrast, the present embodiment forms the capacitive element 433 by using the first scan line 424 and the same metal layer as the drain of the third thin film transistor 432, so that the capacitive element 433 does not occupy the first pixel electrode 411 and the second pixel electrode 412.
  • the light transmission area in which it is located can increase the aperture ratio.
  • the capacitive element 433 may also be formed without using a metal layer of the first scan line 424.
  • a metal layer may be additionally formed in the vertical projection region 311 of the opaque region 321 to form the capacitive element 433.
  • the capacitor element 433 may be replaced by another electronic component.
  • a resistor may be used instead.
  • FIG. 5 is a schematic structural diagram of another embodiment of the array substrate 31 shown in FIG. 3, wherein only one pixel unit 51 and its corresponding driving circuit 52 and control circuit 53 are shown.
  • a pixel structure constructed.
  • the control circuit 53 of the present embodiment includes a third thin film transistor 531 and a capacitive element 532 corresponding to the first scan corresponding to the third thin film transistor 531 of the pixel unit 51 and the adjacent next pixel unit. Line 524' is connected.
  • the vertical projection area 311 of the opaque region 321 of the color filter substrate 32 on the array substrate 31 includes a region between two pixel units 51 and a first pixel electrode in one pixel unit 51. A region between 511 and the second pixel electrode 512.
  • the first pixel electrode 511 and the second pixel electrode 512 are sequentially arranged along the extending direction of the first scan line 524, and the first thin film transistor 521, the second thin film transistor 522, and the first scan line 524 in the driving circuit 52 are located in the vertical direction.
  • the data line 523 is located perpendicular to the opaque region 321 between the first pixel electrode 511 and the second pixel electrode 512.
  • the third thin film transistor 531 and the capacitive element 532 are located in the vertical projection region 311 of the opaque region 321 between the adjacent two pixel units arranged in the horizontal direction.
  • the first scan line 524 is electrically connected to the gate of the first thin film transistor 521 and the gate of the second thin film transistor 522, respectively, to control the first thin film transistor 521 and
  • the second thin film transistor 522 is turned on and off;
  • the data line 523 is electrically connected to the source of the first thin film transistor 521 and the source of the second thin film transistor 522, respectively;
  • the gate of the third thin film transistor 531 is electrically connected to the first scan line 524' corresponding to the next pixel unit adjacent to the pixel unit 51, and the sum is
  • the next pixel unit adjacent to the pixel unit 51 is a next pixel unit arranged in the vertical direction and adjacent to the pixel unit 51;
  • the source of the third thin film transistor 531 is electrically connected to the second pixel electrode 512, and the third
  • the drain of the thin film transistor 531 is connected to one end of the capacitive element 532, and the other end of the capacitive element 532 is connected to the common electrode 54 of the array substrate 31.
  • the first corresponding to the pixel unit 51 is stopped.
  • the scan line 524 inputs a scan signal, and inputs a scan signal to the first scan line 524 ′ corresponding to the next pixel unit adjacent to the pixel unit 51 , thereby causing the third thin film transistor 531 corresponding to the pixel unit 51 to be turned on.
  • the partial charge of the second pixel 512 is caused to flow to the capacitive element 532, so that the second pixel electrode 512 and the first pixel electrode 511 form a voltage difference, whereby the effect of reducing the color shift can be achieved.
  • the third thin film transistor of the upper row by using the next first scanning line, the number of scanning lines can be reduced, the cost can be reduced, and the aperture ratio can be further improved.
  • the first plate 5321 of the capacitor element 532 and the drain of the third thin film transistor 531 are made of the same metal layer, and the second plate 5322 and the first scan line 524 corresponding to the pixel unit 51 are made of the same metal layer. Therefore, the capacitive element 532 can be formed in the vertical projection region 311 of the opaque region 321, whereby the aperture ratio can be improved.
  • the present invention also provides an embodiment of an array substrate, wherein the array substrate is the array substrate according to any of the above embodiments.

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Abstract

一种阵列基板（31）及液晶显示面板，所述阵列基板（31）包括像素单元（41）和与所述像素单元（41）对应的驱动电路（42）、控制电路（43），所述像素单元（41）包括第一像素电极（411）和第二像素电极（412）；所述驱动电路（42）用于实现对所述像素单元（41）输入显示信号，所述控制电路（43）用于改变第一像素电极（411）或第二像素电极（412）的电荷以使得第一像素电极（411）和第二像素电极（412）之间存在电压差，控制电路（43）位于不透光区域（321）的垂直投影区域（311）内。通过上述方式，能够降低色偏，提高开口率。

Description

阵列基板及液晶显示面板
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种阵列基板及液晶显示面板。
【背景技术】
液晶显示面板通常会存在色偏（color shift）的问题，大尺寸的液晶显示面板色偏尤为严重，观看角度越大，色偏也越明显。
为了提高视角降低色偏，液晶显示面板一般会做Low color shift(低色偏)设计。如图1和图2所示，液晶显示面板中，通常将一个像素单元10划分为主像素电极101和次像素电极102两部分。薄膜晶体管Q1和主像素电极101连接，薄膜晶体管Q2和次像素电极102连接。当扫描线G1输入扫描信号以控制薄膜晶体管Q1和Q2导通时，数据线D1输入显示信号至主像素电极101和次像素电极102中。为了达到降低色偏的目的，像素结构中还设置有一个共享电容Cb。共享电容Cb通过薄膜晶体管Q3与次像素电极102，扫描线G2连接薄膜晶体管Q3，以控制薄膜晶体管Q3的导通和关闭。在数据线D1对主像素电极101和次像素电极102充电（即输入显示信号）后，主像素电极101和次像素电极102具有相同的电位。然后使薄膜晶体管Q3导通，此时共享电容Cb与次像素电极102连通，次像素电极102的部分电荷将释放到共享电容Cb中，由此使得主像素电极101和次像素电极102具有电位差，由此可达到降低色偏的目的。
然而，虽然上述结构可以实现低色偏，但是，如图1所示，共享电容Cb是利用公共电极层103和与形成薄膜晶体管Q3的漏极相同的金属层104形成，而公共电极层103通常是位于用于透光显示的像素电极所在的透光区域中，因此共享电容Cb会占据部分像素电极区域，导致开口率下降。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及液晶显示面板，能够提高开口率。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包括像素单元和与所述像素单元对应的驱动电路、控制电路，所述像素单元包括第一像素电极和第二像素电极；所述第一像素电极和所述第二像素电极均为鱼骨状电极；所述驱动电路包括第一开关管、第二开关管、数据线以及第一扫描线；所述第一扫描线用以控制所述第一开关管和第二开关管的导通与关闭，在所述第一开关管和所述第二开关管导通时，所述数据线用以分别通过所述第一开关管和所述第二开关管对所述第一像素电极和所述第二像素电极输入显示信号；所述控制电路包括第二扫描线、第三开关管和电容元件，所述电容元件位于不透光区域的垂直投影区域内，所述第二扫描线用以控制所述第三开关管的导通与关闭，所述电容元件通过所述第三开关管与所述第二像素电极连接，以在所述第三开关管导通时改变所述第二像素电极的电压，进而使所述第一像素电极和所述第二像素电极之间存在预设电压差。
其中，所述第一开关管、第二开关管以及第三开关管均为薄膜晶体管，所述电容元件包括第一极板和第二极板，形成所述第一极板的金属层与形成所述第三开关管的漏极的金属层为同一金属层，所述第二极板为形成所述第一扫描线的金属层。
其中，所述第一像素电极和所述第二像素电极沿所述数据线方向依次排列，所述控制电路和部分所述驱动电路位于所述第一像素电极和所述第二像素电极之间。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括像素单元和与所述像素单元对应的驱动电路、控制电路，所述像素单元包括第一像素电极和第二像素电极；所述驱动电路与所述第一像素电极和所述第二像素电极连接以对所述第一像素电极和所述第二像素电极输入显示信号；所述控制电路与所述第一像素电极和所述第二像素电极中的其中一个连接以控制所述第一像素电极和所述第二像素电极之间形成预定电压差；所述控制电路位于不透光区域的垂直投影区域内。
其中，所述驱动电路包括第一开关管、第二开关管、数据线以及第一扫描线；所述第一扫描线用以控制所述第一开关管和第二开关管的导通与关闭，在所述第一开关管和所述第二开关管导通时，所述数据线用以分别通过所述第一开关管和所述第二开关管对所述第一像素电极和所述第二像素电极输入显示信号；所述控制电路包括第二扫描线、第三开关管和电容元件，所述电容元件位于不透光区域的垂直投影区域内，所述第二扫描线用以控制所述第三开关管的导通与关闭，所述电容元件通过所述第三开关管与所述第二像素电极连接，以在所述第三开关管导通时改变所述第二像素电极的电压，进而使所述第一像素电极和所述第二像素电极之间存在预设电压差。
其中，所述第一开关管、第二开关管以及第三开关管均为薄膜晶体管，所述电容元件包括第一极板和第二极板，形成所述第一极板的金属层与形成所述第三开关管的漏极的金属层为同一金属层，所述第二极板为形成所述第一扫描线的金属层。
其中，所述第一像素电极和所述第二像素电极沿所述数据线方向依次排列，所述控制电路和部分所述驱动电路位于所述第一像素电极和所述第二像素电极之间。
其中，所述驱动电路包括第一开关管、第二开关管、数据线以及第一扫描线；所述第一扫描线用以控制所述第一开关管和第二开关管的导通与关闭，在所述第一开关管和所述第二开关管导通时，所述数据线用以分别通过所述第一开关管和所述第二开关管对所述第一像素电极和所述第二像素电极输入显示信号；所述控制电路包括第三开关管和电容元件，所述电容元件位于相邻两个像素单元之间的不透光区域的垂直投影区域内，所述第三开关管与相邻下一像素单元对应的驱动电路中的第一扫描线连接，以在所述相邻下一像素单元对应的驱动电路中的第一扫描线的作用下实现导通与关闭，所述电容元件通过所述第三开关管与所述第二像素电极连接，以在所述第三开关管导通时改变所述第二像素电极的电压，进而使所述第一像素电极和所述第二像素电极之间存在预设电压差。
其中，所述第一像素电极和所述第二像素电极沿所述第一扫描线的方向依次排列，所述控制电路和部分所述驱动电路位于相邻两个像素单元之间。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板，包括阵列基板、彩色滤光基板以及位于所述阵列基板和所述彩色滤光基板之间的液晶层，所述彩色滤光基板包括不透光区域，所述阵列基板包括像素单元和与所述像素单元对应的驱动电路、控制电路，所述像素单元包括第一像素电极和第二像素电极；所述驱动电路与所述第一像素电极和所述第二像素电极连接以对所述第一像素电极和所述第二像素电极输入显示信号；所述控制电路与所述第一像素电极和所述第二像素电极中的其中一个连接以控制所述第一像素电极和所述第二像素电极之间形成预定电压差；所述控制电路位于所述不透光区域的垂直投影区域内。
其中，所述驱动电路包括第一开关管、第二开关管、数据线以及第一扫描线；所述第一扫描线用以控制所述第一开关管和第二开关管的导通与关闭，在所述第一开关管和所述第二开关管导通时，所述数据线用以分别通过所述第一开关管和所述第二开关管对所述第一像素电极和所述第二像素电极输入显示信号；所述控制电路包括第二扫描线、第三开关管和电容元件，所述电容元件位于不透光区域的垂直投影区域内，所述第二扫描线用以控制所述第三开关管的导通与关闭，所述电容元件通过所述第三开关管与所述第二像素电极连接，以在所述第三开关管导通时改变所述第二像素电极的电压，进而使所述第一像素电极和所述第二像素电极之间存在预设电压差。
其中，所述第一开关管、第二开关管以及第三开关管均为薄膜晶体管，所述电容元件包括第一极板和第二极板，形成所述第一极板的金属层与形成所述第三开关管的漏极的金属层为同一金属层，所述第二极板为形成所述第一扫描线的金属层。
其中，所述第一像素电极和所述第二像素电极沿所述数据线方向依次排列，所述控制电路和部分所述驱动电路位于所述第一像素电极和所述第二像素电极之间。
其中，所述驱动电路包括第一开关管、第二开关管、数据线以及第一扫描线；所述第一扫描线用以控制所述第一开关管和第二开关管的导通与关闭，在所述第一开关管和所述第二开关管导通时，所述数据线用以分别通过所述第一开关管和所述第二开关管对所述第一像素电极和所述第二像素电极输入显示信号；所述控制电路包括第三开关管和电容元件，所述电容元件位于相邻两个像素单元之间的不透光区域的垂直投影区域内，所述第三开关管与相邻下一像素单元对应的驱动电路中的第一扫描线连接，以在所述相邻下一像素单元对应的驱动电路中的第一扫描线的作用下实现导通与关闭，所述电容元件通过所述第三开关管与所述第二像素电极连接，以在所述第三开关管导通时改变所述第二像素电极的电压，进而使所述第一像素电极和所述第二像素电极之间存在预设电压差。
其中，所述第一像素电极和所述第二像素电极沿所述第一扫描线的方向依次排列，所述控制电路和部分所述驱动电路位于相邻两个像素单元之间。
本发明的有益效果是：区别于现有技术的情况，本发明阵列基板中，通过控制电路的作用使得第一像素电极和第二像素电极之间形成预定电压差，由此可达到降低色偏的效果，并且控制电路是位于不透光区域的垂直投影区域内，不需要占据像素电极所在区域，由此能够提高开口率。
【附图说明】
图1是现有技术中一种液晶显示面板的像素结构示意图；
图2是图1所示的像素结构的等效电路图；
图3是本发明液晶显示面板一实施方式的结构示意图；
图4是图3所示的阵列基板一实施方式的结构示意图；
图5是图3所示的阵列基板另一实施方式的结构示意图。
【具体实施方式】
下面将结合附图和实施方式对本发明进行详细的说明。
参阅图3，本发明液晶显示面板一实施方式中，液晶显示面板包括阵列基板31、彩色滤光基板32以及位于阵列基板31和彩色滤光基本32之间的液晶层33。其中，彩色滤光基板32包括不透光区域321，该不透光区域321为黑色矩阵（BM）所在的区域。阵列基板31包括不透光区域321在阵列基板31上的垂直投影区域311。
参阅图4，图4为图3所示的阵列基板31一实施方式的结构示意图，阵列基板31包括多个像素单元41、多个驱动电路42以及多个控制电路43，每个像素单元41对应一个驱动电路42和一个控制电路43。其中，图4仅示出了由一个像素单元41以及与其对应的驱动电路42和控制电路43所构成的一个像素结构。
像素单元41包括第一像素电极411和第二像素电极422，第一像素电极411和第二像素电极422作为阵列基板31的透光区，用以实现画面的显示。如图4所示，第一像素电极411和第二像素电极412均为鱼骨状电极，第一像素电极411具有电极条排列方向不同的四个区域（domain），第二像素电极412也具有电极条排列方向不同的四个区域（domain），由此整个像素单元41分为8个电极区域，使得液晶层33中的液晶分子具有多个不同的排列方向，从而可以提高视角，改善大视角下的色偏。当然，在其他实施方式中，第一像素电极和第二像素电极也可以是其他形状的电极，例如为一整块的条形状电极。
驱动电路42分别与第一像素电极411和第二像素电极422连接以对第一像素电极411和第二像素电极412输入显示信号。具体地，驱动电路42包括第一薄膜晶体管421、第二薄膜晶体管422、数据线423以及第一扫描线424。数据线423沿竖直方向延伸且位于两个像素单元41之间，第一扫描线424沿水平方向延伸，所述的竖直方向和水平方向均是以图4所示的视图为准进行描述，在以别的视图基础上，也可以是别的表述方式。第一扫描线424分别与第一薄膜晶体管421的栅极和第二薄膜晶体管422的栅极电连接，以控制第一薄膜晶体管421和第二薄膜晶体管422的导通和关闭；数据线423分别与第一薄膜晶体管421的源极和第二薄膜晶体管422的源极电连接；第一薄膜晶体管421的漏极与第一像素电极411电连接，第二薄膜晶体管422的漏极与第二像素电极412电连接。
其中，第一薄膜晶体管421和第二薄膜晶体管422分别为驱动电路42的第一开关管和第二开关管，在其他实施方式中，其也可以使用达林顿管、三极管等其他开关管来代替。
控制电路43位于不透光区域321的垂直投影区域311内，其包括第二扫描线431、第三薄膜晶体管432以及电容元件433。第二扫描线431与第三薄膜晶体管432的栅极电连接，用以控制第三薄膜晶体管432的导通和关闭，第三薄膜晶体管432的源极和第二像素电极电连接，第三薄膜晶体管432的漏极与电容元件433的一端电连接，电容元件433的另一端和阵列基板31上的公共电极44电连接。
其中，第三薄膜晶体管432为控制电路43的第三开关管，在其他实施方式中，第三薄膜晶体管432也可以使用达林顿管、三极管等开关管代替。
本实施方式中，当需要驱动像素单元41以显示相应的画面时，第一扫描线424输入扫描信号以控制第一薄膜晶体管421和第二薄膜晶体管422导通，然后数据线423分别通过第一薄膜晶体管421和第二薄膜晶体管422将显示所需的显示信号输入至第一像素电极411和第二像素电极412中，此时第一像素电极411和第二像素电极412的电荷相同。之后，停止对第一扫描线424输入扫描信号以关闭第一薄膜晶体管421和第二薄膜晶体管422，并对第二扫描线431输入扫描信号以控制第三薄膜晶体管432导通。由此，当第三薄膜晶体管432导通时，第二像素电极412与电容元件433电连接，使得第二像素电极412的部分电荷流入到电容元件433中，从而第二像素电极412的电荷发生改变而与第一像素电极411具有电压差，由此有利于改善色偏情况，能够达到显示画面的低色偏效果。
在其他实施方式中，控制电路43也可以是与第一像素电极411连接用以改变第一像素电极411的电荷，即第三薄膜晶体管的源极可以是和第一像素电极411连接，从而当第三薄膜晶体管432导通时使得第一像素电极411与电容元件433导通进而改变第一像素电极411的电荷，由此使得第一像素电极411和第二像素电极412之间存在电压差。
其中，可以根据实际显示的需要设置电容元件433的大小，以控制流入电容元件433的电荷大小，从而可控制第一像素电极411和第二像素电极412之间达到预设电压差。
其中，作为电荷共享电容的电容元件433位于不透光区域321在阵列基板31上的垂直投影区域311内。本实施方式中，第一像素电极411和第二像素电极412沿数据线423的延伸方向依次排列，彩色滤光基板32的不透光区域321在阵列基板31上的垂直投影区域311包括第一像素电极411和第二像素电极412之间的区域和两个像素单元43之间的区域。与现有的将共享电容设置在像素透光区的做法相比，本实施方式的控制电路43以及驱动电路42中的第一扫描线424、第一薄膜晶体管421、第二薄膜晶体管422均位于不透光区域321的垂直投影区域311内，也即设置在第一像素电极411和第二像素电极412之间，由此使得包括电容元件433的控制电路43以及驱动电路42中的部分器件不占据第一像素电极411和第二像素电极412所在的区域，即不占据阵列基板31的透光区域，从而能够提高面板的开口率。
在本发明液晶显示面板的实施方式中，电容元件433包括第一极板4331和第二极板4332，第一极板4331与第三薄膜晶体管432的漏极电性连接，第二极板4332与阵列基板31的公共电极44电性连接。其中，形成第一极板4331的金属层与形成第三薄膜晶体管432的漏极的金属层为同一金属层，即在形成第三薄膜晶体管432的光刻制程中，第一极板4331和第三薄膜晶体管432的漏极为在同一金属层上蚀刻形成。第二极板4332为形成第一扫描线424的金属层，即电容元件433为第三薄膜晶体管432的漏极所在的金属层和第一扫描线424所在的金属层形成，而第三薄膜晶体管432和第一扫描线424的位置与彩色滤光基板32的黑色矩阵的位置相对应，即位于不透光区域321的垂直投影区域311内。现有技术中由于利用公共电极形成共享电容的其中一个极板，而公共电极通常是位于阵列基板的透光区域中，因此现有技术中的共享电容需要占据一定的透光区域，与现有做法相比，本实施方式利用第一扫描线424和与第三薄膜晶体管432的漏极的同一金属层形成电容元件433，可以使得电容元件433不占据第一像素电极411和第二像素电极412所在的透光区域，能够提高开口率。
在其他实施方式中，电容元件433也可以不使用第一扫描线424的金属层制成，例如可以在不透光区域321的垂直投影区域311内另外制作一层金属层以形成电容元件433的第二极板4332。另外，电容元件433也可以使用其他的电子元件代替，例如可以使用电阻代替，此时当第三薄膜晶体管432导通时，第二像素电极412和电阻形成通路，第二像素电极412的电荷流向电阻，从而可改变第二像素电极412的电荷以和第一像素电极411形成电压差，达到低色偏的目的。
参阅图5并结合图3，图5为图3所示的阵列基板31另一实施方式的结构示意图，其中，图中仅示出由一个像素单元51以及与其对应的驱动电路52和控制电路53所构成的一个像素结构。与上述实施方式不同的是，本实施方式的控制电路53包括第三薄膜晶体管531和电容元件532，对应本像素单元51的第三薄膜晶体管531与相邻下一像素单元所对应的第一扫描线524’连接。
此外，本实施方式中，彩色滤光基板32的不透光区域321在阵列基板31上的垂直投影区域311包括了两个像素单元51之间的区域以及一个像素单元51中的第一像素电极511和第二像素电极512之间的区域。第一像素电极511和第二像素电极512沿第一扫描线524的延伸方向依次排列，驱动电路52中的第一薄膜晶体管521、第二薄膜晶体管522以及第一扫描线524位于沿竖直方向依次排列且相邻的两个像素单元之间的不透光区域321的垂直投影区域311内，数据线523位于第一像素电极511和第二像素电极512之间的不透光区域321的垂直投影区域311内。第三薄膜晶体管531和电容元件532位于沿水平方向依次排列且相邻的两个像素单元之间的不透光区域321的垂直投影区域311内。
其中，对应于本像素单元51的驱动电路52中，其第一扫描线524分别与第一薄膜晶体管521的栅极和第二薄膜晶体管522的栅极电连接，以控制第一薄膜晶体管521和第二薄膜晶体管522的导通和关闭；数据线523分别与第一薄膜晶体管521的源极和第二薄膜晶体管522的源极电连接；第一薄膜晶体管521的漏极与第一像素电极511电连接，第二薄膜晶体管522的漏极与第二像素电极512电连接。对应于本像素单元51的控制电路53中，其第三薄膜晶体管531的栅极与和本像素单元51相邻的下一像素单元对应的第一扫描线524’电性连接，所述的和本像素单元51相邻的下一像素单元为沿竖直方向排列且与本像素单元51相邻的下一像素单元；第三薄膜晶体管531的源极和第二像素电极512电连接，第三薄膜晶体管531的漏极和电容元件532的一端连接，电容元件532的另一端连接阵列基板31的公共电极54。
在本像素单元51对应的第一扫描线524和数据线523的共同作用下对第一像素电极511和第二像素电极512输入显示所需的显示信号后，停止对本像素单元51对应的第一扫描线524输入扫描信号，并对与本像素单元51相邻的下一像素单元对应的第一扫描线524’输入扫描信号，由此使得对应本像素单元51的第三薄膜晶体管531导通，使得第二像素512的部分电荷流向电容元件532，从而使得第二像素电极512和第一像素电极511形成电压差，由此可以达到降低色偏的效果。此外，通过利用下一条第一扫描线来控制上一行的第三薄膜晶体管，可以减少扫描线的数量，降低成本的同时还可以进一步提高开口率。
其中，电容元件532的第一极板5321与第三薄膜晶体管531的漏极为使用同一金属层制成，第二极板5322与对应本像素单元51的第一扫描线524为使用同一金属层制成，因此可以将电容元件532形成于不透光区域321的垂直投影区域311内，由此能够提高开口率。
本发明还提供阵列基板的一实施方式，其中，阵列基板为上述任一实施方式所述的阵列基板。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种阵列基板，其中，包括像素单元和与所述像素单元对应的驱动电路、控制电路，所述像素单元包括第一像素电极和第二像素电极；
    所述第一像素电极和所述第二像素电极均为鱼骨状电极；
    所述驱动电路包括第一开关管、第二开关管、数据线以及第一扫描线；
    所述第一扫描线用以控制所述第一开关管和第二开关管的导通与关闭，在所述第一开关管和所述第二开关管导通时，所述数据线用以分别通过所述第一开关管和所述第二开关管对所述第一像素电极和所述第二像素电极输入显示信号；
    所述控制电路包括第二扫描线、第三开关管和电容元件，所述电容元件位于不透光区域的垂直投影区域内，所述第二扫描线用以控制所述第三开关管的导通与关闭，所述电容元件通过所述第三开关管与所述第二像素电极连接，以在所述第三开关管导通时改变所述第二像素电极的电压，进而使所述第一像素电极和所述第二像素电极之间存在预设电压差。
  2. 根据权利要求1所述的阵列基板，其中，
    所述第一开关管、第二开关管以及第三开关管均为薄膜晶体管，所述电容元件包括第一极板和第二极板，形成所述第一极板的金属层与形成所述第三开关管的漏极的金属层为同一金属层，所述第二极板为形成所述第一扫描线的金属层。
  3. 根据权利要求2所述的阵列基板，其中，
    所述第一像素电极和所述第二像素电极沿所述数据线方向依次排列，所述控制电路和部分所述驱动电路位于所述第一像素电极和所述第二像素电极之间。
  4. 一种阵列基板，其中，包括像素单元和与所述像素单元对应的驱动电路、控制电路，所述像素单元包括第一像素电极和第二像素电极；
    所述驱动电路与所述第一像素电极和所述第二像素电极连接以对所述第一像素电极和所述第二像素电极输入显示信号；所述控制电路与所述第一像素电极和所述第二像素电极中的其中一个连接以控制所述第一像素电极和所述第二像素电极之间形成预定电压差；
    所述控制电路位于不透光区域的垂直投影区域内。
  5. 根据权利要求4所述的阵列基板，其中，
    所述驱动电路包括第一开关管、第二开关管、数据线以及第一扫描线；
    所述第一扫描线用以控制所述第一开关管和第二开关管的导通与关闭，在所述第一开关管和所述第二开关管导通时，所述数据线用以分别通过所述第一开关管和所述第二开关管对所述第一像素电极和所述第二像素电极输入显示信号；
    所述控制电路包括第二扫描线、第三开关管和电容元件，所述电容元件位于不透光区域的垂直投影区域内，所述第二扫描线用以控制所述第三开关管的导通与关闭，所述电容元件通过所述第三开关管与所述第二像素电极连接，以在所述第三开关管导通时改变所述第二像素电极的电压，进而使所述第一像素电极和所述第二像素电极之间存在预设电压差。
  6. 根据权利要求5所述的阵列基板，其中，
    所述第一开关管、第二开关管以及第三开关管均为薄膜晶体管，所述电容元件包括第一极板和第二极板，形成所述第一极板的金属层与形成所述第三开关管的漏极的金属层为同一金属层，所述第二极板为形成所述第一扫描线的金属层。
  7. 根据权利要求6所述的阵列基板，其中，
    所述第一像素电极和所述第二像素电极沿所述数据线方向依次排列，所述控制电路和部分所述驱动电路位于所述第一像素电极和所述第二像素电极之间。
  8. 根据权利要求4所述的阵列基板，其中，
    所述驱动电路包括第一开关管、第二开关管、数据线以及第一扫描线；
    所述第一扫描线用以控制所述第一开关管和第二开关管的导通与关闭，在所述第一开关管和所述第二开关管导通时，所述数据线用以分别通过所述第一开关管和所述第二开关管对所述第一像素电极和所述第二像素电极输入显示信号；
    所述控制电路包括第三开关管和电容元件，所述电容元件位于相邻两个像素单元之间的不透光区域的垂直投影区域内，所述第三开关管与相邻下一像素单元对应的驱动电路中的第一扫描线连接，以在所述相邻下一像素单元对应的驱动电路中的第一扫描线的作用下实现导通与关闭，所述电容元件通过所述第三开关管与所述第二像素电极连接，以在所述第三开关管导通时改变所述第二像素电极的电压，进而使所述第一像素电极和所述第二像素电极之间存在预设电压差。
  9. 根据权利要求8所述的阵列基板，其中，
    所述第一像素电极和所述第二像素电极沿所述第一扫描线的方向依次排列，所述控制电路和部分所述驱动电路位于相邻两个像素单元之间。
  10. 一种液晶显示面板，其中，包括阵列基板、彩色滤光基板以及位于所述阵列基板和所述彩色滤光基板之间的液晶层，所述彩色滤光基板包括不透光区域，所述阵列基板包括像素单元和与所述像素单元对应的驱动电路、控制电路，所述像素单元包括第一像素电极和第二像素电极；
    所述驱动电路与所述第一像素电极和所述第二像素电极连接以对所述第一像素电极和所述第二像素电极输入显示信号；所述控制电路与所述第一像素电极和所述第二像素电极中的其中一个连接以控制所述第一像素电极和所述第二像素电极之间形成预定电压差；
    所述控制电路位于所述不透光区域的垂直投影区域内。
  11. 根据权利要求10所述的液晶显示面板，其中，
    所述驱动电路包括第一开关管、第二开关管、数据线以及第一扫描线；
    所述第一扫描线用以控制所述第一开关管和第二开关管的导通与关闭，在所述第一开关管和所述第二开关管导通时，所述数据线用以分别通过所述第一开关管和所述第二开关管对所述第一像素电极和所述第二像素电极输入显示信号；
    所述控制电路包括第二扫描线、第三开关管和电容元件，所述电容元件位于不透光区域的垂直投影区域内，所述第二扫描线用以控制所述第三开关管的导通与关闭，所述电容元件通过所述第三开关管与所述第二像素电极连接，以在所述第三开关管导通时改变所述第二像素电极的电压，进而使所述第一像素电极和所述第二像素电极之间存在预设电压差。
  12. 根据权利要求11所述的液晶显示面板，其中，
    所述第一开关管、第二开关管以及第三开关管均为薄膜晶体管，所述电容元件包括第一极板和第二极板，形成所述第一极板的金属层与形成所述第三开关管的漏极的金属层为同一金属层，所述第二极板为形成所述第一扫描线的金属层。
  13. 根据权利要求12所述的液晶显示面板，其中，
    所述第一像素电极和所述第二像素电极沿所述数据线方向依次排列，所述控制电路和部分所述驱动电路位于所述第一像素电极和所述第二像素电极之间。
  14. 根据权利要求10所述的液晶显示面板，其中，
    所述驱动电路包括第一开关管、第二开关管、数据线以及第一扫描线；
    所述第一扫描线用以控制所述第一开关管和第二开关管的导通与关闭，在所述第一开关管和所述第二开关管导通时，所述数据线用以分别通过所述第一开关管和所述第二开关管对所述第一像素电极和所述第二像素电极输入显示信号；
    所述控制电路包括第三开关管和电容元件，所述电容元件位于相邻两个像素单元之间的不透光区域的垂直投影区域内，所述第三开关管与相邻下一像素单元对应的驱动电路中的第一扫描线连接，以在所述相邻下一像素单元对应的驱动电路中的第一扫描线的作用下实现导通与关闭，所述电容元件通过所述第三开关管与所述第二像素电极连接，以在所述第三开关管导通时改变所述第二像素电极的电压，进而使所述第一像素电极和所述第二像素电极之间存在预设电压差。
  15. 根据权利要求14所述的液晶显示面板，其中，
    所述第一像素电极和所述第二像素电极沿所述第一扫描线的方向依次排列，所述控制电路和部分所述驱动电路位于相邻两个像素单元之间。
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