WO2014059690A1 - 一种阵列基板及液晶显示装置 - Google Patents

一种阵列基板及液晶显示装置 Download PDF

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Publication number
WO2014059690A1
WO2014059690A1 PCT/CN2012/083502 CN2012083502W WO2014059690A1 WO 2014059690 A1 WO2014059690 A1 WO 2014059690A1 CN 2012083502 W CN2012083502 W CN 2012083502W WO 2014059690 A1 WO2014059690 A1 WO 2014059690A1
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Prior art keywords
switching element
scan line
pixel electrode
pixel
electrically connected
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PCT/CN2012/083502
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English (en)
French (fr)
Inventor
陈政鸿
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深圳市华星光电技术有限公司
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Priority to DE112012006930.7T priority Critical patent/DE112012006930B4/de
Priority to US13/699,633 priority patent/US8928704B2/en
Publication of WO2014059690A1 publication Critical patent/WO2014059690A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular to an array substrate and a liquid crystal display device.
  • the FPR 3D display system includes a lower glass substrate 11, an upper glass substrate 12, and a polarization (Patterned Retarder) film 13.
  • the lower glass substrate 11 and the upper glass substrate are used to form a liquid crystal display panel
  • the liquid crystal display panel includes an image unit 14 for displaying an image
  • the image unit 14 includes a left image unit 141 corresponding to one pixel unit and for displaying a left eye image, and A right image unit 142 corresponding to one pixel and used to display a right eye image.
  • the polarizing film 13 is attached to the liquid crystal display panel, and cooperates with the polarizing glasses 16 to separate the 3D picture into the left eye image 21 and the right eye image 22. And respectively transmitted to the left and right eyes of the viewer to achieve stereoscopic display.
  • crosstalk between the left and right eye images may occur.
  • the left eye image 23 originally sent to the left eye is simultaneously observed by the right eye, resulting in Binocular signal crosstalk.
  • a common solution is to increase the black matrix between the left image unit 141 and the right image unit 142 (Black
  • the width of the Matrix, BM) 15 is to reduce the possibility of crosstalk of the binocular signals, and the width of the black matrix 15 needs to reach a certain width to reduce the crosstalk of the two eyes to some extent.
  • the display color of the large viewing angle is greatly different from the color displayed by the front view.
  • the Charge-shared (charge sharing) technique is generally adopted. Achieve low color cast.
  • FIG. 2 in a Charge-shared pixel design, one pixel Pixel(N) 30 is divided into a main pixel (N) and a sub-pixel (N), and one Pixel (N) 30 corresponds to two different times and The scan line (N) and the scan line (M) are sequentially turned on.
  • the scan line (N) When the scan line (N) is at a high potential, the thin film transistor 31 and the thin film transistor 32 are simultaneously turned on, and the data line (x) simultaneously sends a voltage signal to the main pixel (N) and the sub-pixel (N) through the thin film transistors 31 and 32, respectively.
  • the main pixel (N) and the sub-pixel (N) have the same potential.
  • the scan line (M) After the scan line (N) is turned off, the scan line (M) inputs a high potential to turn on the thin film transistor 33, the input end of the thin film transistor 33 is connected to the pixel electrode of the sub-pixel (N), and the output end is connected to one end of the storage capacitor 34, and is stored.
  • the other end of the capacitor 34 is typically connected to a common electrode (Com) of another substrate.
  • Com common electrode
  • the two scan lines (N) and scan lines (M) of the pixel Pixel (N) 30 are located between the main pixel (N) and the sub-pixel (N), and are scanned.
  • the thin film transistors 31 and 32 connected to the line (N), and the thin film transistor 33 and the storage capacitor 34 connected to the scanning line (M) are located between the main pixel (N) and the sub-pixel (N). As shown in FIG.
  • this causes the main dark area 35 of the pixel Pixel(N) 30 corresponding to the opaque area to be located between the main pixel (N) and the sub-pixel (N) of the pixel Pixel(N) 30, mainly dark 35
  • the width of the dark region 36 corresponding to the opaque region between the pixel Pixel (N) 30 and the pixel Pixel (N+1) 40 is relatively small, so that the FPR will be When 3D display technology is applied to MVA panels, it corresponds to FPR
  • the width of the black matrix 15 between the left image unit 141 and the right image unit 142 in the 3D display mode (as shown in FIG. 1) is also relatively small, which is disadvantageous for reducing binocular signal crosstalk. Therefore, the above-mentioned Charge-shared pixel design is not suitable for FPR. 3D display mode.
  • one pixel Pixel(N) 50 is divided into a main pixel (N) and a sub-pixel (N), and two corresponding scan lines are sequentially opened.
  • (N) and the scan line (M) are located on the same side of the pixel Pixel (N) 50.
  • the scan line (N) is connected to the pixel electrodes of the main pixel (N) and the sub-pixel (N) through the thin film transistors 51 and 52, respectively, and the scan line (M) is connected to the pixel electrode of the sub-pixel (N) through the thin film transistor 53.
  • the output terminal of the thin film transistor 53 is connected to the storage capacitor 54.
  • the pixel-designed pixel design, the pixel corresponding to the pixel Pixel (N) 50 and the thin film transistor are located on the same side of the pixel Pixel (N) 50, as shown in Figure 5, so that two different pixels Pixel ( The width of the region between N) 50 and Pixel (N+1) 60 becomes larger, that is, the width of the main dark region 57 corresponding to the opaque region is larger, so that FPR is When 3D display technology is applied to MVA panels, it corresponds to FPR
  • the width of the black matrix 15 between the left image unit 141 and the right image unit 142 in the 3D display mode (shown in FIG. 1) is also relatively large, and the binocular signal crosstalk can be reduced. Therefore, this Charge-shared pixel design is more suitable for FPR than the Charge-shared pixel design shown in Figure 2. 3D display mode.
  • the line 55 connected to the pixel electrode of the sub-pixel (N) needs to pass through the area where the main pixel (N) is located, resulting in the main pixel (N) and the sub-pixel ( There is a large parasitic capacitance 56 between the pixel electrodes of N).
  • the parasitic capacitance 56 reduces the potential of the main pixel (N) and the sub-pixel (N), and in the case of four mask processes (4PEP), the parasitic capacitance 56 changes due to illumination, which affects the reliability of the liquid crystal display panel.
  • the area where the line 55 passes through the main pixel (N) also causes a decrease in the transmittance and the aperture ratio.
  • the technical problem to be solved by the present invention is to provide an array substrate and a liquid crystal display device, which can reduce the phenomenon of double-eye signal crosstalk in the 3D display mode, effectively improve the yield of the liquid crystal display panel process, and can reduce the color difference at a large viewing angle. , improve penetration and aperture ratio.
  • a technical solution adopted by the present invention is to provide an array substrate applied to an MVA type liquid crystal display panel, including at least a plurality of first scan lines, second scan lines, data lines, and a plurality of rows and columns.
  • a pixel unit each of which includes a switching element and a pixel electrode, each pixel unit corresponding to at least one first scan line, a second scan line, and a data line;
  • the switching element of each pixel unit includes a control end, an input end, and The output ends are at least three, at least respectively a first switching element, a second switching element and a third switching element;
  • the pixel electrode comprises a main pixel electrode and a sub-pixel electrode, and the first scan line and the second scan line respectively A switching element and a second switching element are connected to respectively control on and off of the first switching element and the second switching element, and the data lines are respectively connected to the main pixel electrode through a region where the main pixel electrode is located and a region where the sub-pixel electrode is located And a sub-pixel electrode with an input voltage signal;
  • the array substrate further includes a dark region corresponding to the opaque region, and the dark region One portion is disposed between the pixel units, and the first scan line, the second scan line, and the switching element
  • the first scan line and the first switching element of the pixel unit are both located on one side of the pixel unit, and the second scan line, the second switching element and the third switching element of the pixel unit are both located on the other side of the pixel unit.
  • the storage capacitor is composed of a metal layer on the same side of the array substrate and a common electrode of the liquid crystal display panel, and the polarity of the charge stored in the storage capacitor and the polarity of the charge of the sub-pixel electrode before the third switching element is not turned on in contrast.
  • the first switching element, the second switching element, and the third switching element are respectively a first thin film transistor, a second thin film transistor, and a third thin film transistor;
  • the first thin film transistor includes a first gate, a first source, and a first a drain, the first source is electrically connected to the data line as an input end, the first drain is electrically connected to the main pixel electrode as an output end, and the first gate is electrically connected to the first scan line as a control end to control the first thin film transistor Turning on and off;
  • the second thin film transistor includes a second gate, a second source, and a second drain, the second source is electrically connected to the data line as an input terminal, and the second drain is used as an output terminal and a sub-pixel
  • the electrode is electrically connected, the second gate is electrically connected to the second scan line as a control terminal to control conduction and disconnection of the second thin film transistor, and the third thin film transistor includes a third gate, a third source, and a third drain The third source is electrically
  • a liquid crystal display device including a polarizing film and a liquid crystal display panel
  • the liquid crystal display panel includes an array substrate and a color filter substrate
  • the color filter substrate includes a black matrix
  • the polarizing film is disposed on an outer side of the color filter substrate;
  • the array substrate includes at least a plurality of first scan lines, second scan lines, data lines, and a plurality of pixel units arranged in rows and columns, each of the pixel units including a switching element and a pixel electrode
  • Each pixel unit corresponds to at least one first scan line, second scan line, and data line;
  • the switching element of each pixel unit includes a control end, an input end, and an output end, and the number is at least three, at least respectively, the first switch An element, a second switching element, and a third switching element;
  • the pixel electrode includes a main pixel electrode and a sub-pixel electrode, and the first scan line and the second scan line are respectively connected to the first switching element and the second switching element to respectively control the first switch
  • the element and the second switching element are turned on and off, and the data lines pass through the main pixel electrode respectively
  • the area and the sub-pixel electrode are connected to the main pixel electrode and the sub-
  • the first scan line and the first switching element of the pixel unit are both located on one side of the pixel unit, and the second scan line, the second switching element and the third switching element of the pixel unit are both located on the other side of the pixel unit.
  • the storage capacitor is composed of a metal layer on the same side of the array substrate and a common electrode of the liquid crystal display panel, and the polarity of the charge stored in the storage capacitor and the polarity of the charge of the sub-pixel electrode before the third switching element is not turned on in contrast.
  • the first switching element, the second switching element, and the third switching element are respectively a first thin film transistor, a second thin film transistor, and a third thin film transistor;
  • the first thin film transistor includes a first gate, a first source, and a first a drain, the first source is electrically connected to the data line as an input end, the first drain is electrically connected to the main pixel electrode as an output end, and the first gate is electrically connected to the first scan line as a control end to control the first thin film transistor Turning on and off;
  • the second thin film transistor includes a second gate, a second source, and a second drain, the second source is electrically connected to the data line as an input terminal, and the second drain is used as an output terminal and a sub-pixel
  • the electrode is electrically connected, the second gate is electrically connected to the second scan line as a control terminal to control conduction and disconnection of the second thin film transistor, and the third thin film transistor includes a third gate, a third source, and a third drain The third source is electrically
  • the liquid crystal display panel is an MVA type liquid crystal display panel.
  • the array substrate of the present invention has at least one first scan line, a second scan line, and a data line for each pixel unit, each pixel unit includes a switching element and a pixel electrode, and the pixel electrode includes a main pixel.
  • An electrode and a sub-pixel electrode wherein the data line is connected to the main pixel electrode and the sub-pixel electrode through a region where the main pixel electrode is located and a region where the sub-pixel electrode is located to input a voltage signal, so that the connection line connected to the sub-pixel electrode does not need to pass through the main pixel
  • the region where the electrode is located is connected to the sub-pixel electrode, thereby reducing the parasitic capacitance between the region where the main pixel electrode is located and the region where the sub-pixel electrode is located, so as to improve the reliability of the liquid crystal display panel in the subsequent process, and at the same time
  • the transmittance is increased to some extent; and the first scan line, the second scan line, and the switching element are disposed between the adjacent pixel units, and the area between the pixel units is a dark area corresponding to the opaque area.
  • the sub-pixel electrode is connected to the storage capacitor through the third switching element, and when the third switching element is turned on, the charge of the sub-pixel electrode is neutralized with the charge of the storage capacitor, so that the sub-pixel electrode The electric field is reduced, causing the voltage to decrease.
  • a preset voltage difference exists between the main pixel electrode and the sub-pixel electrode, thereby reducing the color difference at a large viewing angle and achieving a low color shift effect.
  • FIG. 1 is a schematic structural view of an FPR 3D display system in the prior art, and shows optical path differences under two viewing angle conditions;
  • FIG. 2 is a schematic structural view of a pixel of an MVA type liquid crystal display panel in the prior art
  • FIG. 3 is a schematic plan view of a pixel of the liquid crystal display panel of FIG. 2;
  • FIG. 4 is a schematic structural view of a pixel of another MVA type liquid crystal display panel in the prior art
  • Figure 5 is a plan view showing the pixel of the liquid crystal display panel of Figure 4.
  • FIG. 6 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • FIG. 7 is a schematic structural view of an embodiment of a pixel unit of the array substrate of FIG. 6;
  • Figure 8 is a plan view of the pixel unit of Figure 7.
  • an embodiment of the present invention applied to an array substrate of an MVA type liquid crystal display panel includes a plurality of first scan lines 101, second scan lines 102, data lines 103, and a plurality of pixel units 104 arranged in rows and columns.
  • Each of the pixel units 104 includes a switching element 1041 and a pixel electrode 1042.
  • Each of the pixel units 104 corresponds to one first scan line 101, second scan line 102, and data line 103.
  • FIG. 7 is a schematic structural diagram of an embodiment of a pixel unit of the array substrate of FIG. 6, and FIG. 7 shows any three adjacent pixel units arranged in the direction of the data line 203 of FIG. a structure in which three adjacent pixel units arranged along the direction of the data line 203 are shown, and the intermediate pixel unit, the following pixel unit, and the preceding pixel unit are the first pixel unit 204, the second pixel unit 205, and the The three pixel unit 206, the third pixel unit 206 shows only a partial structure.
  • the number of switching elements of the first pixel unit 204 is three, which are the first switching element 2041, the second switching element 2042, and the third switching element 2043, respectively.
  • the pixel electrode 2010 of the first pixel unit 204 includes a main pixel electrode 2044 and a sub-pixel electrode 2045.
  • the area where the main pixel electrode 2044 is located is the main pixel area 2046
  • the area where the sub-pixel electrode 2045 is located is the sub-pixel area 2047.
  • the first scan line 201 is connected to the first switching element 2041 to input a scan signal, thereby controlling the on and off of the first switching element 2041; the second scan line 202 is connected to the second switching element 2042 to input a scan signal, thereby controlling The second switching element 2042 is turned on and off.
  • the data line 203 is connected to the main pixel electrode 2044 through the first switching element 2041, and the connection line (ie, the connection line between the first output end 20413 of the first switching element 2041 and the main pixel electrode 2044) directly passes through the main pixel area 2046 and The main pixel electrode 2044 is connected to input a data signal to the main pixel electrode 2044.
  • the data line 203 is connected to the sub-pixel electrode 2045 through the second switching element 2042, and the connection line (ie, the connection line between the second output end 20423 of the second switching element 2042 and the sub-pixel electrode 2045) directly passes through the sub-pixel region 2047.
  • the sub-pixel electrode 2045 can be connected to the sub-pixel electrode 2045 without passing through the main pixel region 2046 to input a data signal.
  • connection line connected to the main pixel electrode 2044 does not need to be connected to the main pixel electrode 2044 via the sub-pixel region 2047, and the connection line connected to the sub-pixel electrode 2045 does not need to pass through the main pixel region 2046 and the sub-pixel electrode 2045.
  • the connection thereby reduces the parasitic capacitance between the main pixel region 2046 and the sub-pixel region 2047.
  • the array substrate further includes a dark region 300 (shaded portion in FIG. 8 ) corresponding to the opaque region, and the first scan line 201 and the second corresponding to the first pixel unit 204 .
  • the scan line 202, the first switching element 2041, the second switching element 2042, and the third switching element 2043 are disposed between the first pixel unit 204 and the pixel units 206, 205 adjacent to each other.
  • a portion of the dark region 300 corresponding to the opaque region is disposed between the pixel units, such as the dark region 301 between the first pixel unit 204 and the second pixel unit 205, that is, between three adjacent pixel units.
  • the area is a portion of the dark area 300 corresponding to the opaque area.
  • the first scan line 201 and the first switching element 2041 corresponding to the first pixel unit 204 are both located on the upper side of the first pixel unit 204, and the second scan corresponding to the third pixel unit 206 (only a partial structure is shown)
  • the line 207, the second switching element 2061 and the third switching element 2062 are adjacent to each other to input a scan signal to the main pixel electrode 2044; and the second pixel line 204 corresponding to the first pixel unit 204, the second switching element 2042 and the third switch
  • the element 2043 is located on the lower side of the first pixel unit 204, and the first scan line 208 corresponding to the second pixel unit 205 is adjacent to the first switching element 209 to input a scan signal to the sub-pixel electrode 2045.
  • the array substrate of the present embodiment is assembled to form a liquid crystal display panel, and when the liquid crystal display panel is driven to display, the main pixel electrode 2044 and the sub-pixel electrode 2045 are controlled to have a preset voltage difference so that the liquid crystal display panel has a large viewing angle. Low color cast effect.
  • the first control terminal 20411 of the first switching element 2041 of the first pixel unit 204 is electrically connected to the first scan line 201
  • the first input terminal 20412 is electrically connected to the data line 203
  • the first output terminal 20413 is electrically connected to the main pixel electrode 2044.
  • the second control terminal 20421 of the second switching element 2042 is electrically connected to the second scan line 202, the second input terminal 20422 is electrically connected to the data line 203, and the second output terminal 20423 is electrically connected to the sub-pixel electrode 2045.
  • the third control terminal 20431 of the third switching element 2043 is electrically connected to the first scan line 208 corresponding to the second pixel unit 205, the third input terminal 20432 is electrically connected to the sub-pixel electrode 2045, and the third output terminal 20433 is used for electrically connecting the storage capacitor. 2011.
  • the storage capacitor 2011 is composed of a metal layer on the same side of the array substrate and a common electrode (Com) of another substrate (usually a color filter substrate), and the third output terminal 20433 of the third switching element 2043 is electrically connected to form a storage.
  • the metal layer of the capacitor 2011 is such that the storage capacitor 2011 is connected to the sub-pixel electrode 2045 through the third switching element 2043.
  • the first scan line 201 and the second scan line 202 corresponding to the first pixel unit 204 input scan signals to the first control terminal 20411 and the second control terminal 20421 to respectively control the first switching element 2041 and
  • the second switching element 2042 is turned on, and then the data line 203 inputs a data signal to the first input terminal 20411 and the second input terminal 20421, so that the data signal is transmitted to the first pixel through the first output terminal 20413 and the second output terminal 20423, respectively.
  • the main pixel electrode 2044 and the sub-pixel electrode 2045 have the same potential. Turning off the first scan line 201 and the second scan line 202 to stop inputting the scan signal to the first pixel unit 204, and starting to drive the display of the subsequent pixel unit, that is, the second pixel unit 205, firstly corresponding to the second pixel unit 205
  • the scan line 208 inputs a scan signal to control the conduction of the first switching element 209 of the second pixel unit 205.
  • the third control terminal 20431 of the third switching element 2043 corresponding to the first pixel unit 204 is electrically connected to the first scan line 208 corresponding to the second pixel unit 205, when the scan signal is input on the first scan line 208, The third switching element 2043 is turned on.
  • the liquid crystal display panel When driving the display of the liquid crystal display panel, the liquid crystal display panel has a polarity switching, and the display voltage is continuously replaced between the positive polarity and the negative polarity to avoid the characteristic damage caused by the liquid crystal molecules being always fixed in one direction. .
  • the display voltage When the voltage of the pixel electrode 2010 is higher than the common electrode voltage, the display voltage is positive polarity, and vice versa.
  • the polarity of the charge stored in the storage capacitor 2011 is opposite to the polarity of the charge of the sub-pixel electrode 2045 of the first pixel unit 204, so
  • the charge of the sub-pixel electrode 2045 is neutralized by the charge of the third switching element 2043 and the storage capacitor 2011, so that the electric field of the sub-pixel electrode 2045 is reduced, thereby causing the main pixel electrode 2044 and the second.
  • the size of the storage capacitor 2011 is adjusted such that there is a preset voltage difference between the main pixel electrode 2044 and the sub-pixel electrode 2045 to control the deflection of the liquid crystal molecules, thereby reducing the color difference at a large viewing angle and achieving a low color shift. Effect.
  • the first switching element 2041, the second switching element 2042, and the third switching element 2043 of the present embodiment are respectively a first thin film transistor, a second thin film transistor, and a third thin film transistor, and each thin film transistor includes a gate as a control end.
  • the first gate of the first thin film transistor is electrically connected to the first scan line 201 to control the on and off of the first thin film transistor
  • the first source is electrically connected to the data line 203, the first drain and the main
  • the pixel electrode 2044 is electrically connected such that the data line 203 inputs a data signal to the main pixel electrode 2044 through the first thin film transistor
  • the second gate of the second thin film transistor is electrically connected to the second scan line 202 to control the second thin film transistor.
  • the second source is electrically connected to the data line 203, and the second drain is electrically connected to the sub-pixel electrode 2045, so that the data line 203 inputs the data signal to the sub-pixel electrode 2045 through the second thin film transistor;
  • the third gate of the three thin film transistor is electrically connected to the first scan line 208 corresponding to the second pixel unit 205 to control the conduction and disconnection of the third thin film transistor, and the third source is electrically connected to the sub-pixel electrode 2045, and the third The drain is used to electrically connect to the storage capacitor 2011 to control the presence of a preset voltage difference between the main pixel electrode 2044 and the sub-pixel electrode 2045.
  • the pixel electrode 2010 in the first pixel unit 204 includes a main pixel electrode 2044 and a sub-pixel electrode 2045, so that the connection line between the first output end 20413 of the first switching element 2041 and the main pixel electrode 2044 passes directly.
  • the main pixel region 2046 where the main pixel electrode 2044 is located is connected to the main pixel electrode 2044, and the second output terminal 20423 of the second switching element 2042 and the third input terminal 20432 of the third switching element 2043 are connected to the sub-pixel electrode 2045.
  • the line directly passes through the sub-pixel region 2047 where the sub-pixel electrode 2045 is located without connecting the sub-pixel electrode 2045 through the main pixel region 2046, and can reduce the parasitic capacitance between the main pixel region 2046 and the sub-pixel region 2047, and improve the subsequent four masks.
  • the reliability of the liquid crystal display panel in the process can also improve the transmittance and the aperture ratio to some extent.
  • the area between the pixel units adjacent in the direction of the data line 203 is the dark area area 301 corresponding to the opaque area
  • the first scan line 201 corresponding to the first pixel unit 204 and the first switching element 2041 are disposed at the first Between the pixel unit 204 and the third pixel unit 206, the second scan line 202, the second switching element 2042, and the third switching element 2043 are disposed between the first pixel unit 204 and the second pixel unit 205 such that the scan lines and
  • the switching elements are arranged between the adjacent pixel units, increasing the width of the dark area 301 between the pixel units, thereby reducing the crosstalk phenomenon of the two eyes at a large viewing angle in the 3D display mode, and also improving Penetration rate.
  • the sub-pixel electrode 2045 is connected to the storage capacitor 2011 through the third switching element 2043.
  • a preset voltage difference between the main pixel electrode 2044 and the sub-pixel electrode 2045 can be controlled, thereby controlling the liquid crystal molecules.
  • the deflection makes it possible to reduce the color difference at a large viewing angle and achieve a low color shift effect.
  • the present invention also provides an embodiment of a liquid crystal display device comprising a polarizing film and a liquid crystal display panel.
  • the polarizing film is used to separate the 3D picture displayed by the liquid crystal display panel into a left eye signal and a right eye signal for simultaneous transmission to the viewer's eyes, so that the viewer can see less flickering 3D pictures.
  • the liquid crystal display panel includes an array substrate and a color filter substrate.
  • the color filter substrate includes a black matrix, and the polarizing film is disposed outside the color filter substrate.
  • the array substrate is the array substrate described in the above embodiment.
  • the array substrate includes a plurality of first scan lines 101, second scan lines 102, data lines 103, and a plurality of pixel units 104 arranged in rows and columns.
  • Each of the pixel units 104 includes a switching element 1041 and a pixel unit 1042, and each of the pixel units 104 corresponds to at least one first scan line 101, second scan line 102, and data line 103.
  • the dark area 301 between the first pixel unit 204 and the second pixel unit 205 shown in FIG. 7 and FIG. 8 is a vertical projection coverage area of the black matrix of the color filter substrate, and the first scan line is 201, the second scan line 202 and the three switching elements 2041-2043 are disposed in the vertical projection coverage area of the black matrix, and the transmittance and aperture ratio of the liquid crystal display panel can also be improved.
  • the liquid crystal display panel of the present embodiment is an MVA liquid crystal display panel.

Abstract

一种阵列基板，包括多条第一扫描线（201）、第二扫描线（202）、数据线（203）以及多个像素单元（204、205、206），每个像素单元（204）对应一条第一扫描线（201）、第二扫描线（202）和数据线（203）。每个像素单元（204）均包括开关元件（2041、2042、2043）和像素电极（2010），像素电极（2010）包括主像素电极（2044）和次像素电极（2045），数据线（203）分别经过主像素电极（2044）所在的区域和次像素电极（2045）所在的区域而连接主像素电极（2044）和次像素电极（2045）以输入电压信号。第一扫描线（201）、第二扫描线（202）以及开关元件（2041、2042、2043）设置于第一像素单元（204）与前后相邻的像素单元（205、206）之间，且像素单元（204、205、206）之间的区域为对应不透光区域的暗区（300）。该阵列基板能够减小3D显示模式下的信号串扰，同时减小大视角下的颜色差异。还公开了一种液晶显示装置。

Description

一种阵列基板及液晶显示装置
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种阵列基板及液晶显示装置。
【背景技术】
FPR（Film-type Patterned Retarder，偏光式）是现有3D液晶显示的成像方式之一。如图1所示，FPR 3D显示系统包括下玻璃基板11、上玻璃基板12、偏振（Patterned Retarder）薄膜13。下玻璃基板11和上玻璃基板用以形成液晶显示面板，液晶显示面板包括用于显示图像的图像单元14，图像单元14包括对应于一个像素单元并用于显示左眼图像的左图像单元141，以及对应于一个像素并用于显示右眼图像的右图像单元142。偏振薄膜13贴附在液晶显示面板上，通过与偏振眼镜16的配合以将3D画面分离为左眼图像21和右眼图像22。并分别传送至观看者的左眼和右眼以实现立体显示。但是在3D显示模式下，当观看者处于较大视角时，会出现左右眼影像互相串扰（Crosstalk）的现象，例如，原本送到左眼的左眼图像23同时被右眼观察到了，产生了双眼信号串扰。通常的解决方案是增加左图像单元141和右图像单元142之间的黑色矩阵（Black Matrix，BM）15的宽度，以减小双眼信号串扰的可能性，并且，黑色矩阵15的宽度需达到一定的宽度才能在一定程度上减少双眼信号串扰。
而在MVA（Multi-domain vertical alignment，多域分割垂直配向）型面板的液晶显示模式中，大视角的显示颜色与正视所显示的颜色存在较大差异，为了解决此色偏问题，一般采用Charge-shared（电荷共享）技术以达到低色偏的效果。如图2所示，在一种Charge-shared像素设计中，将一个像素Pixel（N）30分为主像素（N）和次像素（N），一个Pixel（N）30对应两条不同时间且依序开启的扫描线（N）和扫描线（M）。扫描线（N）为高电位时使得薄膜晶体管31和薄膜晶体管32同时导通，数据线（x）分别通过薄膜晶体管31和32将电压信号同时送至主像素（N）和次像素（N）的像素电极中，使得主像素（N）和次像素（N）电位相同。关闭扫描线（N）后，扫描线（M）输入高电位以导通薄膜晶体管33，薄膜晶体管33的输入端连接次像素（N）的像素电极，输出端连接储存电容34的一端，而储存电容34的另一端通常与另一基板的公共电极（Com）连接。驱动液晶显示面板显示时会有极性上的切换，在薄膜晶体管33开启前储存电容34所存储的电荷的极性会与目前次像素（N）的电荷极性相反，因此薄膜晶体管33开启后会导致次像素（N）的电荷被储存电容34中和，减小了次像素（N）的电场，使得主像素（N）和次像素（N）的电场产生差异，从而能达到大视角色偏补偿的目的。
但是，采用此种Charge-shared技术的像素设计，像素Pixel（N）30的两条扫描线（N）和扫描线（M）位于主像素（N）和次像素（N）之间，与扫描线（N）相连的薄膜晶体管31和32、以及与扫描线（M）相连的薄膜晶体管33和储存电容34均位于主像素（N）和次像素（N）之间。如图3所示，这会使得像素Pixel（N）30对应不透光区域的主要暗区35位于像素Pixel（N）30的主像素（N）和次像素（N）之间，主要暗35的宽度较大，而像素Pixel（N）30和像素Pixel（N+1）40之间的对应不透光区域的暗区36宽度相对较小，从而在将FPR 3D显示技术应用于MVA面板时，对应于FPR 3D显示模式下（如图1所示）的左图像单元141和右图像单元142之间的黑色矩阵15的宽度也相对较小，不利于减少双眼信号串扰。因此上述的Charge-shared像素设计并不适合用于FPR 3D显示模式。
在另一种Charge-shared像素设计中，参阅图4，同样地，一个像素Pixel（N）50分为主像素（N）和次像素（N），所对应的两条依序打开的扫描线（N）和扫描线（M）位于像素Pixel（N）50的同一侧。其中，扫描线（N）分别通过薄膜晶体管51和52与主像素（N）和次像素（N）的像素电极连接，扫描线（M）通过薄膜晶体管53与次像素（N）的像素电极相连，薄膜晶体管53的输出端连接存储电容54。此种Charge-shared的像素设计，像素Pixel（N）50所对应的扫描线以及薄膜晶体管等元件均位于像素Pixel（N）50的同一侧，如图5所示，使得两个不同像素Pixel（N）50和Pixel（N+1）60之间的区域宽度变大，即对应不透光区域的主要暗区57的宽度较大，从而在将FPR 3D显示技术应用于MVA面板时，对应于FPR 3D显示模式下（如图1所示）的左图像单元141和右图像单元142之间的黑色矩阵15的宽度也相对较大，能够减少双眼信号串扰。因此，此种Charge-shared像素设计相较于图2所示的Charge-shared像素设计更适合用于FPR 3D显示模式。
但是，在图4所示的Charge-shared像素设计中，与次像素（N）的像素电极连接的连线55需要经过主像素（N）所在的区域，导致主像素（N）和次像素（N）的像素电极之间存在较大的寄生电容56。寄生电容56会降低主像素（N）和次像素（N）的电位，且在四道光罩制程（4PEP）的情况下，寄生电容56会因光照而产生变化，影响了液晶显示面板的可靠性。同时，连线55经过主像素（N）所在的区域也会导致穿透率和开口率降低。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及液晶显示装置，能够减少3D显示模式下双眼信号串扰的现象，有效提高液晶显示面板制程的良率，同时能够减小大视角下的颜色差异，提高穿透率和开口率。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种应用于MVA型液晶显示面板的阵列基板，包括至少多条第一扫描线、第二扫描线、数据线以及多个行列排列的像素单元，每个像素单元均包括开关元件和像素电极，每个像素单元对应至少一条第一扫描线、第二扫描线以及数据线；每个像素单元的开关元件包括控制端、输入端以及输出端，数量为至少三个，至少分别是第一开关元件、第二开关元件以及第三开关元件；像素电极包括主像素电极和次像素电极，第一扫描线和第二扫描线分别与第一开关元件和第二开关元件连接以分别控制第一开关元件和第二开关元件的导通与断开，数据线分别经过主像素电极所在的区域和次像素电极所在的区域而连接主像素电极和次像素电极以输入电压信号；阵列基板还包括对应不透光区域的暗区，暗区的至少一部分设置于像素单元之间，第一扫描线、第二扫描线以及开关元件布局于像素单元之间；其中，对于任意三个沿数据线方向排列的相邻像素单元，位于中间的像素单元对应的第一扫描线和第一开关元件与前面的像素单元对应的第二扫描线、第二开关元件以及第三开关元件相邻，以对主像素电极输入扫描信号，中间的像素单元对应的第二扫描线、第二开关元件以及第三开关元件与后面的像素单元对应的第一扫描线和第一开关元件相邻，以对次像素电极输入扫描信号；第一开关元件的输出端电连接主像素电极，第二开关元件的输出端电连接次像素电极，第三开关元件的输出端用于电连接储存电容，第一开关元件和第二开关元件的输入端分别电连接数据线，第三开关的输入端电连接次像素电极，第一开关元件的控制端电连接第一扫描线，第二开关元件的控制端电连接第二扫描线，第三开关元件的控制端电连接后面的像素单元对应的第一扫描线；其中，在进入3D显示模式时，中间的像素单元对应的第一扫描线和第二扫描线输入扫描信号以分别控制第一开关元件和第二开关元件导通，数据线分别通过第一开关元件和第二开关元件同时输入电压信号至中间的像素单元的主像素电极和次像素电极，随后停止输入扫描信号至第一扫描线和第二扫描线；停止输入扫描信号至第一扫描线和第二扫描线后，与第三开关元件的控制端电连接的后面的像素单元对应的第一扫描线输入扫描信号以控制第三开关元件导通，中间的像素单元的次像素电极的电压信号通过第三开关元件耦合至与第三开关元件的输出端电连接的储存电容，调整储存电容的大小以控制中间的像素单元的主像素电极和次像素电极之间存在预设电压差。
其中，像素单元的第一扫描线和第一开关元件均位于像素单元的一侧，像素单元的第二扫描线、第二开关元件以及第三开关元件均位于像素单元的另一侧。
其中，储存电容由与阵列基板同一侧的金属层和液晶显示面板的公共电极构成，在第三开关元件未导通之前，储存电容所存储的电荷的极性与次像素电极的电荷的极性相反。
其中，第一开关元件、第二开关元件以及第三开关元件分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；第一薄膜晶体管包括第一栅极、第一源极以及第一漏极，第一源极作为输入端与数据线电连接，第一漏极作为输出端与主像素电极电连接，第一栅极作为控制端与第一扫描线电连接以控制第一薄膜晶体管的导通与断开；第二薄膜晶体管包括第二栅极、第二源极以及第二漏极，第二源极作为输入端与数据线电连接，第二漏极作为输出端与次像素电极电连接，第二栅极作为控制端与第二扫描线电连接以控制第二薄膜晶体管的导通与断开；第三薄膜晶体管包括第三栅极、第三源极以及第三漏极，第三源极与次像素电极电连接，第三漏极作为输出端用于与储存电容电连接，第三栅极与相邻一像素单元对应的第一扫描线电连接以控制第三薄膜晶体管的导通与断开。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种液晶显示装置，包括偏振薄膜以及液晶显示面板，液晶显示面板包括阵列基板和彩色滤光基板；彩色滤光基板包括黑色矩阵，偏振薄膜设置于彩色滤光基板的外侧；阵列基板包括至少多条第一扫描线、第二扫描线、数据线以及多个行列排列的像素单元，每个像素单元均包括开关元件和像素电极，每个像素单元对应至少一条第一扫描线、第二扫描线以及数据线；每个像素单元的开关元件包括控制端、输入端和输出端，数量为至少三个，至少分别是第一开关元件、第二开关元件以及第三开关元件；像素电极包括主像素电极和次像素电极，第一扫描线和第二扫描线分别与第一开关元件和第二开关元件连接以分别控制第一开关元件和第二开关元件的导通与断开，数据线分别经过主像素电极所在的区域和次像素电极所在的区域而连接主像素电极和次像素电极以输入电压信号；阵列基板还包括多个暗区，暗区位于黑色矩阵的垂直投影覆盖区域内，并且暗区的至少一部分设置于像素单元之间，第一扫描线、第二扫描线以及开关元件布局于像素单元之间；其中，对于任意三个沿数据线方向排列的相邻像素单元，位于中间的像素单元对应的第一扫描线和第一开关元件与前面的像素单元对应的第二扫描线、第二开关元件以及第三开关元件相邻，以对主像素电极输入扫描信号，中间的像素单元对应的第二扫描线、第二开关元件以及第三开关元件与后面的像素单元对应的第一扫描线和第一开关元件相邻，以对次像素电极输入扫描信号；第一开关元件的输出端电连接主像素电极，第二开关元件的输出端电连接次像素电极，第三开关元件的输出端用于电连接储存电容，第一开关元件和第二开关元件的输入端分别电连接数据线，第三开关的输入端电连接次像素电极，第一开关元件的控制端电连接第一扫描线，第二开关元件的控制端电连接第二扫描线，第三开关元件的控制端电连接后面的像素单元对应的第一扫描线；其中，在进入3D显示模式时，中间的像素单元对应的第一扫描线和第二扫描线输入扫描信号以分别控制第一开关元件和第二开关元件导通，数据线通过第一开关元件和第二开关元件同时输入电压信号至中间的像素单元的主像素电极和次像素电极，随后停止输入扫描信号至第一扫描线和第二扫描线；停止输入扫描信号至第一扫描线和第二扫描线后，与第三开关元件的控制端电连接的后面的像素单元对应的第一扫描线输入扫描信号以控制第三开关元件导通，中间的像素单元的次像素电极的电压信号通过第三开关元件耦合至与第三开关元件的输出端电连接的储存电容，调整储存电容的大小以控制中间的像素单元的主像素电极和次像素电极之间存在预设电压差。
其中，像素单元的第一扫描线和第一开关元件均位于像素单元的一侧，像素单元的第二扫描线、第二开关元件以及第三开关元件均位于像素单元的另一侧。
其中，储存电容由与阵列基板同一侧的金属层和液晶显示面板的公共电极构成，在第三开关元件未导通之前，储存电容所存储的电荷的极性与次像素电极的电荷的极性相反。
其中，第一开关元件、第二开关元件以及第三开关元件分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；第一薄膜晶体管包括第一栅极、第一源极以及第一漏极，第一源极作为输入端与数据线电连接，第一漏极作为输出端与主像素电极电连接，第一栅极作为控制端与第一扫描线电连接以控制第一薄膜晶体管的导通与断开；第二薄膜晶体管包括第二栅极、第二源极以及第二漏极，第二源极作为输入端与数据线电连接，第二漏极作为输出端与次像素电极电连接，第二栅极作为控制端与第二扫描线电连接以控制第二薄膜晶体管的导通与断开；第三薄膜晶体管包括第三栅极、第三源极以及第三漏极，第三源极与次像素电极电连接，第三漏极作为输出端用于与储存电容电连接，第三栅极与相邻一像素单元对应的第一扫描线电连接以控制第三薄膜晶体管的导通与断开。
其中，液晶显示面板是MVA型液晶显示面板。
本发明的有益效果是：本发明的阵列基板，其每个像素单元对应至少一条第一扫描线、第二扫描线以及数据线，每个像素单元包括开关元件和像素电极，像素电极包括主像素电极和次像素电极，数据线分别经过主像素电极所在的区域和次像素电极所在的区域而连接主像素电极和次像素电极以输入电压信号，使得与次像素电极连接的连接线无需经过主像素电极所在的区域而与次像素电极连接，由此能够减小主像素电极所在的区域和次像素电极所在的区域之间的寄生电容，以提高后续制程中液晶显示面板的可靠性，同时能在一定程度上提高穿透率；并且，将第一扫描线、第二扫描线以及开关元件布局于上下相邻的像素单元之间，且像素单元之间的区域为对应不透光区域的暗区，能够增大像素单元之间的不透光暗区的宽度，从而能减少3D显示模式下双眼信号串扰的现象；此外，使次像素电极通过第三开关元件与储存电容连接，在第三开关元件导通时，次像素电极的电荷会与储存电容的电荷发生中和，使得次像素电极的电场减小，造成电压降低，通过调整储存电容的大小可使得主像素电极和次像素电极之间存在预设电压差，从而能够减小大视角下的颜色差异，达到低色偏的效果。
【附图说明】
图1是现有技术中一种FPR 3D显示系统的结构示意图，同时示出两种视角条件下的光路差异；
图2是现有技术中一种MVA型液晶显示面板的像素的结构示意图；
图3是图2中液晶显示面板的像素的平面示意图；
图4是现有技术中另一种MVA型液晶显示面板的像素的结构示意图；
图5是图4中液晶显示面板的像素的平面示意图；
图6是本发明阵列基板一实施方式的结构示意图；
图7是图6中阵列基板的像素单元的一实施方式的结构示意图；
图8是图7中像素单元的平面示意图。
【具体实施方式】
下面将结合附图和实施方式对本发明进行详细说明。
参阅图6，本发明应用于MVA型液晶显示面板的阵列基板的一实施方式包括：多条第一扫描线101、第二扫描线102、数据线103以及多个行列排列的像素单元104。每个像素单元104均包括开关元件1041和像素电极1042。每个像素单元104对应一条第一扫描线101、第二扫描线102以及数据线103。
具体地，参阅图7，图7为图6中阵列基板的像素单元的一实施方式的结构示意图，并且图7示出了图6中任意三个沿数据线203方向排列的相邻像素单元的结构，其中所示的三个沿数据线203方向排列的相邻像素单元中，中间的像素单元、后面的像素单元以及前面的像素单元分别是第一像素单元204、第二像素单元205以及第三像素单元206，第三像素单元206只示出部分结构。以第一像素单元204为例，第一像素单元204的开关元件的数量为三个，分别是第一开关元件2041、第二开关元件2042以及第三开关元件2043。第一像素单元204的像素电极2010包括主像素电极2044和次像素电极2045。对应地，主像素电极2044所在的区域为主像素区域2046，次像素电极2045所在的区域为次像素区域2047。第一扫描线201与第一开关元件2041连接以输入扫描信号，从而控制第一开关元件2041的导通与断开；第二扫描线202与第二开关元件2042连接以输入扫描信号，从而控制第二开关元件2042的导通与断开。数据线203通过第一开关元件2041与主像素电极2044连接，并且连接线（即第一开关元件2041的第一输出端20413与主像素电极2044之间的连接线）直接经过主像素区域2046与主像素电极2044连接以对主像素电极2044输入数据信号。数据线203通过第二开关元件2042与次像素电极2045连接，并且连接线（即第二开关元件2042的第二输出端20423与次像素电极2045之间的连接线）直接经过次像素区域2047而无需经过主像素区域2046即可与次像素电极2045连接以对次像素电极2045输入数据信号。
通过上述方式，与主像素电极2044连接的连接线不需要经过次像素区域2047与主像素电极2044连接，而与次像素电极2045连接的连接线也不需要经过主像素区域2046与次像素电极2045连接，由此减小了主像素区域2046和次像素区域2047之间的寄生电容。
本实施方式中，请参阅图7和图8，阵列基板还包括对应不透光区域的暗区300（图8中的阴影部分），第一像素单元204对应的第一扫描线201、第二扫描线202、第一开关元件2041、第二开关元件2042以及第三开关元件2043相应设置在第一像素单元204与前后相邻的像素单元206、205之间。具体地，对应不透光区域的暗区300的一部分设置在像素单元之间，如第一像素单元204和第二像素单元205之间的暗区区域301，即三个相邻像素单元之间的区域为对应不透光区域的暗区300的一部分。第一像素单元204对应的第一扫描线201和第一开关元件2041均位于第一像素单元204的上一侧，其与第三像素单元206（图只示出部分结构）对应的第二扫描线207、第二开关元件2061以及第三开关元件2062相邻，以对主像素电极2044输入扫描信号；而第一像素单元204对应的第二扫描线202、第二开关元件2042以及第三开关元件2043位于第一像素单元204的下一侧，其与第二像素单元205对应的第一扫描线208和第一开关元件209相邻，以对次像素电极2045输入扫描信号。
进一步地，将本实施方式的阵列基板组装以形成液晶显示面板，在驱动液晶显示面板显示时，控制主像素电极2044和次像素电极2045存在预设电压差以使液晶显示面板在大视角下具有低色偏的效果。具体地，第一像素单元204的第一开关元件2041的第一控制端20411电连接第一扫描线201，第一输入端20412电连接数据线203，第一输出端20413电连接主像素电极2044。第二开关元件2042的第二控制端20421电连接第二扫描线202，第二输入端20422电连接数据线203，第二输出端20423电连接次像素电极2045。第三开关元件2043的第三控制端20431电连接第二像素单元205所对应的第一扫描线208，第三输入端20432电连接次像素电极2045，第三输出端20433用于电连接储存电容2011。其中，储存电容2011由与阵列基板同一侧的金属层和另一基板（通常为彩色滤光基板）的公共电极（Com）所构成，第三开关元件2043的第三输出端20433电连接形成储存电容2011的金属层，使得储存电容2011通过第三开关元件2043与次像素电极2045连接。
在进入3D显示模式时，第一像素单元204对应的第一扫描线201和第二扫描线202输入扫描信号至第一控制端20411和第二控制端20421，以分别控制第一开关元件2041和第二开关元件2042导通，然后数据线203输入数据信号至第一输入端20411和第二输入端20421，以使得数据信号分别通过第一输出端20413和第二输出端20423传送至第一像素单元204的主像素电极2044和次像素电极2045。数据线203将数据信号同时输入至主像素电极2044和次像素电极2045中后，主像素电极2044和次像素电极2045电位相同。关闭第一扫描线201和第二扫描线202以停止对第一像素单元204输入扫描信号，开始驱动后面的像素单元即第二像素单元205显示，首先需对第二像素单元205对应的第一扫描线208输入扫描信号以控制第二像素单元205的第一开关元件209的导通。此时，由于第一像素单元204对应的第三开关元件2043的第三控制端20431电连接第二像素单元205对应的第一扫描线208，在第一扫描线208输入扫描信号时，此时第三开关元件2043被导通。
在驱动液晶显示面板显示时，液晶显示面板会有极性上的切换，显示电压在正极性和负极性之间不停的更换，以避免液晶分子的转向一直固定在一个方向而造成的特性破坏。当像素电极2010的电压高于公共电极电压时，显示电压为正极性，反之则为负极性。因此，在第一像素单元204对应的第三开关元件2043未导通之前，储存电容2011所储存的电荷的极性与第一像素单元204的次像素电极2045的电荷极性相反，所以在第三开关元件2043导通时，次像素电极2045的电荷会通过第三开关元件2043与储存电容2011的电荷发生中和，使得次像素电极2045的电场减小，由此造成主像素电极2044和次像素电极2045之间存在电压差。根据视角需求，调整储存电容2011的大小使得主像素电极2044和次像素电极2045之间存在预设电压差，以控制液晶分子的偏转，从而能够减小大视角下的色彩差异，达到低色偏的效果。
其中，本实施方式的第一开关元件2041、第二开关元件2042以及第三开关元件2043分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，每个薄膜晶体管均包括作为控制端的栅极、作为输入端的源极以及作为输出端的漏极。相应地，第一薄膜晶体管的第一栅极与第一扫描线201电连接以控制第一薄膜晶体管的导通与断开，第一源极与数据线203电连接，第一漏极与主像素电极2044电连接，以使得数据线203通过第一薄膜晶体管将数据信号输入至主像素电极2044；第二薄膜晶体管的第二栅极与第二扫描线202电连接以控制第二薄膜晶体管的导通与断开，第二源极与数据线203电连接，第二漏极与次像素电极2045电连接，以使得数据线203通过第二薄膜晶体管将数据信号输入至次像素电极2045；第三薄膜晶体管的第三栅极与第二像素单元205对应的第一扫描线208电连接以控制第三薄膜晶体管的导通与断开，第三源极与次像素电极2045电连接，第三漏极用于与储存电容2011电连接，以控制主像素电极2044和次像素电极2045之间存在预设电压差。
本实施方式中，第一像素单元204中的像素电极2010包括主像素电极2044和次像素电极2045，使第一开关元件2041的第一输出端20413与主像素电极2044之间的连接线直接经过主像素电极2044所在的主像素区域2046与主像素电极2044连接，而第二开关元件2042的第二输出端20423和第三开关元件2043的第三输入端20432与次像素电极2045之间的连接线直接经过次像素电极2045所在的次像素区域2047而无需经过主像素区域2046与次像素电极2045连接，能够减小主像素区域2046和次像素区域2047之间的寄生电容，提高后续四道光罩制程中液晶显示面板的可靠性，同时也能在一定程度上提高穿透率和开口率。并且，沿数据线203方向相邻的像素单元之间的区域为对应不透光区域的暗区区域301，第一像素单元204对应的第一扫描线201和第一开关元件2041设置在第一像素单元204和第三像素单元206之间，第二扫描线202、第二开关元件2042以及第三开关元件2043设置在第一像素单元204和第二像素单元205之间，使得这些扫描线和开关元件均布局于上下相邻的像素单元之间，增大了像素单元之间的暗区区域301的宽度，由此能够在3D显示模式下减少大视角下双眼信号串扰的现象，也能提高穿透率。此外，次像素电极2045通过第三开关元件2043与储存电容2011连接，通过调整储存电容2011的大小能够控制主像素电极2044和次像素电极2045之间存在预设电压差，以此控制液晶分子的偏转，从而能够减小大视角下的颜色差异，达到低色偏的效果。
本发明还提供液晶显示装置的一实施方式，其包括偏振薄膜以及液晶显示面板。偏振薄膜用于将液晶显示面板显示的3D画面分离为左眼信号和右眼信号以同时发送至观看者眼中，使观看者能看到较少闪烁的3D画面。液晶显示面板包括阵列基板和彩色滤光基板。彩色滤光基板包括黑色矩阵，偏振薄膜设置于彩色滤光基板的外侧。阵列基板为上述实施方式所述的阵列基板。
具体地，参阅图6，阵列基板包括多条第一扫描线101、第二扫描线102、数据线103以及多个行列排列的像素单元104。每个像素单元104包括开关元件1041和像素单元1042，并且每个像素单元104对应至少一条第一扫描线101、第二扫描线102以及数据线103。
其中，像素单元104的具体结构，可参考图7所示的实施方式进行，此处不进行一一赘述。值得注意的是，图7和图8所示的第一像素单元204和第二像素单元205之间的暗区区域301为彩色滤光基板的黑色矩阵的垂直投影覆盖区域，将第一扫描线201、第二扫描线202以及三个开关元件2041-2043设置在黑色矩阵的垂直投影覆盖区域内，也能提高液晶显示面板的穿透率和开口率。
其中，本实施方式的液晶显示面板为MVA型液晶显示面板。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (9)

  1. 一种应用于MVA型液晶显示面板的阵列基板，其中：
    所述阵列基板包括至少多条第一扫描线、第二扫描线、数据线以及多个行列排列的像素单元，每个所述像素单元均包括开关元件和像素电极，每个所述像素单元对应至少一条第一扫描线、第二扫描线以及数据线；
    每个所述像素单元的开关元件包括控制端、输入端以及输出端，数量为至少三个，至少分别是第一开关元件、第二开关元件以及第三开关元件；
    所述像素电极包括主像素电极和次像素电极，所述第一扫描线和第二扫描线分别与第一开关元件和第二开关元件连接以分别控制第一开关元件和第二开关元件的导通与断开，所述数据线分别经过主像素电极所在的区域和次像素电极所在的区域而连接主像素电极和次像素电极以输入电压信号；
    所述阵列基板还包括对应不透光区域的暗区，所述暗区的至少一部分设置于像素单元之间，所述第一扫描线、第二扫描线以及开关元件布局于像素单元之间；
    其中，对于任意三个沿数据线方向排列的相邻像素单元，位于中间的所述像素单元对应的第一扫描线和第一开关元件与前面的像素单元对应的第二扫描线、第二开关元件以及第三开关元件相邻，以对主像素电极输入扫描信号，所述中间的像素单元对应的第二扫描线、第二开关元件以及第三开关元件与后面的像素单元对应的第一扫描线和第一开关元件相邻，以对次像素电极输入扫描信号；
    所述第一开关元件的输出端电连接主像素电极，所述第二开关元件的输出端电连接次像素电极，所述第三开关元件的输出端用于电连接储存电容，所述第一开关元件和第二开关元件的输入端分别电连接数据线，所述第三开关的输入端电连接次像素电极，所述第一开关元件的控制端电连接第一扫描线，所述第二开关元件的控制端电连接第二扫描线，所述第三开关元件的控制端电连接后面的像素单元对应的第一扫描线；
    其中，在进入3D显示模式时，所述中间的像素单元对应的第一扫描线和第二扫描线输入扫描信号以分别控制第一开关元件和第二开关元件导通，所述数据线分别通过第一开关元件和第二开关元件同时输入电压信号至所述中间的像素单元的主像素电极和次像素电极，随后停止输入扫描信号至所述第一扫描线和第二扫描线；停止输入扫描信号至所述第一扫描线和第二扫描线后，与所述第三开关元件的控制端电连接的后面的像素单元对应的第一扫描线输入扫描信号以控制第三开关元件导通，所述中间的像素单元的次像素电极的电压信号通过第三开关元件耦合至与第三开关元件的输出端电连接的储存电容，调整储存电容的大小以控制所述中间的像素单元的主像素电极和次像素电极之间存在预设电压差。
  2. 根据权利要求1所述的阵列基板，其中，
    所述像素单元的第一扫描线和第一开关元件均位于像素单元的一侧，所述像素单元的第二扫描线、第二开关元件以及第三开关元件均位于像素单元的另一侧。
  3. 根据权利要求1所述的阵列基板，其中，
    所述储存电容由与所述阵列基板同一侧的金属层和所述液晶显示面板的公共电极构成，在所述第三开关元件未导通之前，所述储存电容所存储的电荷的极性与所述次像素电极的电荷的极性相反。
  4. 根据权利要求1所述的阵列基板，其中，
    所述第一开关元件、第二开关元件以及第三开关元件分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；
    所述第一薄膜晶体管包括第一栅极、第一源极以及第一漏极，所述第一源极作为输入端与数据线电连接，所述第一漏极作为输出端与主像素电极电连接，所述第一栅极作为控制端与第一扫描线电连接以控制第一薄膜晶体管的导通与断开；
    所述第二薄膜晶体管包括第二栅极、第二源极以及第二漏极，所述第二源极作为输入端与数据线电连接，所述第二漏极作为输出端与次像素电极电连接，所述第二栅极作为控制端与第二扫描线电连接以控制第二薄膜晶体管的导通与断开；
    所述第三薄膜晶体管包括第三栅极、第三源极以及第三漏极，所述第三源极与次像素电极电连接，所述第三漏极作为输出端用于与储存电容电连接，所述第三栅极与相邻一像素单元对应的第一扫描线电连接以控制第三薄膜晶体管的导通与断开。
  5. 一种液晶显示装置，其中，包括偏振薄膜以及液晶显示面板，所述液晶显示面板包括阵列基板和彩色滤光基板；
    所述彩色滤光基板包括黑色矩阵，所述偏振薄膜设置于彩色滤光基板的外侧；
    所述阵列基板包括至少多条第一扫描线、第二扫描线、数据线以及多个行列排列的像素单元，每个所述像素单元均包括开关元件和像素电极，每个所述像素单元对应至少一条第一扫描线、第二扫描线以及数据线；
    每个所述像素单元的开关元件包括控制端、输入端和输出端，数量为至少三个，至少分别是第一开关元件、第二开关元件以及第三开关元件；
    所述像素电极包括主像素电极和次像素电极，所述第一扫描线和第二扫描线分别与第一开关元件和第二开关元件连接以分别控制第一开关元件和第二开关元件的导通与断开，所述数据线分别经过主像素电极所在的区域和次像素电极所在的区域而连接主像素电极和次像素电极以输入电压信号；
    所述阵列基板还包括多个暗区，所述暗区位于黑色矩阵的垂直投影覆盖区域内，并且所述暗区的至少一部分设置于像素单元之间，所述第一扫描线、第二扫描线以及开关元件布局于像素单元之间；
    其中，对于任意三个沿数据线方向排列的相邻像素单元，位于中间的像素单元对应的第一扫描线和第一开关元件与前面的像素单元对应的第二扫描线、第二开关元件以及第三开关元件相邻，以对主像素电极输入扫描信号，所述中间的像素单元对应的第二扫描线、第二开关元件以及第三开关元件与后面的像素单元对应的第一扫描线和第一开关元件相邻，以对次像素电极输入扫描信号；
    所述第一开关元件的输出端电连接主像素电极，所述第二开关元件的输出端电连接次像素电极，所述第三开关元件的输出端用于电连接储存电容，所述第一开关元件和第二开关元件的输入端分别电连接数据线，所述第三开关的输入端电连接次像素电极，所述第一开关元件的控制端电连接第一扫描线，所述第二开关元件的控制端电连接第二扫描线，所述第三开关元件的控制端电连接后面的像素单元对应的第一扫描线；
    其中，在进入3D显示模式时，所述中间的像素单元对应的第一扫描线和第二扫描线输入扫描信号以分别控制第一开关元件和第二开关元件导通，所述数据线通过第一开关元件和第二开关元件同时输入电压信号至所述中间的像素单元的主像素电极和次像素电极，随后停止输入扫描信号至所述第一扫描线和第二扫描线；停止输入扫描信号至所述第一扫描线和第二扫描线后，与所述第三开关元件的控制端电连接的后面的像素单元对应的第一扫描线输入扫描信号以控制第三开关元件导通，所述中间的像素单元的次像素电极的电压信号通过第三开关元件耦合至与第三开关元件的输出端电连接的储存电容，调整储存电容的大小以控制所述中间的像素单元的主像素电极和次像素电极之间存在预设电压差。
  6. 根据权利要求5所述的液晶显示装置，其中，
    所述像素单元的第一扫描线和第一开关元件均位于像素单元的一侧，所述像素单元的第二扫描线、第二开关元件以及第三开关元件均位于像素单元的另一侧。
  7. 根据权利要求5所述的液晶显示装置，其中，
    所述储存电容由与所述阵列基板同一侧的金属层和所述液晶显示面板的公共电极构成，在所述第三开关元件未导通之前，所述储存电容所存储的电荷的极性与所述次像素电极的电荷的极性相反。
  8. 根据权利要求5所述的液晶显示装置，其中，
    所述第一开关元件、第二开关元件以及第三开关元件分别为第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；
    所述第一薄膜晶体管包括第一栅极、第一源极以及第一漏极，所述第一源极作为输入端与数据线电连接，所述第一漏极作为输出端与主像素电极电连接，所述第一栅极作为控制端与第一扫描线电连接以控制第一薄膜晶体管的导通与断开；
    所述第二薄膜晶体管包括第二栅极、第二源极以及第二漏极，所述第二源极作为输入端与数据线电连接，所述第二漏极作为输出端与次像素电极电连接，所述第二栅极作为控制端与第二扫描线电连接以控制第二薄膜晶体管的导通与断开；
    所述第三薄膜晶体管包括第三栅极、第三源极以及第三漏极，所述第三源极与次像素电极电连接，所述第三漏极作为输出端用于与储存电容电连接，所述第三栅极与相邻一像素单元对应的第一扫描线电连接以控制第三薄膜晶体管的导通与断开。
  9. 根据权利要求5所述的液晶显示装置，其中，
    所述液晶显示面板是MVA型液晶显示面板。
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