WO2015006992A1 - 一种阵列基板及液晶显示面板 - Google Patents

一种阵列基板及液晶显示面板 Download PDF

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Publication number
WO2015006992A1
WO2015006992A1 PCT/CN2013/080001 CN2013080001W WO2015006992A1 WO 2015006992 A1 WO2015006992 A1 WO 2015006992A1 CN 2013080001 W CN2013080001 W CN 2013080001W WO 2015006992 A1 WO2015006992 A1 WO 2015006992A1
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Prior art keywords
pixel electrode
switch
pixel
scan line
scan
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PCT/CN2013/080001
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English (en)
French (fr)
Inventor
姚晓慧
许哲豪
党娟宁
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to RU2016105304A priority Critical patent/RU2623185C1/ru
Priority to US13/985,796 priority patent/US20150022510A1/en
Priority to KR1020167004364A priority patent/KR101764548B1/ko
Priority to GB1522483.5A priority patent/GB2529975B/en
Priority to JP2016526395A priority patent/JP6171098B2/ja
Publication of WO2015006992A1 publication Critical patent/WO2015006992A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
    • G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H04N13/356—Image reproducers having separate monoscopic and stereoscopic modes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a liquid crystal display panel.
  • the liquid crystal display has the advantages of no flickering picture, color saturation and small volume, and mainly realizes display by utilizing the physical structure and optical characteristics of the liquid crystal molecules.
  • the alignment of the liquid crystal molecules is not the same, so that the effective refractive index of the liquid crystal molecules is also different, thereby causing a change in the transmitted light intensity, which is manifested by a decrease in light transmission capability at oblique viewing angles.
  • the color of the viewing angle and the positive viewing direction are inconsistent, and chromatic aberration occurs, so color distortion is observed at a large viewing angle.
  • liquid crystal displays are compatible with 2D and 3D display functions.
  • 3D FPR Flexible-type Patterned In the Retarder (polarized) stereoscopic display technology
  • two adjacent rows of pixels respectively correspond to the left and right eyes of the viewer to respectively generate a left eye image corresponding to the left eye and a right eye image corresponding to the right eye, and the left and right eyes of the viewer
  • the left and right eye images are synthesized by the brain to make the viewer feel the stereoscopic display effect.
  • the left eye image and the right eye image are prone to crosstalk, which causes the viewer to see overlapping images, which affects the viewing effect.
  • an additional blackout area BM is usually added between adjacent two pixels (Black) Matrix, black matrix) masks the way the crosstalk signal is blocked to reduce crosstalk between the two eyes.
  • Black Matrix, black matrix
  • the technical problem to be solved by the present invention is to provide an array substrate and a liquid crystal display panel, which can improve the aperture ratio in the 2D display mode and reduce the color distortion in a large viewing angle, and can reduce the binocular signal crosstalk in the 3D display mode.
  • the present invention adopts a technical solution to provide an array substrate including a plurality of first scan lines arranged in a plurality of rows, a plurality of second scan lines arranged in a plurality of rows, a plurality of data lines, and a plurality of branches.
  • each pixel unit includes a first pixel electrode, a second pixel electrode, a third pixel electrode, a first switch, a second switch and a third switch, wherein the first pixel electrode is connected to the first scan line and the data line corresponding to the pixel unit through the first switch, and the second pixel electrode passes through the second switch and the first scan line corresponding to the pixel unit
  • the data line is connected, the third pixel electrode is connected to the second pixel electrode and the second scan line corresponding to the pixel unit through the third switch; in the 2D display mode, the first scan line inputs the scan signal to control the first switch and the second The switch is turned on, and the first pixel electrode and the second pixel electrode receive the data signal from the data line to be in a state of displaying an image corresponding to the 2D picture, Then, the second scan line inputs a scan signal to control the third switch to be turned on, so that
  • the state of the image is such that the voltage of the second pixel electrode is changed by the third pixel electrode, and the third switch is a thin film transistor, and the aspect ratio of the thin film transistor is smaller than a set value, so that the second pixel is controlled during the on time thereof
  • the voltage difference between the electrode and the third pixel electrode is not zero, wherein the first row of pixel cells adjacent to the row of pixel cells and most recently scanned while scanning the first scan line corresponding to one row of pixel cells Corresponding second scan line scans; in the 3D display mode, the first scan line inputs a scan signal to control the first switch and the second switch to be turned on, and the first pixel electrode and the second pixel electrode receive data from the data line
  • the signal is in a state of displaying an image corresponding to the 3D picture, and the second scanning line controls the third switch to be turned off, so that the third pixel electrode is in the display State of the image corresponding to the black picture.
  • the array substrate further includes a switch unit and a short circuit in a peripheral area of the array substrate;
  • the switch unit includes a plurality of controlled switches, and the controlled switch includes a control end, an input end, and an output end, and the input end of each controlled switch is connected to one line.
  • a first scan line corresponding to the pixel unit the output end is connected to a second scan line corresponding to the row of pixel units adjacent to the row of pixel units, and the control ends of all the controlled switches are connected with the short-circuit line; in the 2D display mode,
  • the short-circuit line inputs a control signal to control the conduction of all the controlled switches.
  • the scan signal When the scan signal is input to the first scan line corresponding to the row of pixel units, the scan signal is simultaneously input to the second end connected to the output of the controlled switch through the controlled switch.
  • the short-circuit line In the scan line, to control the corresponding third switch to be turned on, in the 3D display mode, the short-circuit line inputs a control signal to control all controlled switches to open to control all third switches to open.
  • the area of the region where the third pixel electrode is located is smaller than the area of the region where the first pixel electrode and the second pixel electrode are located.
  • an array substrate including a plurality of first scan lines, a plurality of second scan lines, a plurality of data lines, and a plurality of pixel units, each pixel The unit corresponds to a first scan line, a second scan line, and a data line; each pixel unit includes a first pixel electrode, a second pixel electrode, a third pixel electrode, a first switch, a second switch, and a third switch, The first pixel electrode is connected to the first scan line and the data line corresponding to the pixel unit through the first switch, and the second pixel electrode is connected to the first scan line and the data line corresponding to the pixel unit through the second switch, the third pixel electrode Connected to the second pixel electrode and the second scan line corresponding to the pixel unit through the third switch; in the 2D display mode, the first scan line inputs a scan signal to control the first switch and the second switch to be turned on, the first pixel electrode And the second
  • the plurality of pixel units are arranged in a row, and the plurality of first scan lines and the second scan lines are also arranged in a row, and in the 2D display mode, while scanning the first scan line corresponding to the row of pixel units, The second scan line corresponding to the pixel unit of the previous row that is adjacent to the pixel unit is scanned.
  • the array substrate further includes a switch unit and a short circuit in a peripheral area of the array substrate;
  • the switch unit includes a plurality of controlled switches, and the controlled switch includes a control end, an input end, and an output end, and the input end of each controlled switch is connected to one line.
  • a first scan line corresponding to the pixel unit the output end is connected to a second scan line corresponding to the row of pixel units adjacent to the row of pixel units, and the control ends of all the controlled switches are connected with the short-circuit line; in the 2D display mode,
  • the short-circuit line inputs a control signal to control the conduction of all the controlled switches.
  • the scan signal When the scan signal is input to the first scan line corresponding to the row of pixel units, the scan signal is simultaneously input to the second end connected to the output of the controlled switch through the controlled switch.
  • the short-circuit line In the scan line, to control the corresponding third switch to be turned on, in the 3D display mode, the short-circuit line inputs a control signal to control all controlled switches to open to control all third switches to open.
  • the area of the region where the third pixel electrode is located is smaller than the area of the region where the first pixel electrode and the second pixel electrode are located.
  • the third switch is a thin film transistor, and the aspect ratio of the thin film transistor is less than a set value, so that the voltage difference between the second pixel electrode and the third pixel electrode is controlled to be non-zero during the time when it is turned on.
  • a liquid crystal display panel including an array substrate, a color filter substrate, and a liquid crystal layer between the array substrates;
  • the array substrate includes a plurality of first scan lines a plurality of second scan lines, a plurality of data lines, and a plurality of pixel units, each of the pixel units corresponding to a first scan line, a second scan line, and a data line;
  • each pixel unit includes a first pixel electrode, a second pixel electrode, a third pixel electrode, a first switch, a second switch, and a third switch, wherein the first pixel electrode is connected to the first scan line and the data line corresponding to the pixel unit through the first switch, and the second pixel electrode passes through the first pixel
  • the second switch is connected to the first scan line and the data line corresponding to the pixel unit, and the third pixel electrode is connected to the second pixel electrode and the second scan line corresponding to the pixel unit through the third switch; in the 2
  • the plurality of pixel units are arranged in a row, and the plurality of first scan lines and the second scan lines are also arranged in a row, and in the 2D display mode, while scanning the first scan line corresponding to the row of pixel units, The second scan line corresponding to the pixel unit of the previous row that is adjacent to the pixel unit is scanned.
  • the array substrate further includes a switch unit and a short circuit in a peripheral area of the array substrate;
  • the switch unit includes a plurality of controlled switches, and the controlled switch includes a control end, an input end, and an output end, and the input end of each controlled switch is connected to one line.
  • a first scan line corresponding to the pixel unit the output end is connected to a second scan line corresponding to the row of pixel units adjacent to the row of pixel units, and the control ends of all the controlled switches are connected with the short-circuit line; in the 2D display mode,
  • the short-circuit line inputs a control signal to control the conduction of all the controlled switches.
  • the scan signal When the scan signal is input to the first scan line corresponding to the row of pixel units, the scan signal is simultaneously input to the second end connected to the output of the controlled switch through the controlled switch.
  • the short-circuit line In the scan line, to control the corresponding third switch to be turned on, in the 3D display mode, the short-circuit line inputs a control signal to control all controlled switches to open to control all third switches to open.
  • the area of the region where the third pixel electrode is located is smaller than the area of the region where the first pixel electrode and the second pixel electrode are located.
  • the third switch is a thin film transistor, and the aspect ratio of the thin film transistor is less than a set value, so that the voltage difference between the second pixel electrode and the third pixel electrode is controlled to be non-zero during the time when it is turned on.
  • each pixel unit includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, and the first pixel in the 2D display mode
  • the electrode and the second pixel electrode receive the data signal from the data line to be in a state of displaying an image corresponding to the 2D picture
  • the third pixel electrode is connected to the second pixel electrode through the third switch, and then the third switch is turned on to make the second
  • the pixel electrode and the third pixel electrode are electrically connected
  • the third pixel electrode receives the data signal from the second pixel electrode to be in a state of displaying an image corresponding to the 2D picture, thereby causing the first to third pixel electrodes in the 2D display mode
  • the state of the image corresponding to the 2D picture is displayed, the aperture ratio can be increased, and the voltage of the second pixel electrode is changed by the third pixel electrode, so that the voltage between the second pixel electrode and the first pixel electrode is different,
  • the second pixel electrode and the third pixel electrode are not connected, so that the third pixel electrode cannot receive the data signal of the second pixel electrode, that is, the third pixel electrode has no data signal, that is, the third pixel electrode has no
  • the data signal further causes the third pixel electrode to be in a state of displaying an image corresponding to the black screen, whereby the binocular signal crosstalk can be reduced.
  • FIG. 1 is a schematic structural view of an embodiment of an array substrate of the present invention
  • FIG. 2 is a schematic structural view of a pixel unit of FIG. 1;
  • FIG. 3 is a structural equivalent circuit diagram of the pixel unit of FIG. 1;
  • FIG. 4 is a schematic diagram showing a display effect of a third pixel electrode of the pixel unit of FIG. 1 in a 3D display mode
  • FIG. 5 is a structural equivalent circuit diagram of a pixel unit in another embodiment of the array substrate of the present invention.
  • FIG. 6 is a schematic structural view of an embodiment of a liquid crystal display panel of the present invention.
  • one pixel is usually divided into a plurality of pixel regions having different liquid crystal pointing, and the voltages of each pixel region are controlled to be different, so that two The liquid crystal molecules in the pixel regions are arranged differently, thereby improving the color distortion at a large viewing angle to achieve LCS (Low)
  • LCS Low color shift
  • the array substrate includes a plurality of first scan lines 11 , a plurality of second scan lines 12 , a plurality of data lines 13 , and a plurality of pixel units 14 .
  • a plurality of pixel units 14 are arranged in an array, and each of the pixel units 14 is connected to a first scan line 11, a second scan line 12, and a data line 13.
  • each pixel unit 14 includes a first pixel electrode M1, a second pixel electrode M2, a third pixel electrode M3, and a first pixel electrode M1 and a second pixel electrode M2, respectively.
  • the control end of the first switch T1 and the control end of the second switch T2 are electrically connected to the first scan line 11, and the input end of the first switch T1 and the input end of the second switch T2 are electrically connected to the data line 13, first The output end of the switch T1 is electrically connected to the first pixel electrode M1, and the output end of the second switch T2 is electrically connected to the second pixel electrode M2.
  • the control end of the third switch T3 is electrically connected to the second scan line 12, the input end of the third switch T3 is electrically connected to the second pixel electrode M2, and the output end of the third switch T3 is electrically connected to the third pixel electrode M3. .
  • the first switch T1, the second switch T2, and the third switch T3 of the present embodiment are all thin film transistors, wherein the control ends of the three switches T1, T2, and T3 correspond to the gate of the thin film transistor, and the input end corresponds to the thin film transistor.
  • the source corresponds to the output of the thin film transistor.
  • the three switches may also be switching elements such as a triode or a Darlington tube.
  • the color difference observed at a large viewing angle in the 2D display mode can be reduced, the aperture ratio can be improved, and the binocular signal crosstalk in the 3D display mode can be reduced.
  • the present embodiment scans the first scan line 11 and the second scan line 12 in a progressive scan manner.
  • the first scan line 11 inputs a high level scan signal to control the first switch T1 and the second switch T2 to be turned on
  • the data line 13 inputs a data signal
  • the first pixel electrode M1 and the second pixel electrode M2 respectively pass the first switch T1 and the second switch T2 receive the same voltage from the data signal from the data line 13, and the first pixel electrode M1 and the second pixel electrode M2 are in a state of displaying an image corresponding to the 2D picture.
  • the first scan line 11 stops inputting the scan signal of the high level to turn off the first switch T1 and the second switch T2, and the second scan line 12 inputs the scan signal of the high level to control the third switch T3 to be turned on.
  • the second pixel electrode M2 and the third pixel electrode M3 are electrically connected through the third switch T3, and the data signal stored on the second pixel electrode M2 is input to the third pixel electrode M3 through the third switch T3, and the third pixel electrode M3 After receiving the data signal from the second pixel electrode M2, it is in a state of displaying an image corresponding to the 2D picture.
  • the three pixel electrodes M1, M2, and M3 are all in a state of displaying an image corresponding to the 2D screen, whereby the aperture ratio of the 2D display mode can be improved.
  • the voltage of the second pixel electrode M2 is changed by the third pixel electrode M3 when the third switch T3 is turned on, that is, the voltage of the second pixel electrode M2 passes through the liquid crystal capacitor Clc3 (common by the third pixel electrode M3 and another substrate)
  • the charge sharing between the electrodes caused by the liquid crystal molecules between them changes.
  • the positive polarity (the data signal is greater than the common voltage)
  • the partial charge of the second pixel electrode M2 is transferred to the third pixel electrode M3, so that the voltage of the second pixel electrode M2 is lowered, and the third pixel electrode M3 is The voltage is increased such that the voltage of the second pixel electrode M2 is no longer the same as the voltage of the first pixel electrode M1, that is, there is a non-zero voltage difference between the two; the negative polarity (the data signal is less than the common voltage) is reversed.
  • the third pixel electrode M3 retains the positive polarity voltage of the previous time frame
  • the partial charge of the third pixel electrode M3 is transferred to the second pixel electrode M2 when the third switch T3 is turned on, so that the second pixel electrode M2
  • the voltage is increased such that the voltage of the second pixel electrode M2 is no longer the same as the voltage of the first pixel electrode M1.
  • the third switch T3 controls the voltage difference between the second pixel electrode M2 and the third pixel electrode M3 to be non-zero during the period in which it is turned on, so that the second switch T3 does not cause the second time during the on time.
  • the pixel electrode M2 and the third pixel electrode M3 reach a discharge equilibrium state, whereby the voltages between the first pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 are different, and the 2D display mode can be reduced.
  • the color difference of the viewing angle achieves a low color shift effect.
  • the third switch T3 of the present embodiment is a thin film transistor, and the third switch T3 can be controlled to control the second pixel electrode M2 and the third pixel electrode M3 in its conduction by controlling the aspect ratio of the third switch T3.
  • the voltage difference between the two is not zero, that is, the current passing capability of the third switch T3 at the time of conduction is controlled by controlling the aspect ratio of the third switch T3.
  • the charge transfer speed between the second pixel electrode M2 and the third pixel electrode M3 may be controlled. Slower, further by making the width to length ratio of the third switch T3 smaller than a set value, for example, the set value is 0.3, so that the second pixel electrode M2 and the third pixel electrode are in a time when the third switch T3 is turned on The voltage difference between M3 is not zero.
  • the current passing capability of the third switch T3 when turned on can also be controlled by controlling the magnitude of the gate voltage of the third switch T3 (ie, the magnitude of the scan signal input by the second scan line 12). There are no restrictions here.
  • the first scan line 11 and the second scan line 12 corresponding to the row of pixel units 14 After the scanning of the first scan line 11 and the second scan line 12 corresponding to the row of pixel units 14 is completed, the first scan line 11 and the second scan line 12 corresponding to the next row of pixel units are scanned.
  • the third pixel electrode M3 is first turned off by using the black screen signal, that is, the data line 13 inputs a data signal indicating the corresponding black image to the first pixel electrode M1 and the second pixel electrode M2, and controls the third.
  • the switch T3 is turned on so that the third pixel electrode M3 is in a state of displaying an image corresponding to a black screen to turn off the third pixel electrode M3.
  • the first scan line 11 inputs a high level scan signal to control the first switch T1 and the second switch T2 to be turned on, and the data line 13 passes through the first switch T1 and the second switch T3 to the first pixel electrode M1 and the first
  • the two-pixel electrode M2 inputs a data signal such that the first pixel electrode M1 and the second pixel electrode M2 are in a state of displaying an image corresponding to the 3D picture.
  • the second scan line 12 is turned off, that is, the scan signal is not input to the second scan line 12 to control the third switch T3 to be in an off state, so that the third pixel electrode M3 remains in the corresponding black frame. The state of the image.
  • the first pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 are sequentially arranged in the column direction, and the adjacent two rows of pixel units 14 respectively display a left eye image and a right eye image corresponding to the 3D picture.
  • the third pixel electrode M3 is in a state of displaying an image corresponding to a black screen by the disconnection of the third switch T3, which is in a state of displaying an image of the image corresponding to the black screen.
  • the pixel electrode M3 is a light-shielding region (equivalent to a black matrix, Black Matrix, BM), thereby causing the pixel electrodes of the left eye image (the second pixel electrode and the third pixel electrode in one row of pixel units) and the pixel electrode displaying the right eye image in the adjacent two rows of pixel units 14 (another row A light-shielding region exists between the second pixel electrode and the third pixel electrode in the pixel unit, and the cross-talk signal of the left-eye image and the right-eye image is blocked by the light-shielding region, so that the binocular signal crosstalk in the 3D display mode can be reduced.
  • BM black matrix
  • the third pixel electrode M3 is mainly used to form a light-shielding region in the 3D display mode to reduce the crosstalk of the 3D signal, and thus the area of the region where the third pixel electrode M3 is located is smaller than the area of the first pixel electrode M1 and the second pixel electrode M2.
  • the area can also be designed according to the actual shading needs to occupy the area of the third pixel electrode M3 to minimize the 3D binocular signal crosstalk phenomenon.
  • the three pixel electrodes may also be arranged in the row direction, and the adjacent two columns of pixel units respectively display the left eye image and the right eye image corresponding to the 3D picture.
  • the third pixel electrode can also be in a state of displaying a black screen by inserting black, and the blanking time at the first scan line (Blanking) Time) Insert black.
  • the first pixel electrode and the second pixel electrode are in a state of displaying an image corresponding to the 3D picture, and the third pixel electrode is still in a state of displaying an image corresponding to the black screen, and in the next scan.
  • the first pixel electrode, the second pixel electrode, and the third pixel electrode are all in a state in which the image corresponding to the black image is displayed in the time frame, and then the first pixel electrode and the second pixel electrode are restored to the image in the 3D picture.
  • a state in which the third pixel electrode remains in a state in which an image corresponding to the 3D picture is displayed that is, a state in which the first pixel electrode and the second pixel electrode are alternately displayed in an image displaying the 3D picture and a state in which the image corresponding to the black picture is displayed, and
  • the third pixel electrode always maintains a state in which an image corresponding to the 3D picture is displayed.
  • the first and second scan lines are scanned by using a progressive scan mode in the 2D display mode.
  • corresponding pixel units of different rows may also be scanned simultaneously.
  • the plurality of pixel units 44 are arranged in a row, and a plurality of first scan lines (only three are shown in the figure, including the first scan lines 41_1, 41_2, and 41_3) and a plurality of second scan lines (only three are shown in the figure)
  • the second scan lines 42_1, 42_2, and 42_3 are also arranged in a row, and one row of pixel units corresponds to one first scan line and one second scan line.
  • the adjacent first row of pixel cells A1 and the second row of pixel cells A2 are taken as an example, and while the first scan line 41_2 corresponding to the second row of pixel cells A2 is scanned, The second row of pixel units A2 are adjacent to each other and the second scan line 42_1 corresponding to the first row of pixel cells A1 of the previous row is scanned.
  • the array substrate of the present embodiment further includes a switch unit 45 and a short-circuit line 46 located in a peripheral region of the array substrate.
  • the switching unit 45 includes a plurality of controlled switches (only four are shown in the figure, including the controlled switches T4_1, T4_2).
  • the controlled switch includes a control terminal, an input terminal, and an output terminal.
  • the control switch T4_1 between the first row of pixel units A1 and the second row of pixel units A2 is illustrated.
  • the input end of the controlled switch T4_1 is connected to the first scan line 41_2 corresponding to the second row of pixel units A2, and the controlled switch T4_1
  • the output end is connected to the second scan line 42_1 corresponding to the first row of pixel units A1, and the control ends of all the controlled switches are connected to the short-circuit line 46.
  • the controlled switch is a thin film transistor, and the control end of the controlled switch corresponds to the gate of the thin film transistor, and the input end of the controlled switch corresponds to the source of the thin film transistor, and the output end of the controlled switch corresponds to the drain of the thin film transistor.
  • the short-circuit line inputs a high-level control signal to control all of the controlled switches in the switching unit 45 to be turned on, and then scans the first scan line 41 line by line.
  • the first scan line 41_1 corresponding to the first row of pixel units A1 inputs a scan signal to control the first switch T1 and the second switch T2 in the first row of pixel units A1 to be turned on
  • the data line 43 inputs a data signal to make the first
  • the first pixel electrode M1 and the second pixel electrode M2 in the row pixel unit A1 are in a state of displaying an image corresponding to a 2D picture.
  • the first scan line 41_2 corresponding to the second row of pixel units A2 inputs a scan signal to control the first switch T1 and the second switch T2 in the second row of pixel units A2 to be turned on, at the same time, due to the controlled switch T4_1 In the on state, the scan signal input by the first scan line 41_2 is input to the second scan line 42_1 corresponding to the first row of pixel units A1 through the controlled switch T4_1 to control the third row in the first row of pixel units A1.
  • the switch T3 is turned on, so that the second pixel electrode M2 and the third pixel electrode M3 in the first row of pixel units A1 are electrically connected, thereby causing the third pixel electrode M3 in the first row of pixel units A1 to be in the display corresponding to 2D.
  • the state of the image of the screen can increase the aperture ratio in the 2D display mode, and the voltage of the second pixel electrode M2 in the first row of pixel units A1 is changed by the third pixel electrode M3 so that the pixel in the first row of pixel units A1
  • the voltages of the three pixel electrodes M1, M2, and M2 are all different, so that the effect of low color shift can be achieved.
  • the first scan line 41_2 corresponding to the pixel unit A2 of the second row is scanned, and at the same time, the second row is controlled by the controlled switch T4_2.
  • the second scan line 42_2 corresponding to the pixel unit A2 is also scanned at the same time, and the scanning mode of the remaining scan lines is similarly pushed.
  • the short-circuit line 46 inputs a control signal to control all of the controlled switches in the switch unit 45 to be in an off state, and inputs a scan signal to the first scan line 41_1 to control the first switch in the first row of pixel units A1.
  • T1 and the second switch T2 are turned on, and the data line 43 inputs a data signal such that the first pixel electrode M1 and the second pixel electrode M2 in the first row of pixel units A1 are in a state of displaying an image corresponding to the 3D picture.
  • a scan signal is input to the first scan line 41_2 corresponding to the second row of pixel units A2 to control the first switch T1 and the second switch T2 in the second row of pixel units A2 to be turned on, and since the controlled switch T4_1 is turned off a state, therefore, the scan signal input by the first scan line 41_2 does not enter the third switch T3 in the first row of pixel units A1, so that the third switch T3 is in an off state, thereby making the first row of pixel units A1
  • the three-pixel electrode M3 is in a state of displaying an image corresponding to a black screen, and the binocular signal crosstalk in the 3D display mode can be reduced by the third pixel electrode M3 in a state in which the image of the black screen is displayed.
  • the first scanning line 41_3 corresponding to the pixel unit A3 of the next row is scanned, and so on, and the controlled switch T4 is always in the 3D display mode. Is disconnected.
  • the switching unit 45 and the short-circuit line 46 of the present embodiment only need one scanning driving chip to apply a control signal to the short-circuit line to control the conduction or the closing of the controlled switch in the switching unit 45, thereby correspondingly controlling the third switch T3 to be turned on or Disconnection not only enables low color shift and higher aperture ratio in 2D display mode, but also low crosstalk in 3D display mode, while reducing the number of scan drive chips and reducing cost.
  • simultaneously scanning the two scan lines (such as the second scan line 42_1 corresponding to the first row of pixel units A1 and the first scan line 41_2 corresponding to the second row of pixel units A2) in the same scan time frame, thereby correspondingly extending The scan time of each scan line helps to perform high update frequency operations.
  • the plurality of pixel units may also be arranged in a column, and the plurality of first scan lines and the second scan lines are also arranged in a column, and the first scan lines corresponding to the columns of the pixel units are scanned.
  • the second scan line corresponding to the pixel unit of the previous column that is adjacent to the column of the pixel unit may be scanned.
  • the simultaneous scanning of the first scan line and the second scan line corresponding to different rows of pixel units may be implemented without using the above-described switch unit 45 and the short-circuit line 46, but each scan line is included (including The first scan line and the second scan line are independent of each other, and each scan line is connected to one scan drive chip to individually control scanning of one scan line, thereby simultaneously inputting a scan signal to a first scan line corresponding to one row of pixel units The scan signal is also input to the second scan line corresponding to the pixel unit of the previous row. In this manner, the scan of the two scan lines can also be performed simultaneously.
  • the liquid crystal display panel includes an array substrate 601 , a color filter substrate 602 , and a liquid crystal layer 603 between the array substrate 601 and the color filter substrate 602 .
  • the array substrate is the array substrate in each of the above embodiments.

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Abstract

提供了一种阵列基板及液晶显示面板。该阵列基板中，每个像素单元（14）包括第一像素电极（Ml）、第二像素电极（M2）以及第三像素电极（M3），其中，第三像素电极（M3）通过一第三开关（T3）与第二像素电极（M2）连接，在2D显示模式下使第三开关（T3）导通以使得第二像素电极（M2）和第三像素电极（M3）电性连接，以使得三个像素电极（Ml、M2、M3）均处于显示对应2D画面的图像的状态，并使得第二像素电极（M2）的电压通过第三像素电极（M3）的电压改变；在3D显示模式下，使第二像素电极（M2）和第三像素电极（M3）不连通，以使得第三像素电极（M3）处于显示对应黑画面的图像的状态。通过上述方式，能够提高2D显示模式下的开口率和减小大视角下的色彩失真，同时能够降低3D显示模式下的双眼信号串扰。

Description

一种阵列基板及液晶显示面板
【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板及液晶显示面板。
【背景技术】
液晶显示器相较于传统显示器相比具有无闪烁画面、色彩饱和以及体积小等优点，其主要是利用液晶分子的物理结构和光学特性实现显示。然而，在不同的视角下，液晶分子的排列指向并不相同，使得液晶分子的有效折射率也不相同，由此会引起透射光强的变化，具体表现为斜视角下透光能力降低，斜视角方向和正视角方向所表现的颜色不一致，发生色差，因此在大视角下会观察到颜色失真。
此外，随着液晶显示技术的发展，大部分液晶显示器已兼容2D和3D显示功能。在3D FPR（Film-type Patterned Retarder，偏光式）立体显示技术中，相邻两行像素分别对应观看者的左眼和右眼，以分别产生对应左眼的左眼图像和对应右眼的右眼图像，观看者的左右眼分别接收到相应的左眼图像和右眼图像后，通过大脑对左右眼图像进行合成以使得观看者感受到立体显示效果。而左眼图像和右眼图像容易发生串扰，会导致观看者看到重叠的影像，影响了观看效果。为了避免双眼图像信号发生串扰，通常在相邻两像素之间增加额外的遮光区域BM（Black Matrix，黑色矩阵）遮蔽的方式来阻挡发生串扰的信号，以降低双眼信号串扰。然而，采用此种方式会导致2D显示模式下的开口率大大降低，降低了2D显示模式下的显示亮度。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及液晶显示面板，能够提高2D显示模式下的开口率和减小大视角下的色彩失真，同时能够降低3D显示模式下的双眼信号串扰。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包括多条分行排列的第一扫描线、多条分行排列的第二扫描线、多条数据线以及多个分行排列的像素单元，每个像素单元对应一条第一扫描线、一条第二扫描线以及一条数据线；每个像素单元包括第一像素电极、第二像素电极、第三像素电极、第一开关、第二开关以及第三开关，第一像素电极通过第一开关与对应本像素单元的第一扫描线和数据线连接，第二像素电极通过第二开关与对应本像素单元的第一扫描线和数据线连接，第三像素电极通过第三开关与第二像素电极和对应本像素单元的第二扫描线连接；在2D显示模式下，第一扫描线输入扫描信号以控制第一开关和第二开关导通，第一像素电极和第二像素电极接收来自数据线的数据信号以处于显示对应2D画面的图像的状态，随后第二扫描线输入扫描信号以控制第三开关导通，以使得第二像素电极和第三像素电极电性连接，第三像素电极接收来自第二像素电极的数据信号以处于显示对应2D画面的图像的状态，使得第二像素电极的电压通过第三像素电极改变，第三开关为薄膜晶体管，薄膜晶体管的宽长比小于设定值，以使得在其导通的时间内控制第二像素电极和第三像素电极之间的电压差不为零，其中，在对一行像素单元所对应的第一扫描线进行扫描的同时，对与一行像素单元相邻且最近被扫描的上一行像素单元所对应的第二扫描线进行扫描；在3D显示模式下，第一扫描线输入扫描信号以控制第一开关和第二开关导通，第一像素电极和第二像素电极接收来自数据线的数据信号以处于显示对应3D画面的图像的状态，第二扫描线控制第三开关断开，以使得第三像素电极处于显示对应黑画面的图像的状态。
其中，阵列基板还包括位于阵列基板外围区域的开关单元和短路线；开关单元包括多个受控开关，受控开关包括控制端、输入端以及输出端，每个受控开关的输入端连接一行像素单元所对应的第一扫描线，输出端连接与一行像素单元相邻的上一行像素单元所对应的第二扫描线，所有受控开关的控制端与短路线连接；在2D显示模式下，短路线输入控制信号以控制所有受控开关导通，在一行像素单元所对应的第一扫描线输入扫描信号时，扫描信号通过受控开关同时输入至与受控开关的输出端连接的第二扫描线中，以控制相应的第三开关导通，在3D显示模式下，短路线输入控制信号以控制所有受控开关断开，以控制所有第三开关断开。
其中，第三像素电极所在区域的面积小于第一像素电极和第二像素电极所在区域的面积。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括多条第一扫描线、多条第二扫描线、多条数据线以及多个像素单元，每个像素单元对应一条第一扫描线、一条第二扫描线以及一条数据线；每个像素单元包括第一像素电极、第二像素电极、第三像素电极、第一开关、第二开关以及第三开关，第一像素电极通过第一开关与对应本像素单元的第一扫描线和数据线连接，第二像素电极通过第二开关与对应本像素单元的第一扫描线和数据线连接，第三像素电极通过第三开关与第二像素电极和对应本像素单元的第二扫描线连接；在2D显示模式下，第一扫描线输入扫描信号以控制第一开关和第二开关导通，第一像素电极和第二像素电极接收来自数据线的数据信号以处于显示对应2D画面的图像的状态，随后第二扫描线输入扫描信号以控制第三开关导通，以使得第二像素电极和第三像素电极电性连接，第三像素电极接收来自第二像素电极的数据信号以处于显示对应2D画面的图像的状态，使得第二像素电极的电压通过第三像素电极改变，第三开关在其导通的时间内控制第二像素电极和第三像素电极之间的电压差不为零；在3D显示模式下，第一扫描线输入扫描信号以控制第一开关和第二开关导通，第一像素电极和第二像素电极接收来自数据线的数据信号以处于显示对应3D画面的图像的状态，第二扫描线控制第三开关断开，以使得第三像素电极处于显示对应黑画面的图像的状态。
其中，多个像素单元分行排列，多条第一扫描线和第二扫描线也分行排列，在2D显示模式下，在对一行像素单元所对应的第一扫描线进行扫描的同时，对与一行像素单元相邻且最近被扫描的上一行像素单元所对应的第二扫描线进行扫描。
其中，阵列基板还包括位于阵列基板外围区域的开关单元和短路线；开关单元包括多个受控开关，受控开关包括控制端、输入端以及输出端，每个受控开关的输入端连接一行像素单元所对应的第一扫描线，输出端连接与一行像素单元相邻的上一行像素单元所对应的第二扫描线，所有受控开关的控制端与短路线连接；在2D显示模式下，短路线输入控制信号以控制所有受控开关导通，在一行像素单元所对应的第一扫描线输入扫描信号时，扫描信号通过受控开关同时输入至与受控开关的输出端连接的第二扫描线中，以控制相应的第三开关导通，在3D显示模式下，短路线输入控制信号以控制所有受控开关断开，以控制所有第三开关断开。
其中，第三像素电极所在区域的面积小于第一像素电极和第二像素电极所在区域的面积。
其中，第三开关为薄膜晶体管，薄膜晶体管的宽长比小于设定值，以使得在其导通的时间内控制第二像素电极和第三像素电极之间的电压差不为零。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板，包括阵列基板、彩色滤光基板以及位于阵列基板之间的液晶层；阵列基板包括多条第一扫描线、多条第二扫描线、多条数据线以及多个像素单元，每个像素单元对应一条第一扫描线、一条第二扫描线以及一条数据线；每个像素单元包括第一像素电极、第二像素电极、第三像素电极、第一开关、第二开关以及第三开关，第一像素电极通过第一开关与对应本像素单元的第一扫描线和数据线连接，第二像素电极通过第二开关与对应本像素单元的第一扫描线和数据线连接，第三像素电极通过第三开关与第二像素电极和对应本像素单元的第二扫描线连接；在2D显示模式下，第一扫描线输入扫描信号以控制第一开关和第二开关导通，第一像素电极和第二像素电极接收来自数据线的数据信号以处于显示对应2D画面的图像的状态，随后第二扫描线输入扫描信号以控制第三开关导通，以使得第二像素电极和第三像素电极电性连接，第三像素电极接收来自第二像素电极的数据信号以处于显示对应2D画面的图像的状态，使得第二像素电极的电压通过第三像素电极改变，第三开关在其导通的时间内控制第二像素电极和第三像素电极之间的电压差不为零；在3D显示模式下，第一扫描线输入扫描信号以控制第一开关和第二开关导通，第一像素电极和第二像素电极接收来自数据线的数据信号以处于显示对应3D画面的图像的状态，第二扫描线控制第三开关断开，以使得第三像素电极处于显示对应黑画面的图像的状态。
其中，多个像素单元分行排列，多条第一扫描线和第二扫描线也分行排列，在2D显示模式下，在对一行像素单元所对应的第一扫描线进行扫描的同时，对与一行像素单元相邻且最近被扫描的上一行像素单元所对应的第二扫描线进行扫描。
其中，阵列基板还包括位于阵列基板外围区域的开关单元和短路线；开关单元包括多个受控开关，受控开关包括控制端、输入端以及输出端，每个受控开关的输入端连接一行像素单元所对应的第一扫描线，输出端连接与一行像素单元相邻的上一行像素单元所对应的第二扫描线，所有受控开关的控制端与短路线连接；在2D显示模式下，短路线输入控制信号以控制所有受控开关导通，在一行像素单元所对应的第一扫描线输入扫描信号时，扫描信号通过受控开关同时输入至与受控开关的输出端连接的第二扫描线中，以控制相应的第三开关导通，在3D显示模式下，短路线输入控制信号以控制所有受控开关断开，以控制所有第三开关断开。
其中，第三像素电极所在区域的面积小于第一像素电极和第二像素电极所在区域的面积。
其中，第三开关为薄膜晶体管，薄膜晶体管的宽长比小于设定值，以使得在其导通的时间内控制第二像素电极和第三像素电极之间的电压差不为零。
本发明的有益效果是：区别于现有技术的情况，本发明的阵列基板中，每个像素单元包括第一像素电极、第二像素电极以及第三像素电极，在2D显示模式下第一像素电极和第二像素电极接收来自数据线的数据信号以处于显示对应2D画面的图像的状态，第三像素电极通过第三开关与第二像素电极连接，之后使第三开关导通以使得第二像素电极和第三像素电极电性连接，第三像素电极接收来自第二像素电极的数据信号以处于显示对应2D画面的图像的状态，由此使得在2D显示模式下第一至第三像素电极均处于显示对应2D画面的图像的状态，能够提高开口率，此外第二像素电极的电压通过第三像素电极而改变，使得第二像素电极和第一像素电极之间的电压不相同，进而使得两者之间的电压差不为零，并且通过第三开关的控制作用使得第二像素电极和第三像素电极之间的电压差不为零，从而使得三个像素电极的电压均不相同，由此能够减小大视角下的颜色差异，减小色彩失真。在3D显示模式下，使第二像素电极和第三像素电极不连通，从而使得第三像素电极无法接收第二像素电极的数据信号，即第三像素电极没有数据信号，即第三像素电极没有数据信号，进而使得第三像素电极处于显示对应黑画面的图像的状态，由此能够降低双眼信号串扰。
【附图说明】
图1是本发明阵列基板一实施方式的结构示意图；
图2是图1中一个像素单元的结构示意图；
图3是图1中像素单元的结构等效电路图；
图4是图1中像素单元的第三像素电极在3D显示模式下的显示效果示意图；
图5是本发明阵列基板的另一实施方式中，像素单元的结构等效电路图；
图6是本发明液晶显示面板一实施方式的结构示意图。
【具体实施方式】
在液晶显示技术中，为了改善大视角下的颜色失真，在像素设计中，通常将一个像素分为具有不同液晶指向的多个像素区域，通过控制每个像素区域的电压不相同，以使得两个像素区中的液晶分子排列不相同，进而改善大视角下的颜色失真，以达到LCS（Low Color Shift，低色偏）的效果，即获得大视角下颜色差异较小的效果。
下面将结合实施方式和附图对本发明进行详细说明。
参阅图1，本发明阵列基板的一实施方式中，阵列基板包括多条第一扫描线11、多条第二扫描线12、多条数据线13以及多个像素单元14。多个像素单元14呈阵列排列，每个像素单元14与一条第一扫描线11、一条第二扫描线12以及一条数据线13连接。
其中，结合图2和图3，每个像素单元14包括第一像素电极M1、第二像素电极M2、第三像素电极M3，以及分别作用于第一像素电极M1、第二像素电极M2以及第三像素电极M3的第一开关T1、第二开关T2和第三开关T3。第一开关T1的控制端和第二开关T2的控制端与第一扫描线11电性连接，第一开关T1的输入端和第二开关T2的输入端与数据线13电性连接，第一开关T1的输出端与第一像素电极M1电性连接，第二开关T2的输出端与第二像素电极M2电性连接。第三开关T3的控制端与第二扫描线12电性连接，第三开关T3的输入端与第二像素电极M2电性连接，第三开关T3的输出端与第三像素电极M3电性连接。
本实施方式的第一开关T1、第二开关T2以及第三开关T3均为薄膜晶体管，其中，三个开关T1、T2、T3的控制端对应为薄膜晶体管的栅极，输入端对应为薄膜晶体管的源极，输出端对应为薄膜晶体管的漏极。当然，在其他实施方式中，三个开关也可以是三极管、达林顿管等开关元件。
通过本实施方式的阵列基板，能够降低2D显示模式下大视角观察到的颜色差异，提高开口率，同时能够降低3D显示模式下的双眼信号串扰。
具体地，在2D显示模式下，本实施方式采用逐行扫描的方式对第一扫描线11和第二扫描线12进行扫描。首先第一扫描线11输入高电平的扫描信号以控制第一开关T1和第二开关T2导通，数据线13输入数据信号，第一像素电极M1和第二像素电极M2分别通过第一开关T1和第二开关T2接收来自数据线13的数据信号而具有相同的电压，第一像素电极M1和第二像素电极M2处于显示对应2D画面的图像的状态。随后第一扫描线11停止输入高电平的扫描信号以使得第一开关T1和第二开关T2断开，第二扫描线12输入高电平的扫描信号以控制第三开关T3导通，此时第二像素电极M2和第三像素电极M3通过第三开关T3电性连接，存储在第二像素电极M2上的数据信号通过第三开关T3输入至第三像素电极M3，第三像素电极M3接收来自第二像素电极M2的数据信号后处于显示对应2D画面的图像的状态。因此，在2D显示模式下，三个像素电极M1、M2、M3均处于显示对应2D画面的图像的状态，由此能够提高2D显示模式的开口率。并且，第三开关T3导通时第二像素电极M2的电压通过第三像素电极M3改变，即第二像素电极M2的电压通过与液晶电容Clc3（由第三像素电极M3和另一基板的公共电极之间夹有液晶分子而造成的等效电容）之间的电荷分享而改变。具体为，在正极性（数据信号大于公共电压）反转时，第二像素电极M2的部分电荷转移至第三像素电极M3中，使得第二像素电极M2的电压降低，第三像素电极M3的电压升高，从而使得第二像素电极M2的电压与第一像素电极M1的电压不再相同，即两者之间存在不为零的电压差；在负极性（数据信号小于公共电压）反转时，由于第三像素电极M3保留着前一时帧的正极性电压，因此在第三开关T3导通时第三像素电极M3的部分电荷转移至第二像素电极M2中，使得第二像素电极M2的电压增加，从而使得第二像素电极M2的电压与第一像素电极M1的电压不再相同。此外，第三开关T3在其导通的时间内控制第二像素电极M2和第三像素电极M3之间的电压差不为零，使得在第三开关T3导通的时间内不会使得第二像素电极M2和第三像素电极M3达到放电平衡状态，由此，第一像素电极M1、第二像素电极M2以及第三像素电极M3之间的电压均不相同，能够减小2D显示模式下大视角的颜色差异，达到低色偏效果。
进一步地，本实施方式的第三开关T3为薄膜晶体管，可通过控制第三开关T3的宽长比来控制第三开关T3在其导通内控制第二像素电极M2和第三像素电极M3之间的电压差不为零，即通过控制第三开关T3的宽长比来控制第三开关T3在导通时的电流通过能力。第三开关T3的宽长比越大，第三开关T3在导通时的电流通过能力越大，第二像素电极M2和第三像素电极M3之间的电荷转移速度也越快，而第三开关T3的宽长比越小，第三开关T3在导通时的电流通过能力越小，第二像素电极M2和第三像素电极M3之间的电荷转移速度也越慢。为了保证在第三开关T3导通的时间内使得第二像素电极M2的电压和第三像素电极M3的电压不相同，可控制第二像素电极M2和第三像素电极M3之间的电荷转移速度较慢，进一步可通过使得第三开关T3的宽长比小于设定值，例如该设定值为0.3，以使得在第三开关T3导通的时间内第二像素电极M2和第三像素电极M3之间的电压差不为零。在其他实施方式中，也可以通过控制第三开关T3的栅极电压的大小（即第二扫描线12所输入的扫描信号的大小）来控制第三开关T3在导通时的电流通过能力，此处不进行限制。
在完成一行像素单元14所对应的第一扫描线11和第二扫描线12的扫描后，对下一行像素单元对应的第一扫描线11和第二扫描线12进行扫描。
结合图4，在3D显示模式下，首先利用黑画面信号关闭第三像素电极M3，即数据线13对第一像素电极M1和第二像素电极M2输入显示对应黑画面的数据信号，控制第三开关T3导通使得第三像素电极M3处于显示对应黑画面的图像的状态，以关闭第三像素电极M3。之后，第一扫描线11输入高电平的扫描信号以控制第一开关T1和第二开关T2导通，数据线13分别通过第一开关T1和第二开关T3对第一像素电极M1和第二像素电极M2输入数据信号，以使得第一像素电极M1和第二像素电极M2处于显示对应3D画面的图像的状态。在3D显示模式下，关闭第二扫描线12，即不对第二扫描线12输入扫描信号，以控制第三开关T3处于断开的状态，从而使得第三像素电极M3保持处于显示对应黑画面的图像的状态。
本实施方式中，第一像素电极M1、第二像素电极M2以及第三像素电极M3沿列方向依次排列，相邻两行像素单元14分别显示对应3D画面的左眼图像和右眼图像。在3D显示模式下，如图4所示，通过第三开关T3的断开作用使得第三像素电极M3处于显示对应黑画面的图像的状态，该处于显示对应黑画面的图像的状态的第三像素电极M3为遮光区域（等效于黑矩阵，Black Matrix，BM），从而使得相邻两行像素单元14中，显示左眼图像的像素电极（一行像素单元中的第二像素电极和第三像素电极）和显示右眼图像的像素电极（另一行像素单元中的第二像素电极和第三像素电极）之间存在一遮光区域，通过该遮光区域阻挡左眼图像和右眼图像的串扰信号，从而能够降低3D显示模式下的双眼信号串扰。此外，第三像素电极M3主要用于在3D显示模式下形成遮光区域以降低3D信号串扰，因此第三像素电极M3所在区域的面积均小于第一像素电极M1和第二像素电极M2所在区域的面积，当然也可根据实际的遮光需要设计第三像素电极M3所占的面积，以尽可能减少3D双眼信号串扰现象。
当然，在备选实施方式中，三个像素电极也可以沿行方向排列，此时相邻两列像素单元分别显示对应3D画面的左眼图像和右眼图像。通过显示对应黑画面的图像的第三像素电极，能够减少3D显示模式下的双眼信号串扰。此外，在3D显示模式时，也可以利用插黑的方式使第三像素电极处于显示黑画面的状态，并且在第一扫描线的消隐时间（Blanking time）进行插黑。进一步而言，在一个扫描时帧里使第一像素电极和第二像素电极处于显示对应3D画面的图像的状态，而第三像素电极仍然处于显示对应黑画面的图像的状态，而在下一个扫描时帧里使第一像素电极、第二像素电极、以及第三像素电极均处于显示对应黑画面的图像的状态，之后第一像素电极和第二像素电极又恢复到处于显示3D画面的图像的状态，而第三像素电极仍然保持处于显示对应3D画面的图像的状态，即第一像素电极和第二像素电极交替处于显示3D画面的图像的状态和处于显示对应黑画面的图像的状态，而第三像素电极一直保持着显示对应3D画面的图像的状态。通过上述插黑方式，能够防止第二像素电极由于漏电而出现漏光。
上述实施方式中，在2D显示模式下采用逐行扫描的方式对第一、第二扫描线进行扫描，参阅图5，本发明阵列基板另一实施方式中，也可以同时扫描对应不同行像素单元的第一扫描线和第二扫描线。多个像素单元44分行排列，且多条第一扫描线（图中仅示出3条，包括第一扫描线41_1、41_2、41_3）和多条第二扫描线（图中仅示出3条，包括第二扫描线42_1、42_2、42_3）也分行排列，一行像素单元对应一条第一扫描线和一条第二扫描线。
在2D显示模式下，以相邻的第一行像素单元A1和第二行像素单元A2为例进行说明，在对第二行像素单元A2所对应的第一扫描线41_2扫描的同时，对与第二行像素单元A2相邻且上一行最近被扫描的第一行像素单元A1所对应的第二扫描线42_1进行扫描。
具体地，本实施方式的阵列基板还包括位于阵列基板外围区域的开关单元45和一条短路线46。开关单元45包括多个受控开关（图中仅示出4个，其中包括受控开关T4_1、T4_2）。受控开关包括控制端、输入端和输出端。以第一行像素单元A1和第二行像素单元A2之间的受控开关T4_1进行说明，受控开关T4_1的输入端连接第二行像素单元A2对应的第一扫描线41_2，受控开关T4_1的输出端连接第一行像素单元A1对应的第二扫描线42_1，所有受控开关的控制端均与短路线46连接。其中，受控开关为薄膜晶体管，受控开关的控制端对应为薄膜晶体管的栅极，受控开关的输入端对应为薄膜晶体管的源极，受控开关的输出端对应为薄膜晶体管的漏极。
在2D显示模式下，短路线输入高电平的控制信号以控制开关单元45中的所有受控开关导通，然后逐行扫描第一扫描线41。首先第一行像素单元A1对应的第一扫描线41_1输入扫描信号以控制第一行像素单元A1中的第一开关T1和第二开关T2导通，数据线43输入数据信号，以使得第一行像素单元A1中的第一像素电极M1和第二像素电极M2处于显示对应2D画面的图像的状态。之后，第二行像素单元A2所对应的第一扫描线41_2输入扫描信号以控制第二行像素单元A2中的第一开关T1和第二开关T2导通，与此同时，由于受控开关T4_1为导通状态，第一扫描线41_2所输入的扫描信号通过受控开关T4_1输入至第一行像素单元A1所对应的第二扫描线42_1中，以控制第一行像素单元A1中的第三开关T3导通，从而使得第一行像素单元A1中的第二像素电极M2和第三像素电极M3电性连接，由此使得第一行像素单元A1中的第三像素电极M3处于显示对应2D画面的图像的状态，能够提高2D显示模式下的开口率，并且第一行像素单元A1中的第二像素电极M2的电压通过第三像素电极M3发生改变，使得第一行像素单元A1中的三个像素电极M1、M2、M2的电压均不相同，由此能够达到低色偏的效果，具体的原理可参考上述实施方式，此处不进行一一赘述。在完成第二行像素单元A2所对应的第一扫描线41_2的扫描后，对下一行像素单元A3所对应的第一扫描线41_3进行扫描，与此同时，通过受控开关T4_2使得第二行像素单元A2所对应的第二扫描线42_2也同时进行扫描，并以此类推剩余的扫描线的扫描方式。
在3D显示模式下，短路线46输入控制信号以控制开关单元45中的所有受控开关处于断开状态，对第一扫描线41_1输入扫描信号以控制第一行像素单元A1中的第一开关T1和第二开关T2导通，数据线43输入数据信号，以使得第一行像素单元A1中的第一像素电极M1和第二像素电极M2处于显示对应3D画面的图像的状态。之后，对第二行像素单元A2对应的第一扫描线41_2输入扫描信号以控制第二行像素单元A2中的第一开关T1和第二开关T2导通，而由于受控开关T4_1处于断开状态，因此第一扫描线41_2输入的扫描信号不会进入第一行像素单元A1中的第三开关T3，以使得第三开关T3处于断开状态，从而使得第一行像素单元A1中的第三像素电极M3处于显示对应黑画面的图像的状态，通过该处于显示黑画面的图像的状态的第三像素电极M3能够降低3D显示模式下的双眼信号串扰。完成第二行像素单元A2对应的第一扫描线41_2的扫描后，对下一行像素单元A3对应的第一扫描线41_3进行扫描，并以此类推，而在3D显示模式下受控开关T4始终为断开状态。
本实施方式的开关单元45和短路线46，仅需一个扫描驱动芯片对短路线施加控制信号以控制开关单元45中的受控开关的导通或关闭，从而相应控制第三开关T3导通或断开，不仅能够实现2D显示模式下的低色偏和较高开口率，以及3D显示模式下的低串扰，同时能够减少扫描驱动芯片的数量，降低成本。并且，在同一扫描时帧里同时对两条扫描线（如第一行像素单元A1对应的第二扫描线42_1和第二行像素单元A2对应的第一扫描线41_2）进行扫描，从而相应延长了每一条扫描线的扫描时间，有助于进行高更新频率的操作。
此外，在其他实施方式中，多个像素单元也可以分列排列，而多条第一扫描线和第二扫描线也分列排列，在对一列像素单元所对应的第一扫描线进行扫描的同时，也可以对与该列像素单元相邻且最近被扫描的前一列像素单元所对应的第二扫描线进行扫描，具体的可参考上述实施方式进行，此处不进行一一赘述。当然，在其他实施方式中，也可以不采用上述的开关单元45和短路线46实现对应不同行像素单元的第一扫描线和第二扫描线的同时扫描，而是使各条扫描线（包括第一扫描线和第二扫描线）相互独立，每条扫描线连接一个扫描驱动芯片以单独控制一条扫描线的扫描，由此在对一行像素单元对应的第一扫描线输入扫描信号时，同时也对上一行像素单元对应的第二扫描线输入扫描信号，采用这种方式同样能够实现同时对两条扫描线进行扫描。
参阅图6，本发明液晶显示面板的一实施方式中，液晶显示面板包括阵列基板601、彩色滤光基板602以及位于阵列基板601和彩色滤光基板602之间的液晶层603。其中，阵列基板为上述各实施方式中的阵列基板。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (13)

  1. 一种阵列基板，其中，包括多条分行排列的第一扫描线、多条分行排列的第二扫描线、多条数据线以及多个分行排列的像素单元，每个所述像素单元对应一条第一扫描线、一条第二扫描线以及一条数据线；
    每个所述像素单元包括第一像素电极、第二像素电极、第三像素电极、第一开关、第二开关以及第三开关，所述第一像素电极通过所述第一开关与对应本像素单元的第一扫描线和数据线连接，所述第二像素电极通过所述第二开关与对应本像素单元的第一扫描线和数据线连接，所述第三像素电极通过所述第三开关与所述第二像素电极和对应本像素单元的第二扫描线连接；
    在2D显示模式下，所述第一扫描线输入扫描信号以控制所述第一开关和第二开关导通，所述第一像素电极和第二像素电极接收来自所述数据线的数据信号以处于显示对应2D画面的图像的状态，随后所述第二扫描线输入扫描信号以控制所述第三开关导通，以使得所述第二像素电极和所述第三像素电极电性连接，所述第三像素电极接收来自所述第二像素电极的数据信号以处于显示对应2D画面的图像的状态，使得所述第二像素电极的电压通过所述第三像素电极改变，所述第三开关为薄膜晶体管，所述薄膜晶体管的宽长比小于设定值，以使得在其导通的时间内控制所述第二像素电极和第三像素电极之间的电压差不为零，其中，在对一行所述像素单元所对应的第一扫描线进行扫描的同时，对与所述一行像素单元相邻且最近被扫描的上一行像素单元所对应的第二扫描线进行扫描；
    在3D显示模式下，所述第一扫描线输入扫描信号以控制所述第一开关和第二开关导通，所述第一像素电极和第二像素电极接收来自所述数据线的数据信号以处于显示对应3D画面的图像的状态，所述第二扫描线控制所述第三开关断开，以使得所述第三像素电极处于显示对应黑画面的图像的状态。
  2. 根据权利要求1所述的阵列基板，其中，
    所述阵列基板还包括位于阵列基板外围区域的开关单元和短路线；
    所述开关单元包括多个受控开关，所述受控开关包括控制端、输入端以及输出端，每个所述受控开关的输入端连接一行所述像素单元所对应的第一扫描线，输出端连接与所述一行像素单元相邻的上一行像素单元所对应的第二扫描线，所有所述受控开关的控制端与所述短路线连接；
    在2D显示模式下，所述短路线输入控制信号以控制所有所述受控开关导通，在一行所述像素单元所对应的第一扫描线输入扫描信号时，所述扫描信号通过所述受控开关同时输入至与所述受控开关的输出端连接的第二扫描线中，以控制相应的第三开关导通，在3D显示模式下，所述短路线输入控制信号以控制所有所述受控开关断开，以控制所有所述第三开关断开。
  3. 根据权利要求1所述的阵列基板，其中，
    所述第三像素电极所在区域的面积小于所述第一像素电极和第二像素电极所在区域的面积。
  4. 一种阵列基板，其中，包括多条第一扫描线、多条第二扫描线、多条数据线以及多个像素单元，每个所述像素单元对应一条第一扫描线、一条第二扫描线以及一条数据线；
    每个所述像素单元包括第一像素电极、第二像素电极、第三像素电极、第一开关、第二开关以及第三开关，所述第一像素电极通过所述第一开关与对应本像素单元的第一扫描线和数据线连接，所述第二像素电极通过所述第二开关与对应本像素单元的第一扫描线和数据线连接，所述第三像素电极通过所述第三开关与所述第二像素电极和对应本像素单元的第二扫描线连接；
    在2D显示模式下，所述第一扫描线输入扫描信号以控制所述第一开关和第二开关导通，所述第一像素电极和第二像素电极接收来自所述数据线的数据信号以处于显示对应2D画面的图像的状态，随后所述第二扫描线输入扫描信号以控制所述第三开关导通，以使得所述第二像素电极和所述第三像素电极电性连接，所述第三像素电极接收来自所述第二像素电极的数据信号以处于显示对应2D画面的图像的状态，使得所述第二像素电极的电压通过所述第三像素电极改变，所述第三开关在其导通的时间内控制所述第二像素电极和第三像素电极之间的电压差不为零；
    在3D显示模式下，所述第一扫描线输入扫描信号以控制所述第一开关和第二开关导通，所述第一像素电极和第二像素电极接收来自所述数据线的数据信号以处于显示对应3D画面的图像的状态，所述第二扫描线控制所述第三开关断开，以使得所述第三像素电极处于显示对应黑画面的图像的状态。
  5. 根据权利要求4所述的阵列基板，其中，
    多个所述像素单元分行排列，多条所述第一扫描线和第二扫描线也分行排列，在2D显示模式下，在对一行所述像素单元所对应的第一扫描线进行扫描的同时，对与所述一行像素单元相邻且最近被扫描的上一行像素单元所对应的第二扫描线进行扫描。
  6. 根据权利要求5所述的阵列基板，其中，
    所述阵列基板还包括位于阵列基板外围区域的开关单元和短路线；
    所述开关单元包括多个受控开关，所述受控开关包括控制端、输入端以及输出端，每个所述受控开关的输入端连接一行所述像素单元所对应的第一扫描线，输出端连接与所述一行像素单元相邻的上一行像素单元所对应的第二扫描线，所有所述受控开关的控制端与所述短路线连接；
    在2D显示模式下，所述短路线输入控制信号以控制所有所述受控开关导通，在一行所述像素单元所对应的第一扫描线输入扫描信号时，所述扫描信号通过所述受控开关同时输入至与所述受控开关的输出端连接的第二扫描线中，以控制相应的第三开关导通，在3D显示模式下，所述短路线输入控制信号以控制所有所述受控开关断开，以控制所有所述第三开关断开。
  7. 根据权利要求4所述的阵列基板，其中，
    所述第三像素电极所在区域的面积小于所述第一像素电极和第二像素电极所在区域的面积。
  8. 根据权利要求4所述的阵列基板，其中，
    所述第三开关为薄膜晶体管，所述薄膜晶体管的宽长比小于设定值，以使得在其导通的时间内控制所述第二像素电极和第三像素电极之间的电压差不为零。
  9. 一种液晶显示面板，其中，包括阵列基板、彩色滤光基板以及位于所述阵列基板之间的液晶层；
    所述阵列基板包括多条第一扫描线、多条第二扫描线、多条数据线以及多个像素单元，每个所述像素单元对应一条第一扫描线、一条第二扫描线以及一条数据线；
    每个所述像素单元包括第一像素电极、第二像素电极、第三像素电极、第一开关、第二开关以及第三开关，所述第一像素电极通过所述第一开关与对应本像素单元的第一扫描线和数据线连接，所述第二像素电极通过所述第二开关与对应本像素单元的第一扫描线和数据线连接，所述第三像素电极通过所述第三开关与所述第二像素电极和对应本像素单元的第二扫描线连接；
    在2D显示模式下，所述第一扫描线输入扫描信号以控制所述第一开关和第二开关导通，所述第一像素电极和第二像素电极接收来自所述数据线的数据信号以处于显示对应2D画面的图像的状态，随后所述第二扫描线输入扫描信号以控制所述第三开关导通，以使得所述第二像素电极和所述第三像素电极电性连接，所述第三像素电极接收来自所述第二像素电极的数据信号以处于显示对应2D画面的图像的状态，使得所述第二像素电极的电压通过所述第三像素电极改变，所述第三开关在其导通的时间内控制所述第二像素电极和第三像素电极之间的电压差不为零；
    在3D显示模式下，所述第一扫描线输入扫描信号以控制所述第一开关和第二开关导通，所述第一像素电极和第二像素电极接收来自所述数据线的数据信号以处于显示对应3D画面的图像的状态，所述第二扫描线控制所述第三开关断开，以使得所述第三像素电极处于显示对应黑画面的图像的状态。
  10. 根据权利要求9所述的显示面板，其中，
    多个所述像素单元分行排列，多条所述第一扫描线和第二扫描线也分行排列，在2D显示模式下，在对一行所述像素单元所对应的第一扫描线进行扫描的同时，对与所述一行像素单元相邻且最近被扫描的上一行像素单元所对应的第二扫描线进行扫描。
  11. 根据权利要求10所述的显示面板，其中，
    所述阵列基板还包括位于阵列基板外围区域的开关单元和短路线；
    所述开关单元包括多个受控开关，所述受控开关包括控制端、输入端以及输出端，每个所述受控开关的输入端连接一行所述像素单元所对应的第一扫描线，输出端连接与所述一行像素单元相邻的上一行像素单元所对应的第二扫描线，所有所述受控开关的控制端与所述短路线连接；
    在2D显示模式下，所述短路线输入控制信号以控制所有所述受控开关导通，在一行所述像素单元所对应的第一扫描线输入扫描信号时，所述扫描信号通过所述受控开关同时输入至与所述受控开关的输出端连接的第二扫描线中，以控制相应的第三开关导通，在3D显示模式下，所述短路线输入控制信号以控制所有所述受控开关断开，以控制所有所述第三开关断开。
  12. 根据权利要求9所述的显示面板，其中，
    所述第三像素电极所在区域的面积小于所述第一像素电极和第二像素电极所在区域的面积。
  13. 根据权利要求9所述的显示面板，其中，
    所述第三开关为薄膜晶体管，所述薄膜晶体管的宽长比小于设定值，以使得在其导通的时间内控制所述第二像素电极和第三像素电极之间的电压差不为零。
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CN103353698A (zh) 2013-10-16
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