WO2014043926A1 - 一种阵列基板及液晶显示面板 - Google Patents

一种阵列基板及液晶显示面板 Download PDF

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Publication number
WO2014043926A1
WO2014043926A1 PCT/CN2012/081917 CN2012081917W WO2014043926A1 WO 2014043926 A1 WO2014043926 A1 WO 2014043926A1 CN 2012081917 W CN2012081917 W CN 2012081917W WO 2014043926 A1 WO2014043926 A1 WO 2014043926A1
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Prior art keywords
pixel region
pixel
sub
charge
electrical signal
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PCT/CN2012/081917
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English (en)
French (fr)
Inventor
王醉
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US13/642,532 priority Critical patent/US8896773B2/en
Priority to DE112012006820.3T priority patent/DE112012006820B4/de
Publication of WO2014043926A1 publication Critical patent/WO2014043926A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B30/00—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images
    • G02B30/20—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images by providing first and second parallax images to an observer's left and right eyes
    • G02B30/22—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images by providing first and second parallax images to an observer's left and right eyes of the stereoscopic type
    • G02B30/25—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images by providing first and second parallax images to an observer's left and right eyes of the stereoscopic type using polarisation techniques

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to an array substrate and a liquid crystal display panel.
  • the FPR 3D display system includes a liquid crystal display panel 11, polarized (Patterned Retarder film 12 and polarized glasses 13.
  • the liquid crystal display panel 101 includes pixels 16 that form a left-eye signal, pixels 17 that form a right-eye signal, and a BM between them (Black) Matrix, black matrix) 18.
  • the 3D display system mainly separates the 3D picture into the left eye image 14 and the right eye image 15 by the polarizing film 12 attached to the liquid crystal display panel 11, and then sends the left eye image 14 and the right eye image 15 to the left eye image 15 through the polarizing glasses 13 respectively.
  • the user's left and right eyes receive two sets of images, and then the brain synthesizes stereoscopic images.
  • FPR The 3D display mode has a viewing angle limitation problem. When the viewer is in a large viewing position, the phenomenon of crosstalk between the two eyes will occur. For example, the signal that should be sent to the right eye is observed by the left eye at the same time, as shown by the dotted line in Fig. 1, which will cause severe crosstalk of the picture. The image clarity is poor.
  • the usual solution is to add BM between two pixels. The width of 18 to reduce the possibility of crosstalk between the two eyes.
  • VA Vertical Alignment, liquid crystal vertical alignment type liquid crystal display panel tends to have a color drift phenomenon when viewed from a large viewing angle, and color shift tends to occur when viewed from a large viewing angle.
  • the liquid crystal display panel is usually subjected to low color shift (Low). Color washout) design. As shown in FIG.
  • the pixel area 2 of the liquid crystal display panel includes a main pixel (Main Pixel) area 21 and a sub-pixel (Sub A region 22, at the junction 20 of the main pixel region 21 and the sub-pixel region 22, is provided with a metal trace 23, and the metal trace 23 includes a charging scan line (Charge) Gate) 23a, charge sharing scan line (Share Gate) 23b and charge sharing capacitor 23c.
  • the charge scan line 23a is turned on while the charge share scan line 23b is turned off, and the main pixel area 21 and the sub-pixel area 22 are charged to the same potential.
  • the charge scan line 23a is turned off, and the charge share scan line 23b is turned on, and the potential of the sub-pixel region 22 is lower than the potential of the main pixel region 21 due to the action of the charge share capacitor 23c.
  • the different potentials cause the liquid crystal molecules of the main pixel region 21 and the sub-pixel region 22 to have different steering distributions, thereby providing a low polarization effect.
  • the VA type display panel has a relatively high contrast ratio and a short response time compared to the conventional display panel, and therefore, the FPR is usually used.
  • 3D display technology is applied to the VA type display panel to view 3D images for a better visual experience.
  • the width of the BM 30 between the two pixels must be increased.
  • the aperture ratio of the pixel is greatly reduced, thereby causing a decrease in the transmittance, and the display panel is The brightness is also reduced, and the cost is increased; on the other hand, the increased BM 30 causes the ratio of the area of the area corresponding to the main pixel area 31 and the sub-pixel area 32 to be largely changed, resulting in a serious color shift in the upper and lower viewing angles.
  • the technical problem to be solved by the present invention is to provide an array substrate and a liquid crystal display panel, which can meet the viewing angle requirements of the liquid crystal display panel in the three-dimensional display mode, improve the aperture ratio and transmittance of the liquid crystal display panel, and increase the brightness of the panel.
  • a technical solution adopted by the present invention is to provide an array substrate applied to a polarized three-dimensional liquid crystal display, comprising a plurality of pixel units, each of which includes a main pixel area and a sub-pixel area; a circuit of the pixel unit, the circuit is arranged between the pixel units; wherein the circuit comprises a charging scan line, a charge sharing scan line and a charge sharing capacitor, wherein the charging scan line, the charge sharing scan line and the charge sharing capacitor of one pixel unit respectively correspond to The charge sharing scan line of the adjacent one pixel unit is adjacent to the charge sharing capacitor and the charge scan line of the adjacent another pixel unit; the array substrate further includes a first thin film transistor, a second thin film transistor, and a third thin film transistor, the first thin film The transistor and the second thin film transistor are respectively used for controlling display and off of the main pixel region and the sub-pixel region, and the third thin film crystal is connected to the charge sharing capacitor to control a voltage difference between the main pixel region and the
  • the circuit includes a secondary data line for inputting an electrical signal to the sub-pixel region, and the secondary data line passes through the primary pixel region and the secondary pixel region to input an electrical signal to the sub-pixel region and the charge sharing capacitor.
  • the circuit includes a secondary data line for inputting an electrical signal to the sub-pixel region, the secondary data line bypassing the main pixel region and passing through the sub-pixel region to input an electrical signal to the sub-pixel region and the charge sharing capacitor.
  • the circuit includes a secondary data line for inputting an electrical signal to the sub-pixel region, the secondary data line bypassing the primary pixel region and the secondary pixel region to input an electrical signal to the sub-pixel region and the charge sharing capacitor.
  • an array substrate applied to a polarized three-dimensional liquid crystal display comprising a plurality of pixel units, each of which includes a main pixel area and a sub-pixel area; In the circuit of the pixel unit, the circuit is arranged between the pixel units.
  • the circuit includes a charge scan line, a charge share scan line, and a charge sharing capacitor, wherein the charge scan line, the charge share scan line, and the charge share capacitor of one pixel unit respectively correspond to the charge share scan line and charge sharing of the adjacent one pixel unit.
  • the capacitor is adjacent to the charging scan line of another adjacent pixel unit.
  • the circuit includes a secondary data line for inputting an electrical signal to the sub-pixel region, and the secondary data line passes through the primary pixel region and the secondary pixel region to input an electrical signal to the sub-pixel region and the charge sharing capacitor.
  • the circuit includes a secondary data line for inputting an electrical signal to the sub-pixel region, the secondary data line bypassing the main pixel region and passing through the sub-pixel region to input an electrical signal to the sub-pixel region and the charge sharing capacitor.
  • the circuit includes a secondary data line for inputting an electrical signal to the sub-pixel region, the secondary data line bypassing the primary pixel region and the secondary pixel region to input an electrical signal to the sub-pixel region and the charge sharing capacitor.
  • a polarized three-dimensional liquid crystal display panel comprising an array substrate and a color filter substrate; the color filter substrate comprises a black matrix; and the array substrate comprises: a plurality of pixels a unit, each of which includes a main pixel area and a sub-pixel area; a circuit that acts on the pixel unit, the circuit is disposed between the pixel units, and is at least partially located within the black matrix vertical projection area.
  • the circuit includes a charge scan line, a charge share scan line, and a charge sharing capacitor, wherein the charge scan line, the charge share scan line, and the charge share capacitor of one pixel unit respectively correspond to the charge share scan line and charge sharing of the adjacent one pixel unit.
  • the capacitor is adjacent to the charging scan line of another adjacent pixel unit.
  • the circuit includes a data line for inputting an electrical signal to the sub-pixel region, the data line passing through the main pixel region and the sub-pixel region to input an electrical signal to the sub-pixel region and the charge sharing capacitor.
  • the circuit includes a data line for inputting an electrical signal to the sub-pixel region, the data line bypassing the main pixel region and passing through the sub-pixel region to input an electrical signal to the sub-pixel region and the charge sharing capacitor.
  • the circuit includes a data line for inputting an electrical signal to the sub-pixel region, the data line bypassing the main pixel region and the sub-pixel region to input an electrical signal to the sub-pixel region and the charge sharing capacitor.
  • the array substrate of the present invention divides the pixel unit into a main pixel area and a sub-pixel area, and lays out a circuit acting on the pixel unit between the pixel units, In the three-dimensional display mode, the aperture ratio and the transmittance of the liquid crystal display panel can be increased, and the brightness of the liquid crystal display panel can be increased.
  • FIG. 1 is a schematic structural view of an FPR 3D display system in the prior art, and shows optical path differences under two viewing angle conditions;
  • FIG. 2 is a schematic structural diagram of a metal trace layout of a pixel unit of a FPR 3D display system in the prior art
  • FIG. 3 is a schematic diagram showing a distribution of a black matrix of the pixel unit of FIG. 2 in a 3D display mode
  • FIG. 4 is a schematic structural view of an embodiment of an array substrate applied to a polarized liquid crystal display according to the present invention
  • Figure 5 is a schematic structural view of an embodiment of the circuit of Figure 4.
  • FIG. 6 is a schematic structural view of another embodiment of the circuit of FIG. 4;
  • Figure 7 is a schematic structural view of still another embodiment of the circuit of Figure 4.
  • Fig. 8 is a schematic structural view of an embodiment of a liquid crystal display panel of the present invention.
  • the invention is applied to an array substrate of a polarized three-dimensional liquid crystal display and a liquid crystal display panel, and can improve the aperture ratio and the transmittance of the liquid crystal display panel in the three-dimensional display mode, and increase the brightness of the liquid crystal display panel.
  • the array substrate 100 in an embodiment of the present invention applied to an array substrate of a polarized three-dimensional liquid crystal display, includes a plurality of pixel units 101 and a circuit 102 acting on the pixel unit 101.
  • Each of the pixel units 101 includes a main pixel area 1011 and a sub-pixel area 1012.
  • the circuit 102 includes a charge scan line 1021, a charge share scan line 1022, and a charge sharing capacitor 1023.
  • the circuit 102 is arranged between the pixel units 101 adjacent to each other.
  • the present embodiment is described by taking two pixel units adjacent to each other in FIG. 4 as an example.
  • the two pixel units are the first pixel unit 201 and the second pixel unit 202 respectively.
  • the first pixel unit 201 includes a first main pixel area 2011 and a first sub-pixel area 2012
  • the second pixel unit 202 includes a second main pixel area 2021 and a second sub-pixel area 2022.
  • the first circuit acts on the first pixel unit 201 and includes a first charge scan line 2031, a first charge share scan line 2032, and a first charge share capacitor 2033.
  • a second circuit acts on the second pixel unit 202 and includes a second charge scan line 2041, a second charge share scan line 2042, and a second charge share capacitor 2043.
  • the first charging scan line 2031 of the first circuit is disposed at the upper end of the first pixel unit 201, and the first charge sharing scan line 2032 and the second charge sharing capacitor 2033 are correspondingly disposed at the lower bottom end of the first pixel unit 201;
  • the second charging scan line 2041 of the second circuit is disposed at the upper top end of the second pixel unit 202, and the second charge sharing scan line 2042 and the second charge sharing capacitor 2043 are correspondingly disposed at the lower bottom end of the second pixel unit 202.
  • the second charging scan line 2041 corresponding to the second pixel unit 202 is adjacent to the first charge sharing scan line 2032 and the first charge sharing capacitor 2033 of the adjacent first pixel unit 201, and the second A charging scan line corresponding to the second charge-sharing scan line 2042 and the second charge-sharing capacitor 2043 corresponding to the pixel unit 202 and the adjacent another pixel unit 207 (below the second pixel unit 202, only a partial structure is shown in the figure) 2071 adjacent to the first pixel unit 201 corresponding to the first charge scan line 2031 and another adjacent pixel unit (located above the first pixel unit 201, not shown) charge sharing scan line and charge sharing capacitance (Figure None of them are adjacent.
  • the first circuit disposed on the first pixel unit 201 is disposed at a boundary between the first pixel unit 201 and other upper and lower adjacent pixel units, such as a boundary 205 with the second pixel unit 202;
  • the second circuit layout of the two pixel unit 202 is at the intersection of the second pixel unit 202 and other upper and lower adjacent pixel units, such as the interface 205 with the first pixel unit 201.
  • Each circuit layout is at the intersection of the adjacent pixel units, and the boundary between the main pixel area and the sub-pixel area of the corresponding pixel unit is also changed into a penetration area, which increases the area of the display area.
  • the interface 205 of the two pixel units is located in the coverage area 206 of the black matrix (not shown) vertically projected, and each trace of each circuit also has the effect of a black matrix, which is disposed in the coverage area 206 of the vertical projection of the black matrix.
  • the area of the display area is saved, and when the black matrix is added to meet the viewing angle requirement of the three-dimensional display, the influence on the area ratio of the main pixel area and the sub-pixel area can be reduced, and the opening of the liquid crystal display panel can also be improved in the three-dimensional display mode. Rate and transmittance increase the brightness of the LCD panel.
  • the circuit of the present embodiment further includes a secondary data line for inputting an electrical signal to the sub-pixel region.
  • a secondary data line for inputting an electrical signal to the sub-pixel region.
  • the first pixel unit in FIG. 5 as an example for description, with continued reference to FIG. 5, in the region of the first charging scan line 2031, the first main pixel area 2011 and the first sub-pixel area 2012 are respectively displayed and turned off.
  • a third thin film transistor 2036 is further provided in a region of the first charge share scan line 2032 and the first charge share capacitor 2033.
  • Each thin film crystal includes a gate, a source, and a drain.
  • the first circuit further includes a main data line 2037 for supplying an electrical signal to the first main pixel area 2011 and the first sub-pixel area 2012, and a sub-data line 2038 for transmitting an electrical signal to the main data line 2037 and the second data line 2038.
  • the first pixel region 2012 wherein the electrical signal is a data signal.
  • the first main pixel region 2011 is provided with a main pixel electrode 20111
  • the first sub-pixel region 2012 is provided with a sub-pixel electrode 20121.
  • the first gate electrode 20341 of the first thin film transistor 2034 is electrically connected to the first charging scan line 2031
  • the first source electrode 20342 is electrically connected to the main data line 2037
  • the first drain electrode 20343 is electrically connected to the main pixel electrode 20111.
  • the second gate 20351 of the second thin film transistor 2035 is electrically connected to the first charging scan line 2031
  • the second source 20352 is electrically connected to the main data line 2037
  • the second drain 20353 is electrically connected to the secondary data line 2038 to pass the secondary data line 2038. It is electrically connected to the sub-pixel electrode 20121.
  • the third gate 20361 of the third thin film crystal 2036 is electrically connected to the first charge sharing scan line 2032, and the third source 20362 is electrically connected to the secondary data line 2038 to be electrically connected to the subpixel electrode 20121 through the secondary data line 2038.
  • the pole 20363 electrically connects the first charge sharing capacitor 2033.
  • the secondary data line 2038 passes through the first main pixel area 2011 and the first sub-pixel area 2012 to transmit the data signal provided by the main data line 2037 to the first sub-pixel area 2012 and the first charge sharing capacitor 2033. At the office.
  • the first charging scan line 2031 inputs a scan signal to turn on the first thin film transistor 2034 and the second thin film transistor 2035, and then the main data line 2037 inputs a data signal required for three-dimensional display.
  • the data signal entering the first main pixel region 2011 is input from the first source 20342 to the first thin film transistor 2034, and is output to the main pixel electrode 20111 through the first drain 20343, so that the first main pixel region 2011 displays a three-dimensional picture.
  • the data signal entering the first pixel region 2012 is input from the second source 20352 to the second thin film transistor 2035, and is output to the secondary data line 2038 through the second drain 20353, and the data signal is transmitted to the sub-pixel electrode through the secondary data line 2038.
  • the main pixel electrode 20111 and the sub-pixel electrode 20121 have the same potential, that is, the first main pixel region 2011 and the first sub-pixel region 2012 have the same potential. Stopping the input of the scan signal to the first charge scan line 2031, the first charge share scan line 2032 inputting the scan signal to turn on the third thin film transistor 2036, since the third source 20361 is electrically connected to the sub-pixel electrode 20121 through the secondary data line 2038, When the third thin film transistor 2036 is turned on, the voltage signal of the sub-pixel electrode 20121 is transmitted to the third source 20361 through the sub-data line 2038, and then coupled to the first charge-sharing capacitor 2033 electrically connected to the third drain 20363. Under the action of the first charge-sharing capacitor 2033, the potential of the sub-pixel electrode 20121 is made lower than the potential of the main pixel electrode 20111, that is, the first main pixel region 2011 and the first sub-pixel region 2012 have a potential difference.
  • the liquid crystal display panel can improve the color difference of the large viewing angle to some extent in the three-dimensional display mode. , reduce color distortion and improve display.
  • the secondary data line 3038 of the present embodiment can also bypass the first main pixel region 3011 and pass through the first sub-pixel region 3012.
  • the sub-pixel electrode 30121 is connected to the third thin film transistor 3036 through the sub-data line 3038 to transmit the data signal to the first charge-sharing capacitor 3033.
  • a voltage difference exists between the first main pixel region 3011 and the first sub-pixel region 3012 by the first charge sharing capacitor 3033.
  • FIG. 7 a schematic structural diagram of still another embodiment of the circuit of the present invention is different from the layout of the circuit shown in FIG. 5 in that the secondary data line 4038 of the present embodiment bypasses the first main pixel region 4011 and the first The sub-pixel region 4012, that is, passes through the edges of the first main pixel region 4011 and the first sub-pixel region 4012 to transmit the data signal to the sub-pixel electrode 40121 of the first sub-pixel region 4012, and the sub-pixel electrode 40121 is disposed at the same time.
  • the sub-pixel electrode 40121 is connected to the third thin film transistor 4036 through the sub-data line 4038 to transmit the data signal to the first charge-sharing capacitor 4033.
  • the first main pixel region 4011 and the first sub-pixel region 4012 have a voltage difference due to the first charge sharing capacitor 4033.
  • the specific circuit connection relationship and the driving principle can be referred to the above embodiments, and will not be further described herein.
  • the array substrate of the present embodiment can improve the color difference of the large viewing angle to a certain extent, reduce the color distortion, and also improve the aperture ratio and the wearing of the liquid crystal display panel. Transparency increases the brightness of the LCD panel.
  • the liquid crystal display panel 500 includes: an array substrate 501 and a color filter base 502, wherein, in the figure, the display is better
  • the array substrate 501 and the color filter substrate 502 are placed in the same plane tiling manner.
  • the color filter substrate 502 includes a black matrix 5021;
  • the array substrate includes: a plurality of pixel units 5011, each of the pixel units 5011 includes a main pixel region 50111 and a sub-pixel region 50112; a circuit 5012 acting on the pixel unit 5011, the circuit 5012
  • the layout is between the pixel units 5011 and at least partially within the vertical projection area of the black matrix 5021.
  • the circuit 5012 includes a charge scan line 50121, a charge share scan line 50122, and a charge sharing capacitor 50123.
  • the charge scan line 50121, the charge share scan line 50122, and the charge share capacitor 50123 of one pixel unit 5011 respectively correspond to the charge share scan line 50122 and the charge share capacitor 50123 of the adjacent one pixel unit 5011, and another adjacent pixel unit.
  • the charging scan line 50121 of 5011 is adjacent. It can be understood that the circuit 5012 is arranged between pixel units adjacent to each other.
  • the circuit 5012 of the present embodiment further includes a secondary data line (not shown) for inputting a data signal to the sub-pixel region 50112 and the charge sharing capacitor 50123 such that the main pixel region 50111 and the sub-pixel region 50112 are in the charge sharing capacitor. There is a voltage difference under the action of 50123, so that the liquid crystal display panel has a low color shift effect in the three-dimensional display mode.
  • a secondary data line (not shown) for inputting a data signal to the sub-pixel region 50112 and the charge sharing capacitor 50123 such that the main pixel region 50111 and the sub-pixel region 50112 are in the charge sharing capacitor.
  • There is a voltage difference under the action of 50123 so that the liquid crystal display panel has a low color shift effect in the three-dimensional display mode.
  • the various traces in circuit 5012 also have the effect of a black matrix that is placed in the projected area of black matrix 5021 of color filter substrate 502 without the need to occupy additional display area.
  • the width of the black matrix 5021 is increased to satisfy the viewing angle requirement in the three-dimensional display mode, the influence on the area of the two display regions of the main pixel region 50111 and the sub-pixel region 50112 can be reduced, thereby improving the aperture ratio and penetration of the liquid crystal display panel. Rate, increase the brightness of the LCD panel.

Abstract

提供了一种应用于偏光式三维液晶显示的阵列基板（100），包括多个像素单元（101）和作用于像素单元（101）的电路（102），将像素单元（101）分为主像素区域（1011）和次像素区域（1012），并将电路（102）布局在像素单元（101）之间。还提供一种偏光式三维液晶显示面板（500）。本发明能够在三维显示模式下能够提高液晶显示面板（500）的开口率和穿透率，增加液晶显示面板（500）的亮度。

Description

一种阵列基板及液晶显示面板
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种阵列基板及液晶显示面板。
【背景技术】
FPR（Film-type Patterned Retarder，偏光式）是现有3D液晶显示的成像方式之一。如图1所示，FPR 3D显示系统包括液晶显示面板11、偏光（Patterned Retarder）薄膜12以及偏光眼镜13。液晶显示面板101包括形成左眼信号的像素16、形成右眼信号的像素17以及两者之间的BM（Black Matrix，黑色矩阵）18。FPR 3D显示系统主要是通过附着在液晶显示面板11上的偏光薄膜12将3D画面分离成左眼图像14和右眼图像15，再经过偏光眼镜13将左眼图像14和右眼图像15分别送至用户的左、右眼睛。用户的左右眼接收到两组图像，再经大脑合成立体影像。FPR 3D显示模式存在视角限制问题。当观看者处于较大视角位置时会出现双眼信号相互串扰的现象，如本应送到右眼的信号却被左眼同时观察到了，如图1虚线部分所示，由此会导致画面严重串扰，图像清晰度差。通常的解决方案是增加两个像素间BM 18的宽度，以减小双眼信号串扰的可能性。
VA（Vertical Alignment，液晶垂直取向）型液晶显示面板在大视角观察时往往会发生颜色漂移现象，在大视角观看时容易出现色偏。为了提高大视角显示效果，通常会对液晶显示面板进行低色偏（Low color washout）设计。如图2所示，液晶显示面板的像素区域2包括主像素（Main Pixel）区域21和次像素（Sub Pixel）区域22，在主像素区域21和次像素区域22的交界处20设置有金属走线23，金属走线23包括充电扫描线（Charge Gate）23a、电荷共享扫描线（Share Gate）23b和电荷共享电容23c。在正常显示时，充电扫描线23a打开，同时电荷共享扫描线23b关闭，主像素区域21和次像素区域22充电至相同的电位。随后，充电扫描线23a关闭，打开电荷共享扫描线23b，由于电荷共享电容23c的作用，使得次像素区域22的电位低于主像素区域21的电位。不同的电位使得主像素区域21和次像素区域22的液晶分子转向分布不相同，从而具备低射偏的效果。
VA型显示面板相较于传统显示面板而言具有相当高的对比度和较短的响应时间，因此，通常将FPR 3D显示技术应用于VA型显示面板上来观看3D影像以获得更好的视觉体验。但是，在将上述的低色偏设计和FPR 3D显示技术相结合时，如图3所示，为了保证3D模式下的视角要求必须增加两像素间BM30的宽度。而对于低色偏的像素设计，一方面由于金属走线33所在的区域已存在BM，再增加其他区域的BM30宽度则会导致像素的开口率大幅降低，从而导致穿透率降低，显示面板的亮度也随之降低，成本增加；在另一方面，增加的BM30使得主像素区域31和次像素区域32相对应的区域面积比例大幅改变，导致上下视角会出现严重色偏。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及液晶显示面板，能够满足液晶显示面板在三维显示模式的视角要求，提高液晶显示面板的开口率和穿透率，增加面板的亮度。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种应用于偏光式三维液晶显示的阵列基板，包括多个像素单元，每个像素单元包括主像素区域和次像素区域；作用于像素单元的电路，电路布局于像素单元之间；其中，电路包括充电扫描线、电荷共享扫描线以及电荷共享电容，其中一个像素单元的充电扫描线、电荷共享扫描线以及电荷共享电容分别对应与相邻一像素单元的电荷共享扫描线和电荷共享电容、相邻另一像素单元的充电扫描线相邻；阵列基板还包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，第一薄膜晶体管和第二薄膜晶体管分别用于控制主像素区域和次像素区域的显示和关闭，第三薄膜晶体与电荷共享电容连接以控制主像素区域和次像素区域之间存在电压差。
其中，电路包括用于对次像素区域输入电信号的次数据线，次数据线穿过主像素区域和次像素区域，以对次像素区域和电荷共享电容输入电信号。
其中，电路包括用于对次像素区域输入电信号的次数据线，次数据线绕开主像素区域并穿过次像素区域，以对次像素区域和电荷共享电容输入电信号。
其中，电路包括用于对次像素区域输入电信号的次数据线，次数据线绕开主像素区域和次像素区域，以对次像素区域和电荷共享电容输入电信号。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种应用于偏光式三维液晶显示的阵列基板，包括多个像素单元，每个像素单元包括主像素区域和次像素区域；作用于像素单元的电路，电路布局于像素单元之间。
其中，电路包括充电扫描线、电荷共享扫描线以及电荷共享电容，其中一个像素单元的充电扫描线、电荷共享扫描线以及电荷共享电容分别对应与相邻一像素单元的电荷共享扫描线和电荷共享电容、相邻另一像素单元的充电扫描线相邻。
其中，电路包括用于对次像素区域输入电信号的次数据线，次数据线穿过主像素区域和次像素区域，以对次像素区域和电荷共享电容输入电信号。
其中，电路包括用于对次像素区域输入电信号的次数据线，次数据线绕开主像素区域并穿过次像素区域，以对次像素区域和电荷共享电容输入电信号。
其中，电路包括用于对次像素区域输入电信号的次数据线，次数据线绕开主像素区域和次像素区域，以对次像素区域和电荷共享电容输入电信号。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种偏光式三维液晶显示面板，包括阵列基板和彩色滤光基板；彩色滤光基板包括黑色矩阵；阵列基板包括：多个像素单元，每个像素单元包括主像素区域和次像素区域；作用于像素单元的电路，电路布局于像素单元之间，并且至少部分位于黑色矩阵垂直投影区域内。
其中，电路包括充电扫描线、电荷共享扫描线以及电荷共享电容，其中一个像素单元的充电扫描线、电荷共享扫描线以及电荷共享电容分别对应与相邻一像素单元的电荷共享扫描线和电荷共享电容、相邻另一像素单元的充电扫描线相邻。
其中，电路包括用于对次像素区域输入电信号的数据线，数据线穿过主像素区域和次像素区域，以对次像素区域和电荷共享电容输入电信号。
其中，电路包括用于对次像素区域输入电信号的数据线，数据线绕开主像素区域并穿过次像素区域，以对次像素区域和电荷共享电容输入电信号。
其中，电路包括用于对次像素区域输入电信号的数据线，数据线绕开主像素区域和次像素区域，以对次像素区域和电荷共享电容输入电信号。
本发明的有益效果是：区别于现有技术的情况，本发明的阵列基板，将像素单元分为主像素区域和次像素区域，并将作用于像素单元的电路布局在像素单元之间，以在三维显示模式下能够提高液晶显示面板的开口率和穿透率，增加液晶显示面板的亮度。
【附图说明】
图1是现有技术中一种FPR 3D显示系统的结构示意图，同时示出两种视角条件下的光路差异；
图2是现有技术中一种FPR 3D显示系统的像素单元的金属走线布局的结构示意图；
图3是图2中的像素单元在3D显示模式下黑色矩阵的分布示意图；
图4是本发明应用于偏光式液晶显示的阵列基板的一实施方式的结构示意图；
图5是图4中的电路的一实施方式的结构示意图；
图6是图4中的电路的另一实施方式的结构示意图；
图7是图4中的电路的又一实施方式的结构示意图；
图8是本发明液晶显示面板的一实施方式的结构示意图。
【具体实施方式】
本发明应用于偏光式三维液晶显示的阵列基板以及液晶显示面板，能够在三维显示模式下提高液晶显示面板的开口率和穿透率，增加液晶显示面板的亮度。
下面将结合附图和实施方式对本发明进行详细说明。
参阅图4，在本发明应用于偏光式三维液晶显示的阵列基板的一实施方式中，阵列基板100包括多个像素单元101和作用于像素单元101的电路102。
每个像素单元101包括主像素区域1011和次像素区域1012。电路102包括充电扫描线1021、电荷共享扫描线1022以及电荷共享电容1023。电路102布局于上下相邻的像素单元101之间。
具体地，参阅图5，本实施方式以图4中上下相邻的两个像素单元为例进行说明，两个像素单元分别为第一像素单元201和第二像素单元202。第一像素单元201包括第一主像素区域2011和第一次像素区域2012，第二像素单元202包括第二主像素区域2021和第二次像素区域2022。第一电路（未标示）作用于第一像素单元201，包括第一充电扫描线2031、第一电荷共享扫描线2032以及第一电荷共享电容2033。第二电路（未标示）作用于第二像素单元202，包括第二充电扫描线2041、第二电荷共享扫描线2042以及第二电荷共享电容2043。
其中，第一电路的第一充电扫描线2031设置于第一像素单元201的上顶端，第一电荷共享扫描线2032和第二电荷共享电容2033对应设置于第一像素单元201的下底端；第二电路的第二充电扫描线2041设置于第二像素单元202的上顶端，第二电荷共享扫描线2042和第二电荷共享电容2043对应设置于第二像素单元202的下底端。
通过上述电路的布局，使得第二像素单元202对应的第二充电扫描线2041与相邻的第一像素单元201的第一电荷共享扫描线2032和第一电荷共享电容2033相邻，而第二像素单元202对应的第二电荷共享扫描线2042和第二电荷共享电容2043与相邻的另一像素单元207（位于第二像素单元202下方，图中只只示出部分结构）的充电扫描线2071相邻，第一像素单元201对应的第一充电扫描线2031与相邻的另一像素单元（位于第一像素单元201的上方，图未示）的电荷共享扫描线和电荷共享电容（图均未示）相邻。
本实施方式将作用于第一像素单元201的第一电路布局在第一像素单元201与其他上下相邻的像素单元的交界处，如与第二像素单元202的交界处205；将作用于第二像素单元202的第二电路布局在第二像素单元202与其他上下相邻的像素单元的交界处，如与第一像素单元201的交界处205。各电路布局在上下相邻的像素单元的交界处，也使得对应像素单元的主像素区域和次像素区域的交界处变为穿透区域，增加了显示区域面积。并且，两像素单元的交界处205位于黑色矩阵（图未示）垂直投影的覆盖区域206，而各电路的各走线也具有黑色矩阵的效果，将其设在黑色矩阵垂直投影的覆盖区域206，节省了显示区域面积，在增加黑色矩阵以满足三维显示的视角要求时，能够减少对主像素区域和次像素区域的面积比例的影响，同时也能在三维显示模式下提高液晶显示面板的开口率和穿透率，增加液晶显示面板的亮度。
进一步地，本实施方式的电路还包括用于对次像素区域输入电信号的次数据线。以图5中的第一像素单元为例进行说明，继续参阅图5，在第一充电扫描线2031的区域，还设置有分别控制第一主像素区域2011和第一次像素区域2012显示和关闭的第一薄膜晶体管2034和第二薄膜晶体管2035。在第一电荷共享扫描线2032和第一电荷共享电容2033的区域，还设置有第三薄膜晶体管2036。每个薄膜晶体均包括栅极、源极以及漏极。第一电路还包括主数据线2037和次数据线2038，主数据线2037用于对第一主像素区域2011和第一次像素区域2012提供电信号，次数据线2038用于将电信号传输至第一次像素区域2012，其中电信号为数据信号。此外，第一主像素区域2011设置有主像素电极20111，第一次像素区域2012设置有次像素电极20121。
其中，第一薄膜晶体管2034的第一栅极20341电连接第一充电扫描线2031，第一源极20342电连接主数据线2037，第一漏极20343电连接主像素电极20111。第二薄膜晶体管2035的第二栅极20351电连接第一充电扫描线2031，第二源极20352电连接主数据线2037，第二漏极20353电连接次数据线2038，以通过次数据线2038与次像素电极20121电连接。第三薄膜晶体2036的第三栅极20361电连接第一电荷共享扫描线2032，第三源极20362电连接次数据线2038，以通过次数据线2038与次像素电极20121电连接，第三漏极20363电连接第一电荷共享电容2033。
本实施方式中，次数据线2038穿过第一主像素区域2011和第一次像素区域2012，以将主数据线2037提供的数据信号传输至第一次像素区域2012和第一电荷共享电容2033处。
在三维显示模式下，第一充电扫描线2031输入扫描信号以打开第一薄膜晶体管2034和第二薄膜晶体管2035，然后主数据线2037输入三维显示所需的数据信号。进入第一主像素区域2011的数据信号从第一源极20342输入至第一薄膜晶体管2034，并通过第一漏极20343输出至主像素电极20111，以使得第一主像素区域2011显示三维画面。进入第一次像素区域2012的数据信号从第二源极20352输入至第二薄膜晶体管2035，并通过第二漏极20353输出至次数据线2038，数据信号通过次数据线2038传输至次像素电极20121。此时主像素电极20111和次像素电极20121电位相同，即第一主像素区域2011和第一次像素区域2012电位相同。停止对第一充电扫描线2031输入扫描信号，第一电荷共享扫描线2032输入扫描信号以打开第三薄膜晶体管2036，由于第三源极20361通过次数据线2038与次像素电极20121电连接，因此在第三薄膜晶体管2036打开时，次像素电极20121的电压信号通过次数据线2038传输至第三源极20361，然后耦合至与第三漏极20363电连接的第一电荷共享电容2033。在第一电荷共享电容2033的作用下，使得次像素电极20121的电位低于主像素电极20111的电位，即第一主像素区域2011和第一次像素区域2012存在电位差。
第一主像素区域2011和第一次像素区域2012存在电位差，使得两像素区域的液晶分子的转向分布不同，从而能够使液晶显示面板在三维显示模式下在一定程度上改善大视角的颜色差异，降低色彩失真，提高显示效果。
此外，参阅图6，本实施方式与图5所示的电路的布局的主要区别在于，本实施方式的次数据线3038还可以绕开第一主像素区域3011并穿过第一次像素区域3012以将数据信号传输至第一次像素区域3012的次像素电极30121，次像素电极30121通过次数据线3038与第三薄膜晶体管3036连接以将数据信号传输至第一电荷共享电容3033。在第一电荷共享电容3033的作用下使第一主像素区域3011和第一次像素区域3012存在电压差。具体的电路连接关系以及驱动原理可参考上述实施方式进行，在此不进行赘述。
参阅图7，本发明的电路的又一实施方式的结构示意图，与图5所示的电路的布局的主要区别在于，本实施方式的次数据线4038绕开第一主像素区域4011和第一次像素区域4012，即经过第一主像素区域4011和第一次像素区域4012的边缘，以将数据信号传输至第一次像素区域4012的次像素电极40121，此时次像素电极40121布局在第一电荷共享扫描线4032和第一电荷共享电容4033所在的区域。次像素电极40121通过次数据线4038与第三薄膜晶体管4036连接以将数据信号传输至第一电荷共享电容4033。在第一电荷共享电容4033的作用下使第一主像素区域4011和第一次像素区域4012存在电压差。具体的电路连接关系以及驱动原理可参考上述实施方式进行，在此也不进行一一赘述。
综上所述，本实施方式的阵列基板，在三维显示模式下，能够使液晶显示面板在一定程度上改善大视角的颜色差异，降低色彩失真，同时也能提高液晶显示面板的开口率和穿透率，增加液晶显示面板的亮度。
参阅图8，本发明偏光式三维液晶显示面板的一实施方式中，液晶显示面板500包括：阵列基板501和彩色滤光基版502，其中，图中为更好显示，是将正常为上下叠置的阵列基板501和彩色滤光基版502改为同一平面平铺的方式。其中，彩色滤光基版502包括黑色矩阵5021；阵列基板包括：多个像素单元5011，每个像素单元5011包括主像素区域50111和次像素区域50112；作用于像素单元5011的电路5012，电路5012布局于像素单元5011之间，并且至少部分位于黑色矩阵5021垂直投影区域内。
电路5012包括充电扫描线50121、电荷共享扫描线50122以及电荷共享电容50123。其中，一个像素单元5011的充电扫描线50121、电荷共享扫描线50122和电荷共享电容50123分别对应与相邻的一像素单元5011的电荷共享扫描线50122和电荷共享电容50123、相邻另一像素单元5011的充电扫描线50121相邻。可以理解为，电路5012布局在上下相邻的像素单元之间。
本实施方式的电路5012还包括次数据线（图未示），次数据线用于对次像素区域50112和电荷共享电容50123输入数据信号，使得主像素区域50111和次像素区域50112在电荷共享电容50123的作用下存在电压差，从而使液晶显示面板在三维显示模式下具有低色偏的效果。次数据线的具体布局可参考图5-图7所示的电路布局，在此不进行一一赘述。
电路5012中的各种走线也具备黑色矩阵的效果，将其设置在彩色滤光基板502的黑色矩阵5021的投影区域，而不需要占用另外的显示区域面积。在增加黑色矩阵5021的宽度以满足三维显示模式下的视角要求时，能够减少对主像素区域50111和次像素区域50112两个显示区域面积的影响，从而能够提高液晶显示面板的开口率和穿透率，增加液晶显示面板亮度。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (14)

  1. 一种应用于偏光式三维液晶显示的阵列基板，其中，包括：
    多个像素单元，每个所述像素单元包括主像素区域和次像素区域；
    作用于所述像素单元的电路，所述电路布局于像素单元之间；
    其中，所述电路包括充电扫描线、电荷共享扫描线以及电荷共享电容，其中一个所述像素单元的充电扫描线、电荷共享扫描线以及电荷共享电容分别对应与相邻一像素单元的电荷共享扫描线和电荷共享电容、相邻另一像素单元的充电扫描线相邻；
    所述阵列基板还包括第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管，所述第一薄膜晶体管和第二薄膜晶体管分别用于控制主像素区域和次像素区域的显示和关闭，所述第三薄膜晶体与电荷共享电容连接以控制所述主像素区域和次像素区域之间存在电压差。
  2. 根据权利要求1所述的阵列基板，其中，
    所述电路包括用于对次像素区域输入电信号的次数据线，所述次数据线穿过主像素区域和次像素区域，以对次像素区域和电荷共享电容输入电信号。
  3. 根据权利要求1所述的阵列基板，其中，
    所述电路包括用于对次像素区域输入电信号的次数据线，所述次数据线绕开主像素区域并穿过次像素区域，以对次像素区域和电荷共享电容输入电信号。
  4. 根据权利要求1所述的阵列基板，其中，
    所述电路包括用于对次像素区域输入电信号的次数据线，所述次数据线绕开主像素区域和次像素区域，以对次像素区域和电荷共享电容输入电信号。
  5. 一种应用于偏光式三维液晶显示的阵列基板，其中，包括：
    多个像素单元，每个所述像素单元包括主像素区域和次像素区域；
    作用于所述像素单元的电路，所述电路布局于像素单元之间。
  6. 根据权利要求5所述的阵列基板，其中，
    所述电路包括充电扫描线、电荷共享扫描线以及电荷共享电容，其中一个所述像素单元的充电扫描线、电荷共享扫描线以及电荷共享电容分别对应与相邻一像素单元的电荷共享扫描线和电荷共享电容、相邻另一像素单元的充电扫描线相邻。
  7. 根据权利要求6所述的阵列基板，其中
    所述电路包括用于对次像素区域输入电信号的次数据线，所述次数据线穿过主像素区域和次像素区域，以对次像素区域和电荷共享电容输入电信号。
  8. 根据权利要求6所述的阵列基板，其中，
    所述电路包括用于对次像素区域输入电信号的次数据线，所述次数据线绕开主像素区域并穿过次像素区域，以对次像素区域和电荷共享电容输入电信号。
  9. 根据权利要求6所述的阵列基板，其中，
    所述电路包括用于对次像素区域输入电信号的次数据线，所述次数据线绕开主像素区域和次像素区域，以对次像素区域和电荷共享电容输入电信号。
  10. 一种偏光式三维液晶显示面板，其中：
    包括阵列基板和彩色滤光基板；
    所述彩色滤光基板包括黑色矩阵；
    所述阵列基板包括：
    多个像素单元，每个所述像素单元包括主像素区域和次像素区域；
    作用于所述像素单元的电路，所述电路布局于像素单元之间，并且至少部分位于所述黑色矩阵垂直投影区域内。
  11. 根据权利要求10所述的液晶显示面板，其中，
    所述电路包括充电扫描线、电荷共享扫描线以及电荷共享电容，其中一个所述像素单元的充电扫描线、电荷共享扫描线以及电荷共享电容分别对应与相邻一像素单元的电荷共享扫描线和电荷共享电容、相邻另一像素单元的充电扫描线相邻。
  12. 根据权利要求11所述的液晶显示面板，其中，
    所述电路包括用于对次像素区域输入电信号的数据线，所述数据线穿过主像素区域和次像素区域，以对次像素区域和电荷共享电容输入电信号。
  13. 根据权利要求11所述的液晶显示面板，其特征在在于，
    所述电路包括用于对次像素区域输入电信号的数据线，所述数据线绕开主像素区域并穿过次像素区域，以对次像素区域和电荷共享电容输入电信号。
  14. 根据权利要求11所述的液晶显示面板，其中，
    所述电路包括用于对次像素区域输入电信号的数据线，所述数据线绕开主像素区域和次像素区域，以对次像素区域和电荷共享电容输入电信号。
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