WO2015010348A1 - 一种阵列基板及液晶显示面板 - Google Patents

一种阵列基板及液晶显示面板 Download PDF

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Publication number
WO2015010348A1
WO2015010348A1 PCT/CN2013/080976 CN2013080976W WO2015010348A1 WO 2015010348 A1 WO2015010348 A1 WO 2015010348A1 CN 2013080976 W CN2013080976 W CN 2013080976W WO 2015010348 A1 WO2015010348 A1 WO 2015010348A1
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Prior art keywords
pixel electrode
switch
scan
scan line
control circuit
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PCT/CN2013/080976
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English (en)
French (fr)
Inventor
薛景峰
许哲豪
姚晓慧
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深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/233,879 priority Critical patent/US9052540B2/en
Priority to JP2016528289A priority patent/JP6127213B2/ja
Priority to KR1020167004702A priority patent/KR101789947B1/ko
Priority to RU2016105818A priority patent/RU2624843C1/ru
Priority to GB1522485.0A priority patent/GB2529977B/en
Publication of WO2015010348A1 publication Critical patent/WO2015010348A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/13306—Circuit arrangements or driving methods for the control of single liquid crystal cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H04N13/302—Image reproducers for viewing without the aid of special glasses, i.e. using autostereoscopic displays
    • H04N13/31—Image reproducers for viewing without the aid of special glasses, i.e. using autostereoscopic displays using parallax barriers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H04N13/356—Image reproducers having separate monoscopic and stereoscopic modes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
    • H04N13/30—Image reproducers
    • H04N13/398—Synchronisation thereof; Control thereof
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to an array substrate and a liquid crystal display panel.
  • VA Vertical Alignment, vertical alignment type liquid crystal display panel has the advantages of fast response speed and high contrast, and is the mainstream development direction of liquid crystal display panels.
  • the alignment of the liquid crystal molecules is not the same, so that the effective refractive index of the liquid crystal molecules is also different, thereby causing a change in the transmitted light intensity, which is manifested by a decrease in light transmission capability at oblique viewing angles.
  • the color of the viewing angle and the positive viewing direction are inconsistent, and chromatic aberration occurs, so color distortion is observed at a large viewing angle.
  • one pixel is divided into a main pixel region and a sub-pixel region, and each pixel is divided into four domains (domains, which refer to microscopic regions in which the directors of the liquid crystal molecules are substantially the same).
  • domains which refer to microscopic regions in which the directors of the liquid crystal molecules are substantially the same.
  • each pixel is divided into 8 domains, and the voltages of the main pixel region and the sub-pixel region are controlled to be different, so that the liquid crystal molecules in the two pixel regions are arranged differently, thereby improving color distortion at a large viewing angle to achieve LCS. (Low Color Shift, low color cast) effect.
  • 3D FPR Flexible-type Patterned In the Retarder (polarized) stereoscopic display technology
  • two adjacent rows of pixels respectively correspond to the left and right eyes of the viewer to respectively generate a left eye image corresponding to the left eye and a right eye image corresponding to the right eye, and the left and right eyes of the viewer
  • the left and right eye images are synthesized by the brain to make the viewer feel the stereoscopic display effect.
  • the left eye image and the right eye image are prone to crosstalk, which causes the viewer to see overlapping images, which affects the viewing effect.
  • BM Black
  • Matrix, black matrix masks the way the crosstalk signal is blocked to reduce crosstalk between the two eyes.
  • the aperture ratio in the 2D display mode is greatly reduced, and the display luminance in the 2D display mode is lowered.
  • the technical solution of dividing one pixel into a main pixel region and a sub-pixel region can simultaneously solve the aperture ratio in the 2D display mode and the binocular signal crosstalk problem in the 3D display mode, that is, control the main pixel in the 2D display mode.
  • the area and the sub-pixel area both normally display the 2D image, and in the 3D display mode, the main pixel area displays a black picture equivalent to BM for reducing the binocular signal crosstalk, so that the sub-pixel area normally displays the 3D image.
  • one pixel is divided into three sub-pixel regions A, B, and C, and each sub-pixel is divided into four domains.
  • Each pixel is driven with two data lines and two scan lines.
  • the thin film transistors 1, 2, and 3 are simultaneously turned on by GateN_1, DataN_1 inputs corresponding data signals to the sub-pixel area A, and DataN_2 inputs corresponding data signals to the sub-pixel area B and the sub-pixel area C, so that three The sub-pixel areas A, B, and C normally display the 2D image, thereby being able to increase the opening in the 2D display mode, and the DataN_1 and the DataN_2 can respectively input different data signals to the sub-pixel area A, the sub-pixel area B, and the sub-pixel area C, respectively.
  • the voltages of the sub-pixel region A and the sub-pixel region B and the sub-pixel region C are different, and then the thin film transistor 4 is controlled to be turned on by the GateN_2, so that the voltages of the sub-pixel region B and the sub-pixel region C are different under the action of the capacitor C1.
  • the voltages of the three sub-pixel regions A, B, and C are different, thereby achieving the LCS effect in the 2D display mode.
  • the thin film transistors 1, 2, and 3 are simultaneously turned on by GateN_1, and DataN_1 inputs a corresponding data signal to the sub-pixel area A to cause the sub-pixel area A to display a black picture, and the DataN_2 pair sub-pixel area B and the sub-pixel area.
  • the C inputs a corresponding data signal such that the sub-pixel area B and the sub-pixel area C display a 3D image, so that among the adjacent two rows of pixels, the sub-pixel area B and the sub-pixel area C of the left eye image are displayed in one line of pixels and the other line of pixels
  • the sub-pixel area B in which the right-eye image is displayed and the sub-pixel area C have a sub-pixel area A in which a black picture is displayed, and the sub-pixel area A in which the black picture is displayed is equivalent to BM, so that 3D binocular signal crosstalk can be reduced.
  • the thin film transistor 4 is controlled to be turned on by GateN_2, and the voltages of the sub-pixel region B and the sub-pixel region C are made different by the capacitance 5, thereby realizing the LCS effect in the 3D display mode.
  • each pixel requires two data lines to be driven, which correspondingly increases the number of data drivers, which is disadvantageous for cost reduction.
  • the technical problem to be solved by the present invention is to provide an array substrate and a liquid crystal display panel, which can reduce color difference at a large viewing angle, improve an opening in a 2D display mode, reduce crosstalk of 3D binocular signals, and reduce the number of data drivers. Helps reduce costs.
  • a technical solution adopted by the present invention is to provide an array substrate including a plurality of first scan lines, a plurality of second scan lines, a plurality of third scan lines, a plurality of data lines, and a plurality of a pixel unit arranged in a row and a column and a common electrode for inputting a common voltage, each pixel unit corresponding to one first scan line, one second scan line, one third scan line and one data line; all second scan lines are on the array substrate
  • the peripheral region is electrically connected, and each of the pixel units includes a first pixel electrode, a second pixel electrode, and a third pixel electrode, and a first switch that acts on the first pixel electrode, the second pixel electrode, and the third pixel electrode, respectively a second switch and a third switch, each of the pixel units further includes a first control circuit and a second control circuit, wherein the data lines corresponding to the pixel unit respectively pass through the first switch, the second switch, and the third switch and the first
  • the signal control second control circuit acts between the second pixel electrode and the third pixel electrode, between the second pixel electrode and the third pixel electrode
  • the differential pressure is changed by the second control circuit such that there is a non-zero voltage difference between the first pixel electrode, the second pixel electrode and the third pixel electrode; in the 3D display mode, the second scan line
  • the second scan line Inputting a second scan signal to control the first control circuit to act on the first pixel electrode, and the second pixel electrode and the third pixel electrode are in an image displaying the corresponding 3D image under the action of the first scan line and the data line corresponding to the pixel unit a state in which the first pixel electrode is in a state of displaying an image corresponding to a black screen under the action of the first control circuit
  • the third scan line inputs a third scan signal to control the second control circuit to act on the second pixel electrode and the third
  • the voltage difference between the pixel electrode, the second pixel electrode, and the third pixel electrode is changed by the second control circuit such that
  • the first control circuit includes a fourth switch, the fourth switch includes a control end, a first end, and a second end, the control end of the fourth switch is connected to the second scan line, and the first end of the fourth switch is connected to the first pixel electrode
  • the second end of the fourth switch is connected to the common electrode, and the fourth switch is turned on when the second scan signal is input to the second scan line, so that the first pixel electrode and the common electrode are electrically connected, and the fourth switch is in its on time.
  • the voltage difference between the first pixel electrode and the common electrode is internally controlled to be zero.
  • the second control circuit includes a fifth switch, a first voltage dividing capacitor, and a second voltage dividing capacitor.
  • the fifth switch includes a control end, a first end, and a second end, and the control end of the fifth switch is connected to the third scan line.
  • the first end of the fifth switch is connected to one end of the first voltage dividing capacitor, the other end of the first voltage dividing capacitor is connected to the second pixel electrode, and the second end of the fifth switch is connected to the third pixel electrode, and the second partial voltage is One end of the capacitor is connected to one end of the first voltage dividing capacitor, and the other end of the second voltage dividing capacitor is connected to the common electrode, and the fifth switch is turned on when the third scan signal is input to the third scan line, so that the second pixel electrode and The voltage difference between the third pixel electrodes is changed by the first divided capacitor and the second divided capacitor.
  • the first voltage dividing capacitor is composed of a metal forming a first scan line and a metal forming a data line
  • the second voltage dividing capacitor is composed of a metal forming a first scan line and a transparent electrode.
  • an array substrate including a plurality of first scan lines, a plurality of second scan lines, a plurality of third scan lines, a plurality of data lines, and a plurality of a pixel unit arranged in rows and columns and a common electrode for inputting a common voltage, each pixel unit corresponding to a first scan line, a second scan line, a third scan line and a data line; each pixel unit includes the first a pixel electrode, a second pixel electrode, and a third pixel electrode, and a first switch, a second switch, and a third switch respectively acting on the first pixel electrode, the second pixel electrode, and the third pixel electrode, each of the pixel units further including a first control circuit and a second control circuit, wherein the data lines corresponding to the pixel unit are respectively connected to the first pixel electrode, the second pixel electrode, and the third pixel electrode through the first switch, the second switch, and the third switch to provide data
  • a pixel electrode and a third pixel electrode to change a voltage difference between the second pixel electrode and the third pixel electrode; wherein, in the 2D display mode, the first pixel electrode, the second pixel electrode, and the third pixel electrode are in a corresponding
  • the first scan circuit and the data line are in a state of displaying an image corresponding to the 2D picture, and the first control circuit controls the first pixel electrode to display an image corresponding to the 2D picture when the second scan line inputs the fourth scan signal.
  • the second scan line inputs a second scan signal to control the first control circuit to act on the first pixel electrode, and the second pixel electrode and the third pixel electrode correspond to the first scan line and the data line of the pixel unit
  • the first pixel electrode is in the state of displaying the image corresponding to the black screen under the action of the first control circuit, and then the third scan line inputs the third scan signal to control the second control.
  • the circuit acts on the second pixel electrode and the third pixel electrode, and the voltage difference between the second pixel electrode and the third pixel electrode is changed by the second control circuit so that the second pixel electrode and the third pixel electrode are between There is a voltage difference that is not zero.
  • the first control circuit is connected to the common electrode, and the first control circuit controls the voltage difference between the first pixel electrode and the common electrode to be zero when the second scan signal is input to the second scan line, so that the first pixel electrode is displayed.
  • the first control circuit includes a fourth switch, the fourth switch includes a control end, a first end, and a second end, the control end of the fourth switch is connected to the second scan line, and the first end of the fourth switch is connected to the first pixel electrode
  • the second end of the fourth switch is connected to the common electrode, and the fourth switch is turned on when the second scan signal is input to the second scan line, so that the first pixel electrode and the common electrode are electrically connected, and the fourth switch is in its on time.
  • the voltage difference between the first pixel electrode and the common electrode is internally controlled to be zero.
  • the second control circuit includes a fifth switch, a first voltage dividing capacitor, and a second voltage dividing capacitor.
  • the fifth switch includes a control end, a first end, and a second end, and the control end of the fifth switch is connected to the third scan line.
  • the first end of the fifth switch is connected to one end of the first voltage dividing capacitor, the other end of the first voltage dividing capacitor is connected to the second pixel electrode, and the second end of the fifth switch is connected to the third pixel electrode, and the second partial voltage is One end of the capacitor is connected to one end of the first voltage dividing capacitor, and the other end of the second voltage dividing capacitor is connected to the common electrode, and the fifth switch is turned on when the third scan signal is input to the third scan line, so that the second pixel electrode and The voltage difference between the third pixel electrodes is changed by the first divided capacitor and the second divided capacitor.
  • the first voltage dividing capacitor is composed of a metal forming a first scan line and a metal forming a data line
  • the second voltage dividing capacitor is composed of a metal forming a first scan line and a transparent electrode.
  • all the second scan lines are electrically connected in a peripheral region of the array substrate.
  • a liquid crystal display panel including a plurality of first scan drivers, at least one second scan driver, a plurality of third scan drivers, and a plurality of data drivers.
  • the array substrate includes a plurality of first scan lines, a plurality of second scan lines, a plurality of third scan lines, and a plurality of data lines a pixel unit arranged in a plurality of rows and columns and a common electrode for inputting a common voltage, each pixel unit corresponding to a first scan line, a second scan line, a third scan line and a data line;
  • each first scan The driver is connected to a first scan line to input a first scan signal to the first scan line
  • the at least one second scan driver is connected to the second scan line to input a second scan signal and a fourth scan signal to the second scan line
  • each The third scan driver is connected to a
  • the first pixel electrode, the second pixel electrode, and the third pixel electrode are in a state of displaying an image corresponding to the 2D image under the action of the first scan line and the data line corresponding to the pixel unit, and the first control circuit is in the first
  • the second scan line inputs the fourth scan signal, controlling the first pixel electrode to be in a state of displaying an image corresponding to the 2D picture, and then the third scan line inputting the third scan signal controls the second control circuit to act on the second pixel electrode and the third pixel electrode
  • the voltage difference between the second pixel electrode and the third pixel electrode is changed by the second control circuit such that there is a non-zero between the first pixel electrode, the second pixel electrode, and the third pixel electrode.
  • the second scan line inputs a second scan signal to control the first control circuit to act on the first pixel electrode, and the second pixel electrode and the third pixel electrode correspond to the first scan line of the pixel unit
  • the first pixel electrode is in the display pair under the action of the first control circuit a state of the image of the black screen, and then the third scan line inputs a third scan signal to control the second control circuit to act on the second pixel electrode and the third pixel electrode, and the voltage difference between the second pixel electrode and the third pixel electrode is
  • the second control circuit is changed by the action so that there is a non-zero voltage difference between the second pixel electrode and the third pixel electrode.
  • the first control circuit is connected to the common electrode, and the first control circuit controls the voltage difference between the first pixel electrode and the common electrode to be zero when the second scan signal is input to the second scan line, so that the first pixel electrode is displayed.
  • the first control circuit includes a fourth switch, the fourth switch includes a control end, a first end, and a second end, the control end of the fourth switch is connected to the second scan line, and the first end of the fourth switch is connected to the first pixel electrode
  • the second end of the fourth switch is connected to the common electrode, and the fourth switch is turned on when the second scan signal is input to the second scan line, so that the first pixel electrode and the common electrode are electrically connected, and the fourth switch is in its on time.
  • the voltage difference between the first pixel electrode and the common electrode is internally controlled to be zero.
  • the second control circuit includes a fifth switch, a first voltage dividing capacitor, and a second voltage dividing capacitor.
  • the fifth switch includes a control end, a first end, and a second end, and the control end of the fifth switch is connected to the third scan line.
  • the first end of the fifth switch is connected to one end of the first voltage dividing capacitor, the other end of the first voltage dividing capacitor is connected to the second pixel electrode, and the second end of the fifth switch is connected to the third pixel electrode, and the second partial voltage is One end of the capacitor is connected to one end of the first voltage dividing capacitor, and the other end of the second voltage dividing capacitor is connected to the common electrode, and the fifth switch is turned on when the third scan signal is input to the third scan line, so that the second pixel electrode and The voltage difference between the third pixel electrodes is changed by the first divided capacitor and the second divided capacitor.
  • the first voltage dividing capacitor is composed of a metal forming a first scan line and a metal forming a data line
  • the second voltage dividing capacitor is composed of a metal forming a first scan line and a transparent electrode.
  • all the second scan lines are electrically connected in a peripheral region of the array substrate.
  • each pixel unit is driven by a first scan line, a second scan line, a third scan line and a data line.
  • the number of data lines is reduced, thereby correspondingly reducing the number of data drivers, which is advantageous for reducing production costs.
  • each of the pixel units includes a first control circuit and a second control circuit, and the first control circuit acts on the first pixel electrode when the second scan line inputs the second scan signal, so that the first pixel electrode is in a corresponding display black screen.
  • the second control circuit acts on the second pixel electrode and the third pixel electrode when the third scan line inputs the third scan signal to change the voltage difference between the second pixel electrode and the third pixel electrode.
  • the second scan line controls the first control circuit such that the first control circuit controls the first pixel electrode to be in a voltage state corresponding to the display 2D picture, such that the first pixel electrode is in display corresponding in the 2D display mode.
  • the state of the image of the 2D picture that is, the first pixel electrode, the second pixel electrode, and the third pixel electrode are all in a state of displaying an image corresponding to the 2D picture, thereby increasing the aperture ratio
  • the third scanning line controls the second control circuit So that the second control circuit acts on the second pixel electrode and the third pixel electrode such that there is a non-zero voltage difference between the first pixel electrode, the second pixel electrode, and the third pixel electrode, thereby enabling Reducing the color difference of the large viewing angle in the 2D display mode; in the 3D display mode, the second scanning line controls the first control circuit to act on the first pixel electrode such that the first pixel electrode is in a state of displaying an image corresponding to the black image,
  • the first pixel electrode in a state in which the image corresponding to the black screen is displayed can block the erroneous left eye image and the right eye image, thereby enabling a small 3D binocular signal crosstalk
  • a third scan line controls the second control
  • FIG. 1 is a schematic diagram of a pixel structure of an array substrate in the prior art
  • FIG. 2 is an equivalent circuit diagram of the pixel structure of FIG. 1;
  • FIG. 3 is a schematic structural view of an embodiment of an array substrate of the present invention.
  • FIG. 4 is a schematic structural view of an embodiment of a pixel unit in the array substrate of FIG. 3;
  • Figure 5 is an equivalent circuit diagram of the structure of the pixel unit of Figure 4.
  • FIG. 6 is a side view showing a structure of an embodiment of a liquid crystal display panel of the present invention.
  • FIG. 7 is a schematic top plan view of an embodiment of the liquid crystal display panel of FIG. 6, wherein only the array substrate and the driver in the liquid crystal display panel are shown.
  • the array substrate includes a plurality of first scan lines 11 , a plurality of second scan lines 12 , a plurality of third scan lines 13 , and a plurality of data lines 14 .
  • the array substrate also includes a common electrode 16 for inputting a common voltage.
  • Each of the pixel units 15 corresponds to a first scan line 11, a second scan line 12, a third scan line 13, and a data line 14.
  • each pixel unit 15 includes a first pixel electrode M1, a second pixel electrode M2, and a third pixel electrode M3, and a first pixel electrode M1, a second pixel electrode M2, and a third pixel electrode, respectively.
  • the control terminal of the first switch Q1, the control terminal of the second switch Q2, and the control terminal of the third switch Q3 are electrically connected to the first scan line 11 corresponding to the pixel unit 15 to receive the first scan signal;
  • the input end of the Q1, the input end of the second switch Q2, and the input end of the third switch Q3 are electrically connected to the data line 14 corresponding to the pixel unit 15;
  • the output end of the first switch Q1 is electrically connected to the first pixel electrode M1.
  • the output of the second switch Q2 is electrically connected to the second pixel electrode M2, and the output end of the third switch Q3 is electrically connected to the third pixel electrode M3.
  • the first switch Q1, the second switch Q2, and the third switch Q3 When the first scan signal is input to the first scan line 11, the first switch Q1, the second switch Q2, and the third switch Q3 are turned on, and the data line 14 passes through the first switch Q1, the second switch Q2, and the third switch Q3, respectively.
  • the first pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 provide data signals, thereby driving the first pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 to operate.
  • the first switch Q1, the second switch Q2, and the third switch Q3 are thin film transistors, and the control end thereof corresponds to the gate of the thin film transistor, and the input end thereof corresponds to the source of the thin film transistor, and the output end thereof corresponds to It is the drain of the thin film transistor.
  • the first switch Q1, the second switch Q2, and the third switch Q3 may also be a triode, a Darlington tube, or the like, which is not limited herein.
  • the second scan lines 12 are electrically connected to each other in a peripheral region (a region other than the pixel region) of the array substrate.
  • all the second scan lines 12 may be electrically connected to each other (pixel regions) of the array substrate, or all the second scan lines 12 may be independent of each other, which is not specifically limited.
  • the principle of the display of the liquid crystal display panel is that the pixel electrode can display the corresponding image normally by causing a certain voltage difference between the pixel electrode in the array substrate and the common electrode in the color filter substrate.
  • the pixel electrode displays an image corresponding to the black screen.
  • the common voltage applied by the common electrode in the color filter substrate is the same as the common voltage applied by the common electrode in the array substrate.
  • the pixel unit further includes a first control circuit 151 and a second control circuit 152.
  • the second scan line 12 is electrically connected to the first control circuit 151 to control the first control circuit 151, and the first control circuit 151 is connected to the first pixel electrode M1 and the common electrode 16.
  • the first control circuit 151 acts on the first pixel electrode M1 when the second scan line 12 inputs the second scan signal to control the voltage difference between the first pixel electrode M1 and the common electrode 16 to be zero, such that the first pixel electrode is at Corresponds to the voltage status of the black screen.
  • the third scan line 13 is connected to the second control circuit 152 to control the second control circuit 152.
  • the second control circuit 152 acts on the second pixel electrode M2 and the third pixel electrode M3 when the third scan signal is input to the third scan line. To change the voltage difference between the second pixel electrode M2 and the third pixel electrode M3.
  • the first control circuit 151 includes a fourth switch Q4, and the fourth switch Q4 includes a control end, a first end, and a second end.
  • the control terminal of the fourth switch Q4 is electrically connected to the second scan line 12, the first end of the fourth switch Q4 is electrically connected to the first pixel electrode M1, and the second end of the fourth switch Q4 is electrically connected to the common electrode 16.
  • sexual connection When the second scan line 12 inputs the second scan signal, the fourth switch Q4 is turned on, and the fourth switch Q4 controls the voltage difference between the first pixel electrode M1 and the common electrode 16 to be zero during the time when the second scan line 12 is turned on, so that the first One pixel electrode M1 is in a voltage state corresponding to displaying a black screen.
  • the second control circuit 152 includes a fifth switch Q5, a first capacitive element C1, and a second divided capacitor C2.
  • the first voltage dividing capacitor C1 is composed of a metal forming the first scanning line 11 and a metal forming the data line 14, and the second voltage dividing capacitor C2 is composed of a metal forming the first scanning line 11 and a transparent electrode.
  • the fifth switch Q5 includes a control end, a first end, and a second end.
  • the control terminal of the fifth switch Q5 is electrically connected to the third scan line 13.
  • the first end of the fifth switch Q5 is connected to one end of the first voltage dividing capacitor C1, and the other end of the first voltage dividing capacitor C1 and the second pixel electrode are connected.
  • the second end of the fifth switch Q5 is connected to the third pixel electrode M3, one end of the second voltage dividing capacitor C2 is connected to one end of the first voltage dividing capacitor C1, and the other end of the second voltage dividing capacitor C2 is connected to the common electrode connection.
  • the fifth switch Q5 is turned on, and the second pixel electrode M2 is connected to the third pixel electrode M3 through the first voltage dividing capacitor C1 and the fifth switch Q5, in the first voltage dividing capacitor C1.
  • the voltage of the second pixel electrode M2 and the voltage of the third pixel electrode are both changed by the second voltage dividing capacitor C2 and the fifth voltage switch Q5, thereby changing the voltage between the second pixel electrode M2 and the third pixel electrode M3. difference.
  • the fourth switch Q4 and the fifth switch Q5 of the present embodiment are both thin film transistors, and the control end of the fourth switch Q4 and the control end of the fifth switch Q5 correspond to the gate of the thin film transistor, and the first end of the fourth switch Q4 and The first end of the fifth switch Q5 corresponds to the source of the thin film transistor, and the second end of the fourth switch Q4 and the second end of the fifth switch Q5 correspond to the drain of the thin film transistor.
  • the fourth switch Q4 and the fifth switch Q5 may also be transistors such as a triode or a Darlington tube, and are not limited herein.
  • the color difference at a large viewing angle in the 2D display mode and the 3D display mode can be reduced, and the aperture ratio in the 2D display mode can be improved, and the 3D binocular signal crosstalk can be reduced.
  • the common electrode 16 inputs a fixed common voltage.
  • first inputting a first scan signal to the first scan line 11 to control the first switch Q1, the second switch Q2, and The third switch Q3 is turned on, and the data line 14 inputs data signals to the first pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 through the first switch Q1, the second switch Q2, and the third switch Q3, so that the first The one pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 are in a state of displaying an image corresponding to a 2D screen.
  • the second scan line 12 inputs a fourth scan line signal of a low level (-2 ⁇ -12V) to control the fourth switch Q4 to be turned off, for example, inputting a low level scan signal of -6V, so that
  • the four switches Q4 are kept in the off state in the 2D display mode, so that the first pixel electrode M1 and the common electrode 16 are not in communication, thereby causing the first pixel electrode M1 to be in a voltage state corresponding to the display 2D picture. That is, in the 2D display mode, the three pixel electrodes M1, M2, and M3 are normally in a state of displaying an image corresponding to the 2D screen, whereby the aperture ratio in the 2D display mode can be improved.
  • the first pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 have the same voltage, and the voltage difference between the three is zero at this time.
  • the first scan line 11 stops inputting the scan signal, the three switches Q1, Q2, Q3 are turned off, and the third scan line 13 inputs the third scan signal to control the fifth switch Q5 to be turned on.
  • the fifth switch Q5 is turned on, the partial charge of the third pixel electrode M3 is transferred to the first voltage dividing capacitor C1 and the second voltage dividing capacitor C2.
  • the voltage of the third pixel electrode M3 is lowered, and the voltage of the second pixel electrode M2 is increased by the first voltage dividing capacitor C1, so that the voltages of the second pixel electrode M2 and the third pixel electrode M3 are changed and the voltages of the two are not The same is true, so that the voltage difference between the second pixel electrode M1 and the third pixel electrode M3 is changed, that is, the voltage difference between the two is no longer zero.
  • the voltage of the first pixel electrode M1 still maintains the voltage when the data signal 14 is input to the data line 14 in the previous moment, and the voltage of the second pixel electrode M2 increases, and the voltage of the third pixel electrode M3 decreases, thereby making the first
  • the voltages between the pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 are different, and the first pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 are not zero. The voltage difference.
  • the partial charge of the first voltage dividing capacitor C1 and the second voltage dividing capacitor C2 is transferred to the third pixel electrode M3 when the fifth switch Q5 is turned on, so that The voltage of the third pixel electrode M3 is increased, and the voltage of the second pixel electrode M2 is decreased by the first voltage dividing capacitor C1, so that the voltages of the second pixel electrode M2 and the third pixel electrode M3 are changed and the voltages of the two are different.
  • the voltage difference between the second pixel electrode M1 and the third pixel electrode M3 is changed, that is, the voltage difference between the two is no longer zero.
  • the voltage of the first pixel electrode M1 still maintains the voltage when the data signal 14 is input to the data line 14 at the previous moment, while the voltage of the second pixel electrode M2 decreases, and the voltage of the third pixel electrode M3 increases, thereby making the first
  • the voltages between the pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 are different, and the first pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 are not zero.
  • the voltage difference Therefore, whether the positive polarity reversal or the negative polarity reversal, the second pixel electrode M2 and the third can be made by the first voltage dividing capacitor C1 and the second voltage dividing capacitor C2 when the fifth switch Q5 is turned on.
  • the voltage difference between the pixel electrodes M3 is changed, so that the voltage difference between the three pixel electrodes M1, M2, M3 is not zero.
  • the voltages between the first pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 are all different, so that the first pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 respectively correspond to each other.
  • the deflection of the liquid crystal molecules in the liquid crystal region is also different, thereby making it possible to reduce the color difference observed in the 2D display mode when viewed at a large viewing angle, and to reduce color distortion.
  • the common electrode 16 inputs a fixed common voltage
  • the second scan line 12 inputs a high level (0v ⁇ 33v) second scan signal to control the fourth switch Q4 to be turned on, for example, inputting a high of 10V.
  • the level scan signal causes the fourth switch Q4 to remain in the on state in the 3D display mode.
  • the first scan signal is input to the first scan line 11 to control the first to third switches Q1, Q2, and Q3 to be turned on
  • the data line 14 inputs the data signal to the first pixel electrode M1 through the three switches Q1, Q2, and Q3, respectively.
  • the fourth switch Q4 since the fourth switch Q4 is in an on state, the first pixel electrode M1 and the common electrode 16 are electrically connected, and the first pixel electrode M1 and the common electrode 16 are caused by the driving mode of the positive and negative polarity inversion.
  • electrical connection occurs, charge transfer occurs between the two, and the voltage of the first pixel electrode M1 approaches the voltage of the common electrode 16.
  • the positive polarity is reversed, the voltage of the first pixel electrode M1 is greater than the common voltage of the common electrode 16, so that the partial charge of the first pixel electrode M1 is transferred to the common electrode 16, and the voltage of the first pixel electrode M1 is reduced.
  • the second pixel electrode M1 and the common electrode 16 reach a charge balance state.
  • the voltage of the common electrode 16 remains unchanged, and the charge transferred by the second pixel electrode M1 is discharged through the common electrode 16.
  • the voltage of the first pixel electrode M1 is smaller than the common voltage of the common electrode 16, so that the partial charge of the common electrode 16 is transferred to the first pixel electrode M1, and the voltage of the first pixel electrode M1 increases, and eventually increases.
  • the first pixel electrode M1 and the common electrode 16 reach a charge balance state.
  • the charge transfer speed between the first pixel electrode M1 and the common electrode 16 is controlled by controlling the current passing capability of the fourth switch Q4 at the turn-on, so that the fourth switch Q4 is turned on under the control of the fourth switch Q4.
  • the first pixel electrode M1 and the common electrode 16 are brought into charge balance, that is, the voltages of the two are the same, so that the voltage difference between the first pixel electrode M1 and the common electrode 16 is zero, so that the first pixel electrode M1 is at Corresponding to the voltage state in which the black screen is displayed, that is, the voltage of the first pixel electrode M1 is in the same state as the common voltage of the common electrode 16.
  • the first pixel electrode M1 has its voltage and the common electrode 16 under the conduction of the fourth switch Q4.
  • the voltages are the same so that the first pixel electrode M1 is in a state of displaying an image corresponding to a black screen, and the second pixel electrode M2 and the third pixel electrode M3 are normally in a state of displaying an image corresponding to the 3D screen.
  • the second pixel electrode M2 and the third pixel electrode M3 have the same voltage.
  • the first scan line 11 stops inputting the first scan signal, so that the first switch Q1, the second switch Q2, and the third switch Q3 are turned off, and the third scan line 13 inputs the third scan signal to control the conduction of the fifth switch Q5.
  • the voltage of the second pixel electrode M2 is increased (or decreased) by the action of the first voltage dividing capacitor C1, and the third pixel electrode M3 is reduced by the action of the first voltage dividing capacitor C1 and the second voltage dividing capacitor C2 (or Increasing) such that the voltages of the second pixel electrode M2 and the third pixel electrode M3 are both changed, thereby causing the voltages of the second pixel electrode M2 and the third pixel electrode M3 to be different, that is, the second pixel electrode M2 and the third pixel There is a non-zero voltage difference between the electrodes M3, so that it is possible to reduce the color difference observed in the 3D display mode when viewed at a large viewing angle, and to reduce color distortion.
  • the first pixel electrode M1, the second pixel electrode M2, and the third pixel electrode M3 are sequentially arranged in the column direction, and the adjacent two rows of pixel units 15 respectively display the left eye image and the right eye image corresponding to the 3D image.
  • the first pixel electrode M1 is in a state of displaying an image corresponding to a black screen by the action of the fourth switch Q4, and the first pixel electrode M1 in a state of displaying an image corresponding to the black screen is equivalent to a black matrix.
  • the pixel electrodes of the left eye image (the second pixel electrode and the third pixel electrode of one row of pixel units) and the pixel electrode of the right eye image are displayed in the adjacent two rows of pixel units 15 (in another row of pixel units)
  • There is a black matrix between the second pixel electrode and the third pixel electrode and the crosstalk signal of the left eye image and the right eye image is blocked by the black matrix, so that the binocular signal crosstalk in the 3D display mode can be reduced.
  • the three pixel electrodes may also be arranged in the row direction, and the adjacent two columns of pixel units respectively display the left eye image and the right eye image corresponding to the 3D picture.
  • the second control circuit may not include the second voltage dividing capacitor, that is, the first voltage dividing capacitor is not connected to the common electrode through the second voltage dividing capacitor, and the first voltage dividing capacitor is not connected to the common electrode.
  • the voltage of the third pixel electrode is reduced by the second voltage dividing capacitor, the voltage of the second pixel electrode is increased by the first voltage dividing capacitor, and the voltage reduced by the third pixel electrode is increased by the second pixel electrode.
  • the voltage is basically the same. In this way, the voltage difference between the second pixel electrode and the third pixel electrode can also be changed such that the voltages of the three pixel electrodes are different, thereby reducing the observed color difference at a large viewing angle, Better low color shift effect.
  • the array substrate of the present embodiment can improve the aperture ratio of the 2D display mode and reduce the crosstalk of the two-eye signals in the 3D display mode by the first control circuit 151 and the second control circuit 152, and can be reduced at the same time.
  • the difference in color observed at a large viewing angle in both display modes increases the wide viewing angle.
  • the present embodiment only needs one data line 14 to drive a corresponding one of the pixel units 15, which reduces the amount of data lines used, thereby reducing the number of data driving chips, for example, when the prior art requires When n data driving chips are driven, only n/2 data driving chips are used in the array substrate of the present invention.
  • the present embodiment adds a second scan line 12, the number of scan drive chips is correspondingly increased.
  • the scan drive chip is cheaper than the data drive chip, and thus the production cost can be effectively reduced.
  • all the second scan lines 12 are electrically connected in the peripheral region of the array substrate, so that the second scan line 12 can be scanned only by one scan driving chip, thereby further reducing the cost. .
  • the first control circuit may not be connected to the common electrode, but may be connected to a reference voltage source having a constant voltage output, and the constant voltage output by the reference voltage source and the common voltage of the common electrode. the same.
  • the first end of the fourth switch is connected to the first pixel electrode, the second end is connected to the reference voltage source, and when the second scan line controls the fourth switch to be turned on, a charge transfer occurs between the first pixel electrode and the reference voltage source.
  • the voltage of the first pixel electrode is the same as the voltage of the reference voltage source, so that the voltage difference between the first pixel electrode and the common electrode is zero, so that the first pixel electrode generates a voltage signal corresponding to displaying the black image.
  • the first control circuit may also control the data signal of the first pixel electrode to be completely released when the second scan signal is input to the second scan line, so that there is no data signal available for display on the first pixel electrode, and further The first pixel electrode is caused to be in a state of displaying an image corresponding to a black screen.
  • the first control circuit may be a switching element, such that the first pixel electrode is grounded through the switching element, and the first control circuit electrically connects the first pixel electrode and the ground end when the second scan signal is input to the second scan line, thereby The first pixel electrode is caused to discharge through the ground end, thereby causing the first pixel electrode to be in a state of displaying an image corresponding to the black screen.
  • the second control circuit changes the voltages of the second pixel electrode and the third pixel electrode by using two voltage dividing capacitors, and in other embodiments, it may be realized by two voltage dividing resistors. That is, the second control circuit includes a controlled switch and two voltage dividing resistors connected in series. At this time, the second pixel electrode is connected to one end of the resistor string, the other end of the resistor string is grounded, and one end of the controlled switch is connected to the two. Between the resistors, the other end of the controlled switch is connected to the third pixel electrode.
  • the voltage of the second pixel electrode is reduced by the voltage division of the two voltage dividing resistors, and the third pixel electrode is divided by a voltage dividing resistor, and the second pixel is lowered.
  • the voltage of the electrode is reduced to a greater extent than the voltage of the third pixel electrode, so that the voltages of the second pixel electrode and the third pixel electrode are both reduced by the two voltage dividing resistors, and the The voltages of the two pixel electrodes and the third pixel electrode are also different, so that the voltages between the three pixel electrodes can also be made different, thereby achieving the effect of low color shift.
  • the liquid crystal display panel includes an array substrate 601 , a color filter substrate 602 , and a liquid crystal layer 603 between the array substrate 601 and the color filter substrate 602 .
  • the array substrate 601 is the array substrate shown in FIG. 3.
  • the liquid crystal display panel of the present embodiment further includes a plurality of first scan drivers 604, a second scan driver 605, a plurality of third scan drivers 606, and a plurality of data drivers 607.
  • the array substrate 601 may be the array substrate of any of the above embodiments.
  • FIG. 7 is a schematic top plan view of the liquid crystal display panel of FIG. 6.
  • each of the first scan drivers 604 is connected to a first scan line 11 to input a first scan signal to the first scan line 11;
  • the second scan driver 605 is connected to all of the second scan lines 12 for all second scans.
  • the line inputs a second scan signal and a fourth scan signal;
  • each third scan driver 606 is coupled to a third scan line 13 to input a third scan signal to the third scan line 13;
  • each data driver 606 and one data line 14 Connect to input a data signal to the data line.
  • the liquid crystal display panel display is driven by the first scan driver 604, the second scan driver 605, the third scan driver 606, and the data driver 607.
  • the first scan driver 604, the second scan driver 605, and the third scan driver 606 can be implemented by using a scan driver chip.
  • the scan driver circuit can be implemented by a discrete component.
  • the data driver 607 can be implemented by using a data driver chip. It can also be realized by a data driving circuit composed of discrete components.
  • the liquid crystal display panel of the present embodiment can not only improve the aperture ratio of the 2D display mode, but also reduce the binocular signal crosstalk in the 3D display mode, and can reduce the observation at a large viewing angle in the two display modes. Color differences increase the viewing angle and reduce the number of data drivers, effectively reducing costs.
  • all the second scan lines may also be independent of each other.
  • the liquid crystal display panel may also include a plurality of second scan drivers, and each scan driver is connected to a second scan line.

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Abstract

一种阵列基板，其中，每个像素单元（15）包括第一像素电极（Ml）、第二像素电极（M2）以及第三像素电极（M3），并且每个像素单元（15）包括第一控制电路（151）和第二控制电路（152），第一控制电路（151）作用于第一像素电极（Ml），以使得第一像素电极（Ml）在3D显示模式下处于显示对应黑画面的图像的状态，第二控制电路（152）作用于第二像素电极（M2）和第三像素电极（M3），以改变第二像素电极（M2）和第三像素电极（M3）之间的电压差。从而，能够减小大视角下的颜色差异，提高2D显示模式下的开口，降低3D双眼信号串扰，同时能减少数据驱动器（607）的数量，有利于降低成本。还提供了一种液晶显示面板。

Description

一种阵列基板及液晶显示面板
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种阵列基板及液晶显示面板。
【背景技术】
VA（Vertical Alignment，垂直配向）型液晶显示面板具有响应速度快、对比度高等优点，是目前液晶显示面板的主流发展方向。但是，在不同的视角下，液晶分子的排列指向并不相同，使得液晶分子的有效折射率也不相同，由此会引起透射光强的变化，具体表现为斜视角下透光能力降低，斜视角方向和正视角方向所表现的颜色不一致，发生色差，因此在大视角下会观察到颜色失真。为了改善大视角下的颜色失真，在像素设计中，将一个像素分为主像素区和子像素区，每个像素区分为4个domain（畴，指液晶分子的指向矢基本相同的微小区域），由此每个像素分为8个domain，通过控制主像素区和子像素区的电压不相同，以使得两个像素区中的液晶分子排列不相同，进而改善大视角下的颜色失真，以达到LCS（Low Color Shift，低色偏）的效果。
在3D FPR（Film-type Patterned Retarder，偏光式）立体显示技术中，相邻两行像素分别对应观看者的左眼和右眼，以分别产生对应左眼的左眼图像和对应右眼的右眼图像，观看者的左右眼分别接收到相应的左眼图像和右眼图像后，通过大脑对左右眼图像进行合成以使得观看者感受到立体显示效果。而左眼图像和右眼图像容易发生串扰，会导致观看者看到重叠的影像，影响了观看效果。为了避免双眼图像信号发生串扰，在相邻两行像素之间采用BM（Black Matrix，黑色矩阵）遮蔽的方式来阻挡发生串扰的信号，以降低双眼信号串扰。然而，采用此种方式会导致2D显示模式下的开口率大大降低，降低了2D显示模式下的显示亮度。
上述LCS设计中，将一个像素分为主像素区和次像素区的技术方案能够同时解决2D显示模式下的开口率和3D显示模式下的双眼信号串扰问题，即在2D显示模式下控制主像素区和次像素区均正常显示2D图像，而在3D显示模式下使主像素区显示黑画面以等效于BM，用于降低双眼信号串扰，使次像素区正常显示3D图像。然而，在3D显示模式下，由于主像素区显示黑画面，即在3D显示模式下只有一个次像素区正常显示3D图像，而无法达到LCS效果，在大视角下仍然会观察到颜色失真。
为了解决上述问题，参阅图1和图2，现有技术中，将一个像素划分为三个子像素区A、B、C，每个子像素区分为4个domain。每个像素采用两条数据线和两条扫描线进行驱动。在2D显示模式下，通过GateN_1同时控制薄膜晶体管1、2、3导通，DataN_1对子像素区A输入相应的数据信号，DataN_2对子像素区B和子像素区C输入相应的数据信号，使得三个子像素区A、B、C正常显示2D图像，由此能够提高2D显示模式下的开口，而通过DataN_1和DataN_2能够分别对子像素区A和子像素区B、子像素区C输入不同的数据信号以使得子像素区A与子像素区B、子像素区C的电压不相同，之后通过GateN_2控制薄膜晶体管4导通，在电容C1的作用下使得子像素区B和子像素区C的电压不相同，由此使得三个子像素区A、B、C的电压各不相同，进而达到2D显示模式下的LCS效果。在3D显示模式下，通过GateN_1同时控制薄膜晶体管1、2、3导通，DataN_1对子像素区A输入相应的数据信号以使得子像素区A显示黑画面，DataN_2对子像素区B和子像素区C输入相应的数据信号以使得子像素区B和子像素区C显示3D图像，从而在相邻两行像素中，一行像素中显示左眼图像的子像素区B和子像素区C与另一行像素中显示右眼图像的子像素区B和子像素区C之间具有显示黑画面的子像素区A，显示黑画面的子像素区A等效于BM，从而能够降低3D双眼信号串扰。之后，通过GateN_2控制薄膜晶体管4导通，在电容5的作用下使得子像素区B和子像素区C的电压不相同，由此实现3D显示模式下的LCS效果。
通过上述技术方案，能够解决2D显示模式下的开口率和3D显示模式下的双眼信号串扰问题，同时也能够在2D显示模式下和3D显示模式下实现LCS效果。然而，上述技术方案中，每个像素需要两条数据线驱动，相应地会增加数据驱动器的数量，不利于成本降低。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及液晶显示面板，能够减小大视角下的颜色差异，提高2D显示模式下的开口，降低3D双眼信号串扰，同时能够减少数据驱动器的数量，有利于降低成本。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包括多条第一扫描线、多条第二扫描线、多条第三扫描线、多条数据线、多个行列排列的像素单元以及用于输入公共电压的公共电极，每个像素单元对应一条第一扫描线、一条第二扫描线、一条第三扫描线以及一条数据线；所有第二扫描线在阵列基板的外围区域电性连接，每个像素单元包括第一像素电极、第二像素电极以及第三像素电极，以及分别作用于第一像素电极、第二像素电极和第三像素电极的第一开关、第二开关以及第三开关，每个像素单元还包括第一控制电路和第二控制电路，对应本像素单元的数据线分别通过第一开关、第二开关以及第三开关与第一像素电极、第二像素电极以及第三像素电极连接，以提供数据信号，第一开关、第二开关以及第三开关在第一扫描线输入第一扫描信号时导通；第一控制电路与公共电极连接，第一控制电路在第二扫描线输入第二扫描信号时控制第一像素电极和公共电极之间的电压差为零，以使得第一像素电极处于显示对应黑画面的图像的状态，第二控制电路在第三扫描线输入第三扫描信号时作用于第二像素电极和第三像素电极，以改变第二像素电极和第三像素电极之间的电压差；其中，在2D显示模式下，第一像素电极、第二像素电极以及第三像素电极在对应本像素单元的第一扫描线和数据线的作用下处于显示对应2D画面的图像的状态，第一控制电路在第二扫描线输入第四扫描信号时控制第一像素电极处于显示对应2D画面的图像的状态，随后对应本像素单元第三扫描线输入第三扫描信号控制第二控制电路作用于第二像素电极和第三像素电极，第二像素电极和第三像素电极之间的电压差在第二控制电路的作用下改变，以使得第一像素电极、第二像素电极以及第三像素电极两两之间存在不为零的电压差；在3D显示模式下，第二扫描线输入第二扫描信号以控制第一控制电路作用于第一像素电极，第二像素电极和第三像素电极在对应本像素单元的第一扫描线和数据线的作用下处于显示对应3D画面的图像的状态，第一像素电极在第一控制电路的作用下处于显示对应黑画面的图像的状态，随后第三扫描线输入第三扫描信号以控制第二控制电路作用于第二像素电极和第三像素电极，第二像素电极和第三像素电极之间的电压差在第二控制电路的作用下改变，以使得第二像素电极和第三像素电极之间存在不为零的电压差。
其中，第一控制电路包括第四开关，第四开关包括控制端、第一端以及第二端，第四开关的控制端连接第二扫描线，第四开关的第一端连接第一像素电极，第四开关的第二端连接公共电极，在第二扫描线输入第二扫描信号时第四开关导通，以使得第一像素电极和公共电极电性连接，第四开关在其导通时间内控制第一像素电极和公共电极之间的电压差为零。
其中，第二控制电路包括第五开关、第一分压电容和第二分压电容，第五开关包括控制端、第一端以及第二端，第五开关的控制端连接第三扫描线，第五开关的第一端与第一分压电容的一端连接，第一分压电容的另一端与第二像素电极连接，第五开关的第二端与第三像素电极连接，第二分压电容的一端与第一分压电容的一端连接，第二分压电容的另一端与公共电极连接，在第三扫描线输入第三扫描信号时第五开关导通，以使得第二像素电极和第三像素电极之间的电压差通过第一分压电容和第二分压电容改变。
其中，第一分压电容由形成第一扫描线的金属和形成数据线的金属所构成，第二分压电容由形成第一扫描线的金属和透明电极所构成。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括多条第一扫描线、多条第二扫描线、多条第三扫描线、多条数据线、多个行列排列的像素单元以及用于输入公共电压的公共电极，每个像素单元对应一条第一扫描线、一条第二扫描线、一条第三扫描线以及一条数据线；每个像素单元包括第一像素电极、第二像素电极以及第三像素电极，以及分别作用于第一像素电极、第二像素电极和第三像素电极的第一开关、第二开关以及第三开关，每个像素单元还包括第一控制电路和第二控制电路，对应本像素单元的数据线分别通过第一开关、第二开关以及第三开关与第一像素电极、第二像素电极以及第三像素电极连接，以提供数据信号，第一开关、第二开关以及第三开关在第一扫描线输入第一扫描信号时导通；第一控制电路在第二扫描线输入第二扫描信号时作用于第一像素电极，以使得第一像素电极处于显示对应黑画面的图像的状态，第二控制电路在第三扫描线输入第三扫描信号时作用于第二像素电极和第三像素电极，以改变第二像素电极和第三像素电极之间的电压差；其中，在2D显示模式下，第一像素电极、第二像素电极以及第三像素电极在对应本像素单元的第一扫描线和数据线的作用下处于显示对应2D画面的图像的状态，第一控制电路在第二扫描线输入第四扫描信号时控制第一像素电极处于显示对应2D画面的图像的状态，随后第三扫描线输入第三扫描信号控制第二控制电路作用于第二像素电极和第三像素电极，第二像素电极和第三像素电极之间的电压差在第二控制电路的作用下改变，以使得第一像素电极、第二像素电极以及第三像素电极两两之间存在不为零的电压差；在3D显示模式下，第二扫描线输入第二扫描信号以控制第一控制电路作用于第一像素电极，第二像素电极和第三像素电极在对应本像素单元的第一扫描线和数据线的作用下处于显示对应3D画面的图像的状态，第一像素电极在第一控制电路的作用下处于显示对应黑画面的图像的状态，随后第三扫描线输入第三扫描信号以控制第二控制电路作用于第二像素电极和第三像素电极，第二像素电极和第三像素电极之间的电压差在第二控制电路的作用下改变，以使得第二像素电极和第三像素电极之间存在不为零的电压差。
其中，第一控制电路与公共电极连接，第一控制电路在第二扫描线输入第二扫描信号时控制第一像素电极和公共电极之间的电压差为零，以使得第一像素电极处于显示对应黑画面的图像的状态。
其中，第一控制电路包括第四开关，第四开关包括控制端、第一端以及第二端，第四开关的控制端连接第二扫描线，第四开关的第一端连接第一像素电极，第四开关的第二端连接公共电极，在第二扫描线输入第二扫描信号时第四开关导通，以使得第一像素电极和公共电极电性连接，第四开关在其导通时间内控制第一像素电极和公共电极之间的电压差为零。
其中，第二控制电路包括第五开关、第一分压电容和第二分压电容，第五开关包括控制端、第一端以及第二端，第五开关的控制端连接第三扫描线，第五开关的第一端与第一分压电容的一端连接，第一分压电容的另一端与第二像素电极连接，第五开关的第二端与第三像素电极连接，第二分压电容的一端与第一分压电容的一端连接，第二分压电容的另一端与公共电极连接，在第三扫描线输入第三扫描信号时第五开关导通，以使得第二像素电极和第三像素电极之间的电压差通过第一分压电容和第二分压电容改变。
其中，第一分压电容由形成第一扫描线的金属和形成数据线的金属所构成，第二分压电容由形成第一扫描线的金属和透明电极所构成。
其中，所有第二扫描线在阵列基板的外围区域电性连接。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板，包括多个第一扫描驱动器、至少一个第二扫描驱动器、多个第三扫描驱动器、多个数据驱动器、阵列基板、彩色滤光基板以及位于阵列基板和彩色滤光基板之间的液晶层；阵列基板包括多条第一扫描线、多条第二扫描线、多条第三扫描线、多条数据线、多个行列排列的像素单元以及用于输入公共电压的公共电极，每个像素单元对应一条第一扫描线、一条第二扫描线、一条第三扫描线以及一条数据线；每个第一扫描驱动器与一条第一扫描线连接以对第一扫描线输入第一扫描信号，至少一个第二扫描驱动器与第二扫描线连接以对第二扫描线输入第二扫描信号和第四扫描信号，每个第三扫描驱动器与一条第三扫描线连接以对第三扫描线输入第三扫描信号，每个数据驱动器与一条数据线连接以对数据线输入数据信号；每个像素单元包括第一像素电极、第二像素电极以及第三像素电极，以及分别作用于第一像素电极、第二像素电极和第三像素电极的第一开关、第二开关以及第三开关，每个像素单元还包括第一控制电路和第二控制电路，对应本像素单元的数据线分别通过第一开关、第二开关以及第三开关与第一像素电极、第二像素电极以及第三像素电极连接，以提供数据信号，第一开关、第二开关以及第三开关在第一扫描线输入第一扫描信号时导通；第一控制电路在第二扫描线输入第二扫描信号时作用于第一像素电极，以使得第一像素电极处于显示对应黑画面的图像的状态，第二控制电路在第三扫描线输入第三扫描信号时作用于第二像素电极和第三像素电极，以改变第二像素电极和第三像素电极之间的电压差；其中，在2D显示模式下，第一像素电极、第二像素电极以及第三像素电极在对应本像素单元的第一扫描线和数据线的作用下处于显示对应2D画面的图像的状态，第一控制电路在第二扫描线输入第四扫描信号时控制第一像素电极处于显示对应2D画面的图像的状态，随后第三扫描线输入第三扫描信号控制第二控制电路作用于第二像素电极和第三像素电极，第二像素电极和第三像素电极之间的电压差在第二控制电路的作用下改变，以使得第一像素电极、第二像素电极以及第三像素电极三者之间存在不为零的电压差；在3D显示模式下，第二扫描线输入第二扫描信号以控制第一控制电路作用于第一像素电极，第二像素电极和第三像素电极在对应本像素单元的第一扫描线和数据线的作用下处于显示对应3D画面的图像的状态，第一像素电极在第一控制电路的作用下处于显示对应黑画面的图像的状态，随后第三扫描线输入第三扫描信号以控制第二控制电路作用于第二像素电极和第三像素电极，第二像素电极和第三像素电极之间的电压差在第二控制电路的作用下改变，以使得第二像素电极和第三像素电极之间存在不为零的电压差。
其中，第一控制电路与公共电极连接，第一控制电路在第二扫描线输入第二扫描信号时控制第一像素电极和公共电极之间的电压差为零，以使得第一像素电极处于显示对应黑画面的图像的状态。
其中，第一控制电路包括第四开关，第四开关包括控制端、第一端以及第二端，第四开关的控制端连接第二扫描线，第四开关的第一端连接第一像素电极，第四开关的第二端连接公共电极，在第二扫描线输入第二扫描信号时第四开关导通，以使得第一像素电极和公共电极电性连接，第四开关在其导通时间内控制第一像素电极和公共电极之间的电压差为零。
其中，第二控制电路包括第五开关、第一分压电容和第二分压电容，第五开关包括控制端、第一端以及第二端，第五开关的控制端连接第三扫描线，第五开关的第一端与第一分压电容的一端连接，第一分压电容的另一端与第二像素电极连接，第五开关的第二端与第三像素电极连接，第二分压电容的一端与第一分压电容的一端连接，第二分压电容的另一端与公共电极连接，在第三扫描线输入第三扫描信号时第五开关导通，以使得第二像素电极和第三像素电极之间的电压差通过第一分压电容和第二分压电容改变。
其中，第一分压电容由形成第一扫描线的金属和形成数据线的金属所构成，第二分压电容由形成第一扫描线的金属和透明电极所构成。
其中，所有第二扫描线在阵列基板的外围区域电性连接。
本发明的有益效果是：区别于现有技术的情况，本发明的阵列基板，每个像素单元使用一条第一扫描线、一条第二扫描线、一条第三扫描线以及一条数据线驱动，相较于现有技术减少了数据线的数量，进而相应减少数据驱动器的数量，有利于降低生产成本。此外，每个像素单元包括第一控制电路和第二控制电路，第一控制电路在第二扫描线输入第二扫描信号时作用于第一像素电极，以使得第一像素电极处于对应显示黑画面的电压状态，第二控制电路在第三扫描线输入第三扫描信号时作用于第二像素电极和第三像素电极，以改变第二像素电极和第三像素电极之间的电压差。在2D显示模式下，第二扫描线控制第一控制电路，以使得第一控制电路控制第一像素电极处于对应显示2D画面的电压状态，从而使得第一像素电极在2D显示模式下处于显示对应2D画面的图像的状态，即第一像素电极、第二像素电极和第三像素电极均处于显示对应2D画面的图像的状态，由此提高了开口率，而第三扫描线控制第二控制电路，以使得第二控制电路作用于第二像素电极和第三像素电极，以使得第一像素电极、第二像素电极以及第三像素电极两两之间存在不为零的电压差，由此能够减小2D显示模式下大视角的颜色差异；在3D显示模式下，第二扫描线控制第一控制电路作用于第一像素电极，以使得第一像素电极处于显示对应黑画面的图像的状态，通过处于显示对应黑画面的图像的状态的第一像素电极能够阻挡错误的左眼图像和右眼图像，由此能够减小3D双眼信号串扰，而第三扫描线控制第二控制电路作用于第二像素电极和第三像素电极，以改变第二像素电极和第三像素电极之间的电压差，以使得第二像素电极与第三像素电极之间具有不为零的电压差，由此能够减小3D显示模式下大视角的颜色差异。
【附图说明】
图1是现有技术中一种阵列基板的像素结构示意图；
图2是图1中的像素结构的等效电路图；
图3是本发明阵列基板一实施方式的结构示意图；
图4是图3的阵列基板中，像素单元一实施方式的结构示意图；
图5是图4的像素单元的结构的等效电路图；
图6是本发明液晶显示面板一实施方式的侧视结构示意图；
图7是图6的液晶显示面板一实施方式的俯视结构示意图，其中，图中只示出液晶显示面板中的阵列基板与驱动器。
【具体实施方式】
下面将结合附图和实施方式对本发明进行详细说明。
参阅图3-图5，本发明阵列基板的一实施方式中，阵列基板包括多条第一扫描线11、多条第二扫描线12、多条第三扫描线13、多条数据线14以及多个行列排列的像素单元15。阵列基板还包括用于输入公共电压的公共电极16。每个像素单元15对应一条第一扫描线11、一条第二扫描线12、一条第三扫描线13以及数据线14。
其中，参阅图5，每个像素单元15包括第一像素电极M1、第二像素电极M2以及第三像素电极M3，以及分别作用于第一像素电极M1、第二像素电极M2以及第三像素电极M3的第一开关Q1、第二开关Q2以及第三开关Q3。第一开关Q1的控制端、第二开关Q2的控制端以及第三开关Q3的控制端均与对应本像素单元15的第一扫描线11电性连接，以接收第一扫描信号；第一开关Q1的输入端、第二开关Q2的输入端以及第三开关Q3的输入端均与对应本像素单元15的数据线14电性连接；第一开关Q1的输出端与第一像素电极M1电性连接，第二开关Q2的输出端与第二像素电极M2电性连接，第三开关Q3的输出端与第三像素电极M3电性连接。在第一扫描线11输入第一扫描信号时，第一开关Q1、第二开关Q2以及第三开关Q3导通，数据线14分别通过第一开关Q1、第二开关Q2以及第三开关Q3对第一像素电极M1、第二像素电极M2以及第三像素电极M3提供数据信号，从而驱动第一像素电极M1、第二像素电极M2以及第三像素电极M3工作。本实施方式中，第一开关Q1、第二开关Q2和第三开关Q3均为薄膜晶体管，其控制端对应为薄膜晶体管的栅极，其输入端对应为薄膜晶体管的源极，其输出端对应为薄膜晶体管的漏极。当然，在其他实施方式中，第一开关Q1、第二开关Q2和第三开关Q3也可以是三极管、达林顿管等，此处不进行限定。
其中，所有第二扫描线12在阵列基板的外围区域（像素区域之外的区域）电性连接。当然，在其他实施方式中，所有第二扫描线12也可以在阵列基板的内部区域（像素区域）电性连接，或者，所有第二扫描线12也可以是相互独立，对此不作具体限定。
在液晶显示技术中，液晶显示面板实现显示的原理是通过使阵列基板中的像素电极和彩色滤光基板中的公共电极之间存在一定的电压差，从而使像素电极能够正常显示相应的图像，当阵列基板中的像素电极和彩色滤光基板中的公共电极之间的电压差为零时，像素电极显示对应黑画面的图像。而彩色滤光基板中的公共电极所施加的公共电压与阵列基板中的公共电极所施加的公共电压相同。
本实施方式中，像素单元还包括第一控制电路151和第二控制电路152。第二扫描线12与第一控制电路151电性连接以控制第一控制电路151，第一控制电路151与第一像素电极M1和公共电极16连接。第一控制电路151在第二扫描线12输入第二扫描信号时作用于第一像素电极M1，以控制第一像素电极M1和公共电极16之间的电压差为零，使得第一像素电极处于对应显示黑画面的电压状态。第三扫描线13与第二控制电路152连接以控制第二控制电路152，第二控制电路152在第三扫描线输入第三扫描信号时作用于第二像素电极M2和第三像素电极M3，以改变第二像素电极M2和第三像素电极M3之间的电压差。
具体地，第一控制电路151包括第四开关Q4，第四开关Q4包括控制端、第一端和第二端。其中，第四开关Q4的控制端与第二扫描线12电性连接，第四开关Q4的第一端与第一像素电极M1电性连接，第四开关Q4的第二端与公共电极16电性连接。第二扫描线12输入第二扫描信号时第四开关Q4导通，第四开关Q4在其导通的时间内控制第一像素电极M1和公共电极16之间的电压差为零，以使得第一像素电极M1处于对应显示黑画面的电压状态。第二控制电路152包括第五开关Q5、第一电容元件C1以及第二分压电容C2。其中，第一分压电容C1由形成第一扫描线11的金属和形成数据线14的金属所构成，第二分压电容C2由形成第一扫描线11的金属和透明电极所构成。第五开关Q5包括控制端、第一端和第二端。第五开关Q5的控制端与第三扫描线13电性连接，第五开关Q5的第一端与第一分压电容C1的一端连接，第一分压电容C1的另一端与第二像素电极M2连接，第五开关Q5的第二端与第三像素电极M3连接，第二分压电容C2的一端与第一分压电容C1的一端连接，第二分压电容C2的另一端与公共电极连接。第三扫描线13输入第三扫描信号时第五开关Q5导通，第二像素电极M2通过第一分压电容C1和第五开关Q5与第三像素电极M3连接，在第一分压电容C1、第二分压电容C2以及第五开关Q5的作用下第二像素电极M2的电压和第三像素电极的电压均发生改变，从而改变第二像素电极M2和第三像素电极M3之间的电压差。本实施方式的第四开关Q4和第五开关Q5均为薄膜晶体管，第四开关Q4的控制端和第五开关Q5的控制端对应为薄膜晶体管的栅极，第四开关Q4的第一端和第五开关Q5的第一端对应为薄膜晶体管的源极，第四开关Q4的第二端和第五开关Q5的第二端对应为薄膜晶体管的漏极。
在其他实施方式中，第四开关Q4和第五开关Q5也可以是三极管、达林顿管等晶体管，此处不进行限制。
通过本实施方式的阵列基板，能够减小2D显示模式和3D显示模式下大视角下的颜色差异，并能够提高2D显示模式下的开口率，降低3D双眼信号串扰。
在2D显示模式下，公共电极16输入固定不变的公共电压，对一行像素单元15进行扫描时，首先对第一扫描线11输入第一扫描信号以控制第一开关Q1、第二开关Q2以及第三开关Q3导通，数据线14通过第一开关Q1、第二开关Q2以及第三开关Q3对第一像素电极M1、第二像素电极M2以及第三像素电极M3输入数据信号，以使得第一像素电极M1、第二像素电极M2以及第三像素电极M3处于显示对应2D画面的图像的状态。在此显示模式下，第二扫描线12输入低电平（-2~-12V）的第四扫描线信号以控制第四开关Q4断开，例如输入-6V的低电平扫描信号，使得第四开关Q4在2D显示模式下保持断开的状态，从而使得第一像素电极M1与公共电极16不连通，进而使得第一像素电极M1处于对应显示2D画面的电压状态。即在2D显示模式下，三个像素电极M1、M2、M3均正常处于显示对应2D画面的图像的状态，由此能够提高2D显示模式下的开口率。
此时，第一像素电极M1、第二像素电极M2以及第三像素电极M3具有相同的电压，此时三者之间的电压差为零。随后，第一扫描线11停止输入扫描信号，三个开关Q1、Q2、Q3断开，第三扫描线13输入第三扫描信号以控制第五开关Q5导通。在正极性（即数据信号大于公共电压）反转驱动期间，在第五开关Q5导通时使得第三像素电极M3的部分电荷转移至第一分压电容C1和第二分压电容C2中，使得第三像素电极M3的电压降低，并且第二像素电极M2的电压通过第一分压电容C1而增加，从而使得第二像素电极M2和第三像素电极M3的电压发生改变并且两者电压不相同，从而使得第二像素电极M1和第三像素电极M3之间的电压差发生改变，即两者电压差不再为零。此种情况下，第一像素电极M1的电压仍然维持前一刻数据线14输入数据信号时的电压，而第二像素电极M2的电压增加，第三像素电极M3的电压减小，从而使得第一像素电极M1、第二像素电极M2以及第三像素电极M3两两之间的电压均不相同，第一像素电极M1、第二像素电极M2和第三像素电极M3两两之间存在不为零的电压差。在负极性（数据信号小于公共电压）反转驱动期间，在第五开关Q5导通时第一分压电容C1和第二分压电容C2的部分电荷会转移至第三像素电极M3中，使得第三像素电极M3的电压增加，并且第二像素电极M2的电压通过第一分压电容C1减小，从而使得第二像素电极M2和第三像素电极M3的电压发生改变并且两者电压不相同，从而使得第二像素电极M1和第三像素电极M3之间的电压差发生改变，即两者电压差不再为零。此种情况下，第一像素电极M1的电压仍然维持前一刻数据线14输入数据信号时的电压，而第二像素电极M2的电压减小，第三像素电极M3的电压增加，从而使得第一像素电极M1、第二像素电极M2以及第三像素电极M3两两之间的电压均不相同，第一像素电极M1、第二像素电极M2和第三像素电极M3两两之间存在不为零的电压差。因此，不管是正极性反转还是负极性反转，在第五开关Q5导通时在第一分压电容C1和第二分压电容C2的作用下都能够使得第二像素电极M2和第三像素电极M3之间的电压差发生改变，进而使得三个像素电极M1、M2、M3之间的电压差不为零。而第一像素电极M1、第二像素电极M2以及第三像素电极M3三者之间的电压均不相同，从而使得第一像素电极M1、第二像素电极M2和第三像素电极M3分别对应的液晶区域中液晶分子的偏转也不相同，由此能够减小2D显示模式下在大视角观看时所观察到的颜色差异，减小色彩失真。
在3D显示模式下，公共电极16输入固定不变的公共电压，第二扫描线12输入高电平（0v~33v）的第二扫描信号以控制第四开关Q4导通，例如输入10V的高电平扫描信号，使得第四开关Q4在3D显示模式下保持导通的状态。对第一扫描线11输入第一扫描信号以控制第一至第三开关Q1、Q2、Q3导通，数据线14分别通过三个开关Q1、Q2、Q3输入数据信号至第一像素电极M1、第二像素电极M2以及第三像素电极M3中。
此时由于第四开关Q4处于导通状态，从而使得第一像素电极M1和公共电极16电性连接，而由于正负极性反转的驱动方式，使得第一像素电极M1和公共电极16在电性连接时两者之间发生电荷转移，第一像素电极M1的电压向公共电极16的电压靠拢。具体而言，当正极性反转时，第一像素电极M1的电压大于公共电极16的公共电压，使得第一像素电极M1的部分电荷转移至公共电极16中，第一像素电极M1的电压减小，并最终减小至与公共电极16相同的电压，第二像素电极M1和公共电极16达到电荷平衡状态。公共电极16的电压仍然保持不变，第二像素电极M1所转移的电荷通过公共电极16释放。当负极性反转时，第一像素电极M1的电压小于公共电极16的公共电压，使得公共电极16的部分电荷转移至第一像素电极M1中，第一像素电极M1的电压增加，并最终增加至与公共电极16相同的电压，第一像素电极M1和公共电极16达到电荷平衡状态。通过控制第四开关Q4在导通时的电流通过能力来控制第一像素电极M1和公共电极16之间的电荷转移速度，从而在第四开关Q4的控制作用下，在第四开关Q4导通的时间内使第一像素电极M1和公共电极16达到电荷平衡，即两者电压相同，从而使得第一像素电极M1和公共电极16之间的电压差为零，进而使得第一像素电极M1处于对应显示黑画面的电压状态，即第一像素电极M1的电压处于与公共电极16的公共电压相同的状态。因此，在数据线14输入数据信号至第一像素电极M1、第二像素电极M2以及第三像素电极M3时，第一像素电极M1在第四开关Q4的导通作用下其电压与公共电极16的电压相同而使得第一像素电极M1处于显示对应黑画面的图像的状态，第二像素电极M2和第三像素电极M3则正常处于显示对应3D画面的图像的状态。此时第二像素电极M2和第三像素电极M3具有相同的电压。
随后，第一扫描线11停止输入第一扫描信号，使得第一开关Q1、第二开关Q2以及第三开关Q3断开，第三扫描线13输入第三扫描信号以控制第五开关Q5的导通，第二像素电极M2的电压通过第一分压电容C1的作用增加（或减小），第三像素电极M3通过第一分压电容C1和第二分压电容C2的作用减小（或增加），从而使得第二像素电极M2和第三像素电极M3的电压均发生改变，进而使得第二像素电极M2和第三像素电极M3的电压不相同，即第二像素电极M2和第三像素电极M3之间存在不为零的电压差，从而能够减小3D显示模式下在大视角观看时所观察到的颜色差异，减小色彩失真。具体的原理过程可参考上述2D显示模式的过程，此处不进行一一赘述。
此外，本实施方式中，第一像素电极M1、第二像素电极M2以及第三像素电极M3沿列方向依次排列，相邻两行像素单元15分别显示对应3D画面的左眼图像和右眼图像。在3D显示模式下，通过第四开关Q4的作用使得第一像素电极M1处于显示对应黑画面的图像的状态，该处于显示对应黑画面的图像的状态的第一像素电极M1等效于黑矩阵，从而使得相邻两行像素单元15中，显示左眼图像的像素电极（一行像素单元中的第二像素电极和第三像素电极）和显示右眼图像的像素电极（另一行像素单元中的第二像素电极和第三像素电极）之间存在一黑矩阵，通过该黑矩阵阻挡左眼图像和右眼图像的串扰信号，从而能够降低3D显示模式下的双眼信号串扰。
当然，在备选实施方式中，三个像素电极也可以沿行方向排列，此时相邻两列像素单元分别显示对应3D画面的左眼图像和右眼图像。通过处于显示对应黑画面的图像的状态的第一像素电极，能够减少3D显示模式下的双眼信号串扰。第二控制电路也可以不包括第二分压电容，即第一分压电容不通过第二分压电容与公共电极连接，并且第一分压电容也不与公共电极连接，此时当第五开关导通时，第三像素电极的电压通过第二分压电容减小，第二像素电极的电压通过第一分压电容增大，第三像素电极所减少的电压与第二像素电极所增加的电压基本相同。通过这种方式，同样能够改变第二像素电极和第三像素电极之间的电压差，以使得三个像素电极的电压不相同，由此减小大视角下的所观察到的颜色差异，获得更好的低色偏效果。
通过上述方式，本实施方式的阵列基板，在第一控制电路151和第二控制电路152的作用下，能够提高2D显示模式的开口率，减少3D显示模式下的双眼信号串扰，同时能够减小两种显示模式下在大视角所观察的颜色差异，增大广视角。并且，与现有技术相比，本实施方式只需一条数据线14驱动相应的一个像素单元15，减少了数据线的使用量，由此减少了数据驱动芯片的数量，例如当现有技术需要n个数据驱动芯片驱动时，采用本发明的阵列基板则只需使用n/2个数据驱动芯片。虽然本实施方式增加了一条第二扫描线12，相应也会增加扫描驱动芯片的数量，然而扫描驱动芯片与数据驱动芯片相比更为便宜，因此也能够有效降低生产成本。进一步地，本实施方式的阵列基板，所有的第二扫描线12在阵列基板的外围区域电性连接，由此只需一个扫描驱动芯片即可对第二扫描线12进行扫描，进一步降低了成本。
另外，在备选实施方式中，第一控制电路也可以不与公共电极连接，而是与一具有恒压输出的参考电压源连接，该参考电压源所输出的恒定电压与公共电极的公共电压相同。此时第四开关的第一端连接第一像素电极，第二端连接该参考电压源，在第二扫描线控制第四开关导通时第一像素电极和参考电压源之间发生电荷转移，从而使得第一像素电极的电压与参考电压源的电压相同，进而使得第一像素电极和公共电极之间的电压差为零，使得第一像素电极产生对应显示黑画面的电压信号。
在备选实施方式中，第一控制电路也可以在第二扫描线输入第二扫描信号时控制第一像素电极的数据信号完全释放，使得第一像素电极上没有可用于显示的数据信号，进而使得第一像素电极处于显示对应黑画面的图像的状态。例如，第一控制电路可以是一开关元件，使第一像素电极通过该开关元件接地，第一控制电路在第二扫描线输入第二扫描信号时使第一像素电极和地端电连接，从而使得第一像素电极通过地端放电，进而使得第一像素电极处于显示对应黑画面的图像的状态。
此外，上述实施方式中第二控制电路使用两个分压电容改变第二像素电极和第三像素电极的电压，在其他实施方式中，也可以通过两个分压电阻实现。即第二控制电路包括一受控开关和串联在一起的两个分压电阻，此时，使第二像素电极连接电阻串的一端，电阻串的另一端接地，受控开关的一端连接在两个电阻之间，受控开关的另一端与第三像素电极连接。当第三扫描线控制受控开关导通时，第二像素电极的电压通过两个分压电阻的分压后降低，而第三像素电极通过一个分压电阻的分压后降低，第二像素电极的电压降低的程度大于第三像素电极的电压降低的程度，因此在两个分压电阻的作用下第二像素电极和第三像素电极的电压均降低，当因降低的程度不同而使得第二像素电极和第三像素电极的电压也不相同，因此也能够使得三个像素电极之间的电压均不相同，从而达到低色偏的效果。
参阅图6，本发明液晶显示面板的一实施方式中，液晶显示面板包括阵列基板601、彩色滤光基板602以及位于阵列基板601和彩色滤光基板602之间的液晶层603。其中，阵列基板601为图3所示的阵列基板。此外，本实施方式的液晶显示面板还包括多个第一扫描驱动器604、一个第二扫描驱动器605、多个第三扫描驱动器606以及多个数据驱动器607。在其他实施方式中，阵列基板601也可以为上述任一实施方式的阵列基板。
参阅图7，图7是图6的液晶显示面板的俯视结构示意图。其中，每个第一扫描驱动器604与一条第一扫描线11连接以对第一扫描线11输入第一扫描信号；第二扫描驱动器605与所有第二扫描线12连接以对所有的第二扫描线输入第二扫描信号和第四扫描信号；每个第三扫描驱动器606与一条第三扫描线13连接以对第三扫描线13输入第三扫描信号；每个数据驱动器606与一条数据线14连接以对数据线输入数据信号。通过第一扫描驱动器604、第二扫描驱动器605、第三扫描驱动器606以及数据驱动器607以共同驱动液晶显示面板显示。第一扫描驱动器604、第二扫描驱动器605、第三扫描驱动器606可以采用扫描驱动芯片实现，当然也可以通过分立元件所构成的扫描驱动电路实现，数据驱动器607可以采用数据驱动芯片实现，当然同样也可以通过分立元件所构成的数据驱动电路实现。本实施方式的液晶显示面板，与现有技术相比，不仅能够提高2D显示模式的开口率，减少3D显示模式下的双眼信号串扰，同时能够减小两种显示模式下在大视角所观察的颜色差异，增大广视角，并且能够减少数据驱动器的数量，有效降低成本。
此外，在其他实施方式中，所有第二扫描线也可以相互独立，此时液晶显示面板也可以包括多个第二扫描驱动器，并使每个扫描驱动器与一条第二扫描线连接。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (16)

  1. 一种阵列基板，其中，包括多条第一扫描线、多条第二扫描线、多条第三扫描线、多条数据线、多个行列排列的像素单元以及用于输入公共电压的公共电极，每个所述像素单元对应一条第一扫描线、一条第二扫描线、一条第三扫描线以及一条数据线；
    所有所述第二扫描线在所述阵列基板的外围区域电性连接，每个所述像素单元包括第一像素电极、第二像素电极以及第三像素电极，以及分别作用于所述第一像素电极、第二像素电极和第三像素电极的第一开关、第二开关以及第三开关，每个所述像素单元还包括第一控制电路和第二控制电路，对应本像素单元的所述数据线分别通过所述第一开关、第二开关以及第三开关与所述第一像素电极、第二像素电极以及第三像素电极连接，以提供数据信号，所述第一开关、第二开关以及第三开关在所述第一扫描线输入第一扫描信号时导通；
    所述第一控制电路与所述公共电极连接，所述第一控制电路在所述第二扫描线输入第二扫描信号时控制所述第一像素电极和所述公共电极之间的电压差为零，以使得所述第一像素电极处于显示对应黑画面的图像的状态，所述第二控制电路在所述第三扫描线输入第三扫描信号时作用于所述第二像素电极和第三像素电极，以改变所述第二像素电极和第三像素电极之间的电压差；
    其中，在2D显示模式下，所述第一像素电极、第二像素电极以及第三像素电极在对应本像素单元的所述第一扫描线和所述数据线的作用下处于显示对应2D画面的图像的状态，所述第一控制电路在所述第二扫描线输入第四扫描信号时控制所述第一像素电极处于显示对应2D画面的图像的状态，随后对应本像素单元所述第三扫描线输入第三扫描信号控制所述第二控制电路作用于第二像素电极和第三像素电极，所述第二像素电极和第三像素电极之间的电压差在所述第二控制电路的作用下改变，以使得所述第一像素电极、第二像素电极以及第三像素电极两两之间存在不为零的电压差；在3D显示模式下，所述第二扫描线输入第二扫描信号以控制所述第一控制电路作用于所述第一像素电极，所述第二像素电极和第三像素电极在对应本像素单元的所述第一扫描线和数据线的作用下处于显示对应3D画面的图像的状态，所述第一像素电极在所述第一控制电路的作用下处于显示对应黑画面的图像的状态，随后所述第三扫描线输入第三扫描信号以控制所述第二控制电路作用于第二像素电极和第三像素电极，所述第二像素电极和第三像素电极之间的电压差在所述第二控制电路的作用下改变，以使得所述第二像素电极和第三像素电极之间存在不为零的电压差。
  2. 根据权利要求1所述的阵列基板，其中，
    所述第一控制电路包括第四开关，所述第四开关包括控制端、第一端以及第二端，所述第四开关的控制端连接所述第二扫描线，所述第四开关的第一端连接第一像素电极，所述第四开关的第二端连接所述公共电极，在所述第二扫描线输入第二扫描信号时所述第四开关导通，以使得所述第一像素电极和所述公共电极电性连接，所述第四开关在其导通时间内控制所述第一像素电极和所述公共电极之间的电压差为零。
  3. 根据权利要求1所述的阵列基板，其中，
    所述第二控制电路包括第五开关、第一分压电容和第二分压电容，所述第五开关包括控制端、第一端以及第二端，所述第五开关的控制端连接所述第三扫描线，所述第五开关的第一端与所述第一分压电容的一端连接，所述第一分压电容的另一端与所述第二像素电极连接，所述第五开关的第二端与所述第三像素电极连接，所述第二分压电容的一端与所述第一分压电容的一端连接，所述第二分压电容的另一端与所述公共电极连接，在所述第三扫描线输入第三扫描信号时所述第五开关导通，以使得所述第二像素电极和第三像素电极之间的电压差通过所述第一分压电容和第二分压电容改变。
  4. 根据权利要求3所述的阵列基板，其中，
    所述第一分压电容由形成所述第一扫描线的金属和形成所述数据线的金属所构成，所述第二分压电容由形成所述第一扫描线的金属和透明电极所构成。
  5. 一种阵列基板，其中，包括多条第一扫描线、多条第二扫描线、多条第三扫描线、多条数据线、多个行列排列的像素单元以及用于输入公共电压的公共电极，每个所述像素单元对应一条第一扫描线、一条第二扫描线、一条第三扫描线以及一条数据线；
    每个所述像素单元包括第一像素电极、第二像素电极以及第三像素电极，以及分别作用于所述第一像素电极、第二像素电极和第三像素电极的第一开关、第二开关以及第三开关，每个所述像素单元还包括第一控制电路和第二控制电路，对应本像素单元的所述数据线分别通过所述第一开关、第二开关以及第三开关与所述第一像素电极、第二像素电极以及第三像素电极连接，以提供数据信号，所述第一开关、第二开关以及第三开关在所述第一扫描线输入第一扫描信号时导通；
    所述第一控制电路在所述第二扫描线输入第二扫描信号时作用于所述第一像素电极，以使得所述第一像素电极处于显示对应黑画面的图像的状态，所述第二控制电路在所述第三扫描线输入第三扫描信号时作用于所述第二像素电极和第三像素电极，以改变所述第二像素电极和第三像素电极之间的电压差；
    其中，在2D显示模式下，所述第一像素电极、第二像素电极以及第三像素电极在对应本像素单元的所述第一扫描线和所述数据线的作用下处于显示对应2D画面的图像的状态，所述第一控制电路在所述第二扫描线输入第四扫描信号时控制所述第一像素电极处于显示对应2D画面的图像的状态，随后对应本像素单元所述第三扫描线输入第三扫描信号控制所述第二控制电路作用于第二像素电极和第三像素电极，所述第二像素电极和第三像素电极之间的电压差在所述第二控制电路的作用下改变，以使得所述第一像素电极、第二像素电极以及第三像素电极两两之间存在不为零的电压差；在3D显示模式下，所述第二扫描线输入第二扫描信号以控制所述第一控制电路作用于所述第一像素电极，所述第二像素电极和第三像素电极在对应本像素单元的所述第一扫描线和数据线的作用下处于显示对应3D画面的图像的状态，所述第一像素电极在所述第一控制电路的作用下处于显示对应黑画面的图像的状态，随后所述第三扫描线输入第三扫描信号以控制所述第二控制电路作用于第二像素电极和第三像素电极，所述第二像素电极和第三像素电极之间的电压差在所述第二控制电路的作用下改变，以使得所述第二像素电极和第三像素电极之间存在不为零的电压差。
  6. 根据权利要求5所述的阵列基板，其中，
    所述第一控制电路与所述公共电极连接，所述第一控制电路在所述第二扫描线输入第二扫描信号时控制所述第一像素电极和所述公共电极之间的电压差为零，以使得所述第一像素电极处于显示对应黑画面的图像的状态。
  7. 根据权利要求6所述的阵列基板，其中，
    所述第一控制电路包括第四开关，所述第四开关包括控制端、第一端以及第二端，所述第四开关的控制端连接所述第二扫描线，所述第四开关的第一端连接第一像素电极，所述第四开关的第二端连接所述公共电极，在所述第二扫描线输入第二扫描信号时所述第四开关导通，以使得所述第一像素电极和所述公共电极电性连接，所述第四开关在其导通时间内控制所述第一像素电极和所述公共电极之间的电压差为零。
  8. 根据权利要求5所述的阵列基板，其中，
    所述第二控制电路包括第五开关、第一分压电容和第二分压电容，所述第五开关包括控制端、第一端以及第二端，所述第五开关的控制端连接所述第三扫描线，所述第五开关的第一端与所述第一分压电容的一端连接，所述第一分压电容的另一端与所述第二像素电极连接，所述第五开关的第二端与所述第三像素电极连接，所述第二分压电容的一端与所述第一分压电容的一端连接，所述第二分压电容的另一端与所述公共电极连接，在所述第三扫描线输入第三扫描信号时所述第五开关导通，以使得所述第二像素电极和第三像素电极之间的电压差通过所述第一分压电容和第二分压电容改变。
  9. 根据权利要求8所述的阵列基板，其中，
    所述第一分压电容由形成所述第一扫描线的金属和形成所述数据线的金属所构成，所述第二分压电容由形成所述第一扫描线的金属和透明电极所构成。
  10. 根据权利要求5所述的阵列基板，其中，
    所有所述第二扫描线在所述阵列基板的外围区域电性连接。
  11. 一种液晶显示面板，其中，包括多个第一扫描驱动器、至少一个第二扫描驱动器、多个第三扫描驱动器、多个数据驱动器、阵列基板、彩色滤光基板以及位于所述阵列基板和彩色滤光基板之间的液晶层；
    所述阵列基板包括多条第一扫描线、多条第二扫描线、多条第三扫描线、多条数据线、多个行列排列的像素单元以及用于输入公共电压的公共电极，每个所述像素单元对应一条第一扫描线、一条第二扫描线、一条第三扫描线以及一条数据线；
    每个所述第一扫描驱动器与一条所述第一扫描线连接以对所述第一扫描线输入第一扫描信号，所述至少一个第二扫描驱动器与所述第二扫描线连接以对所述第二扫描线输入第二扫描信号和第四扫描信号，每个所述第三扫描驱动器与一条所述第三扫描线连接以对所述第三扫描线输入第三扫描信号，每个所述数据驱动器与一条所述数据线连接以对所述数据线输入数据信号；
    每个所述像素单元包括第一像素电极、第二像素电极以及第三像素电极，以及分别作用于所述第一像素电极、第二像素电极和第三像素电极的第一开关、第二开关以及第三开关，每个所述像素单元还包括第一控制电路和第二控制电路，对应本像素单元的所述数据线分别通过所述第一开关、第二开关以及第三开关与所述第一像素电极、第二像素电极以及第三像素电极连接，以提供数据信号，所述第一开关、第二开关以及第三开关在所述第一扫描线输入第一扫描信号时导通；
    所述第一控制电路在所述第二扫描线输入第二扫描信号时作用于所述第一像素电极，以使得所述第一像素电极处于显示对应黑画面的图像的状态，所述第二控制电路在所述第三扫描线输入第三扫描信号时作用于所述第二像素电极和第三像素电极，以改变所述第二像素电极和第三像素电极之间的电压差；
    其中，在2D显示模式下，所述第一像素电极、第二像素电极以及第三像素电极在对应本像素单元的所述第一扫描线和所述数据线的作用下处于显示对应2D画面的图像的状态，所述第一控制电路在所述第二扫描线输入第四扫描信号时控制所述第一像素电极处于显示对应2D画面的图像的状态，随后所述第三扫描线输入第三扫描信号控制所述第二控制电路作用于第二像素电极和第三像素电极，所述第二像素电极和第三像素电极之间的电压差在所述第二控制电路的作用下改变，以使得所述第一像素电极、第二像素电极以及第三像素电极两两之间存在不为零的电压差；在3D显示模式下，所述第二扫描线输入第二扫描信号以控制所述第一控制电路作用于所述第一像素电极，所述第二像素电极和第三像素电极在对应本像素单元的所述第一扫描线和数据线的作用下处于显示对应3D画面的图像的状态，所述第一像素电极在所述第一控制电路的作用下处于显示对应黑画面的图像的状态，随后所述第三扫描线输入第三扫描信号以控制所述第二控制电路作用于第二像素电极和第三像素电极，所述第二像素电极和第三像素电极之间的电压差在所述第二控制电路的作用下改变，以使得所述第二像素电极和第三像素电极之间存在不为零的电压差。
  12. 根据权利要求11所述的液晶显示面板，其中，
    所述第一控制电路与所述公共电极连接，所述第一控制电路在所述第二扫描线输入第二扫描信号时控制所述第一像素电极和所述公共电极之间的电压差为零，以使得所述第一像素电极处于显示对应黑画面的图像的状态。
  13. 根据权利要求12所述的液晶显示面板，其中，
    所述第一控制电路包括第四开关，所述第四开关包括控制端、第一端以及第二端，所述第四开关的控制端连接所述第二扫描线，所述第四开关的第一端连接第一像素电极，所述第四开关的第二端连接所述公共电极，在所述第二扫描线输入第二扫描信号时所述第四开关导通，以使得所述第一像素电极和所述公共电极电性连接，所述第四开关在其导通时间内控制所述第一像素电极和所述公共电极之间的电压差为零。
  14. 根据权利要求11所述的液晶显示面板，其中，
    所述第二控制电路包括第五开关、第一分压电容和第二分压电容，所述第五开关包括控制端、第一端以及第二端，所述第五开关的控制端连接所述第三扫描线，所述第五开关的第一端与所述第一分压电容的一端连接，所述第一分压电容的另一端与所述第二像素电极连接，所述第五开关的第二端与所述第三像素电极连接，所述第二分压电容的一端与所述第一分压电容的一端连接，所述第二分压电容的另一端与所述公共电极连接，在所述第三扫描线输入第三扫描信号时所述第五开关导通，以使得所述第二像素电极和第三像素电极之间的电压差通过所述第一分压电容和第二分压电容改变。
  15. 根据权利要求14所述的液晶显示面板，其中，
    所述第一分压电容由形成所述第一扫描线的金属和形成所述数据线的金属所构成，所述第二分压电容由形成所述第一扫描线的金属和透明电极所构成。
  16. 根据权利要求11所述的液晶显示面板，其中，
    所有所述第二扫描线在所述阵列基板的外围区域电性连接。
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