WO2018145343A1 - 一种液晶像素电路及液晶显示装置 - Google Patents

一种液晶像素电路及液晶显示装置 Download PDF

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Publication number
WO2018145343A1
WO2018145343A1 PCT/CN2017/076309 CN2017076309W WO2018145343A1 WO 2018145343 A1 WO2018145343 A1 WO 2018145343A1 CN 2017076309 W CN2017076309 W CN 2017076309W WO 2018145343 A1 WO2018145343 A1 WO 2018145343A1
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Prior art keywords
thin film
film transistor
liquid crystal
pixel region
capacitor
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PCT/CN2017/076309
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English (en)
French (fr)
Inventor
安立扬
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深圳市华星光电技术有限公司
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Priority to US15/524,832 priority Critical patent/US20180322836A1/en
Publication of WO2018145343A1 publication Critical patent/WO2018145343A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0242—Compensation of deficiencies in the appearance of colours
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/028—Improving the quality of display appearance by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a liquid crystal pixel circuit and a liquid crystal display device.
  • VA Vertical alignment mode liquid crystal display device
  • the existing common method for solving the phenomenon of low color shift is to divide each pixel on the liquid crystal display device into a main region and a sub-region, and through a sharing capacitor, the main region and the sub-region obtain different voltages, and the liquid crystal molecules are subjected to The voltage drives two different kinds of steering, which can play the role of viewing angle compensation when viewed from a large viewing angle, so as to achieve the purpose of improving the bias of the large-vision role.
  • the brightness of the panel as a whole is lowered and the transmittance is also lowered at the expense of the brightness of the sub-region.
  • An object of the present invention is to provide a liquid crystal pixel circuit and a liquid crystal display device, so as to solve the problem of reducing the overall brightness of the liquid crystal display device caused by the VA type liquid crystal display device in the prior art. The problem of lowering the rate.
  • the present invention provides a liquid crystal pixel circuit including: a plurality of scan lines, a plurality of data lines, and a plurality of pixels defined by the scan lines and the data lines, each of the pixels comprising: a first pixel region, a two-pixel area and a capacitive coupling module;
  • the first pixel region and the second pixel region are electrically connected to a scan line and a data line at the same time;
  • the capacitive coupling module has a control end, an input end, a first path end, and a second path End, the control end is connected to another scan line, the input end is connected to a first pixel area of another of the pixels, and the first pass end is connected to the first pixel area, the first a second path end is connected to the second pixel area,
  • the first pixel region and the second pixel region are charged to a first potential value; when another scan line is turned on, the first pixel region is charged to a second potential value, The second pixel region is charged to a third potential value, wherein the first potential value is less than the second potential value and the third potential value;
  • the capacitive coupling module includes: a first thin film transistor, a first coupling capacitor, and a second coupling capacitor;
  • a gate of the first thin film transistor is connected to the control end, a source of the first thin film transistor is connected to one end of the first coupling capacitor, and a drain of the first thin film transistor is opposite to the second
  • the other end of the first coupling capacitor is connected to the input end; one end of the second coupling capacitor is connected to the second path end, and the other end of the second coupling capacitor is opposite to the first One-way end connection;
  • the pixels on the same column have the same polarity.
  • the first pixel region includes: a second thin film transistor and a first memory component
  • a gate of the second thin film transistor is connected to the scan line, a source of the second thin film transistor is connected to the data line, a drain of the second thin film transistor and the first storage component and the The first path end connection is described.
  • the first storage component includes: a first liquid crystal capacitor and a first storage capacitor;
  • One end of the first liquid crystal capacitor and the first storage capacitor is connected to a drain of the second thin film transistor, and the other end of the first liquid crystal capacitor is connected to a common electrode, and the other end of the first storage capacitor is common to Wire connection.
  • the input terminal is connected to the drain of the second thin film transistor of the other of the pixels.
  • the second pixel region includes: a third thin film transistor and a second memory component;
  • a gate of the third thin film transistor is connected to the scan line, a source of the third thin film transistor is connected to the data line, a drain of the third thin film transistor and the second storage component and the The second path end is connected.
  • the second storage component includes: a second liquid crystal capacitor and a second storage capacitor;
  • One end of the second liquid crystal capacitor and the second storage capacitor are connected to the drain of the third thin film transistor, the other end of the second liquid crystal capacitor is connected to the common electrode, and the other end of the second storage capacitor is common to Wire connection.
  • the polarities of the pixels on adjacent columns are opposite.
  • the present invention also provides a liquid crystal pixel circuit comprising: a plurality of scan lines, a plurality of data lines, and a plurality of pixels defined by the scan lines and the data lines, each of the pixels comprising: a first pixel region, a second pixel region and a capacitive coupling module;
  • the first pixel region and the second pixel region are electrically connected to a scan line and a data line at the same time;
  • the capacitive coupling module has a control end, an input end, a first path end, and a second path End, the control end is connected to another scan line, the input end is connected to a first pixel area of another of the pixels, and the first pass end is connected to the first pixel area, the first a second path end is connected to the second pixel area,
  • the first pixel region and the second pixel region are charged to a first potential value; when another scan line is turned on, the first pixel region is charged to a second potential value, The second pixel region is charged to a third potential value, wherein the first potential value is less than the second potential value and the third potential value.
  • the capacitive coupling module includes: a first thin film transistor, a first coupling capacitor, and a second coupling capacitor;
  • a gate of the first thin film transistor is connected to the control end, a source of the first thin film transistor is connected to one end of the first coupling capacitor, and a drain of the first thin film transistor is opposite to the second
  • the other end of the first coupling capacitor is connected to the input end; one end of the second coupling capacitor is connected to the second path end, and the other end of the second coupling capacitor is opposite to the first One channel end is connected.
  • the first pixel region includes: a second thin film transistor and a first memory component
  • a gate of the second thin film transistor is connected to the scan line, a source of the second thin film transistor is connected to the data line, a drain of the second thin film transistor and the first storage component and the The first path end connection is described.
  • the first storage component includes: a first liquid crystal capacitor and a first storage capacitor;
  • One end of the first liquid crystal capacitor and the first storage capacitor is connected to a drain of the second thin film transistor, and the other end of the first liquid crystal capacitor is connected to a common electrode, and the other end of the first storage capacitor is common to Wire connection.
  • the input terminal is connected to the drain of the second thin film transistor of the other of the pixels.
  • the second pixel region includes: a third thin film transistor and a second memory component;
  • a gate of the third thin film transistor is connected to the scan line, a source of the third thin film transistor is connected to the data line, a drain of the third thin film transistor and the second storage component and the The second path end is connected.
  • the second storage component includes: a second liquid crystal capacitor and a second storage capacitor;
  • One end of the second liquid crystal capacitor and the second storage capacitor are connected to the drain of the third thin film transistor, the other end of the second liquid crystal capacitor is connected to the common electrode, and the other end of the second storage capacitor is common to Wire connection.
  • the polarities of the pixels on the same column are the same.
  • the polarities of the pixels on adjacent columns are opposite.
  • a liquid crystal display device comprising a liquid crystal pixel circuit comprising: a plurality of scan lines, a plurality of data lines, and a plurality of pixels defined by the scan lines and the data lines
  • a liquid crystal pixel circuit comprising: a plurality of scan lines, a plurality of data lines, and a plurality of pixels defined by the scan lines and the data lines
  • Each of the pixels includes: a first pixel region, a second pixel region, and a capacitive coupling module;
  • the first pixel region and the second pixel region are electrically connected to a scan line and a data line at the same time;
  • the capacitive coupling module has a control end, an input end, a first path end, and a second path End, the control end is connected to another scan line, the input end is connected to a first pixel area of another of the pixels, and the first pass end is connected to the first pixel area, the first a second path end is connected to the second pixel area,
  • the first pixel region and the second pixel region are charged to a first potential value; when another scan line is turned on, the first pixel region is charged to a second potential value, The second pixel region is charged to a third potential value, wherein the first potential value is less than the second potential value and the third potential value.
  • the capacitive coupling module includes: a first thin film transistor, a first coupling capacitor, and a second coupling capacitor;
  • a gate of the first thin film transistor is connected to the control end, a source of the first thin film transistor is connected to one end of the first coupling capacitor, and a drain of the first thin film transistor is opposite to the second
  • the other end of the first coupling capacitor is connected to the input end; one end of the second coupling capacitor is connected to the second path end, and the other end of the second coupling capacitor is opposite to the first One channel end is connected.
  • the first pixel region includes: a second thin film transistor and a first memory component
  • a gate of the second thin film transistor is connected to the scan line, a source of the second thin film transistor is connected to the data line, a drain of the second thin film transistor and the first storage component and the The first path end connection is described.
  • the second pixel region includes: a third thin film transistor and a second memory component;
  • a gate of the third thin film transistor is connected to the scan line, a source of the third thin film transistor is connected to the data line, a drain of the third thin film transistor and the second storage component and the The second path end is connected.
  • the liquid crystal pixel circuit and the liquid crystal display device of the present invention boost the first potential value on the first pixel region to the second potential value and the first potential value on the second pixel region by capacitive coupling of a capacitive coupling module Raising to the third potential value, and adjusting the capacitance value of the first coupling capacitor and the second coupling capacitor, so that the first pixel region and the second pixel region have a certain potential value differential pressure, in improving the large-view role bias problem
  • the overall brightness of the liquid crystal display device is not lowered, and the transmittance is improved.
  • the VA type liquid crystal display device solves the problem of large-view character bias, thereby causing a decrease in the overall brightness of the liquid crystal display device. The problem of reduced penetration.
  • FIG. 1 is a schematic structural view of a preferred embodiment of a liquid crystal pixel circuit of the present invention
  • FIG. 2 is a circuit diagram of the pixel 10 and the pixel 11 shown in FIG. 1.
  • the liquid crystal pixel circuit of the preferred embodiment includes: a plurality of scan lines G(1), G(2), ..., G(n), multiple data lines D(1), D(2), ..., D(n) and scan lines G(1), G(2), ..., G(n) and A plurality of pixels 10 defined by the data lines G(1), G(2), ..., G(n), each of the pixels 10 includes a first pixel region 101, a second pixel region 102, and a capacitive coupling module 103.
  • the first pixel region 101 and the second pixel region 102 of the pixel 10 are electrically connected to a scan line G(1) and a data line D(1) at the same time;
  • the capacitive coupling module 103 has a control terminal a, An input terminal b, a first path end c and a second path end d, the control terminal a is connected to another scan line G(2), and the input terminal b is connected to the first pixel region 101 of the other pixel 11,
  • the first via end c is connected to the first pixel region 101 of the pixel 10, and the second via end d is connected to the second pixel region 102 of the pixel 10.
  • pixels on the same column have the same polarity, and pixels on adjacent columns have opposite polarities.
  • the scan line G(1) is first turned on, the first pixel region 101 and the second pixel region 102 of the pixel 10 are charged to a first potential value; and then another scan line G is turned on.
  • FIG. 2 is a circuit diagram of the pixel 10 and the pixel 11 shown in FIG. 1.
  • the capacitive coupling module 103 includes: a first thin film transistor TFT1, a first coupling capacitor C1, and a second coupling.
  • a capacitor C2 a gate of the first thin film transistor TFT1 is connected to the control terminal a, a source of the first thin film transistor TFT1 is connected to one end of the first coupling capacitor C1, and a drain of the first thin film transistor TFT1 is connected to the second via end d
  • the other end of the first coupling capacitor C1 is connected to the input terminal a; one end of the second coupling capacitor C2 is connected to the second path end d, and the other end of the second coupling capacitor C2 is connected to the first path end c.
  • the first pixel region 101 includes: a second thin film transistor TFT2 and a first memory component; a gate of the second thin film transistor TFT2 is connected to the scan line G(1), and a source of the second thin film transistor TFT2 and the data line D (1) Connected, the drain of the second thin film transistor TFT2 is connected to the first memory component and the first via terminal C.
  • the first storage component includes: a first liquid crystal capacitor Clc1 and a first storage capacitor Cst1; one end of the first liquid crystal capacitor Clc1 and the first storage capacitor Cst1 is connected to the drain of the second thin film transistor TFT2, and the first liquid crystal capacitor Clc1 The other end of the first storage capacitor Cst1 is connected to the common line Acom. Further, the input terminal a is connected to the drain of the second thin film transistor TFT2 of the other pixel 11.
  • the second pixel region 102 includes: a third thin film transistor TFT3 and a second memory component; a gate of the third thin film transistor TFT3 is connected to the scan line G(1), and a source of the third thin film transistor TFT3 and the data line D (1) The connection, the drain of the third thin film transistor TFT3 is connected to the second storage component and the second via end d.
  • the second storage component includes: a second liquid crystal capacitor Clc2 and a second storage capacitor Cst2; one end of the second liquid crystal capacitor Clc2 and the second storage capacitor Cst2 is connected to the drain of the third thin film transistor TFT3, and the second liquid crystal capacitor Clc2 The other end of the second storage capacitor Cst2 is connected to the common line Acom.
  • the scan line G(1) When the scan line G(1) outputs a high-level scan signal, the second thin film transistor TFT2 and the third thin film transistor TFT3 are turned on. At this time, the data line D(1) outputs a data signal to the first pixel region 101 and the first The two pixel area 102 is charged. Specifically, the data signal charges the first liquid crystal capacitor Clc1 and the first storage capacitor Cst1 via the second thin film transistor such that the first pixel region has a first potential value; likewise, the data signal passes through the third thin film transistor to the second liquid crystal capacitor Clc2 is charged with the first storage capacitor Cst2 such that the second pixel region has a first potential value.
  • the scan line G(1) outputs a low-level scan signal
  • the second thin film transistor TFT2 is disconnected from the third thin film transistor TFT3.
  • the other scan line G(2) outputs a high-level scan signal, so that the third thin film transistor TFT3, the second thin film transistor TFT2 of the other pixel 11, and the third thin film transistor TFT3 of the other pixel are turned on, the data line D (1)
  • the output data signal charges the first pixel region 101 and the second pixel region 102 of the other pixel 11.
  • the potential value of the first pixel region 101 of the other pixel 11 is the polarity voltage of the previous frame
  • the current data line D(1) is the potential of the first pixel region from the potential of the previous frame.
  • the value is charged to the current frame potential value, so that the first coupling capacitor and the second coupling capacitor generate a capacitive coupling effect, and the first potential value of the first pixel region 101 of the pixel 10 is further pulled up to a second potential value, the pixel The first potential value of the second pixel region 102 of 10 is further pulled up to the third potential value, thereby increasing the brightness of the liquid crystal display device and increasing the transmittance.
  • the second potential value of the first pixel region 101 and the third potential value of the second pixel region 102 can be adjusted by the capacitance values of the first coupling capacitor and the second coupling capacitor, thereby causing the first pixel region 101 and the second pixel.
  • the region 102 obtains different potential values, so that the liquid crystals of the first pixel region and the second pixel region are differently deflected, which improves the problem of the large-view character bias and improves the display quality of the liquid crystal display device.
  • the liquid crystal pixel circuit of the present invention increases the first potential value on the first pixel region to the second potential value and the first potential value on the second pixel region to the third level through capacitive coupling of a capacitive coupling module a potential value, and by adjusting a capacitance value of the first coupling capacitor and the second coupling capacitor, such that a potential difference between the first pixel region and the second pixel region has a certain value, which does not improve the problem of the large-view character bias
  • the overall brightness of the liquid crystal display device is lowered, and the transmittance is improved.
  • the VA type liquid crystal display device solves the problem of the bias of the large-view function, thereby causing a decrease in the overall brightness of the liquid crystal display device, resulting in a decrease in the transmittance. The problem.
  • the present invention further provides a liquid crystal display device comprising the liquid crystal pixel circuit of the above embodiment.
  • the liquid crystal pixel circuit has been discussed in detail in the above embodiments, and details are not described herein again.
  • the first potential value on the first pixel region is raised to the second potential value and the first potential value on the second pixel region is raised to the third level by capacitive coupling of a capacitive coupling module a potential value, and by adjusting a capacitance value of the first coupling capacitor and the second coupling capacitor, such that a potential difference between the first pixel region and the second pixel region has a certain value, which does not improve the problem of the large-view character bias
  • the overall brightness of the liquid crystal display device is lowered, and the transmittance is improved.
  • the VA type liquid crystal display device solves the problem of the bias of the large-view function, thereby causing a decrease in the overall brightness of the liquid crystal display device, resulting in a decrease in the transmittance. The problem.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

一种液晶像素电路及液晶显示装置，液晶像素电路包括多个像素（10），每个像素（10）包括：第一像素区（101）、第二像素区（102）以及电容耦合模块（103）；其中，当扫描线（G（1））开启时，第一像素区（101）与第二像素区（102）充电至第一电位值；当另一扫描线（G（2））开启时，第一像素区（101）充电至第二电位值，第二像素区（102）充电至第三电位值。

Description

一种液晶像素电路及液晶显示装置 技术领域
本发明涉及液晶显示领域，尤其涉及一种液晶像素电路及液晶显示装置。
 背景技术
随着技术的发展，人们对液晶显示装置的要求越来越高，而现有的VA（Vertical Alignment，垂直排列）模式液晶显示装置具有非常高的正面对比度，但在侧面观看时，由于VA模式液晶分子在垂直方向转动的特点，导致液晶显示装置的对比度下降十分明显，不同视野角下会出现明显的色偏现象。
而现有的解决低色偏现象的常见方法为：将液晶显示装置上的每个像素分为主区和子区，通过一分享电容，使得主区与子区获得不一样的电压，液晶分子受电压驱使有两种不同的转向，在大视角观看时可以起到视角补偿的作用，以实现改善大视角色偏的目的。但是，采用这种方法是以牺牲子区的亮度为代价，面板整体的亮度会下降，穿透率也变低。
故，有必要提供一种液晶像素电路及液晶显示装置，以解决现有技术所存在的问题。
 技术问题
本发明的目的在于提供一种液晶像素电路及液晶显示装置，以解决现有技术中，VA型液晶显示装置为解决大视角色偏问题，从而造成的液晶显示装置整体亮度的降低，致使穿透率降低的问题。
 技术解决方案
本发明提供一种液晶像素电路，其包括：多条扫描线、多条数据线以及所述扫描线与所述数据线限定的多个像素，每个所述像素包括：第一像素区、第二像素区以及电容耦合模块；
所述第一像素区与第二像素区同时电性连接至一所述扫描线与一所述数据线；所述电容耦合模块具有一控制端、一输入端、第一通路端以及第二通路端，所述控制端与另一所述扫描线连接，所述输入端与另一所述像素的第一像素区连接，所述第一通路端与所述第一像素区连接，所述第二通路端与所述第二像素区连接，
当所述扫描线开启时，所述第一像素区与第二像素区充电至第一电位值；当另一所述扫描线开启时，所述第一像素区充电至第二电位值，所述第二像素区充电至第三电位值，其中，所述第一电位值小于所述第二电位值以及所述第三电位值；
所述电容耦合模块包括：第一薄膜晶体管、第一耦合电容以及第二耦合电容；
所述第一薄膜晶体管的栅极与所述控制端连接，所述第一薄膜晶体管的源极与所述第一耦合电容的一端连接，所述第一薄膜晶体管的漏极与所述第二通路端连接，所述第一耦合电容的另一端与所述输入端连接；所述第二耦合电容的一端与所述第二通路端连接，所述第二耦合电容的另一端与所述第一通路端连接；
同一列上的所述像素的极性相同。
在本发明的液晶像素电路中，所述第一像素区包括：第二薄膜晶体管以及第一存储组件；
所述第二薄膜晶体管的栅极与所述扫描线连接，所述第二薄膜晶体管的源极与所述数据线连接，所述第二薄膜晶体管的漏极与所述第一存储组件以及所述第一通路端连接。
在本发明的液晶像素电路中，所述第一存储组件包括：第一液晶电容以及第一存储电容；
所述第一液晶电容与第一存储电容的一端与所述第二薄膜晶体管的漏极连接，所述第一液晶电容的另一端与公共电极连接，所述第一存储电容的另一端与公共线连接。
在本发明的液晶像素电路中，所述输入端与另一所述像素的第二薄膜晶体管的漏极连接。
在本发明的液晶像素电路中，所述第二像素区包括：第三薄膜晶体管以及第二存储组件；
所述第三薄膜晶体管的栅极与所述扫描线连接，所述第三薄膜晶体管的源极与所述数据线连接，所述第三薄膜晶体管的漏极与所述第二存储组件以及所述第二通路端连接。
在本发明的液晶像素电路中，所述第二存储组件包括：第二液晶电容以及第二存储电容；
所述第二液晶电容与第二存储电容的一端与所述第三薄膜晶体管的漏极连接，所述第二液晶电容的另一端与公共电极连接，所述第二存储电容的另一端与公共线连接。
在本发明的液晶像素电路中，相邻列上的所述像素的极性相反。
本发明还提供一种液晶像素电路，其包括：多条扫描线、多条数据线以及所述扫描线与所述数据线限定的多个像素，每个所述像素包括：第一像素区、第二像素区以及电容耦合模块；
所述第一像素区与第二像素区同时电性连接至一所述扫描线与一所述数据线；所述电容耦合模块具有一控制端、一输入端、第一通路端以及第二通路端，所述控制端与另一所述扫描线连接，所述输入端与另一所述像素的第一像素区连接，所述第一通路端与所述第一像素区连接，所述第二通路端与所述第二像素区连接，
当所述扫描线开启时，所述第一像素区与第二像素区充电至第一电位值；当另一所述扫描线开启时，所述第一像素区充电至第二电位值，所述第二像素区充电至第三电位值，其中，所述第一电位值小于所述第二电位值以及所述第三电位值。
在本发明的液晶像素电路中，所述电容耦合模块包括：第一薄膜晶体管、第一耦合电容以及第二耦合电容；
所述第一薄膜晶体管的栅极与所述控制端连接，所述第一薄膜晶体管的源极与所述第一耦合电容的一端连接，所述第一薄膜晶体管的漏极与所述第二通路端连接，所述第一耦合电容的另一端与所述输入端连接；所述第二耦合电容的一端与所述第二通路端连接，所述第二耦合电容的另一端与所述第一通路端连接。
在本发明的液晶像素电路中，所述第一像素区包括：第二薄膜晶体管以及第一存储组件；
所述第二薄膜晶体管的栅极与所述扫描线连接，所述第二薄膜晶体管的源极与所述数据线连接，所述第二薄膜晶体管的漏极与所述第一存储组件以及所述第一通路端连接。
在本发明的液晶像素电路中，所述第一存储组件包括：第一液晶电容以及第一存储电容；
所述第一液晶电容与第一存储电容的一端与所述第二薄膜晶体管的漏极连接，所述第一液晶电容的另一端与公共电极连接， 所述第一存储电容的另一端与公共线连接。
在本发明的液晶像素电路中，所述输入端与另一所述像素的第二薄膜晶体管的漏极连接。
在本发明的液晶像素电路中，所述第二像素区包括：第三薄膜晶体管以及第二存储组件；
所述第三薄膜晶体管的栅极与所述扫描线连接，所述第三薄膜晶体管的源极与所述数据线连接，所述第三薄膜晶体管的漏极与所述第二存储组件以及所述第二通路端连接。
在本发明的液晶像素电路中，所述第二存储组件包括：第二液晶电容以及第二存储电容；
所述第二液晶电容与第二存储电容的一端与所述第三薄膜晶体管的漏极连接，所述第二液晶电容的另一端与公共电极连接，所述第二存储电容的另一端与公共线连接。
在本发明的液晶像素电路中，同一列上的所述像素的极性相同。
在本发明的液晶像素电路中，相邻列上的所述像素的极性相反。
依据本发明的上述目的，还提供一种液晶显示装置，其包括一种液晶像素电路，其包括：多条扫描线、多条数据线以及所述扫描线与所述数据线限定的多个像素，每个所述像素包括：第一像素区、第二像素区以及电容耦合模块；
所述第一像素区与第二像素区同时电性连接至一所述扫描线与一所述数据线；所述电容耦合模块具有一控制端、一输入端、第一通路端以及第二通路端，所述控制端与另一所述扫描线连接，所述输入端与另一所述像素的第一像素区连接，所述第一通路端与所述第一像素区连接，所述第二通路端与所述第二像素区连接，
当所述扫描线开启时，所述第一像素区与第二像素区充电至第一电位值；当另一所述扫描线开启时，所述第一像素区充电至第二电位值，所述第二像素区充电至第三电位值，其中，所述第一电位值小于所述第二电位值以及所述第三电位值。
在本发明的液晶显示装置中，所述电容耦合模块包括：第一薄膜晶体管、第一耦合电容以及第二耦合电容；
所述第一薄膜晶体管的栅极与所述控制端连接，所述第一薄膜晶体管的源极与所述第一耦合电容的一端连接，所述第一薄膜晶体管的漏极与所述第二通路端连接，所述第一耦合电容的另一端与所述输入端连接；所述第二耦合电容的一端与所述第二通路端连接，所述第二耦合电容的另一端与所述第一通路端连接。
在本发明的液晶显示装置中，所述第一像素区包括：第二薄膜晶体管以及第一存储组件；
所述第二薄膜晶体管的栅极与所述扫描线连接，所述第二薄膜晶体管的源极与所述数据线连接，所述第二薄膜晶体管的漏极与所述第一存储组件以及所述第一通路端连接。
在本发明的液晶显示装置中，所述第二像素区包括：第三薄膜晶体管以及第二存储组件；
所述第三薄膜晶体管的栅极与所述扫描线连接，所述第三薄膜晶体管的源极与所述数据线连接，所述第三薄膜晶体管的漏极与所述第二存储组件以及所述第二通路端连接。
 有益效果
本发明的液晶像素电路及液晶显示装置，通过一电容耦合模块的电容耦合作用，将第一像素区上的第一电位值提升至第二电位值以及将第二像素区上的第一电位值提升至第三电位值，并且可以通过调整第一耦合电容与第二耦合电容的电容值，使得第一像素区与第二像素区之间具有一定电位值压差，在改善大视角色偏问题的同时不会降低液晶显示装置的整体亮度，提高了穿透率；解决了现有技术中，VA型液晶显示装置为解决大视角色偏问题，从而造成的液晶显示装置整体亮度的降低，致使穿透率降低的问题。
 附图说明
为让本发明的上述内容能更明显易懂，下文特举优选实施例，并配合所附图式，作详细说明如下：
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
图1为本发明液晶像素电路优选实施例的结构示意图；
图2为图1所示像素10以及像素11的电路图。
 本发明的最佳实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
参阅图1，图1为本发明液晶像素电路优选实施例的结构示意图；如图1所示，本优选实施例的液晶像素电路，包括：多条扫描线G(1)、G(2)、……、G(n)，多条数据线D(1)、D(2)、……、D(n)以及扫描线G(1)、G(2)、……、G(n)与数据线G(1)、G(2)、……、G(n)限定的多个像素10，每个像素10包括：第一像素区101、第二像素区102以及电容耦合模块103。
进一步的，该像素10的第一像素区101与第二像素区102同时电性连接至一扫描线G(1)与一数据线D(1)；该电容耦合模块103具有一控制端a、一输入端b、第一通路端c以及第二通路端d，该控制端a与另一扫描线连接G(2)，该输入端b与另一像素11的第一像素区101连接，该第一通路端c与该像素10的第一像素区101连接，该第二通路端d与该像素10的第二像素区102连接。
特别地，位于同一列上的像素的极性相同，相邻列上的像素的极性相反。
本发明的液晶像素电路工作时，先开启该扫描线G(1)，将该像素10的第一像素区101以及第二像素区102充电至第一电位值；然后再开启另一扫描线G(2)，通过电容耦合模块103的电容耦合作用，将该像素10的第一像素区101充电至第二电位值，该像素10的第二像素区102充电至第三电位值，其中，第一电位值小于第二电位值以及第三电位值。
具体的，参阅图2，图2为图1所示像素10以及像素11的电路图；如图2所示，该电容耦合模块103包括：第一薄膜晶体管TFT1、第一耦合电容C1以及第二耦合电容C2；第一薄膜晶体管TFT1的栅极与控制端a连接，第一薄膜晶体管TFT1的源极与第一耦合电容C1的一端连接，第一薄膜晶体管TFT1的漏极与第二通路端d连接，第一耦合电容C1的另一端与输入端a连接；第二耦合电容C2的一端与第二通路端d连接，第二耦合电容C2的另一端与第一通路端c连接。
该第一像素区101包括：第二薄膜晶体管TFT2以及第一存储组件；第二薄膜晶体管TFT2的栅极与扫描线G(1)连接，第二薄膜晶体管TFT2的源极与数据线D(1)连接，第二薄膜晶体管TFT2的漏极与第一存储组件以及第一通路端C连接。其中，该第一存储组件包括：第一液晶电容Clc1以及第一存储电容Cst1；第一液晶电容Clc1与第一存储电容Cst1的一端与第二薄膜晶体管TFT2的漏极连接，第一液晶电容Clc1的另一端与公共电极连接，第一存储电容Cst1的另一端与公共线Acom连接。进一步地，该输入端a与另一像素11的第二薄膜晶体管TFT2的漏极连接。
该第二像素区102包括：第三薄膜晶体管TFT3以及第二存储组件；第三薄膜晶体管TFT3的栅极与扫描线G（1）连接，第三薄膜晶体管TFT3的源极与数据线D(1)连接，第三薄膜晶体管TFT3的漏极与第二存储组件以及第二通路端d连接。其中，该第二存储组件包括：第二液晶电容Clc2以及第二存储电容Cst2；第二液晶电容Clc2与第二存储电容Cst2的一端与第三薄膜晶体管TFT3的漏极连接，第二液晶电容Clc2的另一端与公共电极连接，第二存储电容Cst2的另一端与公共线Acom连接。
本优选实施例的工作原理如下所述：
当该扫描线G(1)输出高电平扫描信号时，第二薄膜晶体管TFT2与第三薄膜晶体管TFT3导通，此时，数据线D（1）输出数据信号对第一像素区101与第二像素区102进行充电。具体地，数据信号经第二薄膜晶体管对第一液晶电容Clc1与第一存储电容Cst1进行充电，使得第一像素区具有第一电位值；同样，数据信号经第三薄膜晶体管对第二液晶电容Clc2与第一存储电容Cst2进行充电，使得第二像素区具有第一电位值。
随后，该扫描线G（1）输出低电平扫描信号，第二薄膜晶体管TFT2与第三薄膜晶体管TFT3断开。此时，另一扫描线G（2）输出高电平扫描信号，使得第三薄膜晶体管TFT3、另一像素11的第二薄膜晶体管TFT2以及另一像素的第三薄膜晶体管TFT3打开，数据线D（1）输出数据信号对另一像素11的第一像素区101以及第二像素区102进行充电。而此时另一像素11的第一像素区101的电位值为上一帧画面的极性电压，而当前该数据线D（1）将该第一像素区第电位值由上一帧的电位值充电至当前帧电位值，从而使得第一耦合电容与第二耦合电容产生电容耦合效应，将该像素10的第一像素区101的第一电位值进一步拉升至第二电位值，该像素10的第二像素区102的第一电位值进一步拉升至第三电位值，从而提高液晶显示装置的亮度，提高穿透率。
另外，第一像素区101的第二电位值与第二像素区102的第三电位值可通过调整第一耦合电容与第二耦合电容的电容值，从而使得第一像素区101与第二像素区102获得不同的电位值，使得第一像素区与第二像素区的液晶发生不同偏转，改善了大视角色偏问题，提高液晶显示装置的显示质量。
本发明的液晶像素电路，通过一电容耦合模块的电容耦合作用，将第一像素区上的第一电位值提升至第二电位值以及将第二像素区上的第一电位值提升至第三电位值，并且可以通过调整第一耦合电容与第二耦合电容的电容值，使得第一像素区与第二像素区之间具有一定电位值压差，在改善大视角色偏问题的同时不会降低液晶显示装置的整体亮度，提高了穿透率；解决了现有技术中，VA型液晶显示装置为解决大视角色偏问题，从而造成的液晶显示装置整体亮度的降低，致使穿透率降低的问题。
本发明还提供一种液晶显示装置，包括上述实施例的液晶像素电路，该液晶像素电路已经在上述实施例中进行了详细的论述，在此不再赘述。
本发明的液晶显示装置，通过一电容耦合模块的电容耦合作用，将第一像素区上的第一电位值提升至第二电位值以及将第二像素区上的第一电位值提升至第三电位值，并且可以通过调整第一耦合电容与第二耦合电容的电容值，使得第一像素区与第二像素区之间具有一定电位值压差，在改善大视角色偏问题的同时不会降低液晶显示装置的整体亮度，提高了穿透率；解决了现有技术中，VA型液晶显示装置为解决大视角色偏问题，从而造成的液晶显示装置整体亮度的降低，致使穿透率降低的问题。
综上，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种液晶像素电路，其包括：多条扫描线、多条数据线以及所述扫描线与所述数据线限定的多个像素，每个所述像素包括：第一像素区、第二像素区以及电容耦合模块；
    所述第一像素区与第二像素区同时电性连接至一所述扫描线与一所述数据线；所述电容耦合模块具有一控制端、一输入端、第一通路端以及第二通路端，所述控制端与另一所述扫描线连接，所述输入端与另一所述像素的第一像素区连接，所述第一通路端与所述第一像素区连接，所述第二通路端与所述第二像素区连接，
    当所述扫描线开启时，所述第一像素区与第二像素区充电至第一电位值；当另一所述扫描线开启时，所述第一像素区充电至第二电位值，所述第二像素区充电至第三电位值，其中，所述第一电位值小于所述第二电位值以及所述第三电位值；
    所述电容耦合模块包括：第一薄膜晶体管、第一耦合电容以及第二耦合电容；
    所述第一薄膜晶体管的栅极与所述控制端连接，所述第一薄膜晶体管的源极与所述第一耦合电容的一端连接，所述第一薄膜晶体管的漏极与所述第二通路端连接，所述第一耦合电容的另一端与所述输入端连接；所述第二耦合电容的一端与所述第二通路端连接，所述第二耦合电容的另一端与所述第一通路端连接；
    同一列上的所述像素的极性相同。
  2. 根据权利要求1所述的液晶像素电路，其中所述第一像素区包括：第二薄膜晶体管以及第一存储组件；
    所述第二薄膜晶体管的栅极与所述扫描线连接，所述第二薄膜晶体管的源极与所述数据线连接，所述第二薄膜晶体管的漏极与所述第一存储组件以及所述第一通路端连接。
  3. 根据权利要求2所述的液晶像素电路，其中所述第一存储组件包括：第一液晶电容以及第一存储电容；
    所述第一液晶电容与第一存储电容的一端与所述第二薄膜晶体管的漏极连接，所述第一液晶电容的另一端与公共电极连接，所述第一存储电容的另一端与公共线连接。
  4. 根据权利要求3所述的液晶像素电路，其中所述输入端与另一所述像素的第二薄膜晶体管的漏极连接。
  5. 根据权利要求1所述的液晶像素电路，其中所述第二像素区包括：第三薄膜晶体管以及第二存储组件；
    所述第三薄膜晶体管的栅极与所述扫描线连接，所述第三薄膜晶体管的源极与所述数据线连接，所述第三薄膜晶体管的漏极与所述第二存储组件以及所述第二通路端连接。
  6. 根据权利要求5所述的液晶像素电路，其中所述第二存储组件包括：第二液晶电容以及第二存储电容；
    所述第二液晶电容与第二存储电容的一端与所述第三薄膜晶体管的漏极连接，所述第二液晶电容的另一端与公共电极连接，所述第二存储电容的另一端与公共线连接。
  7. 根据权利要求1所述的液晶像素电路，其中相邻列上的所述像素的极性相反。
  8. 一种液晶像素电路，其包括：多条扫描线、多条数据线以及所述扫描线与所述数据线限定的多个像素，每个所述像素包括：第一像素区、第二像素区以及电容耦合模块；
    所述第一像素区与第二像素区同时电性连接至一所述扫描线与一所述数据线；所述电容耦合模块具有一控制端、一输入端、第一通路端以及第二通路端，所述控制端与另一所述扫描线连接，所述输入端与另一所述像素的第一像素区连接，所述第一通路端与所述第一像素区连接，所述第二通路端与所述第二像素区连接，
    当所述扫描线开启时，所述第一像素区与第二像素区充电至第一电位值；当另一所述扫描线开启时，所述第一像素区充电至第二电位值，所述第二像素区充电至第三电位值，其中，所述第一电位值小于所述第二电位值以及所述第三电位值。
  9. 根据权利要求8所述的液晶像素电路，其中所述电容耦合模块包括：第一薄膜晶体管、第一耦合电容以及第二耦合电容；
    所述第一薄膜晶体管的栅极与所述控制端连接，所述第一薄膜晶体管的源极与所述第一耦合电容的一端连接，所述第一薄膜晶体管的漏极与所述第二通路端连接，所述第一耦合电容的另一端与所述输入端连接；所述第二耦合电容的一端与所述第二通路端连接，所述第二耦合电容的另一端与所述第一通路端连接。
  10. 根据权利要求8所述的液晶像素电路，其中所述第一像素区包括：第二薄膜晶体管以及第一存储组件；
    所述第二薄膜晶体管的栅极与所述扫描线连接，所述第二薄膜晶体管的源极与所述数据线连接，所述第二薄膜晶体管的漏极与所述第一存储组件以及所述第一通路端连接。
  11. 根据权利要求10所述的液晶像素电路，其中所述第一存储组件包括：第一液晶电容以及第一存储电容；
    所述第一液晶电容与第一存储电容的一端与所述第二薄膜晶体管的漏极连接，所述第一液晶电容的另一端与公共电极连接，所述第一存储电容的另一端与公共线连接。
  12. 根据权利要求11所述的液晶像素电路，其中所述输入端与另一所述像素的第二薄膜晶体管的漏极连接。
  13. 根据权利要求8所述的液晶像素电路，其中所述第二像素区包括：第三薄膜晶体管以及第二存储组件；
    所述第三薄膜晶体管的栅极与所述扫描线连接，所述第三薄膜晶体管的源极与所述数据线连接，所述第三薄膜晶体管的漏极与所述第二存储组件以及所述第二通路端连接。
  14. 根据权利要求13所述的液晶像素电路，其中所述第二存储组件包括：第二液晶电容以及第二存储电容；
    所述第二液晶电容与第二存储电容的一端与所述第三薄膜晶体管的漏极连接，所述第二液晶电容的另一端与公共电极连接，所述第二存储电容的另一端与公共线连接。
  15. 根据权利要求8所述的液晶像素电路，其中同一列上的所述像素的极性相同。
  16. 根据权利要求8所述的液晶像素电路，其中相邻列上的所述像素的极性相反。
  17. 一种液晶显示装置，其包括一种液晶像素电路，其包括：多条扫描线、多条数据线以及所述扫描线与所述数据线限定的多个像素，每个所述像素包括：第一像素区、第二像素区以及电容耦合模块；
    所述第一像素区与第二像素区同时电性连接至一所述扫描线与一所述数据线；所述电容耦合模块具有一控制端、一输入端、第一通路端以及第二通路端，所述控制端与另一所述扫描线连接，所述输入端与另一所述像素的第一像素区连接，所述第一通路端与所述第一像素区连接，所述第二通路端与所述第二像素区连接，
    当所述扫描线开启时，所述第一像素区与第二像素区充电至第一电位值；当另一所述扫描线开启时，所述第一像素区充电至第二电位值，所述第二像素区充电至第三电位值，其中，所述第一电位值小于所述第二电位值以及所述第三电位值。
  18. 根据权利要求17所述的液晶显示装置，其中所述电容耦合模块包括：第一薄膜晶体管、第一耦合电容以及第二耦合电容；
    所述第一薄膜晶体管的栅极与所述控制端连接，所述第一薄膜晶体管的源极与所述第一耦合电容的一端连接，所述第一薄膜晶体管的漏极与所述第二通路端连接，所述第一耦合电容的另一端与所述输入端连接；所述第二耦合电容的一端与所述第二通路端连接，所述第二耦合电容的另一端与所述第一通路端连接。
  19. 根据权利要求17所述的液晶显示装置，其中所述第一像素区包括：第二薄膜晶体管以及第一存储组件；
    所述第二薄膜晶体管的栅极与所述扫描线连接，所述第二薄膜晶体管的源极与所述数据线连接，所述第二薄膜晶体管的漏极与所述第一存储组件以及所述第一通路端连接。
  20. 根据权利要求17所述的液晶显示装置，其中所述第二像素区包括：第三薄膜晶体管以及第二存储组件；
    所述第三薄膜晶体管的栅极与所述扫描线连接，所述第三薄膜晶体管的源极与所述数据线连接，所述第三薄膜晶体管的漏极与所述第二存储组件以及所述第二通路端连接。
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