WO2017197693A1 - 3t像素结构及液晶显示装置 - Google Patents

3t像素结构及液晶显示装置 Download PDF

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Publication number
WO2017197693A1
WO2017197693A1 PCT/CN2016/086008 CN2016086008W WO2017197693A1 WO 2017197693 A1 WO2017197693 A1 WO 2017197693A1 CN 2016086008 W CN2016086008 W CN 2016086008W WO 2017197693 A1 WO2017197693 A1 WO 2017197693A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
insulating layer
source
disposed
Prior art date
Application number
PCT/CN2016/086008
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English (en)
French (fr)
Inventor
姜祥卫
Original Assignee
深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US15/121,927 priority Critical patent/US10254610B2/en
Publication of WO2017197693A1 publication Critical patent/WO2017197693A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/133345—Insulating layers
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    • G02F1/136213—Storage capacitors associated with the pixel electrode
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
    • H—ELECTRICITY
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to the field of liquid crystal display, and in particular to a 3T pixel structure and a liquid crystal display device.
  • Embodiments of the present invention provide a 3T pixel structure, including:
  • a first insulating layer disposed on the lower common electrode, the scan line, and the substrate;
  • a charge-sharing thin film transistor having a source, a drain, and a gate, wherein a source and a drain of the charge-sharing thin film transistor are disposed on the first insulating layer;
  • a second insulating layer disposed on the source and drain of the charge sharing thin film transistor, the data line, and the first insulating layer;
  • An upper common electrode disposed on the second insulating layer
  • a source via hole is formed in the second insulating layer, and the upper common electrode is in contact with the first source through the source via hole and is electrically connected.
  • the third insulating layer and the pixel electrode layer are further disposed on the common electrode and the second insulating layer, and the pixel electrode layer is disposed on the On the third insulating layer.
  • the main pixel thin film transistor and the sub-pixel thin film transistor are further provided, and the source, the drain and the gate of the main pixel thin film transistor and the sub-pixel thin film transistor are both disposed on the first
  • the first gate is disposed on the second insulating layer on the insulating layer.
  • the source of the main pixel thin film transistor and the drain of the sub-pixel thin film transistor are electrically connected to the data line
  • the source of the sub-pixel thin film transistor and the The drains of the charge sharing thin film transistors are electrically connected
  • the gates of the main pixel thin film transistor, the sub-pixel thin film transistor, and the charge sharing thin film transistor are electrically connected to the scan line.
  • the method further includes a first storage capacitor and a second storage capacitor, the first storage capacitor being configured by the first plate and the lower common electrode disposed on the first insulating layer Forming a portion opposite to the first plate, wherein the second storage capacitor is formed by the second plate disposed on the first insulating layer on the lower common electrode and the second plate Forming a portion, the first plate is electrically connected to a drain of the main pixel thin film transistor, a source of the second plate and the sub-pixel thin film transistor, and a drain of the charge sharing thin film transistor Electrical connection.
  • a source of the sub-pixel thin film transistor is in contact with and electrically connected to a drain of the charge sharing thin film transistor, a source of the sub-pixel thin film transistor and the charge sharing film A common node of the drain of the transistor is electrically coupled to the second plate.
  • the substrate is a transparent glass substrate or a transparent plastic substrate.
  • the upper common electrodes are distributed in a grid shape.
  • the first insulating layer and the second insulating layer are made of silicon nitride and/or silicon dioxide.
  • the present invention also provides a liquid crystal display device comprising the 3T pixel structure described in any of the above.
  • the source of the charge sharing thin film transistor is electrically connected to the lower common electrode through the deep hole and the shallow hole, and the present invention directly and electrically connects the source of the charge sharing thin film transistor.
  • the electrodes are electrically connected through the source vias on the second insulating layer, thereby avoiding the occurrence of overlap of deep and shallow holes in the pixel structure, thereby increasing the aperture ratio.
  • the source of the sub-pixel thin film transistor and the drain of the charge-sharing thin film transistor are directly in contact and electrically connected, the resistance of the sub-pixel thin film transistor and the charge sharing thin film transistor fluctuate simultaneously, and the internal resistance ratio changes little, to Mura The effect is small and the parasitic capacitance can also be reduced.
  • FIG. 1 is a schematic structural view of a preferred embodiment of a 3T pixel structure of the present invention.
  • FIG. 2 is a partial plan perspective structural view of the 3T pixel structure in the embodiment shown in FIG. 1.
  • FIG. 2 is a partial plan perspective structural view of the 3T pixel structure in the embodiment shown in FIG. 1.
  • the 3T pixel structure in the preferred embodiment includes a substrate 10, a lower common electrode 20, a scan line (not shown), a first insulating layer 30, and a main pixel thin film transistor T1.
  • the lower common electrode 20 and the scan line are all disposed on the substrate 10.
  • the data line 80 is disposed on the first insulating layer 30.
  • the main pixel thin film transistor T1, the sub-pixel thin film transistor T2, and the charge sharing thin film transistor T3 are disposed on the first insulating layer 30.
  • the second insulating layer 40 is disposed on the main pixel thin film transistor T1, the sub-pixel thin film transistor T2, the charge sharing thin film transistor T3, the data line 80, and the first insulating layer 30.
  • the upper common electrode 50 is disposed on the second insulating layer 40.
  • the third insulating layer 60 is disposed on the upper common electrode 50.
  • the pixel electrode layer 70 is disposed on the third insulating layer 60.
  • the main pixel thin film transistor T1, the sub-pixel thin film transistor T2, and the charge sharing thin film transistor T3 each have a source, a drain, and a gate.
  • the source, the drain, and the gate of the main pixel thin film transistor T1, the sub-pixel thin film transistor T2, and the charge sharing thin film transistor T3 are all disposed on the first insulating layer 30.
  • the gates of the respective transistors may be disposed on the gate.
  • Other layers are not limited herein.
  • the source of the main pixel thin film transistor T1 and the drain of the sub-pixel thin film transistor T2 are electrically connected to the data line 80.
  • the source of the main pixel thin film transistor T1 is the second source 101.
  • the source of the sub-pixel thin film transistor T2 is electrically connected to the drain of the charge-sharing thin film transistor T3.
  • the source of the sub-pixel thin film transistor T2 is a third source 201, and the drain of the charge-sharing thin film transistor T3 is the first drain. 301.
  • the source of the charge sharing thin film transistor T3 is a first source 91, and the first source 91 is electrically connected to the upper common electrode 50.
  • the second insulating layer 40 defines a source via 41, and the upper common electrode 50 is in contact with and electrically connected to the first source 91 through the source via 41.
  • the source of the charge sharing thin film transistor T3 is connected to the lower common electrode 20, and the first source 91 in this embodiment is directly electrically connected to the upper common electrode 50, thereby avoiding occurrence in the pixel structure.
  • the overlap of the deep hole and the shallow hole increases the aperture ratio and eliminates the potential undesirable phenomenon caused by the overlapping of the shallow and shallow holes.
  • the gates of the main pixel thin film transistor T1, the sub-pixel thin film transistor T2, and the charge sharing thin film transistor T3 are electrically connected to the scanning line.
  • the first insulating layer 30 is further provided with a first electrode plate 100 and a second electrode plate 200.
  • the first electrode plate 100 is electrically connected to the drain of the main pixel thin film transistor T1, that is, the second drain electrode 102.
  • the second plate 200 is electrically connected to the source of the sub-pixel thin film transistor T2 and the drain of the charge sharing thin film transistor T3.
  • the first storage capacitor of the 3T pixel structure is formed by a portion of the first plate 100 and the lower common electrode 20 facing the first plate 100, and the second storage capacitor of the 3T pixel structure is formed by the second plate 200. And a portion of the lower common electrode 20 that faces the second plate 200.
  • the second insulating layer 40 is provided with a first via hole 43, and the third insulating layer 60 is provided with a second via hole (not shown) through which the pixel electrode layer 70 passes through the first via hole 43 and the second via hole.
  • the first plate 100 is in contact and electrically connected.
  • the second insulating layer 40 is formed in the third via hole 42, and the third insulating layer 60 is provided with a fourth via hole.
  • the pixel electrode layer 70 passes through the third via hole 42 and the fourth via hole and the second electrode.
  • the board 200 is in contact and electrically connected.
  • the source (third source 201) of the sub-pixel thin film transistor T2 and the drain (first drain 301) of the charge sharing thin film transistor T3 are in direct contact and electrically connected, and their common node and the second The plates 100 are electrically connected.
  • the present invention separates the drain of the charge-sharing thin film transistor T3 from the source of the sub-pixel thin film transistor T2, in contrast to the prior art in which the source of the sub-pixel thin film transistor T2 is separated from the drain of the charge-sharing thin film transistor T3.
  • the drain of the charge sharing thin film transistor T3 is in direct contact with and electrically connected to the source of the sub-pixel thin film transistor T2, and the parasitic capacitance can be reduced.
  • the source of the sub-pixel thin film transistor T2 and the drain of the charge-sharing thin film transistor T3 may not be in direct contact with each other, and may be electrically connected to the second plate 200, respectively.
  • the substrate 10 is a transparent glass substrate or a transparent plastic substrate.
  • the upper common electrode 50 is distributed in a grid shape.
  • the grid-like distribution can reduce the poor conductivity caused by the partial disconnection of the upper common electrode 50.
  • the first insulating layer 30, the second insulating layer 40 and the third insulating layer 60 are respectively made of silicon nitride and/or silicon dioxide and are formed by chemical meteorological sinking.
  • the source (first source 91) of the charge sharing thin film transistor is contacted with the upper common electrode through a source via hole formed on the second insulating layer.
  • the electrical connection avoids the overlap of deep and shallow holes in the pixel structure, thereby increasing the aperture ratio and eliminating potential undesirable phenomena caused by the overlapping of the shallow and shallow holes.
  • the source (third source 201) of the sub-pixel thin film transistor T2 and the drain (first drain 301) of the charge sharing thin film transistor T3 are in direct contact and electrically connected, the resistance is simultaneously in T2 and T3. Fluctuation, the internal resistance ratio changes little, has little effect on Mura, and can also reduce parasitic capacitance.
  • the present invention also provides a liquid crystal display device comprising the 3T pixel structure in the above embodiment.

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Abstract

一种3T像素结构及液晶显示装置，该3T像素结构包括：一基板；第一绝缘层；电荷共享薄膜晶体管，其具有源极、漏极以及栅极；数据线，其设置于该第一绝缘层上；第二绝缘层，其设置于数据线以及所述第一绝缘层上；上公共电极；第二绝缘层上开设有源极通孔，上公共电极通过源极通孔与第一源极接触并电连接。

Description

3T像素结构及液晶显示装置 技术领域
本发明涉及液晶显示领域，特别是涉及一种3T像素结构及液晶显示装置。
 背景技术
随着液晶显示器亮度、视角、对比度、响应速度等特性的要求越来越高，更多的液晶产品由TN型转到IPS（FFS）或者VA型。而随着精细度的提高，像素的尺寸越来越小。同样的设计前提下，像素开口率也会越越小，影响显示亮度。VA产品3T结构设计被提了出来，它通过去掉Sub-Pixel上的Via孔提升开口率。但因为在Pixel内引入深浅孔，过孔的直径增大，COA产品要求像素结构内过孔CD也相应增大。同时Pixel内深浅孔交叠，对Photo Overlay及刻蚀也提出了很高的要求，有极大的良率损失风险。
因此，现有技术存在缺陷，急需改进。
 技术问题
本发明的目的在于提供一种3T像素结构及液晶显示装置；以解决现有技术中3T像素结构及液晶显示装置深浅孔交叠的技术问题。
 技术解决方案
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种3T像素结构，包括：
一基板，其上形成有下公共电极以及扫描线；
第一绝缘层，其设置于该下公共电极、扫描线以及基板上；
电荷共享薄膜晶体管，其具有源极、漏极以及栅极，该电荷共享薄膜晶体管的源极、漏极均设置于该第一绝缘层上；
数据线，其设置于该第一绝缘层上；
第二绝缘层，其设置于电荷共享薄膜晶体管的源极和漏极、数据线以及所述第一绝缘层上；
上公共电极，其设置于所述第二绝缘层上；
所述第二绝缘层上开设有源极通孔，所述上公共电极通过所述源极通孔与所述第一源极接触并电连接。
在本发明所述的3T像素结构中，还包括第三绝缘层以及像素电极层，所述第三绝缘层设置于所述公共电极以及第二绝缘层上，所述像素电极层设置于所述第三绝缘层上。
在本发明所述的3T像素结构中，还包括主像素薄膜晶体管以及次像素薄膜晶体管，所述主像素薄膜晶体管和次像素薄膜晶体管的源极、漏极以及栅极均设置于所述第一绝缘层上，该第一栅极设置于所述第二绝缘层上。
在本发明所述的3T像素结构中，所述主像素薄膜晶体管的源极、所述次像素薄膜晶体管的漏极均与该数据线电连接，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极电连接，所述主像素薄膜晶体管、所述次像素薄膜晶体管以及所述电荷共享薄膜晶体管的栅极均与所述扫描线电连接。
在本发明所述的3T像素结构中，还包括第一存储电容以及第二存储电容，所述第一存储电容由设置于所述第一绝缘层上的第一极板以及所述下公共电极上的与该第一极板正对的部分形成，所述第二存储电容由设置于所述第一绝缘层上的第二极板以所述下公共电极上的与该第二极板正对的部分形成，所述第一极板与所述主像素薄膜晶体管的漏极电连接，所述第二极板与所述次像素薄膜晶体管的源极以及所述电荷共享薄膜晶体管的漏极电连接。
在本发明所述的3T像素结构中，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极接触并电连接，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极的公共节点与所述第二极板电连接。
在本发明所述的3T像素结构中，所述基板为透明玻璃基板或透明塑料基板。
在本发明所述的3T像素结构中，所述上公共电极呈网格状分布。
在本发明所述的3T像素结构中，所述第一绝缘层、所述第二绝缘层采用氮化硅和/或二氧化硅。
本发明还提供了一种液晶显示装置，其包括上述任一项所述的3T像素结构。
 有益效果
相对于现有技术，相对于现有技术中的将电荷共享薄膜晶体管的源极通过深孔以及浅孔配合从而与下公共电极电连接，本发明将电荷共享薄膜晶体管的源极直接与上公共电极通过该第二绝缘层上的源极通孔电连接，从而避免在像素结构内出现深孔与浅孔的交叠，从而增大了开口率。
进一步地，由于该次像素薄膜晶体管的源极以及该电荷共享薄膜晶体管的漏极直接接触并电连接，在次像素薄膜晶体管与电荷共享薄膜晶体管内电阻同时波动，内电阻比值变化小，对Mura影响小，并且还可以减小寄生电容。
 附图说明
图1为本发明的3T像素结构的一优选实施例的结构示意图；
图2为图1所示实施例中的3T像素结构的局部平面透视结构示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
图1是本发明一优选实施例中的3T像素结构的结构示意图。请同时参照图1以及图2所示，本优选实施例中的3T像素结构包括：基板10、下公共电极20、扫描线（未示出）、第一绝缘层30、主像素薄膜晶体管T1、次像素薄膜晶体管T2、电荷共享薄膜晶体管T3、数据线80、第二绝缘层40、上公共电极50、第三绝缘层60以及像素电极层70。
其中，该下公共电极20以及扫描线均设置于基板10上。
数据线80设置于第一绝缘层30上。主像素薄膜晶体管T1、次像素薄膜晶体管T2、电荷共享薄膜晶体管T3设置于该第一绝缘层30上。第二绝缘层40设置于主像素薄膜晶体管T1、次像素薄膜晶体管T2、电荷共享薄膜晶体管T3、数据线80以及第一绝缘层30之上。上公共电极50设置于该第二绝缘层40上，该第三绝缘层60设置于该上公共电极50上，该像素电极层70设置于该第三绝缘层60上。
具体地，该主像素薄膜晶体管T1、次像素薄膜晶体管T2以及电荷共享薄膜晶体管T3均具有源极、漏极以及栅极。其中，该主像素薄膜晶体管T1、次像素薄膜晶体管T2以及电荷共享薄膜晶体管T3的源极、漏极以及栅极均设置于该第一绝缘层30上，当然该各个三极管的栅极可以设置于其他层，在此并不限定。
该主像素薄膜晶体管T1的源极以及该次像素薄膜晶体管T2的漏极均与该数据线80电连接。该主像素薄膜晶体管T1的源极为第二源极101。该次像素薄膜晶体管T2的源极与该电荷共享薄膜晶体管T3的漏极电连接，该次像素薄膜晶体管T2的源极为第三源极201，该电荷共享薄膜晶体管T3的漏极为第一漏极301。该电荷共享薄膜晶体管T3的源极为第一源极91，该第一源极91与上公共电极50电连接。在本实施例中，该第二绝缘层40开设有源极通孔41，该上公共电极50通过该源极通孔41与该第一源极91接触并电连接。相对于现有技术中，将该电荷共享薄膜晶体管T3的源极与下公共电极20连接，本实施例中的第一源极91直接与上公共电极50电连接，从而避免在像素结构内出现深孔与浅孔的交叠，从而增大了开口率，并可以消除因深浅孔交叠来带来的潜在不良现象。
该主像素薄膜晶体管T1、次像素薄膜晶体管T2以及电荷共享薄膜晶体管T3的栅极均与扫描线电连接。
其中，该第一绝缘层30上还设置有第一极板100以及第二极板200，该第一极板100与主像素薄膜晶体管T1的漏极也即是第二漏极102电连接，该第二极板200与该次像素薄膜晶体管T2的源极以及该电荷共享薄膜晶体管T3的漏极电连接。该3T像素结构的第一存储电容由该第一极板100以及下公共电极20上的与该第一极板100正对的部分形成，3T像素结构的第二存储电容由第二极板200以及该下公共电极20上的与该第二极板200正对的部分形成。
该第二绝缘40层开设有第一过孔43、第三绝缘层60开设有第二过孔（未示出），该像素电极层70通过该第一过孔43以及该第二过孔与该第一极板100接触并电连接。该第二绝缘40层开设在有第三过孔42、第三绝缘层60开设有第四过孔，该像素电极层70通过该第三过孔42以及该第四过孔与该第二极板200接触并电连接。
优选地，该次像素薄膜晶体管T2的源极（第三源极201）以及该电荷共享薄膜晶体管T3的漏极（第一漏极301）直接接触并电连接，且其公共节点与该第二极板100电连接。相对于现有技术中将该次像素薄膜晶体管T2的源极与该电荷共享薄膜晶体管T3的漏极分离设置，本发明将电荷共享薄膜晶体管T3的漏极与次像素薄膜晶体管T2的源极连接设计，T2与T3内电阻同时波动，内电阻比值变化小，对Mura影响小。同时电荷共享薄膜晶体管T3的漏极与次像素薄膜晶体管T2的源极直接接触并电连接，可以减小寄生电容。
当然可以理解地，也可以将次像素薄膜晶体管T2的源极以及该电荷共享薄膜晶体管T3的漏极不直接接触，而采用分别与该第二极板200电连接。
其中，该基板10为透明玻璃基板或透明塑料基板。
其中，上公共电极50呈网格状分布。采用网格状的分布可以降低上公共电极50的局部断线造成的导电不良。
其中，第一绝缘层30、所述第二绝缘层40以及第三绝缘层60均分别采用氮化硅和/或二氧化硅并采用化学气象沉底制成。
在本优选实施例提供的3T像素结构中，采用将该电荷共享薄膜晶体管的源极（第一源极91）通过开设于该第二绝缘层上的源极通孔与该上公共电极接触并电连接，可以避免在像素结构内出现深孔与浅孔的交叠，从而增大了开口率，并可以消除因深浅孔交叠来带来的潜在不良现象。
进一步地，由于该次像素薄膜晶体管T2的源极（第三源极201）以及该电荷共享薄膜晶体管T3的漏极（第一漏极301）直接接触并电连接，在T2与T3内电阻同时波动，内电阻比值变化小，对Mura影响小，并且还可以减小寄生电容。
本发明还提供了一种液晶显示装置，其包括上述实施例中的3T像素结构。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (20)

  1. 一种3T像素结构，其包括：
    一基板，其上形成有下公共电极以及扫描线；
    第一绝缘层，其设置于该下公共电极、扫描线以及基板上；
    电荷共享薄膜晶体管，其具有源极、漏极以及栅极，该电荷共享薄膜晶体管的源极、漏极均设置于该第一绝缘层上；
    数据线，其设置于该第一绝缘层上；
    第二绝缘层，其设置于电荷共享薄膜晶体管的源极和漏极、数据线以及所述第一绝缘层上；
    上公共电极，其设置于所述第二绝缘层上；
    所述第二绝缘层上开设有源极通孔，所述上公共电极通过所述源极通孔与所述第一源极接触并电连接。
  2. 根据权利要求1所述的3T像素结构，其中，还包括第三绝缘层以及像素电极层，所述第三绝缘层设置于所述公共电极以及第二绝缘层上，所述像素电极层设置于所述第三绝缘层上。
  3. 根据权利要求2所述的3T像素结构，其中，还包括主像素薄膜晶体管以及次像素薄膜晶体管，所述主像素薄膜晶体管和次像素薄膜晶体管的源极、漏极以及栅极均设置于所述第一绝缘层上，该电荷共享薄膜晶体管的栅极设置于所述第二绝缘层上。
  4. 根据权利要求3所述的3T像素结构，其中，所述主像素薄膜晶体管的源极、所述次像素薄膜晶体管的漏极均与该数据线电连接，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极电连接，所述主像素薄膜晶体管、所述次像素薄膜晶体管以及所述电荷共享薄膜晶体管的栅极均与所述扫描线电连接。
  5. 根据权利要求1所述的3T像素结构，其中，还包括主像素薄膜晶体管以及次像素薄膜晶体管，所述主像素薄膜晶体管和次像素薄膜晶体管的源极、漏极以及栅极均设置于所述第一绝缘层上，该电荷共享薄膜晶体管的栅极设置于所述第二绝缘层上。
  6. 根据权利要求1所述的3T像素结构，其中，还包括第一存储电容以及第二存储电容，所述第一存储电容由设置于所述第一绝缘层上的第一极板以及所述下公共电极上的与该第一极板正对的部分形成，所述第二存储电容由设置于所述第一绝缘层上的第二极板以所述下公共电极上的与该第二极板正对的部分形成，所述第一极板与所述主像素薄膜晶体管的漏极电连接，所述第二极板与所述次像素薄膜晶体管的源极以及所述电荷共享薄膜晶体管的漏极电连接。
  7. 根据权利要求6所述的3T像素结构，其中，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极接触并电连接，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极的公共节点与所述第二极板电连接。
  8. 根据权利要求1所述的3T像素结构，其中，所述基板为透明玻璃基板或透明塑料基板。
  9. 根据权利要求1所述的3T像素结构，其中，所述上公共电极呈网格状分布。
  10. 根据权利要求1所述的3T像素结构，其中，所述第一绝缘层、所述第二绝缘层采用氮化硅和/或二氧化硅。
  11. 一种3T像素结构，其包括：
    一基板，其上形成有下公共电极以及扫描线；
    第一绝缘层，其设置于该下公共电极、扫描线以及基板上；
    电荷共享薄膜晶体管，其具有源极、漏极以及栅极，该电荷共享薄膜晶体管的源极、漏极均设置于该第一绝缘层上；
    数据线，其设置于该第一绝缘层上；
    第二绝缘层，其设置于电荷共享薄膜晶体管的源极和漏极、数据线以及所述第一绝缘层上；
    上公共电极，其设置于所述第二绝缘层上；
    所述第二绝缘层上开设有源极通孔，所述上公共电极通过所述源极通孔与所述第一源极接触并电连接；
    第三绝缘层以及像素电极层，所述第三绝缘层设置于所述公共电极以及第二绝缘层上，所述像素电极层设置于所述第三绝缘层上；
    主像素薄膜晶体管以及次像素薄膜晶体管，所述主像素薄膜晶体管和次像素薄膜晶体管的源极、漏极以及栅极均设置于所述第一绝缘层上，该电荷共享薄膜晶体管的栅极设置于所述第二绝缘层上；
    所述主像素薄膜晶体管的源极、所述次像素薄膜晶体管的漏极均与该数据线电连接，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极电连接，所述主像素薄膜晶体管、所述次像素薄膜晶体管以及所述电荷共享薄膜晶体管的栅极均与所述扫描线电连接；
    第一存储电容以及第二存储电容，所述第一存储电容由设置于所述第一绝缘层上的第一极板以及所述下公共电极上的与该第一极板正对的部分形成，所述第二存储电容由设置于所述第一绝缘层上的第二极板以所述下公共电极上的与该第二极板正对的部分形成，所述第一极板与所述主像素薄膜晶体管的漏极电连接，所述第二极板与所述次像素薄膜晶体管的源极以及所述电荷共享薄膜晶体管的漏极电连接；
    所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极接触并电连接，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极的公共节点与所述第二极板电连接。
  12. 一种液晶显示装置，其包括3T像素结构，所述3T像素结构包括：
    一基板，其上形成有下公共电极以及扫描线；
    第一绝缘层，其设置于该下公共电极、扫描线以及基板上；
    电荷共享薄膜晶体管，其具有源极、漏极以及栅极，该电荷共享薄膜晶体管的源极、漏极均设置于该第一绝缘层上；
    数据线，其设置于该第一绝缘层上；
    第二绝缘层，其设置于电荷共享薄膜晶体管的源极和漏极、数据线以及所述第一绝缘层上；
    上公共电极，其设置于所述第二绝缘层上；
    所述第二绝缘层上开设有源极通孔，所述上公共电极通过所述源极通孔与所述第一源极接触并电连接。
  13. 根据权利要求12所述的液晶显示装置，其中，还包括第三绝缘层以及像素电极层，所述第三绝缘层设置于所述公共电极以及第二绝缘层上，所述像素电极层设置于所述第三绝缘层上。
  14. 根据权利要求13所述的液晶显示装置，其中，还包括主像素薄膜晶体管以及次像素薄膜晶体管，所述主像素薄膜晶体管和次像素薄膜晶体管的源极、漏极以及栅极均设置于所述第一绝缘层上，该电荷共享薄膜晶体管的栅极设置于所述第二绝缘层上。
  15. 根据权利要求14所述的液晶显示装置，其中，所述主像素薄膜晶体管的源极、所述次像素薄膜晶体管的漏极均与该数据线电连接，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极电连接，所述主像素薄膜晶体管、所述次像素薄膜晶体管以及所述电荷共享薄膜晶体管的栅极均与所述扫描线电连接。
  16. 根据权利要求12所述的液晶显示装置，其中，还包括主像素薄膜晶体管以及次像素薄膜晶体管，所述主像素薄膜晶体管和次像素薄膜晶体管的源极、漏极以及栅极均设置于所述第一绝缘层上，该电荷共享薄膜晶体管的栅极设置于所述第二绝缘层上。
  17. 根据权利要求12所述的液晶显示装置，其中，还包括第一存储电容以及第二存储电容，所述第一存储电容由设置于所述第一绝缘层上的第一极板以及所述下公共电极上的与该第一极板正对的部分形成，所述第二存储电容由设置于所述第一绝缘层上的第二极板以所述下公共电极上的与该第二极板正对的部分形成，所述第一极板与所述主像素薄膜晶体管的漏极电连接，所述第二极板与所述次像素薄膜晶体管的源极以及所述电荷共享薄膜晶体管的漏极电连接。
  18. 根据权利要求17所述的液晶显示装置，其中，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极接触并电连接，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极的公共节点与所述第二极板电连接。
  19. 根据权利要求12所述的液晶显示装置，其中，所述基板为透明玻璃基板或透明塑料基板。
  20. 根据权利要求12所述的液晶显示装置，其中，所述上公共电极呈网格状分布。
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