CN104133332A - 一种显示面板及显示装置 - Google Patents

一种显示面板及显示装置 Download PDF

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CN104133332A
CN104133332A CN201410341497.3A CN201410341497A CN104133332A CN 104133332 A CN104133332 A CN 104133332A CN 201410341497 A CN201410341497 A CN 201410341497A CN 104133332 A CN104133332 A CN 104133332A
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distance
film transistor
thin film
tft
insulation course
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柴立
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to CN201410341497.3A priority Critical patent/CN104133332A/zh
Priority to US14/402,355 priority patent/US9454051B2/en
Priority to PCT/CN2014/083779 priority patent/WO2016008184A1/zh
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
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    • G02F2202/00—Materials and properties
    • G02F2202/10—Materials and properties semiconductor
    • G02F2202/103—Materials and properties semiconductor a-Si

Abstract

本发明提供一种显示面板，所述显示面板包括阵列基板；所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元；所述像素单元包括：具有第一薄膜晶体管的主像素部和具有第二薄膜晶体管的子像素部，第二距离与第一距离不相等，其中所述第一距离为所述第一薄膜晶体管的第一栅极和所述第一薄膜晶体管的半导体层之间的第一绝缘层的厚度，所述第二距离为所述第二薄膜晶体管的第二栅极和所述第二薄膜晶体管的半导体层之间的第二绝缘层的厚度。本发明通过将两个像素部的绝缘层设计为不同厚度的方式，来解决大视角色偏问题、从而提高观看效果、降低生产成本。

Description

一种显示面板及显示装置
【技术领域】
本发明涉及显示技术领域，特别是涉及一种显示面板及显示装置。
【背景技术】
随着液晶面板行业的快速发展，面板的尺寸越做越大，导致显示器功耗增加，以及出现大视角色偏问题，因此显示器的设计对广视角、低能耗等要求也越来越高，使得TFT器件及像素设计多样化发展以应对大尺寸液晶显示器带来的问题。
为了解决大视角色偏的问题，如图1所示，现有技术需要增加一个薄膜晶体管，通过薄膜晶体管控制分享电容开启或者关闭。在主像素部的薄膜晶体管断开时，开启分享电容的薄膜晶体管，通过分享电容降低子像素部的液晶电容的电压，以解决大视角色偏问题，但是上述像素设计结构复杂，导致开口率降低、生产成本较高。
【发明内容】
本发明的一个目的在于提供一种显示面板，能够在不降低开口率的情况下，解决大视角色偏问题、从而提高观看效果、降低生产成本。
为解决上述技术问题，本发明构造了一种显示面板，所述显
示面板包括阵列基板；
所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元；
所述像素单元包括：
主像素部，具有第一薄膜晶体管，所述第一薄膜晶体管的第一栅极与所述第一薄膜晶体管的第一源极和第一漏极之间设置有第一绝缘层，所述第一源极和所述第一漏极通过半导体层连接；
子像素部，具有第二薄膜晶体管，所述第二薄膜晶体管的第二栅极与所述第二薄膜晶体管的第二源极和第二漏极之间设置有第二绝缘层，所述第二源极和所述第二漏极通过半导体层连接；
第二距离与第一距离不相等，其中所述第一距离为所述第一薄膜晶体管的第一栅极和所述第一薄膜晶体管的半导体层之间的第一绝缘层的厚度，所述第二距离为所述第二薄膜晶体管的第二栅极和所述第二薄膜晶体管的半导体层之间的第二绝缘层的厚度。
在本发明的显示面板中，所述第二距离大于所述第一距离。
在本发明的显示面板中，所述第一绝缘层是通过对所述第二绝缘层进行打薄处理形成的。
在本发明的显示面板中，所述第二距离小于所述第一距离。
在本发明的显示面板中，所述第二绝缘层是通过对所述第一绝缘层进行打薄处理形成的。
在本发明的显示面板中，所述第二距离与第一距离的比值范围为0.5-2。
本发明的另一个目的在于提供一种显示装置，所述显示装置包括：显示面板；
所述显示面板包括阵列基板；
所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元；
所述像素单元包括：
主像素部，具有第一薄膜晶体管，所述第一薄膜晶体管的第一栅极与所述第一薄膜晶体管的第一源极和第一漏极之间设置有第一绝缘层，所述第一源极和所述第一漏极通过半导体层连接；
子像素部，具有第二薄膜晶体管，所述第二薄膜晶体管的第二栅极与所述第二薄膜晶体管的第二源极和第二漏极之间设置有第二绝缘层，所述第二源极和所述第二漏极通过半导体层连接；
第二距离与第一距离不相等，其中所述第一距离为所述第一薄膜晶体管的第一栅极和所述第一薄膜晶体管的半导体层之间的第一绝缘层的厚度，所述第二距离为所述第二薄膜晶体管的第二栅极和所述第二薄膜晶体管的半导体层之间的第二绝缘层的厚度。
在本发明的显示装置中，所述第二距离大于所述第一距离。
在本发明的显示装置中，所述第二距离小于所述第一距离。
在本发明的显示装置中，所述第二距离与第一距离的比值范围为0.5-2。
本发明通过提供一种显示面板，通过将主像素部和子像素部的绝缘层设计为不同的厚度，使得主像素部的像素电极和子像素部的像素电极的充电效率不同，进一步使得主像素部所显示的像素的亮度和子像素部所显示的像素的亮度具有一定差异，从而降低大视角色偏、提高观看效果、降低生产成本。
【附图说明】
图1是现有技术中阵列基板的结构示意图；
图2是本发明实施例中第一实施例的阵列基板的结构示意图；
图3是图2中沿A-A’方向的剖面示意图；
图4是图2中沿B-B’方向的剖面示意图；
图5是本发明实施例中第二实施例的阵列基板的结构示意图；
图6是图5中沿A-A’方向的剖面示意图；
图7是图5中沿B-B’方向的剖面示意图。
【具体实施方式】
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。在图中，结构相似的单元是以相同标号表示。
请参照图1，图1是现有技术中阵列基板的结构示意图。
显示面板包括阵列基板；所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元；图1仅给出一个像素单元的结构示意图，所述像素单元包括：主像素部101和子像素部102；其中，所述主像素部101具有第一薄膜晶体管14，所述子像素部102具有第二薄膜晶体管15以及第三薄膜晶体管16，所述第三薄膜晶体管16连接分享电容17。公共线13与所述第三薄膜晶体管的源极形成分享电容17。
其中主像素部101包括第一像素电极、第一像素电极和公共电极之间形成第一液晶电容，子像素部102包括第二像素电极，第二像素电极和公共电极之间形成第二液晶电容。
所述第一薄膜晶体管14的第一栅极和所述第二薄膜晶体管15的第二栅极连接相同的扫描线11；所述第一薄膜晶体管14的第一源极和所述第二薄膜晶体管15的第二源极连接相同的数据线12，所述第三薄膜晶体管16的栅极连接子扫描线11’，所述第一薄膜晶体管14的第一漏极通过贯穿孔18连接第一像素电极和所述第二薄膜晶体管15的第二漏极通过贯穿孔19第二像素电极；所述第一薄膜晶体管14和所述第二薄膜晶体管15关闭时，所述第三薄膜晶体管16导通，这时第二像素电极上的一部分电荷通过第三薄膜晶体管16转移到了分享电容17上，从而使得第二像素电极对应的第二液晶电容两端的电压低于第一液晶电容两端的电压。通过这种结构来降低大视角色偏问题。
请参照图2，图2本发明实施例中第一实施例的阵列基板的结构示意图。
本发明的技术方案省去了图1中的第三薄膜晶体管16以分享电容17，本实施例中显示面板包括阵列基板；
所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元；
所述像素单元包括：主像素部101和子像素部102；
结合图3，所述主像素部101，具有第一薄膜晶体管21和第一像素电极，所述第一薄膜晶体管21的第一栅极210与所述第一薄膜晶体管21的第一源极212和第一漏极213之间设置有第一绝缘层211，所述第一源极212和所述第一漏极213通过半导体层214连接；所述半导体层的材料为非晶硅材料。在所述半导体层214上表面还设置有欧姆接触层215、在所述第一源极212和所述第一漏极213的上表面设置有钝化层216。
结合图4，所述子像素部102，具有第二薄膜晶体管22和第二像素电极，所述第二薄膜晶体管的第二栅极220与所述第二薄膜晶体管的第二源极222和第二漏极223之间设置有第二绝缘层221，所述第二源极222和所述第二漏极223通过半导体层224连接；所述半导体层的材料为非晶硅材料。在所述半导体层224上表面还设置有欧姆接触层225、在所述第二源极222和所述第二漏极223的上表面设置有钝化层226。
所述第一薄膜晶体管21的第一栅极和所述第二薄膜晶体管22的第二栅极连接相同的扫描线11；所述第一薄膜晶体管21的第一源极和所述第二薄膜晶体管22的第二源极连接相同的数据线12，所述第一薄膜晶体管14的第一漏极通过贯穿孔18连接第一像素电极和所述第二薄膜晶体管15的第二漏极通过贯穿孔19第二像素电极；公共线为13。
其中所述第一距离为所述第一薄膜晶体管21的第一栅极210和所述第一薄膜晶体管21的半导体层214之间的第一绝缘层211的厚度，所述第二距离为所述第二薄膜晶体管22的第二栅极220和所述第二薄膜晶体管22的半导体层224之间的第二绝缘层221的厚度，其中第一距离不等于第二距离。
在本优选实施例中，第二距离大于第一距离，如图3所示，通过对在第一栅极210和第一薄膜晶体管的半导体层214之间的第二绝缘层221进行打薄处理，从而在第一栅极210和第一薄膜晶体管的半导体层214之间形成第一绝缘层211。
打薄处理的方式譬如为湿法刻蚀或干法刻蚀。经过打薄处理后，所述第二距离与所述第一距离的比值范围为1.25-2。由于薄膜晶体管的充电效率与绝缘层的厚度成反比，厚度越小，充电效率越高；因此第一距离小于第二距离，造成在相同数据信号驱动下，主像素部101的第一像素电极的电压要大于子像素部102的第二像素电极的电压，使得主像素部101的第一液晶电容的电压要大于子像素部102的第二液晶电容的电压，从而使得主像素部101所显示的像素的亮度和子像素部102所显示的像素的亮度具有一定差异，进而降低了大视角色偏问题。
本实施例的另外一种实现方式为，通过对在第一栅极和第一薄膜晶体管的半导体层之间的第二绝缘层进行加厚处理，从而在第一栅极和第一薄膜晶体管的半导体层之间形成第一绝缘层。加厚处理方式譬如为沉积或者溅射。经过加厚处理后，使得第二距离小于第一距离，所述第二距离与所述第一距离的比值范围为0.56-0.77。
本发明通过提供一种显示面板，通过将主像素部和子像素部的绝缘层设计为不同的厚度，使得主像素部的像素电极和子像素部的像素电极的充电效率不同，进一步使得主像素部所显示的像素的亮度和子像素部所显示的像素的亮度具有一定差异，从而降低大视角色偏、提高观看效果、降低生产成本。
请参照图5，图5是本发明实施例中第二实施例的阵列基板的结构示意图。
本发明的技术方案省去了图1中的第三薄膜晶体管16以分享电容17，本实施例中显示面板包括阵列基板；
所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元；
所述像素单元包括：主像素部101和子像素部102；
结合图6，所述主像素部101，具有第一薄膜晶体管31和第一像素电极，所述第一薄膜晶体管31的第一栅极310与所述第一薄膜晶体管31的第一源极312和第一漏极313之间设置有第一绝缘层311，所述第一源极312和所述第一漏极313通过半导体层314连接；所述半导体层的材料为非晶硅材料。在所述半导体层314上表面还设置有欧姆接触层315、在所述第一源极312和所述第一漏极313的上表面设置有钝化层316。
结合图7，所述子像素部102，具有第二薄膜晶体管32和第二像素电极，所述第二薄膜晶体管的第二栅极320与所述第二薄膜晶体管的第二源极322和第二漏极323之间设置有第二绝缘层321，所述第二源极322和所述第二漏极323通过半导体层324连接；所述半导体层的材料为非晶硅材料。在所述半导体层324上表面还设置有欧姆接触层325、在所述第二源极322和所述第二漏极323的上表面设置有钝化层326。
所述第一薄膜晶体管31的第一栅极和所述第二薄膜晶体管32的第二栅极连接相同的扫描线11；所述第一薄膜晶体管31的第一源极和所述第二薄膜晶体管32的第二源极连接相同的数据线12，所述第一薄膜晶体管31的第一漏极通过贯穿孔18连接第一像素电极和所述第二薄膜晶体管32的第二漏极通过贯穿孔19第二像素电极；公共线为13。
其中所述第一距离为所述第一薄膜晶体管31的第一栅极310和所述第一薄膜晶体管31的半导体层314之间的第一绝缘层311的厚度，所述第二距离为所述第二薄膜晶体管32的第二栅极320和所述第二薄膜晶体管32的半导体层324之间的第二绝缘层321的厚度，其中第一距离不等于第二距离。
在本优选实施例中，第二距离小于第一距离，如图7所示，通过对在第二栅极320和第二薄膜晶体管的半导体层324之间的第一绝缘层311进行打薄处理，从而在第二栅极320和第二薄膜晶体管的半导体层324之间形成第二绝缘层321。
打薄处理的方式譬如为湿法刻蚀或干法刻蚀。经过打薄处理后，所述第二距离与所述第一距离的比值范围为0.5-0.8。由于薄膜晶体管的充电效率与绝缘层的厚度成反比，厚度越小，充电效率越高；因此第一距离大于第二距离，造成在相同数据信号驱动下，主像素部101的第一像素电极的电压要小于子像素部102的第二像素电极的电压，使得主像素部101的第一液晶电容的电压要小于子像素部102的第二液晶电容的电压，从而使得主像素部101所显示的像素的亮度和子像素部102所显示的像素的亮度具有一定差异，进而降低了大视角色偏问题。
本实施例的另外一种实现方式为，通过对在第二栅极和第二薄膜晶体管的半导体层之间的第一绝缘层进行加厚处理，从而在第二栅极和第二薄膜晶体管的半导体层之间形成第二绝缘层。加厚处理方式譬如为沉积或者溅射。经过加厚处理后，使得第二距离大于第一距离，所述第二距离与所述第一距离的比值范围为1.3-1.8。
本发明通过提供一种显示面板，通过将主像素部和子像素部的绝缘层设计为不同的厚度，使得主像素部的像素电极和子像素部的像素电极的充电效率不同，进一步使得主像素部所显示的像素的亮度和子像素部所显示的像素的亮度具有一定差异，从而降低大视角色偏、提高观看效果、降低生产成本。
本发明还包括一种显示装置，所述显示装置包括：显示面板；
所述显示面板包括阵列基板；
所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元；
所述像素单元包括：
主像素部，具有第一薄膜晶体管，所述第一薄膜晶体管的第一栅极与所述第一薄膜晶体管的第一源极和第一漏极之间设置有第一绝缘层，所述第一源极和所述第一漏极通过半导体层连接；
子像素部，具有第二薄膜晶体管，所述第二薄膜晶体管的第二栅极与所述第二薄膜晶体管的第二源极和第二漏极之间设置有第二绝缘层，所述第二源极和所述第二漏极通过半导体层连接；
第二距离与第一距离不相等，其中所述第一距离为所述第一薄膜晶体管的第一栅极和所述第一薄膜晶体管的半导体层之间的第一绝缘层的厚度，所述第二距离为所述第二薄膜晶体管的第二栅极和所述第二薄膜晶体管的半导体层之间的第二绝缘层的厚度。
本发明的显示装置中的显示面板可以为上述两个实施例中的显示面板中的任意一种，鉴于所述显示面板在上文已有详细的描述，此处不再赘述。
本发明通过提供一种显示装置，通过将主像素部和子像素部的绝缘层设计为不同的厚度，使得主像素部的像素电极和子像素部的像素电极的充电效率不同，进一步使得主像素部所显示的像素的亮度和子像素部所显示的像素的亮度具有一定差异，从而降低大视角色偏、提高观看效果、降低生产成本。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

1.一种显示面板，其特征在于：
所述显示面板包括阵列基板；
所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元；
所述像素单元包括：
主像素部，具有第一薄膜晶体管，所述第一薄膜晶体管的第一栅极与所述第一薄膜晶体管的第一源极和第一漏极之间设置有第一绝缘层，所述第一源极和所述第一漏极通过半导体层连接；
子像素部，具有第二薄膜晶体管，所述第二薄膜晶体管的第二栅极与所述第二薄膜晶体管的第二源极和第二漏极之间设置有第二绝缘层，所述第二源极和所述第二漏极通过半导体层连接；
第二距离与第一距离不相等，其中所述第一距离为所述第一薄膜晶体管的第一栅极和所述第一薄膜晶体管的半导体层之间的第一绝缘层的厚度，所述第二距离为所述第二薄膜晶体管的第二栅极和所述第二薄膜晶体管的半导体层之间的第二绝缘层的厚度。
2.根据权利要求1所述的显示面板，其特征在于：所述第二距离大于所述第一距离。
3.根据权利要求2所述的显示面板，其特征在于：所述第一绝缘层是通过对所述第二绝缘层进行打薄处理形成的。
4.根据权利要求1所述的显示面板，其特征在于：所述第二距离小于所述第一距离。
5.根据权利要求4所述的显示面板，其特征在于：所述第二绝缘层是通过对所述第一绝缘层进行打薄处理形成的。
6.根据权利要求1所述的显示面板，其特征在于：所述第二距离与第一距离的比值范围为0.5-2。
7.一种显示装置，其特征在于：所述显示装置包括：显示面板；
所述显示面板包括阵列基板；
所述阵列基板包括数据线、扫描线以及由所述数据线和所述扫描线交错形成的多个像素单元；
所述像素单元包括：
主像素部，具有第一薄膜晶体管，所述第一薄膜晶体管的第一栅极与所述第一薄膜晶体管的第一源极和第一漏极之间设置有第一绝缘层，所述第一源极和所述第一漏极通过半导体层连接；
子像素部，具有第二薄膜晶体管，所述第二薄膜晶体管的第二栅极与所述第二薄膜晶体管的第二源极和第二漏极之间设置有第二绝缘层，所述第二源极和所述第二漏极通过半导体层连接；
第二距离与第一距离不相等，其中所述第一距离为所述第一薄膜晶体管的第一栅极和所述第一薄膜晶体管的半导体层之间的第一绝缘层的厚度，所述第二距离为所述第二薄膜晶体管的第二栅极和所述第二薄膜晶体管的半导体层之间的第二绝缘层的厚度。
8.根据权利要求7所述的显示装置，其特征在于：所述第二距离大于所述第一距离。
9.根据权利要求7所述的显示装置，其特征在于：所述第二距离小于所述第一距离。
10.根据权利要求7所述的显示装置，其特征在于：所述第二距离与第一距离的比值范围为0.5-2。
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