WO2020135023A1 - 显示装置、阵列基板及其工艺方法 - Google Patents

显示装置、阵列基板及其工艺方法 Download PDF

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Publication number
WO2020135023A1
WO2020135023A1 PCT/CN2019/124265 CN2019124265W WO2020135023A1 WO 2020135023 A1 WO2020135023 A1 WO 2020135023A1 CN 2019124265 W CN2019124265 W CN 2019124265W WO 2020135023 A1 WO2020135023 A1 WO 2020135023A1
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Prior art keywords
area
sub
pixel area
array substrate
pixel
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PCT/CN2019/124265
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English (en)
French (fr)
Inventor
曹军红
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惠科股份有限公司
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Publication of WO2020135023A1 publication Critical patent/WO2020135023A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/1323—Arrangements for providing a switchable viewing angle
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G02F1/134354—Subdivided pixels, e.g. for grey scale or redundancy the sub-pixels being capacitively coupled

Definitions

  • the present application relates to the technical field of display products, in particular to a display device, an array substrate, and a process method thereof.
  • Multi-domain Vertical Alignment (abbreviated as MVA)
  • MVA Multi-domain Vertical Alignment
  • the exemplary technology uses voltage division, that is, to separate pixels Different voltages are applied to the two areas of the, so that the two areas exhibit different brightness. Therefore, each pixel must be equipped with a complicated voltage division structure, and the design is more complicated.
  • the main purpose of the present application is to propose an array substrate, which aims to simplify the structure of the array substrate.
  • the array substrate proposed in this application includes:
  • a plurality of pixel units including a plurality of sub-pixels, the sub-pixels including a main pixel area and a sub-pixel area;
  • the thickness of the insulating layer at the main pixel area is a first thickness d1
  • the thickness of the insulating layer at the sub pixel area is a second thickness d2
  • d1 and d2 satisfy: d1>d2.
  • the difference between the first thickness d1 and the second thickness d2 is between 50 nm and 1000 nm.
  • the area of the main pixel area is less than or equal to the area of the sub-pixel area.
  • the area of the main pixel area is larger than the area of the sub-pixel area.
  • control voltages of the main pixel area and the sub-pixel area are equal.
  • the arrangement of the pixel electrodes on the main pixel area and the sub-pixel area is the same.
  • the pixel electrodes in the main pixel area and the sub-pixel area are arranged in a diagonal stripe pattern.
  • the main pixel area and the sub-pixel area are covered with a protective layer.
  • This application also proposes a process method for an array substrate, including the following steps:
  • Pixel electrodes are provided on the first area and the second area, the first area forms a main pixel area, and the second area forms a sub-pixel area.
  • the step of developing the first area and the second area of the photoresist so that the etching degree of the first area relative to the insulating layer is smaller than that of the second area specifically includes:
  • the first filter portion of the light source penetrating the filter hood is irradiated to the first area
  • the second filter portion of the light source penetrating the filter hood is irradiated to the second area
  • the light transmittance of the first filter portion is less than The second part.
  • the step of developing the first area and the second area of the photoresist so that the etching degree of the first area relative to the insulating layer is smaller than that of the second area specifically includes:
  • Two developing light sources with different light intensities are used to irradiate the first area and the second area, respectively.
  • the light transmittance of the first filter part is 0% to 10%, and the light transmittance of the second filter part is 20% to 40%.
  • the light transmittance of the first filter portion is 0%, and the light transmittance of the second filter portion is 30%.
  • a pixel electrode is provided on the first area and the second area, the first area forms a main pixel area, and the second area forms a sub-pixel area after the step of:
  • a protective layer is covered on the side of the main pixel area and the sub-pixel area facing the color filter substrate.
  • the present application also proposes a display device including an array substrate.
  • the array substrate includes:
  • each sub-pixel of the pixel unit includes a main pixel area and a sub-pixel area;
  • the thickness of the insulating layer at the main pixel area is a first thickness d1
  • the thickness of the insulating layer at the sub pixel area is a second thickness d2
  • d1 and d2 satisfy: d1>d2.
  • the display panel includes a color filter substrate matching the array substrate, and the color filter substrate is provided with a common electrode corresponding to the main pixel area and the sub-pixel area.
  • a capacitance is formed between the pixel electrode in the main pixel area and the sub-pixel area.
  • the interval between the array substrate and the color filter substrate is consistent.
  • the sub-pixels of the array substrate of the technical solution of the present application include a main pixel area and a sub-pixel area, and the thickness of the insulating layer on the side of the main pixel area facing away from the color filter substrate is set to be larger than that of the sub-pixel area. And when the distance between it and the color filter substrate is the same, the distance between the pixel electrode of the main pixel area and the common electrode on the color filter substrate is smaller than that of the sub-pixel area, and then the capacitance corresponding to the main pixel area is larger than that of the sub-pixel area Capacitance, when the same voltage is applied, the brightness of the main pixel area is greater than that of the sub-pixel area. Without introducing a voltage-dividing structure, the sub-pixel bright and dark areas are divided to improve the color shift effect under large viewing angles .
  • FIG. 1 is a schematic cross-sectional view of an array substrate and a color filter substrate according to an embodiment of a display device of this application;
  • FIG. 2 is an equivalent circuit diagram of the sub-pixel in FIG. 1;
  • FIG. 3 is an equivalent circuit diagram of the voltage applied to the pixel electrode and the common electrode in FIG. 2;
  • FIG. 5 is a schematic flowchart of the process method of the array substrate in FIG. 4.
  • the directional indications are only set to be interpreted in a specific posture (as shown in the drawings) If the specific posture changes, the directional indicator will change accordingly.
  • the present application provides an array substrate and a display panel having the array substrate.
  • the display panel includes but is not limited to a liquid crystal display panel, an organic light emitting diode display panel, a field emission display panel, a plasma display panel, a curved panel, and the liquid crystal panel includes a thin film Transistor liquid crystal display panel, TN panel, VA panel, IPS panel, etc.
  • the display panel is a liquid crystal display panel, which includes the array substrate 100 and a color filter substrate 200 matched with the array substrate 100.
  • the array substrate 100 includes:
  • a plurality of pixel units includes a plurality of sub-pixels, and the sub-pixels include a main pixel area 111 and a sub-pixel area 112; wherein,
  • the thickness of the insulating layer 12 on the side of the main pixel area 111 facing away from the color filter substrate 200 is the first thickness d1
  • the thickness of the insulating layer 12 on the side of the sub pixel area 112 facing away from the color filter substrate 200 is the second thickness d2
  • d1 and d2 satisfy : D1>d2.
  • the color filter substrate 200 is provided with a common electrode corresponding to the main pixel area 111 and the sub-pixel area 112, and between the common electrode and the pixel electrode 2 in the main pixel area 111 and the sub-pixel area 112 Form a capacitor, according to the capacitor formula:
  • the size of the capacitor is inversely proportional to the distance between the common electrode and the pixel electrode 2, and when the total thickness of the array substrate 100 is constant, the greater the thickness of the insulating layer 12 on the side of the display area away from the color filter substrate 200, the common electrode is The smaller the distance between the pixel electrodes 2 is, since d1>d2, the capacitance of the main pixel area 111 will be greater than that of the sub-pixel area 112.
  • the brightness of the main pixel area 111 will be greater than the brightness of the sub-pixel area 112, that is, the sub-pixel bright and dark areas are divided to improve the color shift effect of the large viewing angle, and because the control voltages applied to the sub-pixels are equal , Therefore, there is no need to additionally introduce a voltage dividing structure, thereby simplifying the overall structure of the array substrate 100, which is beneficial to reduce the production cost of the array substrate 100.
  • a half-tone process is specifically used for the pixel insulating layer 12 to achieve the effect that the thickness of the insulating layer 12 in the main pixel area 111 and the sub-pixel area 112 is not uniform. Specifically, referring to FIGS.
  • the filter cover 3 includes a first filter portion 31 and a second filter portion 32, the light transmittance of the first filter portion 31 and the second filter portion 32 Different, so that the first region corresponding to the first filter portion 31 and the second region corresponding to the second filter portion 32 of the photoresist layer 11 exhibit different degrees of etching relative to the insulating layer 12 after being irradiated, the two The photoresist layer 11 is part of the insulating layer 12, and the pixel electrode 2 is laid on the higher step surface to form the main sub-pixel.
  • the pixel electrode 2 is laid on the lower step surface to form the sub-pixel area 112 of the sub-pixel. Finally, the main pixel area 111 and the sub-pixel area 112 are covered with a protective layer 13
  • the electrode 2 and the common electrode form an insulating isolation, and on the other hand, protect the pixel electrode 2 from being knocked by external structures. It can be understood that in this way, by adjusting the process of the array substrate 100, the thickness of the insulating layer 12 in different sub-regions of the sub-pixels is effectively changed, thereby realizing the division of the bright area and the dark area. It should be noted that the design is not limited to this. In other embodiments, the thickness of the insulating layer 12 corresponding to the main pixel region 111 and the sub-pixel region 112 in the sub-pixels may be changed by other process methods.
  • the sub-pixels of the array substrate 100 include a main pixel region 111 and a sub-pixel region 112, and the thickness of the insulating layer 12 on the side of the main pixel region 111 facing away from the color filter substrate 200 is set to be greater than that of the sub-pixel region 112.
  • the thickness of the array substrate 100 is the same and the distance between the array substrate 100 and the color filter substrate 200 is the same, the distance between the pixel electrode 2 of the main pixel area 111 and the common electrode on the color filter substrate 200 is smaller than that of the sub-pixel area 112.
  • the capacitance corresponding to the main pixel area 111 is greater than that of the sub-pixel area 112.
  • the brightness of the main pixel area 111 is greater than that of the sub-pixel area 112. Without introducing a voltage divider structure, the sub-pixel is realized The division of bright areas and dark areas improves the color cast effect under large viewing angles.
  • the difference between the first thickness d1 and the second thickness d2 is between 50 nm and 1000 nm. It can be understood that if the difference between d1 and d2 is too large, the difference in brightness between the main pixel area 111 and the sub-pixel area 112 will be too large, which will affect the overall imaging effect of the display panel. However, if the difference between d1 and d2 is too small, it will As a result, the difference in brightness between the main pixel area 111 and the sub-pixel area 112 is too small, and the effect of improving color shift in the case of a large viewing angle is too weak.
  • the light transmittance of the first filter portion 31 is 0%, and the light transmittance of the second filter portion 32 is 30%, that is, the first region of the photoresist layer 11 is not completely dissolved in the insulating layer 12, The second region is partially dissolved in the insulating layer 12, so that the difference between d1 and d2 can be satisfied between 50nm and 1000nm; of course, in other embodiments, the light transmittance of the first filter portion 31, the first The light transmittance of the second filter portion 32 may be specifically other values, and the design is not limited thereto.
  • the area of the main pixel area 111 is smaller than or equal to the area of the sub-pixel area 112. It can be understood that, in this way, relative to the sub-pixel, it is beneficial to avoid that the overall brightness of the sub-pixel is too large, which in turn affects the overall imaging effect of the display panel. It should be noted that the design is not limited to this. In other embodiments, the area of the main pixel area 111 may also be larger than the area of the sub-pixel area 112.
  • the arrangement of the pixel electrodes 2 on the main pixel area 111 and the sub-pixel area 112 is consistent. It can be understood that such an arrangement is advantageous for simplifying the overall structural design of the sub-pixels, thereby reducing the production cost of the array substrate 100.
  • the pixel electrodes 2 in the main pixel area 111 and the sub-pixel area 112 are arranged in a diagonal stripe pattern. It can be understood that the arrangement of the diagonal stripe pattern is a method widely used by the existing pixel electrodes 2; Of course, in other embodiments, the pixel electrodes 2 in the main pixel area 111 and the sub-pixel area 112 may also be arranged in other ways, and the design is not limited thereto.
  • the present application also proposes an array substrate processing method, including the following steps:
  • Step S1 Develop the first area and the second area of the photoresist layer 11 so that the etching degree of the first area relative to the insulating layer 12 is smaller than that of the second area;
  • the first region and the second region have different degrees of etching with respect to the insulating layer 12, and the interval between the two and the color filter substrate 200 will be different in the later stage.
  • Step S2 a pixel electrode 2 is provided on the first area and the second area, the first area forms the main pixel area 111, and the second area forms the sub-pixel area 112.
  • the photoresist layer 11 becomes a part of the insulating layer 12, so the thickness of the insulating layer 12 at the main pixel region 111 is greater than that of the sub-pixel region 112, so that the pixel electrode 2 of the main pixel region 111 and the color filter substrate The distance of the common electrode on 200 is closer.
  • the capacitance generated by it is larger than that of the sub-pixel area 112, so that when the same control voltage is applied to the sub-pixel area 112 Under the condition of greater brightness, in other words, the main pixel area 111 and the sub-pixel area 112 realize the division of the bright area and the dark area, and achieve the effect of improving the color shift at a large viewing angle without the need for a voltage divider structure.
  • the step of developing the first area and the second area of the photoresist layer 11 so that the etching degree of the first area relative to the insulating layer 12 is smaller than that of the second area specifically includes: the light source penetrates the first filter of the filter mask 3 The light portion 31 is irradiated to the first area, the light source is transmitted through the second filter portion 32 of the filter hood 3 to the second area, and the light transmittance of the first filter portion 31 is smaller than that of the second portion.
  • the degree of etching of the first region and the second region relative to the insulating layer 12 can be changed conveniently and quickly, so that the two are arranged in a stepped manner. It should be noted that the design is not limited to this. In other embodiments, two developing sources with different light intensities are used to irradiate the first area and the second area, respectively, so that the etching degree of the first area relative to the insulating layer 12 is less than The second area.
  • the light transmittance of the first filter portion 31 is 0% to 10%
  • the light transmittance of the second filter portion 32 is 20% to 40%. It can be understood that the difference in light transmittance between the first filter portion 31 and the second filter portion 32 corresponds to the difference in the thickness of the insulating layer 12 where the main pixel region 111 and the sub-pixel region 112 are located. As a result, the difference in brightness between the main pixel area 111 and the sub-pixel area 112 is too large, which in turn affects the overall imaging effect of the display panel, while the difference is too small, which will cause the difference in brightness between the main pixel area 111 and the sub-pixel area 112 Small, its effect on improving color shift in the case of large viewing angle is too weak.
  • the light transmittance of the first filter part 31 is 0%, and the light transmittance of the second filter part 32 is 30%.
  • the light transmittance of the first filter part 31 The ratio and the light transmittance of the second filter portion 32 may be specifically other values, and the design is not limited to this.
  • the pixel electrode 2 is provided on the first region and the second region, the first region forms the main pixel region 111, and the second region forms the sub-pixel region 112 after the step further includes: Step S3, the main pixel region 111 and the sub-region
  • the side of the pixel region 112 facing the color filter substrate 200 covers the protective layer 13. It can be understood that with this arrangement, on the one hand, the pixel electrode 2 and the common electrode of the color filter substrate 200 are formed with insulating isolation, and on the other hand, the pixel electrode 2 can also be effectively protected from knocking by external structures.
  • the present application also proposes a display device including an array substrate.
  • the specific structure of the array substrate refers to the above embodiments. Since the display device adopts all the technical solutions of all the above embodiments, it has at least the technology of the above embodiments All the beneficial effects brought by the plan will not be repeated here.

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Mathematical Physics (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

一种显示装置、阵列基板及其工艺方法，阵列基板（100）包括：多个像素单元，像素单元包括多个子像素，子像素包括主像素区（111）和副像素区（112）；其中，主像素区（111）处的绝缘层（12）厚度为第一厚度（d1），副像素区（112）处的绝缘层（12）厚度为第二厚度（d2），d1和d2满足：d1＞d2。

Description

显示装置、阵列基板及其工艺方法
相关申请
本申请要求2018年12月25日申请的，申请号为201811598647.3，名称为“显示装置、阵列基板及其工艺方法”的中国专利申请的优先权，在此将其全文引入作为参考。
技术领域
本申请涉及显示产品技术领域，特别涉及一种显示装置、阵列基板及其工艺方法。
背景技术
这里的陈述仅提供与本申请有关的背景信息，而不必然地构成相关技术。
液晶显示屏因液晶分子的轴向透光特性，在解决大视角色偏的技术课题上一直有新的解法出现。广视角主流技术多域垂直对准（Multi-domain Vertical Alignment，简称MVA）阵营多是采用将像素区分为亮区与暗区，以改善大视角的色偏效果，为了实现亮区和暗区，示例性技术采用电压分压的方式，即分别对像素的两个区域施加不同大小的电压，从而使该两个区域呈现不同的亮度，如此，要求每一像素中必须配置有复杂的电压分压结构，设计较为复杂。
发明内容
本申请的主要目的是提出一种阵列基板，旨在简化阵列基板的结构。
为实现上述目的，本申请提出的阵列基板，包括：
多个像素单元，所述像素单元包括多个子像素，所述子像素包括主像素区和副像素区；其中，
所述主像素区处的绝缘层厚度为第一厚度d1，所述副像素区处的绝缘层厚度为第二厚度d2，所述d1和d2满足：d1＞d2。
可选地，所述第一厚度d1与所述第二厚度d2的差值介于50nm~1000nm之间。
可选地，所述主像素区的面积小于或等于所述副像素区的面积。
可选地，所述主像素区的面积大于所述副像素区的面积。
可选地，所述主像素区与副像素区的控制电压相等。
可选地，所述主像素区与副像素区上像素电极的排布方式一致。
可选地，所述主像素区和所述副像素区内的像素电极均采用斜条纹图案的形式排布。
可选地，所述主像素区和所述副像素区覆盖有保护层。
本申请还提出一种阵列基板的工艺方法，包括以下步骤：
对光刻胶层的第一区域和第二区域进行显影，使第一区域相对绝缘层的蚀刻程度小于第二区域；
于所述第一区域和第二区域上设置像素电极，所述第一区域形成主像素区，所述第二区域形成副像素区。
可选地，所述对光刻胶的第一区域和第二区域进行显影，使第一区域相对绝缘层的蚀刻程度小于第二区域的步骤具体包括：
光源透过滤光罩的第一滤光部分照射到所述第一区域，光源透过滤光罩的第二滤光部分照射到所述第二区域，所述第一滤光部分的透光率小于所述第二部分。
可选地，所述对光刻胶的第一区域和第二区域进行显影，使第一区域相对绝缘层的蚀刻程度小于第二区域的步骤具体包括：
分别使用两不同光强的显影光源对所述第一区域和所述第二区域进行照射。
可选地，所述第一滤光部分的透光率为0%~10%，所述第二滤光部分的透光率为20%~40％。
可选地，所述第一滤光部分的透光率为0%，所述第二滤光部分的透光率为30%。
可选地，在所述于所述第一区域和第二区域上设置像素电极，所述第一区域形成主像素区，所述第二区域形成副像素区的步骤之后还包括：
于所述主像素区和副像素区朝向彩膜基板的一侧覆盖保护层。
本申请还提出一种显示装置，包括阵列基板，该阵列基板包括：
像素单元，所述像素单元的每一子像素包括主像素区和副像素区；其中，
所述主像素区处的绝缘层厚度为第一厚度d1，所述副像素区处的绝缘层厚度为第二厚度d2，所述d1和d2满足：d1＞d2。
可选地，所述显示面板包括与所述阵列基板匹配的彩膜基板，所述彩膜基板上设有对应所述主像素区和所述副像素区的公共电极，所述公共电极与所述主像素区和所述副像素区中的像素电极之间构成电容。
可选地，所述阵列基板与所述彩膜基板之间的间隔一致。
本申请技术方案阵列基板的子像素包括主像素区和副像素区，并通过将主像素区处背离彩膜基板一侧的绝缘层厚度设置为比副像素区大，如此，在阵列基板厚度一致、以及其与彩膜基板的间隔一致的情况下，使主像素区的像素电极与彩膜基板上公共电极的间距相对副像素区更小，继而使主像素区对应的电容大于副像素区的电容，在施加同等电压的情况下，主像素区的亮度大于副像素区，在不引入分压结构的情况下，实现子像素亮区和暗区的划分，改善大视角情况下的色偏效果。
附图说明
为了更清楚地说明本申请实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图示出的结构获得其他的附图。
图1为本申请显示装置一实施例的阵列基板和彩膜基板的剖面示意图；
图2为图1中子像素的等效电路图；
图3为图2中像素电极与公共电极施加电压的等效电路图；
图4为本申请阵列基板的工艺方法的加工示意图；
图5为图4中阵列基板的工艺方法的流程示意图。
本申请目的的实现、功能特点及优点将结合实施例，参照附图做进一步说明。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
需要说明，若本申请实施例中有涉及方向性指示（诸如上、下、左、右、前、后……），则该方向性指示仅设置为解释在某一特定姿态（如附图所示）下各部件之间的相对位置关系、运动情况等，如果该特定姿态发生改变时，则该方向性指示也相应地随之改变。
另外，若本申请实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅设置为描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本申请要求的保护范围之内。
本申请提出一种阵列基板以及具有该阵列基板的显示面板，该显示面板包括但不限于液晶显示面板、有机发光二极管显示面板、场发射显示面板、等离子显示面板、曲面型面板，液晶面板包括薄膜晶体管液晶显示面板、TN面板、VA类面板、IPS面板等。
参照图1至图3，本实施例中，该显示面板为液晶显示面板，其包括该阵列基板100、及与该阵列基板100匹配的彩膜基板200。在本申请实施例中，该阵列基板100包括：
多个像素单元，像素单元包括多个子像素，子像素包括主像素区111和副像素区112；其中，
主像素区111处背离彩膜基板200一侧的绝缘层12厚度为第一厚度d1，副像素区112处背离彩膜基板200一侧的绝缘层12厚度为第二厚度d2，d1和d2满足：d1＞d2。
参照图1至图3，可以理解，彩膜基板200上设有对应主像素区111和副像素区112的公共电极，公共电极与主像素区111和副像素区112中的像素电极2之间构成电容，根据电容公式：
C=Q/U=εS/4πd
式中：C——电容量(F)
Q——一个电极板上储存的电荷（C）
U——个电极板上的电位差（V）
ε——绝缘介质的介电常数
S——金属极板的面积（ m 2）
d——极板间的距离（cm）
可知，电容大小与公共电极、像素电极2之间的间距成反比，而在阵列基板100总厚度一定的情况下，显示区背离彩膜基板200一侧的绝缘层12厚度越大，公共电极与像素电极2之间的间距就越小，由于d1＞d2，则主像素区111的电容会大于副像素区112的电容，因此，在对主像素区111和副像素区112施加同等电压的情况下，主像素区111的亮度会大于副像素区112的亮度，即实现了子像素亮区、暗区的划分，以改善大视角的色偏效果，而由于对子像素所施加的控制电压相等， 因此也无需额外引入分压结构，从而简化了阵列基板100的整体结构，有利于降低阵列基板100的生产造价。
本实施例中，通过调整阵列基板100制程的工艺，特别针对像素绝缘层12使用半色调工艺，以达到主像素区111和副像素区112绝缘层12厚度不一致的效果。具体地，参照图1至图3，首先，将光刻胶层11、绝缘层12以及玻璃层14依次由上至下叠放，将显影光源朝向光刻胶层11照射，且显影光源与光刻胶层11之间隔设有一滤光罩3，该滤光罩3包括第一滤光部分31和第二滤光部分32，第一滤光部分31与第二滤光部分32的透光率不同，以使光刻胶层11对应第一滤光部分31的第一区域和对应第二滤光部分32的第二区域在经过照射后，相对绝缘层12呈现不同的蚀刻程度，两者之间表现为呈台阶状设置，待到光刻胶层11完成蚀刻后，光刻胶层11即成为绝缘层12的一部分，于较高的台阶面上铺设像素电极2，以形成子像素的主像素区111，于较低的台阶面上铺设像素电极2，以形成子像素的副像素区112，最后，再对主像素区111和副像素区112覆盖有保护层13，以一方面对像素电极2与公共电极之间形成绝缘隔离，另一方面保护像素电极2不受到外界结构的磕碰。可以理解，如此设置，通过调整阵列基板100工艺的方式，有效改变子像素不同分区的绝缘层12厚度，从而实现亮区和暗区的划分。应当说明的是，本设计不限于此，于其他实施例中，还可具体通过其他工艺方法，来改变子像素中主像素区111和副像素区112所对应的绝缘层12厚度。
本申请技术方案阵列基板100的子像素包括主像素区111和副像素区112，并通过将主像素区111处背离彩膜基板200一侧的绝缘层12厚度设置为比副像素区112大，如此，在阵列基板100厚度一致、以及其与彩膜基板200的间隔一致的情况下，使主像素区111的像素电极2与彩膜基板200上公共电极的间距相对副像素区112更小，继而使主像素区111对应的电容大于副像素区112的电容，在施加同等电压的情况下，主像素区111的亮度大于副像素区112，在不引入分压结构的情况下，实现子像素亮区和暗区的划分，改善大视角情况下的色偏效果。
本实施例中，第一厚度d1与第二厚度d2的差值介于50nm~1000nm之间。可以理解，d1和d2差值过大，会导致主像素区111与副像素区112之间亮度差异过大，继而影响到显示面板的整体成像效果，而d1和d2差值过小，又会导致主像素区111与副像素区112之间亮度差异过小，其对大视角情况下的色偏改善效果太微弱。具体地，第一滤光部分31的透光率为0%，第二滤光部分32的透光率为30%，即光刻胶层11的第一区域完全未溶入绝缘层12内，而第二区域部分溶入绝缘层12内，如此，能够使d1与d2的差值满足在50nm~1000nm之间；当然，于其他实施例中，第一滤光部分31的透光率、第二滤光部分32的透光率还可具体为其他数值，本设计不限于此。
进一步地，主像素区111的面积小于或等于副像素区112的面积。可以理解，如此设置，相对于子像素而言，有利于避免子像素的整体亮度过大，继而影响显示面板的整体成像效果。应当说明的是，本设计不限于此，于其他实施例中，主像素区111的面积也可大于副像素区112的面积。
进一步地，主像素区111与副像素区112上像素电极2的排布方式一致。可以理解，如此设置，有利于简化子像素的整体结构设计，继而降低阵列基板100的生产造价。不失一般性，主像素区111和副像素区112内的像素电极2均采用斜条纹图案的形式排布，可以理解，斜条纹图案的排布形式是现有像素电极2广泛采用的方式；当然，于其他实施例中，主像素区111和副像素区112内的像素电极2还可采用其他方式排布，本设计不限于此。
参照图4和图5，本申请还提出一种阵列基板的工艺方法，包括以下步骤：
步骤S1、对光刻胶层11的第一区域和第二区域进行显影，使第一区域相对绝缘层12的蚀刻程度小于第二区域；
可以理解，在显影过程中，第一区域和第二区域相对绝缘层12的蚀刻程度不同，后期即会导致两者各自与彩膜基板200之间的间隔不同。
步骤S2、于第一区域和第二区域上设置像素电极2，第一区域形成主像素区111，第二区域形成副像素区112。
可以理解，完成显影后，光刻胶层11成为绝缘层12的一部分，因此，主像素区111处的绝缘层12厚度大于副像素区112，以致主像素区111的像素电极2与彩膜基板200上的公共电极的距离更近，根据C=Q/U=εS/4πd可知，其产生的电容相较于副像素区112更大，从而在与副像素区112施加的控制电压相同的情况下，能呈现更大的亮度，换言之，主像素区111和副像素区112实现了亮区和暗区的划分，在无需分压结构的情况下，达到了大视角改善色偏的效果。
进一步地，对光刻胶层11的第一区域和第二区域进行显影，使第一区域相对绝缘层12的蚀刻程度小于第二区域的步骤具体包括：光源透过滤光罩3的第一滤光部分31照射到第一区域，光源透过滤光罩3的第二滤光部分32照射到第二区域，第一滤光部分31的透光率小于第二部分。
可以理解，如此设置，能够方便、快捷地改变第一区域和第二区域相对绝缘层12的蚀刻程度，从而使两者之间呈台阶状设置。应当说明的是，本设计不限于此，于其他实施例中，分别使用两不同光强的显影光源对第一区域和第二区域进行照射，以使第一区域相对绝缘层12的蚀刻程度小于第二区域。
进一步地，第一滤光部分31的透光率为0%~10%，第二滤光部分32的透光率为20%~40%。可以理解，第一滤光部分31和第二滤光部分32透光率的不同，对应的是主像素区111和副像素区112所在位置处绝缘层12厚度的不同，差值过大，会导致主像素区111与副像素区112之间亮度差异过大，继而影响到显示面板的整体成像效果，而差值过小，又会导致主像素区111与副像素区112之间亮度差异过小，其对大视角情况下的色偏改善效果太微弱。例如但不限于，第一滤光部分31的透光率为0%，第二滤光部分32的透光率为30%，当然，于其他实施例中，第一滤光部分31的透光率、第二滤光部分32的透光率还可具体为其他数值，本设计不限于此。
进一步地，在于第一区域和第二区域上设置像素电极2，第一区域形成主像素区111，第二区域形成副像素区112的步骤之后还包括：步骤S3、于主像素区111和副像素区112朝向彩膜基板200的一侧覆盖保护层13。可以理解，如此设置，一方面，对像素电极2与彩膜基板200的公共电极之间形成绝缘隔离，另一方面，也能有效保护像素电极2不受到外界结构的磕碰。
本申请还提出一种显示装置，该显示装置包括阵列基板，该阵列基板的具体结构参照上述实施例，由于本显示装置采用了上述所有实施例的全部技术方案，因此至少具有上述实施例的技术方案所带来的所有有益效果，在此不再一一赘述。
以上所述仅为本申请的可选实施例，并非因此限制本申请的专利范围，凡是在本申请的申请构思下，利用本申请说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本申请的专利保护范围内。

Claims (17)

  1. 一种阵列基板，其中，包括：
    多个像素单元，所述像素单元包括多个子像素，所述子像素包括主像素区和副像素区；其中，
    所述主像素区处的绝缘层厚度为第一厚度d1，所述副像素区处的绝缘层厚度为第二厚度d2，所述d1和d2满足：d1＞d2。
  2. 如权利要求1所述的阵列基板，其中，所述第一厚度d1与所述第二厚度d2的差值介于50nm~1000nm之间。
  3. 如权利要求1所述的阵列基板，其中，所述主像素区的面积小于或等于所述副像素区的面积。
  4. 如权利要求1所述的阵列基板，其中，所述主像素区的面积大于所述副像素区的面积。
  5. 如权利要求1所述的阵列基板，其中，所述主像素区与所述副像素区的控制电压相等。
  6. 如权利要求1所述的阵列基板，其中，所述主像素区与所述副像素区上像素电极的排布方式一致。
  7. 如权利要求1所述的阵列基板，其中，所述主像素区和所述副像素区内的像素电极均采用斜条纹图案的形式排布。
  8. 如权利要求1所述的阵列基板，其中，所述主像素区和所述副像素区覆盖有保护层。
  9. 一种阵列基板的工艺方法，其中，包括以下步骤：
    对光刻胶层的第一区域和第二区域进行显影，使第一区域相对绝缘层的蚀刻程度小于第二区域；
    于所述第一区域和第二区域上设置像素电极，所述第一区域形成主像素区，所述第二区域形成副像素区。
  10. 如权利要求9所述的阵列基板的工艺方法，其中，所述对光刻胶的第一区域和第二区域进行显影，使第一区域相对绝缘层的蚀刻程度小于第二区域的步骤具体包括：
    光源透过滤光罩的第一滤光部分照射到所述第一区域，光源透过滤光罩的第二滤光部分照射到所述第二区域，所述第一滤光部分的透光率小于所述第二滤光部分。
  11. 如权利要求10所述的阵列基板的工艺方法，其中，所述对光刻胶的第一区域和第二区域进行显影，使第一区域相对绝缘层的蚀刻程度小于第二区域的步骤具体包括：
    分别使用两不同光强的显影光源对所述第一区域和所述第二区域进行照射。
  12. 如权利要求11所述的阵列基板的工艺方法，其中，所述第一滤光部分的透光率为0%~10％，所述第二滤光部分的透光率为20%~40％。
  13. 如权利要求12所述的阵列基板的工艺方法，其中，所述第一滤光部分的透光率为0%，所述第二滤光部分的透光率为30%。
  14. 如权利要求10所述的阵列基板的工艺方法，其中，在所述于所述第一区域和第二区域上设置像素电极，所述第一区域形成主像素区，所述第二区域形成副像素区的步骤之后还包括：
    于所述主像素区和副像素区朝向彩膜基板的一侧覆盖保护层。
  15. 一种显示装置，其中，包括阵列基板，所述阵列基板包括：
    多个像素单元，所述像素单元包括多个子像素，所述子像素包括主像素区和副像素区；其中，
    所述主像素区处的绝缘层厚度为第一厚度d1，所述副像素区处的绝缘层厚度为第二厚度d2，所述d1和d2满足：d1＞d2。
  16. 如权利要求15所述的显示装置，其中，所述显示面板包括与所述阵列基板匹配的彩膜基板，所述彩膜基板上设有对应所述主像素区和所述副像素区的公共电极，所述公共电极与所述主像素区和所述副像素区中的像素电极之间构成电容。
  17. 如权利要求16所述的显示装置，其中，所述阵列基板与所述彩膜基板之间的间隔一致。
PCT/CN2019/124265 2018-12-25 2019-12-10 显示装置、阵列基板及其工艺方法 WO2020135023A1 (zh)

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