CN105807520A - 3t像素结构及液晶显示装置 - Google Patents

3t像素结构及液晶显示装置 Download PDF

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Publication number
CN105807520A
CN105807520A CN201610339274.2A CN201610339274A CN105807520A CN 105807520 A CN105807520 A CN 105807520A CN 201610339274 A CN201610339274 A CN 201610339274A CN 105807520 A CN105807520 A CN 105807520A
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China
Prior art keywords
thin film
film transistor
tft
insulating barrier
electrode
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CN201610339274.2A
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Inventor
姜祥卫
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Application filed by Shenzhen China Star Optoelectronics Technology Co Ltd filed Critical Shenzhen China Star Optoelectronics Technology Co Ltd
Priority to CN201610339274.2A priority Critical patent/CN105807520A/zh
Priority to PCT/CN2016/086008 priority patent/WO2017197693A1/zh
Priority to US15/121,927 priority patent/US10254610B2/en
Publication of CN105807520A publication Critical patent/CN105807520A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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Abstract

本发明提供一种3T像素结构及液晶显示装置，该3T像素结构包括：一基板，其上形成有下公共电极以及扫描线；第一绝缘层，其设置于该下公共电极、扫描线以及基板上；电荷共享薄膜晶体管，其具有源极、漏极以及栅极，该电荷共享薄膜晶体管的源极、漏极均设置于该第一绝缘层上；数据线，其设置于该第一绝缘层上；第二绝缘层，其设置于数据线以及所述第一绝缘层上；上公共电极，其设置于第二绝缘层上；第二绝缘层上开设有源极通孔，上公共电极通过源极通孔与第一源极接触并电连接。本发明将电荷共享薄膜晶体管的源极直接与上公共电极通过该第二绝缘层上的源极通孔电连接，从而避免在像素结构内出现深孔与浅孔的交叠，从而增大了开口率。

Description

3T像素结构及液晶显示装置
技术领域
本发明涉及液晶显示领域，特别是涉及一种3T像素结构及液晶显示装置。
背景技术
随着液晶显示器亮度、视角、对比度、响应速度等特性的要求越来越高，更多的液晶产品由TN型转到IPS(FFS)或者VA型。而随着精细度的提高，像素的尺寸越来越小。同样的设计前提下，像素开口率也会越越小，影响显示亮度。VA产品3T结构设计被提了出来，它通过去掉Sub-Pixel上的Via孔提升开口率。但因为在Pixel内引入深浅孔，过孔的直径增大，COA产品要求像素结构内过孔CD也相应增大。同时Pixel内深浅孔交叠，对PhotoOverlay及刻蚀也提出了很高的要求，有极大的良率损失风险。
因此，现有技术存在缺陷，急需改进。
发明内容
本发明的目的在于提供一种3T像素结构及液晶显示装置；以解决现有技术中3T像素结构及液晶显示装置深浅孔交叠的技术问题。
为解决上述问题，本发明提供的技术方案如下：
本发明实施例提供一种3T像素结构，包括：
一基板，其上形成有下公共电极以及扫描线；
第一绝缘层，其设置于该下公共电极、扫描线以及基板上；
电荷共享薄膜晶体管，其具有源极、漏极以及栅极，该电荷共享薄膜晶体管的源极、漏极均设置于该第一绝缘层上；
数据线，其设置于该第一绝缘层上；
第二绝缘层，其设置于电荷共享薄膜晶体管的源极和漏极、数据线以及所述第一绝缘层上；
上公共电极，其设置于所述第二绝缘层上；
所述第二绝缘层上开设有源极通孔，所述上公共电极通过所述源极通孔与所述第一源极接触并电连接。
在本发明所述的3T像素结构中，还包括第三绝缘层以及像素电极层，所述第三绝缘层设置于所述公共电极以及第二绝缘层上，所述像素电极层设置于所述第三绝缘层上。
在本发明所述的3T像素结构中，还包括主像素薄膜晶体管以及次像素薄膜晶体管，所述主像素薄膜晶体管和次像素薄膜晶体管的源极、漏极以及栅极均设置于所述第一绝缘层上，该第一栅极设置于所述第二绝缘层上。
在本发明所述的3T像素结构中，所述主像素薄膜晶体管的源极、所述次像素薄膜晶体管的漏极均与该数据线电连接，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极电连接，所述主像素薄膜晶体管、所述次像素薄膜晶体管以及所述电荷共享薄膜晶体管的栅极均与所述扫描线电连接。
在本发明所述的3T像素结构中，还包括第一存储电容以及第二存储电容，所述第一存储电容由设置于所述第一绝缘层上的第一极板以及所述下公共电极上的与该第一极板正对的部分形成，所述第二存储电容由设置于所述第一绝缘层上的第二极板以所述下公共电极上的与该第二极板正对的部分形成，所述第一极板与所述主像素薄膜晶体管的漏极电连接，所述第二极板与所述次像素薄膜晶体管的源极以及所述电荷共享薄膜晶体管的漏极电连接。
在本发明所述的3T像素结构中，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极接触并电连接，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极的公共节点与所述第二极板电连接。
在本发明所述的3T像素结构中，所述基板为透明玻璃基板或透明塑料基板。
在本发明所述的3T像素结构中，所述上公共电极呈网格状分布。
在本发明所述的3T像素结构中，所述第一绝缘层、所述第二绝缘层采用氮化硅和/或二氧化硅。
本发明还提供了一种液晶显示装置，其包括上述任一项所述的3T像素结构。
相对于现有技术，相对于现有技术中的将电荷共享薄膜晶体管的源极通过深孔以及浅孔配合从而与下公共电极电连接，本发明将电荷共享薄膜晶体管的源极直接与上公共电极通过该第二绝缘层上的源极通孔电连接，从而避免在像素结构内出现深孔与浅孔的交叠，从而增大了开口率。
进一步地，由于该次像素薄膜晶体管的源极以及该电荷共享薄膜晶体管的漏极直接接触并电连接，在次像素薄膜晶体管与电荷共享薄膜晶体管内电阻同时波动，内电阻比值变化小，对Mura影响小，并且还可以减小寄生电容。
附图说明
图1为本发明的3T像素结构的一优选实施例的结构示意图；
图2为图1所示实施例中的3T像素结构的局部平面透视结构示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
图1是本发明一优选实施例中的3T像素结构的结构示意图。请同时参照图1以及图2所示，本优选实施例中的3T像素结构包括：基板10、下公共电极20、扫描线(未示出)、第一绝缘层30、主像素薄膜晶体管T1、次像素薄膜晶体管T2、电荷共享薄膜晶体管T3、数据线80、第二绝缘层40、上公共电极50、第三绝缘层60以及像素电极层70。
其中，该下公共电极20以及扫描线均设置于基板10上。
数据线80设置于第一绝缘层30上。主像素薄膜晶体管T1、次像素薄膜晶体管T2、电荷共享薄膜晶体管T3设置于该第一绝缘层30上。第二绝缘层40设置于主像素薄膜晶体管T1、次像素薄膜晶体管T2、电荷共享薄膜晶体管T3、数据线80以及第一绝缘层30之上。上公共电极50设置于该第二绝缘层40上，该第三绝缘层60设置于该上公共电极50上，该像素电极层70设置于该第三绝缘层60上。
具体地，该主像素薄膜晶体管T1、次像素薄膜晶体管T2以及电荷共享薄膜晶体管T3均具有源极、漏极以及栅极。其中，该主像素薄膜晶体管T1、次像素薄膜晶体管T2以及电荷共享薄膜晶体管T3的源极、漏极以及栅极均设置于该第一绝缘层30上，当然该各个三极管的栅极可以设置于其他层，在此并不限定。
该主像素薄膜晶体管T1的源极以及该次像素薄膜晶体管T2的漏极均与该数据线80电连接。该主像素薄膜晶体管T1的源极为第二源极101。该次像素薄膜晶体管T2的源极与该电荷共享薄膜晶体管T3的漏极电连接，该次像素薄膜晶体管T2的源极为第三源极201，该电荷共享薄膜晶体管T3的漏极为第一漏极301。该电荷共享薄膜晶体管T3的源极为第一源极91，该第一源极91与上公共电极50电连接。在本实施例中，该第二绝缘层40开设有源极通孔41，该上公共电极50通过该源极通孔41与该第一源极91接触并电连接。相对于现有技术中，将该电荷共享薄膜晶体管T3的源极与下公共电极20连接，本实施例中的第一源极91直接与上公共电极50电连接，从而避免在像素结构内出现深孔与浅孔的交叠，从而增大了开口率，并可以消除因深浅孔交叠来带来的潜在不良现象。
该主像素薄膜晶体管T1、次像素薄膜晶体管T2以及电荷共享薄膜晶体管T3的栅极均与扫描线电连接。
其中，该第一绝缘层30上还设置有第一极板100以及第二极板200，该第一极板100与主像素薄膜晶体管T1的漏极也即是第二漏极102电连接，该第二极板200与该次像素薄膜晶体管T2的源极以及该电荷共享薄膜晶体管T3的漏极电连接。该3T像素结构的第一存储电容由该第一极板100以及下公共电极20上的与该第一极板100正对的部分形成，3T像素结构的第二存储电容由第二极板200以及该下公共电极20上的与该第二极板200正对的部分形成。
该第二绝缘40层开设有第一过孔43、第三绝缘层60开设有第二过孔(未示出)，该像素电极层70通过该第一过孔43以及该第二过孔与该第一极板100接触并电连接。该第二绝缘40层开设在有第三过孔42、第三绝缘层60开设有第四过孔，该像素电极层70通过该第三过孔42以及该第四过孔与该第二极板200接触并电连接。
优选地，该次像素薄膜晶体管T2的源极(第三源极201)以及该电荷共享薄膜晶体管T3的漏极(第一漏极301)直接接触并电连接，且其公共节点与该第二极板100电连接。相对于现有技术中将该次像素薄膜晶体管T2的源极与该电荷共享薄膜晶体管T3的漏极分离设置，本发明将电荷共享薄膜晶体管T3的漏极与次像素薄膜晶体管T2的源极连接设计，T2与T3内电阻同时波动，内电阻比值变化小，对Mura影响小。同时电荷共享薄膜晶体管T3的漏极与次像素薄膜晶体管T2的源极直接接触并电连接，可以减小寄生电容。
当然可以理解地，也可以将次像素薄膜晶体管T2的源极以及该电荷共享薄膜晶体管T3的漏极不直接接触，而采用分别与该第二极板200电连接。
其中，该基板10为透明玻璃基板或透明塑料基板。
其中，上公共电极50呈网格状分布。采用网格状的分布可以降低上公共电极50的局部断线造成的导电不良。
其中，第一绝缘层30、所述第二绝缘层40以及第三绝缘层60均分别采用氮化硅和/或二氧化硅并采用化学气象沉底制成。
在本优选实施例提供的3T像素结构中，采用将该电荷共享薄膜晶体管的源极(第一源极91)通过开设于该第二绝缘层上的源极通孔与该上公共电极接触并电连接，可以避免在像素结构内出现深孔与浅孔的交叠，从而增大了开口率，并可以消除因深浅孔交叠来带来的潜在不良现象。
进一步地，由于该次像素薄膜晶体管T2的源极(第三源极201)以及该电荷共享薄膜晶体管T3的漏极(第一漏极301)直接接触并电连接，在T2与T3内电阻同时波动，内电阻比值变化小，对Mura影响小，并且还可以减小寄生电容。
本发明还提供了一种液晶显示装置，其包括上述实施例中的3T像素结构。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。

Claims (10)

1.一种3T像素结构，其特征在于，包括：
一基板，其上形成有下公共电极以及扫描线；
第一绝缘层，其设置于该下公共电极、扫描线以及基板上；
电荷共享薄膜晶体管，其具有源极、漏极以及栅极，该电荷共享薄膜晶体管的源极、漏极均设置于该第一绝缘层上；
数据线，其设置于该第一绝缘层上；
第二绝缘层，其设置于电荷共享薄膜晶体管的源极和漏极、数据线以及所述第一绝缘层上；
上公共电极，其设置于所述第二绝缘层上；
所述第二绝缘层上开设有源极通孔，所述上公共电极通过所述源极通孔与所述第一源极接触并电连接。
2.根据权利要求1所述的3T像素结构，其特征在于，还包括第三绝缘层以及像素电极层，所述第三绝缘层设置于所述公共电极以及第二绝缘层上，所述像素电极层设置于所述第三绝缘层上。
3.根据权利要求1或2所述的3T像素结构，其特征在于，还包括主像素薄膜晶体管以及次像素薄膜晶体管，所述主像素薄膜晶体管和次像素薄膜晶体管的源极、漏极以及栅极均设置于所述第一绝缘层上，该电荷共享薄膜晶体管的栅极设置于所述第二绝缘层上。
4.根据权利要求3所述的3T像素结构，其特征在于，所述主像素薄膜晶体管的源极、所述次像素薄膜晶体管的漏极均与该数据线电连接，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极电连接，所述主像素薄膜晶体管、所述次像素薄膜晶体管以及所述电荷共享薄膜晶体管的栅极均与所述扫描线电连接。
5.根据权利要求1所述的3T像素结构，其特征在于，还包括第一存储电容以及第二存储电容，所述第一存储电容由设置于所述第一绝缘层上的第一极板以及所述下公共电极上的与该第一极板正对的部分形成，所述第二存储电容由设置于所述第一绝缘层上的第二极板以所述下公共电极上的与该第二极板正对的部分形成，所述第一极板与所述主像素薄膜晶体管的漏极电连接，所述第二极板与所述次像素薄膜晶体管的源极以及所述电荷共享薄膜晶体管的漏极电连接。
6.根据权利要求5所述的3T像素结构，其特征在于，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极接触并电连接，所述次像素薄膜晶体管的源极与所述电荷共享薄膜晶体管的漏极的公共节点与所述第二极板电连接。
7.根据权利要求1所述的3T像素结构，其特征在于，所述基板为透明玻璃基板或透明塑料基板。
8.根据权利要求1所述的3T像素结构，其特征在于，所述上公共电极呈网格状分布。
9.根据权利要求1所述的3T像素结构，其特征在于，所述第一绝缘层、所述第二绝缘层采用氮化硅和/或二氧化硅。
10.一种液晶显示装置，其特征在于，包括权利要求1-9任一项所述的3T像素结构。
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