CN104483792B - 阵列基板及显示装置 - Google Patents

阵列基板及显示装置 Download PDF

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CN104483792B
CN104483792B CN201410834652.5A CN201410834652A CN104483792B CN 104483792 B CN104483792 B CN 104483792B CN 201410834652 A CN201410834652 A CN 201410834652A CN 104483792 B CN104483792 B CN 104483792B
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CN104483792A (zh
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阙祥灯
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Abstract

本发明公开了一种阵列基板及显示装置，属于显示技术领域，改善了现有技术中分压电容影响像素单元的开口率的技术问题。该阵列基板，包括若干个像素单元，所述像素单元包括主像素区域、次像素区域、第一分压电容、驱动扫描线和分压扫描线；所述第一分压电容由分压电极与所述驱动扫描线重叠形成，或由分压电极与所述分压扫描线重叠形成。本发明可用于液晶电视、液晶显示器、手机、平板电脑等显示装置。

Description

阵列基板及显示装置
技术领域
本发明涉及显示技术领域，具体地说，涉及一种阵列基板及显示装置。
背景技术
随着显示技术的发展，液晶显示器已经成为最为常见的显示装置。
垂直排列(Vertical Alignment，简称VA)型液晶显示器是一种常见的液晶显示器。目前，为了改善VA型液晶显示器的大视角色偏现象，会将每个像素单元分为主像素区域和次像素区域，再增设分压电容。
如图1和图2所示，分压电容Cdown由公共电极线(Com)3的一部分与分压电极2重叠形成。在显示过程中，先利用驱动扫描线(Gate1)11打开第一晶体管T1和第二晶体管T2，由数据线(Data)4向主像素区域100中的主像素电极(图中未示出)和次像素区域200中的次像素电极(图中未示出)充入相同的电位。然后利用分压扫描线(Gate2)12打开第三晶体管T3，利用分压电容对次像素电极进行分压，使次像素电极的电位低于主像素电极。这样会使次像素区域200的亮度略低于主像素区域100，同时主像素区域100与次像素区域200中液晶分子的偏转角度也不同，从而改善了VA型液晶显示器的大视角色偏现象。
但是，由于公共电极线3和分压电极2都是由金属材料制成，因此分压电容会影响像素单元的开口率。特别是在当前分辨率越来越高，像素单元的面积越来越小的发展趋势下，现有的分压电容对开口率的影响更加明显。
发明内容
本发明的目的在于提供一种阵列基板及显示装置，以改善现有技术中分压电容影响像素单元的开口率的技术问题。
本发明提供一种阵列基板，包括若干个像素单元，所述像素单元包括主像素区域、次像素区域、第一分压电容、驱动扫描线和分压扫描线；
所述第一分压电容由分压电极与所述驱动扫描线重叠形成，或由分压电极与所述分压扫描线重叠形成。
进一步的是，所述像素单元中还包括第二分压电容和公共电极线；
所述第二分压电容由所述分压电极与所述公共电极线重叠形成。
优选的是，所述驱动扫描线、所述分压扫描线、所述公共电极线位于同一图层。
进一步的是，所述像素单元中还包括数据线，所述分压电极与所述数据线位于同一图层。
进一步的是，所述像素单元中还设置有第一晶体管、第二晶体管和第三晶体管；
所述第一晶体管的栅极连接所述驱动扫描线，源极连接所述数据线，漏极连接所述主像素区域中的主像素电极；
所述第二晶体管的栅极连接所述驱动扫描线，源极连接所述数据线，漏极连接所述次像素区域中的次像素电极；
所述第三晶体管的栅极连接所述分压扫描线，源极连接所述次像素电极，漏极连接所述分压电极。
优选的是，所述第三晶体管的漏极和所述分压电极为一体式结构。
本发明还提供一种显示装置，包括彩膜基板和上述的阵列基板。
优选的是，所述显示装置为垂直排列型显示装置。
本发明带来了以下有益效果：本发明提供的阵列基板中，像素单元中的第一分压电容由分压电极与驱动扫描线重叠形成，或由分压电极与分压扫描线重叠形成，而不是由分压电极与公共电极线重叠形成。这样能够减小像素单元中公共电极线的面积，同时也不需要增加驱动扫描线和分压扫描线的面积，从而提高了像素单元的开口率，改善了现有技术中分压电容影响像素单元的开口率的技术问题。
本发明的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得显而易见，或者通过实施本发明而了解。本发明的目的和其他优点可通过在说明书、权利要求书以及附图中所特别指出的结构来实现和获得。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要的附图做简单的介绍：
图1是现有的阵列基板中像素单元的示意图；
图2是现有的阵列基板中像素单元的电路图；
图3是本发明实施例一提供的阵列基板中像素单元的示意图；
图4是本发明实施例一提供的阵列基板中像素单元的电路图；
图5是本发明实施例一提供的阵列基板中像素单元的另一实施方式的示意图；
图6是本发明实施例一提供的阵列基板中像素单元的另一实施方式的电路图；
图7是本发明实施例二提供的阵列基板中像素单元的示意图；
图8是本发明实施例二提供的阵列基板中像素单元的电路图；
图9是本发明实施例二提供的阵列基板中像素单元的另一实施方式的示意图；
图10是本发明实施例二提供的阵列基板中像素单元的另一实施方式的电路图。
具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式，借此对本发明如何应用技术手段来解决技术问题，并达成技术效果的实现过程能充分理解并据以实施。需要说明的是，只要不构成冲突，本发明中的各个实施例以及各实施例中的各个特征可以相互结合，所形成的技术方案均在本发明的保护范围之内。
实施例一：
本发明实施例提供一种阵列基板，可应用于VA型液晶显示器中，该阵列基板中包括若干个像素单元。如图3和图4所示，像素单元包括主像素区域100、次像素区域200、第一分压电容Cdown1、驱动扫描线(Gate1)11和分压扫描线(Gate2)12。主像素区域100设置有主像素电极(图中未示出)，次像素区域200设置有次像素电极(图中未示出)。
本实施例中，第一分压电容由分压电极2与驱动扫描线11重叠形成。在显示过程中，各行像素单元的驱动扫描线11逐行扫描，所以在任意时刻，只有一条驱动扫描线11处于高电位，且任意一条驱动扫描线11处于高电位的时间非常短，即任意一条驱动扫描线11几乎一直处于低电位。因此，由分压电极2与驱动扫描线11重叠形成的第一分压电容，也能够对次像素电极起到很好的分压作用，使次像素区域的亮度略低于主像素区域，同时使主像素区域与次像素区域中液晶分子的偏转角度不同，从而改善VA型液晶显示器的大视角色偏现象。
本实施例中，像素单元中还包括公共电极线(Com)3、数据线(Data)4、第一晶体管T1、第二晶体管T2和第三晶体管T3。
其中，T1的栅极连接驱动扫描线11，源极连接数据线4，漏极连接主像素电极。在主像素区域100中，主像素电极与公共电极线3之间形成主存储电容Cst1，主像素电极与彩膜基板上的公共电极之间形成主液晶电容Clc1。
T2的栅极连接驱动扫描线11，源极连接数据线4，漏极连接次像素电极。在次像素区域200中，次像素电极与公共电极线3之间形成次存储电容Cst2，次像素电极与彩膜基板上的公共电极之间形成次液晶电容Clc2。
T3的栅极连接分压扫描线12，源极连接次像素电极，漏极连接分压电极2。分压电极2与驱动扫描线11之间形成第一分压电容。
作为一个优选方案，驱动扫描线11、分压扫描线12、公共电极线3位于同一图层，并且分压电极2与数据线4位于同一图层。在阵列基板的制造过程中，驱动扫描线11、分压扫描线12、公共电极线3可以在同一次构图工艺中同步制成，分压电极2和数据线4也可以在同一次构图工艺中同步制成，从而简化阵列基板的制造过程。因为T1、T2、T3的源极和漏极也都与数据线位于同一图层，所以作为进一步的优选方案，T3的漏极和分压电极可以为一体式结构。
在显示过程中，先打开驱动扫描线11，关闭分压扫描线12，使T1和T2导通，T3关闭，同时由数据线4通过T1和T2分别向主像素电极和次像素电极充入相等的数据电压，使Clc1、Cst1、Clc2和Cst2具有相等的电压。然后关闭驱动扫描线11，打开分压扫描线12，使T1和T2关闭，T3导通，Cdown1就会通过T3对次像素电极进行分压，降低次像素电极上的数据电压，使Clc2和Cst2的电压降低，而Clc1和Cst1的电压保持不变。此时，Clc2的电压低于Clc1的电压，使次像素区域的亮度略低于主像素区域，同时使主像素区域与次像素区域中液晶分子的偏转角度不同，从而改善VA型液晶显示器的大视角色偏现象。
本发明实施例提供的阵列基板中，像素单元中的第一分压电容由分压电极2与驱动扫描线11重叠形成，而不是由分压电极2与公共电极线3重叠形成。这样能够减小像素单元中公共电极线3的面积，同时也不需要增加驱动扫描线11的面积，从而提高了像素单元的开口率，改善了现有技术中分压电容影响像素单元的开口率的技术问题。
在另一种实施方式中，像素单元中还可以包括第二分压电容Cdown2，如图5和图6所示，第二分压电容由分压电极2与公共电极线3重叠形成。由第一分压电容和第二分压电容共同对次像素电极进行分压，能够进一步降低次像素电极上的电压，从而在更多程度上改善VA型液晶显示器的大视角色偏现象。
当然，用于形成该第二分压电容的公共电极线3的面积也很小，相比于现有技术，仍然显著减小了公共电极线3的面积，从而提高了像素单元的开口率，改善了现有技术中分压电容影响像素单元的开口率的技术问题。
实施例二：
本发明实施例提供一种阵列基板，可应用于VA型液晶显示器中，该阵列基板中包括若干个像素单元。如图7和图8所示，像素单元包括主像素区域100、次像素区域200、第一分压电容Cdown1、驱动扫描线(Gate1)11和分压扫描线(Gate2)12。主像素区域100设置有主像素电极(图中未示出)，次像素区域200设置有次像素电极(图中未示出)。
本实施例中，第一分压电容由分压电极2与分压扫描线12重叠形成。在显示过程中，各行像素单元的分压扫描线12逐行扫描，所以在任意时刻，只有一条分压扫描线12处于高电位，且任意一条分压扫描线12处于高电位的时间非常短，即任意一条分压扫描线12几乎一直处于低电位。因此，由分压电极2与分压扫描线12重叠形成的第一分压电容，也能够对次像素电极起到很好的分压作用，使次像素区域的亮度略低于主像素区域，同时使主像素区域与次像素区域中液晶分子的偏转角度不同，从而改善VA型液晶显示器的大视角色偏现象。
本实施例中，像素单元中还包括公共电极线(Com)3、数据线(Data)4、第一晶体管T1、第二晶体管T2和第三晶体管T3。
其中，T1的栅极连接驱动扫描线11，源极连接数据线4，漏极连接主像素电极。在主像素区域100中，主像素电极与公共电极线3之间形成主存储电容Cst1，主像素电极与彩膜基板上的公共电极之间形成主液晶电容Clc1。
T2的栅极连接驱动扫描线11，源极连接数据线4，漏极连接次像素电极。在次像素区域200中，次像素电极与公共电极线3之间形成次存储电容Cst2，次像素电极与彩膜基板上的公共电极之间形成次液晶电容Clc2。
T3的栅极连接分压扫描线12，源极连接次像素电极，漏极连接分压电极2。分压电极2与分压扫描线12之间形成第一分压电容。
作为一个优选方案，驱动扫描线11、分压扫描线12、公共电极线3位于同一图层，并且分压电极2与数据线4位于同一图层。在阵列基板的制造过程中，驱动扫描线11、分压扫描线12、公共电极线3可以在同一次构图工艺中同步制成，分压电极2和数据线4也可以在同一次构图工艺中同步制成，从而简化阵列基板的制造过程。因为T1、T2、T3的源极和漏极也都与数据线位于同一图层，所以作为进一步的优选方案，T3的漏极和分压电极可以为一体式结构。
在显示过程中，先打开驱动扫描线11，关闭分压扫描线12，使T1和T2导通，T3关闭，同时由数据线4通过T1和T2分别向主像素电极和次像素电极充入相等的数据电压，使Clc1、Cst1、Clc2和Cst2具有相等的电压。然后关闭驱动扫描线11，打开分压扫描线12，使T1和T2关闭，T3导通，Cdown1就会通过T3对次像素电极进行分压，降低次像素电极上的数据电压，使Clc2和Cst2的电压降低，而Clc1和Cst1的电压保持不变。此时，Clc2的电压低于Clc1的电压，使次像素区域的亮度略低于主像素区域，同时使主像素区域与次像素区域中液晶分子的偏转角度不同，从而改善VA型液晶显示器的大视角色偏现象。
本发明实施例提供的阵列基板中，像素单元中的第一分压电容由分压电极2与分压扫描线12重叠形成，而不是由分压电极2与公共电极线3重叠形成。这样能够减小像素单元中公共电极线3的面积，同时也不需要增加分压扫描线12的面积，从而提高了像素单元的开口率，改善了现有技术中分压电容影响像素单元的开口率的技术问题。
在另一种实施方式中，像素单元中还可以包括第二分压电容Cdown2，如图9和图10所示，第二分压电容由分压电极2与公共电极线3重叠形成。由第一分压电容和第二分压电容共同对次像素电极进行分压，能够进一步降低次像素电极上的电压，从而在更多程度上改善VA型液晶显示器的大视角色偏现象。
当然，用于形成该第二分压电容的公共电极线3的面积也很小，相比于现有技术，仍然显著减小了公共电极线3的面积，从而提高了像素单元的开口率，改善了现有技术中分压电容影响像素单元的开口率的技术问题。
实施例三：
本发明实施例提供一种显示装置，优选为VA型显示装置，具体可以是液晶电视、液晶显示器、手机、平板电脑等。该显示装置包括彩膜基板和上述本发明实施例提供的阵列基板。
本发明实施例提供的显示装置，与上述实施例一、实施例二提供的阵列基板具有相同的技术特征，所以也能解决相同的技术问题，达到相同的技术效果。
虽然本发明所公开的实施方式如上，但所述的内容只是为了便于理解本发明而采用的实施方式，并非用以限定本发明。任何本发明所属技术领域内的技术人员，在不脱离本发明所公开的精神和范围的前提下，可以在实施的形式上及细节上作任何的修改与变化，但本发明的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (7)

1.一种阵列基板，包括若干个像素单元，所述像素单元包括主像素区域、次像素区域、第一分压电容、驱动扫描线和分压扫描线；
所述第一分压电容由分压电极与所述分压扫描线重叠形成，
所述像素单元中还包括第二分压电容和公共电极线；
所述第二分压电容由所述分压电极与所述公共电极线重叠形成。
2.根据权利要求1所述的阵列基板，其特征在于，所述驱动扫描线、所述分压扫描线、所述公共电极线位于同一图层。
3.根据权利要求1所述的阵列基板，其特征在于，所述像素单元中还包括数据线，所述分压电极与所述数据线位于同一图层。
4.根据权利要求3所述的阵列基板，其特征在于，所述像素单元中还设置有第一晶体管、第二晶体管和第三晶体管；
所述第一晶体管的栅极连接所述驱动扫描线，源极连接所述数据线，漏极连接所述主像素区域中的主像素电极；
所述第二晶体管的栅极连接所述驱动扫描线，源极连接所述数据线，漏极连接所述次像素区域中的次像素电极；
所述第三晶体管的栅极连接所述分压扫描线，源极连接所述次像素电极，漏极连接所述分压电极。
5.根据权利要求4所述的阵列基板，其特征在于，所述第三晶体管的漏极和所述分压电极为一体式结构。
6.一种显示装置，包括彩膜基板和如权利要求1至5任一项所述的阵列基板。
7.如权利要求6所述的显示装置，其特征在于，所述显示装置为垂直排列型显示装置。
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