WO2021103130A1 - 像素驱动电路和液晶显示面板 - Google Patents

像素驱动电路和液晶显示面板 Download PDF

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Publication number
WO2021103130A1
WO2021103130A1 PCT/CN2019/124177 CN2019124177W WO2021103130A1 WO 2021103130 A1 WO2021103130 A1 WO 2021103130A1 CN 2019124177 W CN2019124177 W CN 2019124177W WO 2021103130 A1 WO2021103130 A1 WO 2021103130A1
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WIPO (PCT)
Prior art keywords
transistor
electrode
liquid crystal
sub
pixel unit
Prior art date
Application number
PCT/CN2019/124177
Other languages
English (en)
French (fr)
Inventor
郝思坤
Original Assignee
武汉华星光电半导体显示技术有限公司
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Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US16/770,990 priority Critical patent/US20210166649A1/en
Publication of WO2021103130A1 publication Critical patent/WO2021103130A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix

Definitions

  • This application relates to the field of display technology, and in particular to a pixel drive circuit and a liquid crystal display panel.
  • the existing liquid crystal display panel has a technical problem that the aperture ratio caused by the solution of the color shift is small, and the display effect is affected.
  • the present application provides a pixel driving circuit and a liquid crystal display panel, which are used to solve the technical problem that the existing liquid crystal display panel has a small aperture ratio caused by solving the color shift and affects the display effect.
  • the present application provides a pixel driving circuit.
  • the pixel driving circuit includes a plurality of scan lines and a plurality of data lines, the plurality of scan lines and the plurality of data lines define a plurality of sub-pixel units, and at least one of the sub-pixel units is connected One scan line and one data line, and the sub-pixel unit includes:
  • the first common electrode terminal
  • the main sub-pixel unit includes a first transistor, a first storage capacitor, and a first liquid crystal capacitor;
  • the sub-pixel unit includes a second transistor, a second storage capacitor, and a second liquid crystal capacitor;
  • a third transistor, the second electrode of the third transistor is connected to the first common electrode terminal;
  • the gates of the first transistor, the second transistor, and the third transistor are connected to the scan line, one electrode of the first transistor is connected to the first electrode of the second transistor, and the second transistor of the second transistor is connected to the scan line.
  • the two electrodes are connected to the first electrode of the third transistor.
  • the first electrode of the first transistor is connected to the data line, and the second electrode of the first transistor is connected to the first electrode of the second transistor.
  • the first transistor is connected in series with the first storage capacitor, and the first transistor is connected in series with the first liquid crystal capacitor.
  • the first plate of the first storage capacitor is connected to the second electrode of the first transistor, and the second plate of the first storage capacitor is connected to the first common electrode terminal. connection.
  • the pixel drive circuit further includes a second common electrode terminal, the first plate of the first liquid crystal capacitor is connected to the second electrode of the first transistor, and the first liquid crystal The second plate of the capacitor is connected to the second common electrode terminal.
  • the second transistor is connected in series with the second storage capacitor, and the second transistor is connected in series with the second liquid crystal capacitor.
  • the first plate of the second storage capacitor is connected to the second electrode of the second transistor, and the second plate of the second storage capacitor is connected to the first common electrode.
  • the electrode terminal is connected.
  • the first plate of the second liquid crystal capacitor is connected to the second electrode of the second transistor, and the second plate of the second liquid crystal capacitor is connected to the second common electrode.
  • the electrode terminal is connected.
  • the first electrode of the first transistor is connected to the data line
  • the first electrode of the second transistor is connected to the data line
  • the first electrode of the first transistor is connected to the data line.
  • the electrode is connected to the first electrode of the second transistor.
  • the sub-pixel unit includes a main sub-pixel unit and a sub-sub-pixel unit, the main sub-pixel unit includes 4 domains, and the sub-sub-pixel unit includes 4 domains.
  • the present application provides a liquid crystal display panel.
  • the liquid crystal display panel includes a pixel drive circuit.
  • the pixel drive circuit includes a plurality of scan lines and a plurality of data lines.
  • At least one sub-pixel unit is connected to one scan line and one data line, and the sub-pixel unit includes:
  • the first common electrode terminal
  • the main sub-pixel unit includes a first transistor, a first storage capacitor, and a first liquid crystal capacitor;
  • the sub-pixel unit includes a second transistor, a second storage capacitor, and a second liquid crystal capacitor;
  • a third transistor, the second electrode of the third transistor is connected to the first common electrode terminal;
  • the gates of the first transistor, the second transistor, and the third transistor are connected to the scan line, one electrode of the first transistor is connected to the first electrode of the second transistor, and the second transistor of the second transistor is connected to the scan line.
  • the two electrodes are connected to the first electrode of the third transistor.
  • the first electrode of the first transistor is connected to the data line
  • the second electrode of the first transistor is connected to the first electrode of the second transistor.
  • the first transistor is connected in series with the first storage capacitor, and the first transistor is connected in series with the first liquid crystal capacitor.
  • the first plate of the first storage capacitor is connected to the second electrode of the first transistor, and the second plate of the first storage capacitor is connected to the first common electrode terminal. connection.
  • liquid crystal display panel provided by the present application, it further includes a second common electrode terminal, the first plate of the first liquid crystal capacitor is connected to the second electrode of the first transistor, and the second electrode of the first liquid crystal capacitor The electrode plate is connected to the second common electrode terminal.
  • the second transistor is connected in series with the second storage capacitor, and the second transistor is connected in series with the second liquid crystal capacitor.
  • the first plate of the second storage capacitor is connected to the second electrode of the second transistor, and the second plate of the second storage capacitor is connected to the first common electrode.
  • the electrode terminal is connected.
  • the first plate of the second liquid crystal capacitor is connected to the second electrode of the second transistor, and the second plate of the second liquid crystal capacitor is connected to the second common electrode.
  • the electrode terminal is connected.
  • the first electrode of the first transistor is connected to the data line
  • the first electrode of the second transistor is connected to the data line
  • the first electrode of the first transistor is connected to the data line.
  • the electrode is connected to the first electrode of the second transistor.
  • the sub-pixel unit includes a main sub-pixel unit and a sub-sub-pixel unit, the main sub-pixel unit includes 4 domains, and the sub-sub-pixel unit includes 4 domains.
  • the present application provides a pixel driving circuit and a liquid crystal display panel.
  • the pixel driving circuit includes a plurality of scan lines and a plurality of data lines, and the plurality of scan lines and the plurality of data lines define a plurality of sub-pixel units, at least one of the The sub-pixel unit is connected to a scan line and a data line.
  • the sub-pixel unit includes a first common electrode terminal, a main sub-pixel unit, a sub-sub-pixel unit, and a third transistor.
  • the main sub-pixel unit includes a first transistor, a first storage A capacitor and a first liquid crystal capacitor; the sub-sub-pixel unit includes a second transistor, a second storage capacitor, and a second liquid crystal capacitor; the second electrode of the third transistor is electrically connected to the first common electrode terminal, wherein the first The gates of a transistor, a second transistor, and a third transistor are connected to the scan line, one electrode of the first transistor is connected to the first electrode of the second transistor, and the second electrode of the second transistor is connected to the The first electrode of the third transistor; the main sub-pixel unit and the sub-sub-pixel unit are controlled by using the first, second, and third transistors, and the gates of the first, second, and third transistors are connected to the scan The three transistors can be controlled by one scan line, and the second electrode of the third transistor is connected to the first common electrode terminal, so that after the voltage signal passes through the first transistor, the second transistor, and the third transistor, the third transistor Connecting the first common electrode terminal causes a potential difference between the main sub-pixel and
  • FIG. 1 is a first schematic diagram of a conventional pixel driving circuit.
  • FIG. 2 is a second schematic diagram of a conventional pixel driving circuit.
  • FIG. 3 is a first schematic diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 4 is a second schematic diagram of a pixel driving circuit provided by an embodiment of the application.
  • FIG. 5 is a schematic diagram of a liquid crystal display panel provided by an embodiment of the application.
  • the present application provides a pixel driving circuit and a liquid crystal display panel.
  • a pixel driving circuit and a liquid crystal display panel.
  • the present application addresses the technical problem of the existing liquid crystal display panel that the aperture ratio is small due to the resolution of the color shift and affects the display effect.
  • the embodiments of the present application are used to solve this problem.
  • the existing pixel driving circuit includes a data line Data, an Nth level scan line Gn, an N+1th level scan line Gn+1, and a main pixel unit A and a sub-pixel unit B.
  • the auxiliary capacitor Ccs (A), the liquid crystal capacitor Clc (A) and the storage capacitor Cst (A) corresponding to the main pixel unit A are required.
  • the sub-pixel unit B is driven, the corresponding The auxiliary capacitor Ccs (B), the liquid crystal capacitor Clc (B), and the storage capacitor Cst (B) of the sub pixel unit B, and the driving of the main pixel unit A needs to use the gate of the Gn control transistor.
  • the capacitor-assisted drive circuit makes the main pixel unit A and the sub-pixel unit B have a voltage difference, so as to avoid color shift, so that the pixel unit normally emits light.
  • the circuit has more storage capacitors and the circuit is less stable, and it needs to use two
  • the control of the scanning lines makes the aperture ratio of the display panel smaller, thereby affecting the display effect; as shown in FIG. 2, the existing pixel driving circuit includes a data line Data, an Nth level scan line Gn, and an N+1th level scan line Gn +1 and the main pixel unit A and the sub-pixel unit B.
  • the existing pixel driving circuit includes a data line Data, an Nth level scan line Gn, and an N+1th level scan line Gn +1 and the main pixel unit A and the sub-pixel unit B.
  • the transistor TFT1 is controlled by Gn, so that TFT1, the liquid crystal capacitor C LCA and the storage capacitor C STA control the normal display of the main pixel unit A.
  • the transistor TFT2 is controlled by Gn , The TFT2, the liquid crystal capacitor C LCB and the storage capacitor C STB control the normal display of the sub-pixel unit B.
  • the transistor TFT3 is controlled through Gn+1, so that TFT3 and the step-down capacitor C Down work together to control the sub-pixel unit B to step down. So that there is a voltage difference between the main pixel unit A and the sub-pixel unit B to avoid voltage drop.
  • Gn-1 indicates that the connection point is connected to Gn-1, but the pixel drive circuit also uses two scan lines to control a pixel
  • the unit also uses a step-down capacitor to reduce the voltage of the sub-pixel unit, which reduces the aperture ratio and affects the display effect. That is, the existing liquid crystal display panel has a technical problem that the aperture ratio is small due to the solution of color shift and affects the display effect.
  • an embodiment of the present application provides a pixel driving circuit, and the pixel driving circuit includes:
  • the sub-pixel unit includes:
  • the first common electrode terminal 16 The first common electrode terminal 16;
  • the main sub-pixel unit 13 includes a first transistor 131, a first storage capacitor 132, and a first liquid crystal capacitor 133;
  • the sub-pixel unit 14 includes a second transistor 141, a second storage capacitor 142, and a second liquid crystal capacitor 143;
  • the third transistor 15, the second electrode of the third transistor 15 is connected to the first common electrode terminal 16;
  • the gates of the first transistor 131, the second transistor 141, and the third transistor 15 are connected to the scan line 11, and one electrode of the first transistor 131 is connected to the first electrode of the second transistor 141, so The second electrode of the second transistor 141 is connected to the first electrode of the third transistor 15.
  • the embodiments of the present application provide a pixel driving circuit and a liquid crystal display panel.
  • the pixel driving circuit includes a plurality of scan lines and a plurality of data lines, and the plurality of scan lines and the plurality of data lines define a plurality of sub-pixel units, at least one The sub-pixel unit is connected to a scan line and a data line.
  • the sub-pixel unit includes a first common electrode terminal, a main sub-pixel unit, a sub-sub-pixel unit, and a third transistor.
  • the main sub-pixel unit includes a first transistor, a first transistor, and a third transistor.
  • the sub-sub-pixel unit includes a second transistor, a second storage capacitor, and a second liquid crystal capacitor;
  • the second electrode of the third transistor is electrically connected to the first common electrode terminal, wherein The gates of the first transistor, the second transistor, and the third transistor are connected to a scan line, one electrode of the first transistor is connected to the first electrode of the second transistor, and the second electrode of the second transistor is connected to The first electrode of the third transistor;
  • the main sub-pixel unit and the sub-sub-pixel unit are controlled by using the first transistor, the second transistor, and the third transistor, and the gates of the first transistor, the second transistor and the third crystal are connected To the scan line, one scan line can control three transistors.
  • the second electrode of the third transistor is connected to the first common electrode terminal, so that after the voltage signal passes through the first transistor, the second transistor, and the third transistor, the first The connection of the three transistors to the first common electrode causes a potential difference between the main sub-pixel and the sub-sub-pixel, thereby reducing color shift.
  • the display Since one sub-pixel unit only needs one scan line to control, and the number of capacitors is reduced, the display The aperture ratio of the panel is increased, and at the same time, parasitic capacitance is avoided, and the display effect is improved.
  • the first electrode of the first transistor 131 is connected to the data line 12, and the second electrode of the first transistor 131 is connected to the second electrode of the second transistor 141.
  • One electrode; the first transistor is connected to the data line, the second transistor is connected to the first transistor, so that when the scan line controls the first transistor, the second transistor and the third transistor to turn on, the voltage signal sent by the data line needs to pass through the first
  • the transistor is then transferred to the second transistor and then to the third transistor, so that when the sub-sub-pixel unit is normally displayed, the main sub-pixel unit is also displayed normally, so that the main sub-pixel unit is guaranteed to simultaneously perform screen display during display.
  • the first transistor 131 is connected in series with the first storage capacitor 132, and the first transistor 131 is connected in series with the first liquid crystal capacitor 133, and the first transistor is turned on. ,
  • the voltage signal charges the first storage capacitor.
  • the first liquid crystal capacitor is charged by the voltage signal at the same time, so that the first liquid crystal capacitor provides the liquid crystal molecule deflection voltage of the main sub-pixel unit.
  • the first storage capacitor In parallel with the first liquid crystal capacitor, a corresponding charging process is performed.
  • the first storage capacitor charges the first liquid crystal capacitor to ensure that the voltage of the first liquid crystal capacitor is stable and the deflection of the liquid crystal molecules is stable.
  • the first storage capacitor is connected in series with the first liquid crystal capacitor.
  • the first plate of the first storage capacitor 132 is connected to the second electrode of the first transistor 131, and the second plate of the first storage capacitor 132 Connected to the first common electrode terminal 16, connect one plate of the first storage capacitor to the second electrode of the first transistor, and one plate to the first common electrode terminal, so that the voltage signal is connected to the first transistor after passing through the first transistor.
  • the storage capacitor is charged.
  • the first plate of the first liquid crystal capacitor 133 is connected to the second electrode of the first transistor 131, and the first The second plate of a liquid crystal capacitor 133 is connected to the second common electrode terminal 17. After the voltage signal passes through the first transistor, the voltage signal charges the second liquid crystal capacitor.
  • the second transistor 141 is connected in series with the second storage capacitor 142, and the second transistor 141 is connected in series with the second liquid crystal capacitor 143. Only after the two transistors can the voltage signal charge the second storage capacitor and the second liquid crystal capacitor, and the second storage capacitor and the second liquid crystal capacitor are connected in parallel at this time, the voltage signal can charge the second storage capacitor and the second liquid crystal capacitor mutually. It does not affect, so that the voltage in the second storage capacitor and the second liquid crystal capacitor meets the predetermined demand.
  • the first plate of the second storage capacitor 142 is connected to the second electrode of the second transistor 141, and the second plate of the second storage capacitor 142 Connected to the first common electrode terminal 16; connecting a plate of the second storage capacitor to the second electrode of the second transistor, the voltage signal can reach the second storage capacitor after passing through the second transistor, thereby saving The capacitor is charged, so that the second transistor controls the charging of the storage capacitor of the sub-pixel capacitor.
  • the first electrode of the second liquid crystal capacitor 143 is connected to the second electrode of the second transistor 141, and the second electrode of the second liquid crystal capacitor 143 Connected to the second common electrode terminal 17; a plate of the second liquid crystal capacitor is connected to the second transistor, so that after passing through the second transistor, the voltage signal can be transmitted to the second liquid crystal capacitor to charge the second liquid crystal capacitor , And the second liquid crystal capacitor is connected in parallel with the second storage capacitor at this time, so that the second storage capacitor and the second liquid crystal capacitor are charged separately without affecting each other.
  • the first electrode of the first transistor 131 is connected to the data line 12, and the first electrode of the second transistor 141 is connected to the data line 12, so The first electrode of the first transistor 131 is connected to the first electrode of the second transistor 141.
  • the main sub-pixel unit and the sub-sub-pixel unit are controlled separately. So that the main sub-pixel unit and the sub-sub-pixel unit do not interfere with each other, and the second transistor is connected to the third transistor, so that the third transistor changes the voltage of the sub-sub-pixel unit, so that there is a voltage difference between the main sub-pixel unit and the sub-sub-pixel unit , So as to solve the color cast.
  • the first electrode is a source and the second electrode is a drain; or the first electrode is a drain and the second electrode is a source.
  • the sub-pixel unit includes a main sub-pixel unit and a sub-sub-pixel unit, the main sub-pixel unit includes 4 domains, and the sub-sub-pixel unit includes 4 domains.
  • the embodiment of the present application does not limit the domains. The number can be used for 2 domains, 4 domains or 8 domains.
  • an embodiment of the present application provides a liquid crystal display panel.
  • the liquid crystal display panel includes a pixel driving circuit.
  • the pixel driving circuit includes a plurality of scan lines and a plurality of data lines.
  • a data line defines a plurality of sub-pixel units, at least one of the sub-pixel units is connected to a scan line and a data line, and the sub-pixel unit includes:
  • the first common electrode terminal
  • the main sub-pixel unit includes a first transistor, a first storage capacitor, and a first liquid crystal capacitor;
  • the sub-pixel unit includes a second transistor, a second storage capacitor, and a second liquid crystal capacitor;
  • a third transistor, the second electrode of the third transistor is connected to the first common electrode terminal;
  • the gates of the first transistor, the second transistor, and the third transistor are connected to the scan line, one electrode of the first transistor is connected to the first electrode of the second transistor, and the second transistor of the second transistor is connected to the scan line.
  • the two electrodes are connected to the first electrode of the third transistor.
  • the liquid crystal display panel includes a pixel drive circuit.
  • the pixel drive circuit includes a plurality of scan lines and a plurality of data lines, and the plurality of scan lines and the plurality of data lines define a plurality of sub- A pixel unit, at least one of the sub-pixel units is connected to a scan line and a data line, the sub-pixel unit includes a first common electrode terminal, a main sub-pixel unit, a sub-sub-pixel unit, and a third transistor, and the main sub-pixel unit includes A first transistor, a first storage capacitor, and a first liquid crystal capacitor; the sub-sub-pixel unit includes a second transistor, a second storage capacitor, and a second liquid crystal capacitor; the second electrode of the third transistor is electrically connected to the first common voltage Terminal, wherein the gates of the first transistor, the second transistor, and the third transistor are connected to a scan line, one electrode of the first transistor is connected to the first electrode of the second transistor, and the second transistor The second electrode is
  • the gate of the crystal is connected to the scan line so that one scan line can control three transistors.
  • the second electrode of the third transistor is connected to the first common electrode terminal, so that the voltage signal is transmitted from the first transistor, the second transistor and the third transistor.
  • the third transistor is connected to the first common electrode terminal to cause a potential difference between the main sub-pixel and the sub-sub-pixel, thereby reducing color shift.
  • one sub-pixel unit since one sub-pixel unit only needs one scan line to control, and the capacitance is reduced
  • the number of the display panel increases the aperture ratio of the display panel, and at the same time, avoids the generation of parasitic capacitance and improves the display effect.
  • the liquid crystal display panel array substrate, the color filter substrate, and the liquid crystal layer located between the array substrate and the color filter substrate includes a substrate, The first metal layer 21, the active layer 22, the source drain layer 23, and the pixel electrode layer 24, the color filter substrate includes a common electrode layer and a color filter layer; the first transistor, the second transistor, and the third transistor
  • the gate is formed by the first metal layer, the first and second electrodes of the first transistor are formed by the source and drain layers, and the first and second electrodes of the second transistor are formed by the source and drain layers.
  • the drain layer is formed, and the first electrode and the second electrode of the third transistor are formed by the source and drain layer.
  • the reference numeral 31 in FIG. 5 includes the gates, the first electrode, and the third transistor of the first transistor, the second transistor, and the third transistor.
  • Two electrodes, 31 in FIG. 5 includes a portion of the first metal layer, a portion of the active layer, and a portion of the source-drain layer. The portion of the source-drain layer forms the first electrode and the second electrode of the first transistor in order from left to right.
  • the first metal layer 21 is formed with scan lines 213, and the source and drain layers are formed with data lines 233.
  • the first plate 231 of the first storage capacitor is formed by the source-drain layer 23, and the second plate 211 of the first storage capacitor is formed by the The first metal layer 21 is formed; the first plate of the first liquid crystal capacitor is formed by the pixel electrode layer, the second plate of the first liquid crystal capacitor is formed by the common electrode layer on the color filter substrate, the first The medium of the liquid crystal capacitor is formed by liquid crystal molecules, and the first plate of the first liquid crystal capacitor is connected to the second electrode of the first transistor, that is, a part of the source and drain layer is connected to a part of the pixel electrode layer.
  • the first plate 232 of the second storage capacitor is formed by the source and drain layer 23, and the second plate 212 of the second storage capacitor is formed by the first metal layer 21
  • the first plate of the second liquid crystal capacitor is formed by the pixel electrode layer
  • the second plate of the second liquid crystal capacitor is formed by the common electrode layer on the color filter substrate
  • the first electrode of the second liquid crystal capacitor The plate is connected to the second electrode of the second transistor, that is, a part of the source and drain layer is connected to a part of the pixel electrode layer.
  • the first common electrode terminal is formed by the first metal layer, and the first common electrode terminal connected to the first storage capacitor, the second storage capacitor, and the third transistor is Different parts of the first metal layer have the same voltage at the first common electrode terminal.
  • the second common electrode terminal is formed by the common electrode layer, and the second common electrode terminal connected to the first liquid crystal capacitor and the second liquid crystal capacitor is a different part of the common electrode layer,
  • the voltages of the second common electrode terminal are the same, and the voltages of the first common electrode terminal and the second common electrode terminal are the same.
  • the first electrode of the first transistor is connected to the data line, and the second electrode of the first transistor is connected to the first electrode of the second transistor.
  • the first transistor in a liquid crystal display panel, is connected in series with the first storage capacitor, and the first transistor is connected in series with the first liquid crystal capacitor.
  • the first electrode of the first storage capacitor is connected to the second electrode of the first transistor, and the second electrode of the first storage capacitor is connected to the first electrode.
  • the common electrode terminal is connected.
  • the liquid crystal display panel further includes a second common electrode terminal, the first plate of the first liquid crystal capacitor is connected to the second electrode of the first transistor, and the first liquid crystal capacitor The second electrode plate is connected to the second common electrode terminal.
  • the second transistor in a liquid crystal display panel, is connected in series with the second storage capacitor, and the second transistor is connected in series with the second liquid crystal capacitor.
  • the first plate of the second storage capacitor is connected to the second electrode of the second transistor, and the second plate of the second storage capacitor is connected to the second electrode of the second transistor.
  • the first common electrode terminal is connected.
  • the first plate of the second liquid crystal capacitor is connected to the second electrode of the second transistor, and the second plate of the second liquid crystal capacitor is connected to the second electrode of the second transistor.
  • the second common electrode terminal is connected.
  • the first electrode of the first transistor is connected to the data line
  • the first electrode of the second transistor is connected to the data line
  • the first transistor The first electrode of is connected to the first electrode of the second transistor.
  • the sub-pixel unit includes a main sub-pixel unit and a sub-sub-pixel unit, the main sub-pixel unit includes 4 domains, and the sub-sub-pixel unit includes 4 domains.
  • the present application provides a pixel driving circuit and a liquid crystal display panel.
  • the pixel driving circuit includes a plurality of scan lines and a plurality of data lines, and the plurality of scan lines and the plurality of data lines define a plurality of sub-pixel units, at least one of the The sub-pixel unit is connected to a scan line and a data line.
  • the sub-pixel unit includes a first common electrode terminal, a main sub-pixel unit, a sub-sub-pixel unit, and a third transistor.
  • the main sub-pixel unit includes a first transistor, a first storage A capacitor and a first liquid crystal capacitor; the sub-sub-pixel unit includes a second transistor, a second storage capacitor, and a second liquid crystal capacitor; the second electrode of the third transistor is electrically connected to the first common electrode terminal, wherein the second The gates of a transistor, a second transistor, and a third transistor are connected to the scan line, an electrode of the first transistor is connected to the first electrode of the second transistor, and the second electrode of the second transistor is connected to the The first electrode of the third transistor; the main sub-pixel unit and the sub-sub-pixel unit are controlled by using the first transistor, the second transistor, and the third transistor, and the gates of the first transistor, the second transistor, and the third transistor are connected to the scan The three transistors can be controlled by one scan line, and the second electrode of the third transistor is connected to the first common electrode terminal, so that after the voltage signal passes through the first transistor, the second transistor, and the third transistor, the third transistor Connecting the first common electrode terminal results in a potential difference

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Abstract

一种像素驱动电路和液晶显示面板，像素驱动电路通过将第一晶体管（131）、第二晶体管（141）和第三晶体（15）的栅极连接至扫描线（11），使得一条扫描线（11）即可控制三个晶体管（131,141,15），同时使得第三晶体管（15）的第二电极连接第一公共电极端（16），使得第三晶体管（15）连接造成主子像素单元（13）与副子像素单元（14）之间存在电位差，从而减小色偏，提高开口率。

Description

像素驱动电路和液晶显示面板
本申请要求于2019年11月28日提交中国专利局、申请号为201911191356.7、发明名称为“像素驱动电路和液晶显示面板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及显示技术领域，尤其是涉及一种像素驱动电路和液晶显示面板。
 背景技术
现有液晶显示面板通过电压驱动改变液晶分子的方向，从而将光线折射出来得到显示画面，而VA（Vertical Alignment，垂直取向）液晶显示面板由于具有较高的对比度被广泛应用，但VA型液晶显示面板存在色偏较严重的问题，为了解决色偏问题，现有液晶显示面板会将子像素的发光区域分为多个畴，使不同畴内的液晶分子的偏转方向不同，从而解决色偏，但该方式会造成显示面板的开口率较小，且存在寄生电容，从而影响显示效果。
所以，现有液晶显示面板存在由于解决色偏导致的开口率较小，影响显示效果的技术问题。
 技术问题
本申请提供一种像素驱动电路和液晶显示面板，用于解决现有液晶显示面板存在由于解决色偏导致的开口率较小，影响显示效果的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请提供一种像素驱动电路，该像素驱动电路包括多条扫描线与多条数据线，所述多条扫描线与多条数据线限定出多个子像素单元，至少一个所述子像素单元连接一条扫描线和一条数据线，所述子像素单元包括：
第一公共电极端；
主子像素单元，包括第一晶体管、第一存储电容和第一液晶电容；
副子像素单元，包括第二晶体管、第二存储电容和第二液晶电容；
第三晶体管，所述第三晶体管的第二电极连接第一公共电极端；
其中，所述第一晶体管、第二晶体管和第三晶体管的栅极连接至扫描线，所述第一晶体管的一电极与所述第二晶体管的第一电极连接，所述第二晶体管的第二电极连接所述第三晶体管的第一电极。
在本申请提供的像素驱动电路中，所述第一晶体管的第一电极与所述数据线连接，所述第一晶体管的第二电极连接所述第二晶体管的第一电极。
在本申请提供的像素驱动电路中，所述第一晶体管与所述第一存储电容串联，所述第一晶体管与所述第一液晶电容串联。
在本申请提供的像素驱动电路中，所述第一存储电容的第一极板与所述第一晶体管的第二电极连接，所述第一存储电容的第二极板与第一公共电极端连接。
在本申请提供的像素驱动电路中，该像素驱动电路还包括第二公共电极端，所述第一液晶电容的第一极板与所述第一晶体管的第二电极连接，所述第一液晶电容的第二极板与所述第二公共电极端连接。
在本申请提供的像素驱动电路中，所述第二晶体管与所述第二存储电容串联，所述第二晶体管与所述第二液晶电容串联。
在本申请提供的像素驱动电路中，所述第二存储电容的第一极板与所述第二晶体管的第二电极连接，所述第二存储电容的第二极板与所述第一公共电极端连接。
在本申请提供的像素驱动电路中，所述第二液晶电容的第一极板与所述第二晶体管的第二电极连接，所述第二液晶电容的第二极板与所述第二公共电极端连接。
在本申请提供的像素驱动电路中，所述第一晶体管的第一电极与所述数据线连接，所述第二晶体管的第一电极与所述数据线连接，所述第一晶体管的第一电极与所述第二晶体管的第一电极连接。
在本申请提供的像素驱动电路中，所述子像素单元包括主子像素单元和副子像素单元，所述主子像素单元包括4个畴，所述副子像素单元包括4个畴。
同时，本申请提供一种液晶显示面板，该液晶显示面板包括像素驱动电路，所述像素驱动电路包括多条扫描线与多条数据线，所述多条扫描线与多条数据线限定出多个子像素单元，至少一个所述子像素单元连接一条扫描线和一条数据线，所述子像素单元包括：
第一公共电极端；
主子像素单元，包括第一晶体管、第一存储电容和第一液晶电容；
副子像素单元，包括第二晶体管、第二存储电容和第二液晶电容；
第三晶体管，所述第三晶体管的第二电极连接第一公共电极端；
其中，所述第一晶体管、第二晶体管和第三晶体管的栅极连接至扫描线，所述第一晶体管的一电极与所述第二晶体管的第一电极连接，所述第二晶体管的第二电极连接所述第三晶体管的第一电极。
在本申请提供的液晶显示面板中，所述第一晶体管的第一电极与所述数据线连接，所述第一晶体管的第二电极连接所述第二晶体管的第一电极。
在本申请提供的液晶显示面板中，所述第一晶体管与所述第一存储电容串联，所述第一晶体管与所述第一液晶电容串联。
在本申请提供的液晶显示面板中，所述第一存储电容的第一极板与所述第一晶体管的第二电极连接，所述第一存储电容的第二极板与第一公共电极端连接。
在本申请提供的液晶显示面板中，还包括第二公共电极端，所述第一液晶电容的第一极板与所述第一晶体管的第二电极连接，所述第一液晶电容的第二极板与所述第二公共电极端连接。
在本申请提供的液晶显示面板中，所述第二晶体管与所述第二存储电容串联，所述第二晶体管与所述第二液晶电容串联。
在本申请提供的液晶显示面板中，所述第二存储电容的第一极板与所述第二晶体管的第二电极连接，所述第二存储电容的第二极板与所述第一公共电极端连接。
在本申请提供的液晶显示面板中，所述第二液晶电容的第一极板与所述第二晶体管的第二电极连接，所述第二液晶电容的第二极板与所述第二公共电极端连接。
在本申请提供的液晶显示面板中，所述第一晶体管的第一电极与所述数据线连接，所述第二晶体管的第一电极与所述数据线连接，所述第一晶体管的第一电极与所述第二晶体管的第一电极连接。
在本申请提供的液晶显示面板中，所述子像素单元包括主子像素单元和副子像素单元，所述主子像素单元包括4个畴，所述副子像素单元包括4个畴。
 有益效果
本申请提供一种像素驱动电路和液晶显示面板，该像素驱动电路包括多条扫描线与多条数据线，所述多条扫描线与多条数据线限定出多个子像素单元，至少一个所述子像素单元连接一条扫描线和一条数据线，所述子像素单元包括第一公共电极端、主子像素单元、副子像素单元和第三晶体管，所述主子像素单元包括第一晶体管、第一存储电容和第一液晶电容；所述副子像素单元包括第二晶体管、第二存储电容和第二液晶电容；所述第三晶体管的第二电极电连接第一公共电极端，其中，所述第一晶体管、第二晶体管和第三晶体管的栅极连接至扫描线，所述第一晶体管的一电极与所述第二晶体管的第一电极连接，所述第二晶体管的第二电极连接所述第三晶体管的第一电极；通过使用第一晶体管、第二晶体管、第三晶体管控制主子像素单元和副子像素单元，并将第一晶体管、第二晶体管和第三晶体的栅极连接至扫描线，使得一条扫描线即可控制三个晶体管，同时使得第三晶体管的第二电极连接第一公共电极端，使得电压信号从第一晶体管、第二晶体管和第三晶体管经过后，第三晶体管连接第一公共电极端造成主子像素与副子像素之间存在电位差，从而减小色偏，同时，由于一个子像素单元仅需一条扫描线控制，且减少了电容的数量，使得显示面板的开口率增大，同时，避免产生寄生电容，提高了显示效果。
 附图说明
图1为现有像素驱动电路的第一示意图。
图2为现有像素驱动电路的第二示意图。
图3为本申请实施例提供的像素驱动电路的第一示意图。
图4为本申请实施例提供的像素驱动电路的第二示意图。
图5为本申请实施例提供的液晶显示面板的示意图。
 本发明的实施方式
本申请提供一种像素驱动电路和液晶显示面板，为使本申请的目的、技术方案及效果更加清楚、明确，以下参照附图并举实施例对本申请进一步详细说明。应当理解，此处所描述的具体实施例仅用以解释本申请，并不用于限定本申请。
本申请针对现有液晶显示面板存在由于解决色偏导致的开口率较小，影响显示效果的技术问题，本申请实施例用以解决该问题。
如图1所示，现有像素驱动电路包括数据线Data，第N级扫描线Gn、第N+1级扫描线Gn+1以及主像素单元A和副像素单元B，从图中可以看到，在对主像素单元A进行驱动时，需要对应主像素单元A的辅助电容Ccs（A），液晶电容Clc（A）和存储电容Cst（A），对副像素单元B进行驱动时，需要对应副像素单元B的辅助电容Ccs（B）、液晶电容Clc（B）、存储电容Cst（B），且对主像素单元A的驱动需要采用Gn控制晶体管的栅极，当Gn控制晶体管的处于工作状态时，主像素单元A处的液晶分子偏转以控制背光模组的光的偏振方向，从而使得主像素单元A正常显示画面，对副像素单元B的驱动需要采用Gn+1控制晶体管的栅极，从而使得副像素单元B正常显示画面，则从图1中可以看出，在对主像素单元和副像素单元进行驱动时，需要采用两条扫描线控制一个像素单元，同时，还需要采用辅助电容辅助驱动电路，使得主像素单元A和副像素单元B存在电压差，从而避免出现色偏，从而使得像素单元正常发光，但该电路中存储电容较多，电路较不稳定，且需要采用两条扫描线控制，使得显示面板的开口率较小，从而影响显示效果；如图2所示，现有像素驱动电路包括数据线Data，第N级扫描线Gn、第N+1级扫描线Gn+1以及主像素单元A和副像素单元B，图2中通过Gn控制晶体管TFT1，使得TFT1、液晶电容C LCA和存储电容C STA控制主像素单元A正常显示、图2中通过Gn控制晶体管TFT2，使得TFT2、液晶电容C LCB和存储电容C STB控制副像素单元B正常显示，同时，通过Gn+1控制晶体管TFT3，使得TFT3和降压电容C Down共同工作，控制副像素单元B降压，从而使得主像素单元A和副像素单元B存在电压差，从而避免压降，图2中Gn-1表示该连接点连接至Gn-1，但该像素驱动电路也使用两条扫描线控制一个像素单元，同时采用了降压电容降低副像素单元的电压，降低了开口率，影响显示效果，即现有的液晶显示面板存在由于解决色偏导致的开口率较小，影响显示效果的技术问题。
如图3所示，本申请实施例提供一种像素驱动电路，该像素驱动电路包括：
多条扫描线11与多条数据线12，所述多条扫描线11与多条数据线12限定出多个子像素单元，至少一个所述子像素单元连接一条扫描线11和一条数据线12，所述子像素单元包括：
第一公共电极端16；
主子像素单元13，包括第一晶体管131、第一存储电容132和第一液晶电容133；
副子像素单元14，包括第二晶体管141、第二存储电容142和第二液晶电容143；
第三晶体管15，所述第三晶体管15的第二电极连接第一公共电极端16；
其中，所述第一晶体管131、第二晶体管141和第三晶体管15的栅极连接至扫描线11，所述第一晶体管131的一电极与所述第二晶体管141的第一电极连接，所述第二晶体管141的第二电极连接所述第三晶体管15的第一电极。
本申请实施例提供一种像素驱动电路和液晶显示面板，该像素驱动电路包括多条扫描线与多条数据线，所述多条扫描线与多条数据线限定出多个子像素单元，至少一个所述子像素单元连接一条扫描线和一条数据线，所述子像素单元包括第一公共电极端、主子像素单元、副子像素单元和第三晶体管，所述主子像素单元包括第一晶体管、第一存储电容和第一液晶电容；所述副子像素单元包括第二晶体管、第二存储电容和第二液晶电容；所述第三晶体管的第二电极电连接第一公共电极端，其中，所述第一晶体管、第二晶体管和第三晶体管的栅极连接至扫描线，所述第一晶体管的一电极与所述第二晶体管的第一电极连接，所述第二晶体管的第二电极连接所述第三晶体管的第一电极；通过使用第一晶体管、第二晶体管、第三晶体管控制主子像素单元和副子像素单元，并将第一晶体管、第二晶体管和第三晶体的栅极连接至扫描线，使得一条扫描线即可控制三个晶体管，同时使得第三晶体管的第二电极连接第一公共电极端，使得电压信号从第一晶体管、第二晶体管和第三晶体管经过后，第三晶体管连接第一公共电极端造成主子像素与副子像素之间存在电位差，从而减小色偏，同时，由于一个子像素单元仅需一条扫描线控制，且减少了电容的数量，使得显示面板的开口率增大，同时，避免产生寄生电容，提高了显示效果。
在一种实施例中，如图3所示，所述第一晶体管131的第一电极与所述数据线12连接，所述第一晶体管131的第二电极连接所述第二晶体管141的第一电极；使第一晶体管连接数据线，第二晶体管连接第一晶体管，从而使得在扫描线控制第一晶体管、第二晶体管和第三晶体管开启时，数据线发出的电压信号需要先经过第一晶体管然后传递到第二晶体管然后传递到第三晶体管，从而使得副子像素单元正常显示时，主子像素单元也正常显示，使得显示时保证主子像素单元同时进行画面显示。
在一种实施例中，如图3所示，所述第一晶体管131与所述第一存储电容132串联，所述第一晶体管131与所述第一液晶电容133串联，在第一晶体管打开，电压信号对第一存储电容进行充电，在该过程中，同时电压信号对第一液晶电容出现充电，使得第一液晶电容提供主子像素单元的液晶分子偏转电压，该过程中，第一存储电容与第一液晶电容并联，相应的进行充电过程，在第一晶体管关闭时，第一存储电容对第一液晶电容充电，以保证第一液晶电容电压稳定，使得液晶分子偏转稳定，该过程中，第一存储电容与第一液晶电容串联。
在一种实施例中，如图3所示，所述第一存储电容132的第一极板与所述第一晶体管131的第二电极连接，所述第一存储电容132的第二极板与第一公共电极端16连接，将第一存储电容的一极板连接第一晶体管的第二电极，一极板连接第一公共电极端，使得电压信号在经过第一晶体管后，对第一存储电容进行充电。
在一种实施例中，如图3所示，还包括第二公共电极端17，所述第一液晶电容133的第一极板与所述第一晶体管131的第二电极连接，所述第一液晶电容133的第二极板与所述第二公共电极端17连接，在电压信号经过第一晶体管后，电压信号对第二液晶电容进行充电。
在一种实施例中，如图3所示，所述第二晶体管141与所述第二存储电容142串联，所述第二晶体管141与所述第二液晶电容143串联，在电压信号经过第二晶体管后，电压信号才能对第二存储电容和第二液晶电容进行充电，且第二存储电容与第二液晶电容此时并联，则电压信号对第二存储电容和第二液晶电容的充电互不影响，从而使得第二存储电容与第二液晶电容内的电压达到预定的需求。
在一种实施例中，如图3所示，所述第二存储电容142的第一极板与所述第二晶体管141的第二电极连接，所述第二存储电容142的第二极板与所述第一公共电极端16连接；使第二存储电容一极板与第二晶体管的第二电极连接，则电压信号在经过第二晶体管后才能达到第二存储电容，从而对第二存储电容进行充电，从而使第二晶体管控制副子像素电容的存储电容的充电。
在一种实施例中，如图3所示，所述第二液晶电容143的第一极板与所述第二晶体管141的第二电极连接，所述第二液晶电容143的第二极板与所述第二公共电极端17连接；第二液晶电容的一极板与第二晶体管连接，使得电压信号在经过第二晶体管后，能够传递到第二液晶电容，对第二液晶电容进行充电，而第二液晶电容此时与第二存储电容并联，使得对第二存储电容和第二液晶电容分开充电，不会互相影响。
在一种实施例中，如图4所示，所述第一晶体管131的第一电极与所述数据线12连接，所述第二晶体管141的第一电极与所述数据线12连接，所述第一晶体管131的第一电极与所述第二晶体管141的第一电极连接，在通过使第一晶体管和第二晶体管均连接至数据线，使得主子像素单元与副子像素单元分开控制，从而使得主子像素单元与副子像素单元互不干扰，且第二晶体管与第三晶体管连接，从而使得第三晶体管改变副子像素单元的电压，从而使得主子像素单元与副子像素单元存在电压差，从而解决色偏。
在一种实施例中，所述第一电极为源极，所述第二电极为漏极；或者所述第一电极为漏极，所述第二电极为源极。
在一种实施例中，所述子像素单元包括主子像素单元和副子像素单元，所述主子像素单元包括4个畴，所述副子像素单元包括4个畴，本申请实施例不限定畴的数量，对于2畴、4畴或者8畴均可。
如图5所示，本申请实施例提供一种液晶显示面板，该液晶显示面板包括像素驱动电路，所述像素驱动电路包括多条扫描线与多条数据线，所述多条扫描线与多条数据线限定出多个子像素单元，至少一个所述子像素单元连接一条扫描线和一条数据线，所述子像素单元包括：
第一公共电极端；
主子像素单元，包括第一晶体管、第一存储电容和第一液晶电容；
副子像素单元，包括第二晶体管、第二存储电容和第二液晶电容；
第三晶体管，所述第三晶体管的第二电极连接第一公共电极端；
其中，所述第一晶体管、第二晶体管和第三晶体管的栅极连接至扫描线，所述第一晶体管的一电极与所述第二晶体管的第一电极连接，所述第二晶体管的第二电极连接所述第三晶体管的第一电极。
本申请实施例提供一种液晶显示面板，该液晶显示面板包括像素驱动电路，该像素驱动电路包括多条扫描线与多条数据线，所述多条扫描线与多条数据线限定出多个子像素单元，至少一个所述子像素单元连接一条扫描线和一条数据线，所述子像素单元包括第一公共电极端、主子像素单元、副子像素单元和第三晶体管，所述主子像素单元包括第一晶体管、第一存储电容和第一液晶电容；所述副子像素单元包括第二晶体管、第二存储电容和第二液晶电容；所述第三晶体管的第二电极电连接第一公共电极端，其中，所述第一晶体管、第二晶体管和第三晶体管的栅极连接至扫描线，所述第一晶体管的一电极与所述第二晶体管的第一电极连接，所述第二晶体管的第二电极连接所述第三晶体管的第一电极；通过使用第一晶体管、第二晶体管、第三晶体管控制主子像素单元和副子像素单元，并将第一晶体管、第二晶体管和第三晶体的栅极连接至扫描线，使得一条扫描线即可控制三个晶体管，同时使得第三晶体管的第二电极连接第一公共电极端，使得电压信号从第一晶体管、第二晶体管和第三晶体管经过后，第三晶体管连接第一公共电极端造成主子像素与副子像素之间存在电位差，从而减小色偏，同时，由于一个子像素单元仅需一条扫描线控制，且减少了电容的数量，使得显示面板的开口率增大，同时，避免产生寄生电容，提高了显示效果。
在一种实施例中，如图5所示，所述液晶显示面板阵列基板、彩膜基板以及位于所述阵列基板与所述彩膜基板之间的液晶层，所述阵列基板包括衬底、第一金属层21、有源层22、源漏极层23、像素电极层24，所述彩膜基板包括公共电极层和彩膜层；所述第一晶体管、第二晶体管、第三晶体管的栅极由所述第一金属层形成，所述第一晶体管的第一电极、第二电极由所述源漏极层形成，所述第二晶体管的第一电极、第二电极由所述源漏极层形成，所述第三晶体管的第一电极、第二电极由所述源漏极层形成。
需要说明的是，为了比较清晰的表示出第一晶体管、第二晶体管和第三晶体管，图5中以标号31包含第一晶体管、第二晶体管和第三晶体管的栅极、第一电极和第二电极，图5中的31包括第一金属层的部分、有源层的部分和源漏极层的部分，源漏极层的部分从左至右依次形成第一晶体管的第一电极、第二电极和第二晶体管的第一电极、第二电极、第三集体管的第一电极、第二电极，其中，第一晶体管的第二电极与第二晶体管的第一电极共用同一部分，第二晶体管的第二电极与第三晶体管的第一电极共用同一部分。
在一种实施例中，所述第一金属层21形成有扫描线213，所述源漏极层形成有数据线233。
在一种实施例中，如图5所示，所述第一存储电容的第一极板231由所述源漏极层23形成，所述第一存储电容的第二极板211由所述第一金属层21形成；所述第一液晶电容的第一极板由像素电极层形成，所述第一液晶电容的第二极板由彩膜基板上的公共电极层形成，所述第一液晶电容的介质由液晶分子形成，所述第一液晶电容的第一极板与所述第一晶体管的第二电极连接，即源漏极层中的一部分与像素电极层的一部分连接。
在一种实施例中，所述第二存储电容的第一极板232由所述源漏极层23形成，所述第二存储电容的第二极板212由所述第一金属层21形成；所述第二液晶电容的第一极板由像素电极层形成，所述第二液晶电容的第二极板由彩膜基板上的公共电极层形成，所述第二液晶电容的第一极板与所述第二晶体管的第二电极连接，即源漏极层中的一部分与像素电极层的一部分连接。。
在一种实施例中，所述第一公共电极端由所述第一金属层形成，所述第一存储电容、所述第二存储电容与所述第三晶体管连接的第一公共电极端为第一金属层的不同部分，第一公共电极端的电压相同。
在一种实施例中，所述第二公共电极端由所述公共电极层形成，所述第一液晶电容、所述第二液晶电容连接的第二公共电极端为公共电极层的不同部分，所述第二公共电极端的电压相同，且所述第一公共电极端与所述第二公共电极端的电压相同。
在一种实施例中，在液晶显示面板中，所述第一晶体管的第一电极与所述数据线连接，所述第一晶体管的第二电极连接所述第二晶体管的第一电极。
在一种实施例中，在液晶显示面板中，所述第一晶体管与所述第一存储电容串联，所述第一晶体管与所述第一液晶电容串联。
在一种实施例中，在液晶显示面板中，所述第一存储电容的第一极板与所述第一晶体管的第二电极连接，所述第一存储电容的第二极板与第一公共电极端连接。
在一种实施例中，在液晶显示面板中，还包括第二公共电极端，所述第一液晶电容的第一极板与所述第一晶体管的第二电极连接，所述第一液晶电容的第二极板与所述第二公共电极端连接。
在一种实施例中，在液晶显示面板中，所述第二晶体管与所述第二存储电容串联，所述第二晶体管与所述第二液晶电容串联。
在一种实施例中，在液晶显示面板中，所述第二存储电容的第一极板与所述第二晶体管的第二电极连接，所述第二存储电容的第二极板与所述第一公共电极端连接。
在一种实施例中，在液晶显示面板中，所述第二液晶电容的第一极板与所述第二晶体管的第二电极连接，所述第二液晶电容的第二极板与所述第二公共电极端连接。
在一种实施例中，在液晶显示面板中，所述第一晶体管的第一电极与所述数据线连接，所述第二晶体管的第一电极与所述数据线连接，所述第一晶体管的第一电极与所述第二晶体管的第一电极连接。
在一种实施例中，在液晶显示面板中，所述子像素单元包括主子像素单元和副子像素单元，所述主子像素单元包括4个畴，所述副子像素单元包括4个畴。
根据以上实施例可知：
本申请提供一种像素驱动电路和液晶显示面板，该像素驱动电路包括多条扫描线与多条数据线，所述多条扫描线与多条数据线限定出多个子像素单元，至少一个所述子像素单元连接一条扫描线和一条数据线，所述子像素单元包括第一公共电极端、主子像素单元、副子像素单元和第三晶体管，所述主子像素单元包括第一晶体管、第一存储电容和第一液晶电容；所述副子像素单元包括第二晶体管、第二存储电容和第二液晶电容；所述第三晶体管的第二电极电连接第一公共电极端，其中，所述第一晶体管、第二晶体管和第三晶体管的栅极连接至扫描线，所述第一晶体管的一电极与所述第二晶体管的第一电极连接，所述第二晶体管的第二电极连接所述第三晶体管的第一电极；通过使用第一晶体管、第二晶体管、第三晶体管控制主子像素单元和副子像素单元，并将第一晶体管、第二晶体管和第三晶体的栅极连接至扫描线，使得一条扫描线即可控制三个晶体管，同时使得第三晶体管的第二电极连接第一公共电极端，使得电压信号从第一晶体管、第二晶体管和第三晶体管经过后，第三晶体管连接第一公共电极端造成主子像素与副子像素之间存在电位差，从而减小色偏，同时，由于一个子像素单元仅需一条扫描线控制，且减少了电容的数量，使得显示面板的开口率增大，同时，避免产生寄生电容，提高了显示效果。
可以理解的是，对本领域普通技术人员来说，可以根据本申请的技术方案及其发明构思加以等同替换或改变，而所有这些改变或替换都应属于本申请所附的权利要求的保护范围。

Claims (20)

  1. 一种像素驱动电路，其包括多条扫描线与多条数据线，所述多条扫描线与多条数据线限定出多个子像素单元，至少一个所述子像素单元连接一条扫描线和一条数据线，所述子像素单元包括：
    第一公共电极端；
    主子像素单元，包括第一晶体管、第一存储电容和第一液晶电容；
    副子像素单元，包括第二晶体管、第二存储电容和第二液晶电容；
    第三晶体管，所述第三晶体管的第二电极连接第一公共电极端；
    其中，所述第一晶体管、第二晶体管和第三晶体管的栅极连接至扫描线，所述第一晶体管的一电极与所述第二晶体管的第一电极连接，所述第二晶体管的第二电极连接所述第三晶体管的第一电极。
  2. 如权利要求1所述的像素驱动电路，其中，所述第一晶体管的第一电极与所述数据线连接，所述第一晶体管的第二电极连接所述第二晶体管的第一电极。
  3. 如权利要求2所述的像素驱动电路，其中，所述第一晶体管与所述第一存储电容串联，所述第一晶体管与所述第一液晶电容串联。
  4. 如权利要求3所述的像素驱动电路，其中，所述第一存储电容的第一极板与所述第一晶体管的第二电极连接，所述第一存储电容的第二极板与第一公共电极端连接。
  5. 如权利要求4所述的像素驱动电路，其中，还包括第二公共电极端，所述第一液晶电容的第一极板与所述第一晶体管的第二电极连接，所述第一液晶电容的第二极板与所述第二公共电极端连接。
  6. 如权利要求5所述的像素驱动电路，其中，所述第二晶体管与所述第二存储电容串联，所述第二晶体管与所述第二液晶电容串联。
  7. 如权利要求6所述的像素驱动电路，其中，所述第二存储电容的第一极板与所述第二晶体管的第二电极连接，所述第二存储电容的第二极板与所述第一公共电极端连接。
  8. 如权利要求7所述的像素驱动电路，其中，所述第二液晶电容的第一极板与所述第二晶体管的第二电极连接，所述第二液晶电容的第二极板与所述第二公共电极端连接。
  9. 如权利要求1所述的像素驱动电路，其中，所述第一晶体管的第一电极与所述数据线连接，所述第二晶体管的第一电极与所述数据线连接，所述第一晶体管的第一电极与所述第二晶体管的第一电极连接。
  10. 如权利要求1所述的像素驱动电路，其中，所述子像素单元包括主子像素单元和副子像素单元，所述主子像素单元包括4个畴，所述副子像素单元包括4个畴。
  11. 一种液晶显示面板，其包括像素驱动电路，所述像素驱动电路包括多条扫描线与多条数据线，所述多条扫描线与多条数据线限定出多个子像素单元，至少一个所述子像素单元连接一条扫描线和一条数据线，所述子像素单元包括：
    第一公共电极端；
    主子像素单元，包括第一晶体管、第一存储电容和第一液晶电容；
    副子像素单元，包括第二晶体管、第二存储电容和第二液晶电容；
    第三晶体管，所述第三晶体管的第二电极连接第一公共电极端；
    其中，所述第一晶体管、第二晶体管和第三晶体管的栅极连接至扫描线，所述第一晶体管的一电极与所述第二晶体管的第一电极连接，所述第二晶体管的第二电极连接所述第三晶体管的第一电极。
  12. 如权利要求11所述的液晶显示面板，其中，所述第一晶体管的第一电极与所述数据线连接，所述第一晶体管的第二电极连接所述第二晶体管的第一电极。
  13. 如权利要求12所述的液晶显示面板，其中，所述第一晶体管与所述第一存储电容串联，所述第一晶体管与所述第一液晶电容串联。
  14. 如权利要求13所述的液晶显示面板，其中，所述第一存储电容的第一极板与所述第一晶体管的第二电极连接，所述第一存储电容的第二极板与第一公共电极端连接。
  15. 如权利要求14所述的液晶显示面板，其中，还包括第二公共电极端，所述第一液晶电容的第一极板与所述第一晶体管的第二电极连接，所述第一液晶电容的第二极板与所述第二公共电极端连接。
  16. 如权利要求15所述的液晶显示面板，其中，所述第二晶体管与所述第二存储电容串联，所述第二晶体管与所述第二液晶电容串联。
  17. 如权利要求16所述的液晶显示面板，其中，所述第二存储电容的第一极板与所述第二晶体管的第二电极连接，所述第二存储电容的第二极板与所述第一公共电极端连接。
  18. 如权利要求17所述的液晶显示面板，其中，所述第二液晶电容的第一极板与所述第二晶体管的第二电极连接，所述第二液晶电容的第二极板与所述第二公共电极端连接。
  19. 如权利要求11所述的液晶显示面板，其中，所述第一晶体管的第一电极与所述数据线连接，所述第二晶体管的第一电极与所述数据线连接，所述第一晶体管的第一电极与所述第二晶体管的第一电极连接。
  20. 如权利要求11所述的液晶显示面板，其中，所述子像素单元包括主子像素单元和副子像素单元，所述主子像素单元包括4个畴，所述副子像素单元包括4个畴。
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