WO2018192048A1 - 八畴像素结构 - Google Patents

八畴像素结构 Download PDF

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WO2018192048A1
WO2018192048A1 PCT/CN2017/084950 CN2017084950W WO2018192048A1 WO 2018192048 A1 WO2018192048 A1 WO 2018192048A1 CN 2017084950 W CN2017084950 W CN 2017084950W WO 2018192048 A1 WO2018192048 A1 WO 2018192048A1
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area
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electrode
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PCT/CN2017/084950
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French (fr)
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甘启明
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深圳市华星光电半导体显示技术有限公司
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Priority to US15/541,472 priority Critical patent/US10222655B2/en
Publication of WO2018192048A1 publication Critical patent/WO2018192048A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • the present invention relates to the field of liquid crystal displays, and more particularly to an eight-domain pixel structure.
  • the liquid crystal display panel is generally composed of a color filter substrate, a thin film transistor array substrate, and a liquid crystal layer disposed between the two substrates, and a pixel electrode and a common electrode are respectively disposed on opposite sides of the two substrates, and the liquid crystal molecules are controlled to change direction by applying a voltage.
  • the light of the backlight module is refracted to produce a picture.
  • the liquid crystal display includes a plurality of display modes such as a twisted nematic (TN) mode, an electronically controlled birefringence (ECB) mode, and a vertical alignment (VA), wherein the VA mode is a high contrast, a wide viewing angle, and no friction alignment. Common display mode.
  • TN twisted nematic
  • EBC electronically controlled birefringence
  • VA vertical alignment
  • Common display mode since the VA mode uses vertically rotating liquid crystals, the difference in birefringence of liquid crystal molecules is relatively large, resulting in a serious color shift problem at a large viewing angle.
  • FIG. 1 it is a schematic circuit diagram of a conventional 3T pixel structure.
  • a plurality of sub-pixels in the liquid crystal display panel are arranged in an array, and each sub-pixel can be divided into a main region and a sub-region, including a main-region thin film transistor TFT_m, a main-region liquid crystal capacitor Clc_m, and a main region storage capacitor Cst_m.
  • the sub-region thin film transistor TFT_s, the sub-region liquid crystal capacitor Clc_s, the sub-region storage capacitor Cst_s, and the shared thin film transistor TFT_share respectively set a scan line Gate corresponding to each row of sub-pixels, and respectively set a data line Data corresponding to each column sub-pixel;
  • the gate of the thin film transistor TFT_m is connected to the scan line Gate, the source/drain is connected to the data line Data, and the main area liquid crystal capacitor Clc_m and the main area storage are connected in parallel between the drain/source and the common electrode A_com (or C_com).
  • the capacitor Cst_m; the gate of the sub-region thin film transistor TFT_s is connected to the scan line Gate, the source/drain is connected to the data line Data, and the sub-region liquid crystal capacitor is connected in parallel between the drain/source and the common electrode A_com (or C_com).
  • Clc_s and sub-region storage capacitor Cst_s; the gate of the shared thin film transistor TFT_share is connected to the scan line Gate, and the source and the drain thereof are respectively connected to the drain/source of the sub-region thin film transistor TFT_s Common electrode A_com.
  • the common electrodes A_com and C_com have different names, in the actual liquid crystal panel, the two potentials are usually The same can be expressed only by the common electrode A_com; for the thin film transistor, since the characteristics of the source and the drain are the same, the source and the drain are not particularly limited in the circuit; in the three-dimensional structure of the liquid crystal display panel, The two poles of the liquid crystal capacitor and the storage capacitor generally correspond to the pixel electrode (or the storage electrode having the same potential as the pixel electrode) and the common electrode, respectively.
  • the present invention provides an eight-domain pixel structure, including a plurality of sub-pixels arranged in an array in a liquid crystal display panel, each sub-pixel being divided into a main area and a sub-area, and one sub-pixel corresponding to each line is respectively disposed.
  • a scan line the scan line is between the main area and the sub-area, and a data line is respectively disposed corresponding to each column of sub-pixels; and further includes a main-area thin film transistor and a main-area storage capacitor, a sub-region thin film transistor and a sub-area storage capacitor;
  • the main area storage capacitor is formed by the first main area storage electrode and the opposite common electrode in the main area;
  • the sub-area storage capacitor is stored by the sub-area storage electrode in the sub-area and the second main area in the main area
  • the electrode is formed with the opposite common electrode, and the sub-region storage electrode and the second main-region storage electrode are electrically connected to each other across the scan line;
  • the gate of the main-region thin film transistor is connected to the scan line, and the source/drain is connected to the data line,
  • the drain/source is connected to the first main-region storage electrode or the pixel electrode of the main region;
  • the gate of the sub-region thin film transistor is connected to the scan line, and the source/drain
  • the main region and the sub-region respectively correspond to liquid crystal molecules of four domains.
  • the first main area storage electrode is connected to the pixel electrode of the main area via a via.
  • the sub-area storage electrode is connected to the pixel electrode of the sub-region via a via.
  • the first main area storage electrode, the secondary area storage electrode and the second main area storage electrode are made of the same metal layer.
  • the gate of the main-region thin film transistor, the gate of the sub-region thin film transistor, and the scan line are formed by the same metal layer.
  • the source and drain of the main-region thin film transistor, the source and drain of the sub-region thin film transistor, and the data line are formed by the same metal layer.
  • the pixel electrodes of the main area and the sub-area are made of indium tin oxide.
  • the present invention also provides an eight-domain pixel structure, comprising a plurality of sub-pixels arranged in an array in a liquid crystal display panel, each sub-pixel being divided into a main area and a sub-area, and each scan line is respectively provided with a scan line, the scan The line is between the main area and the sub-area, and one data line is respectively disposed corresponding to each column of sub-pixels; and the main area thin film transistor and the main area storage capacitor, the sub-region thin film transistor and the sub-area storage capacitor; the main area storage capacitor Forming from the first main area storage electrode in the main area and the opposite common electrode; the sub-area storage capacitor is from the sub-area storage electrode in the sub-area and the second main-area storage electrode in the main area and the opposite common The electrode is formed, the secondary region storage electrode and the second main region storage electrode are electrically connected to each other across the scan line; the gate of the main region thin film transistor is connected to the scan line, and the source/drain is connected to the data line, and the drain/source thereof
  • main region and the sub-region respectively correspond to liquid crystal molecules of four domains
  • the first main area storage electrode is connected to the pixel electrode of the main area via a via.
  • the eight-domain pixel structure of the present invention can achieve the purpose of controlling the differential ratio of the main region and the sub-region by reducing the storage capacitance of the main region and increasing the storage capacitance of the sub-region; in addition, since the discharge is not formed directly with the common electrode A_com The path does not have the problem that the difference between the best common voltages in the main area and the sub-area is too large.
  • 1 is a circuit diagram of a conventional 3T pixel structure
  • FIG. 2 is a circuit diagram of an eight-domain pixel structure of the present invention.
  • FIG. 3 is a schematic diagram of an eight-domain pixel structure of the present invention.
  • FIG. 3 it is a schematic diagram of an eight-domain pixel structure of the present invention. It will be understood by those skilled in the art that the present invention focuses on the improvement of the eight-domain pixel structure, and therefore the general structure included in the liquid crystal display panel and the pixel will not be described in the following description.
  • the eight-domain pixel structure of the present invention includes a plurality of sub-pixels arranged in an array in the liquid crystal display panel. Each sub-pixel is divided into a main area 10 and a sub-area 20, and a scan line 30 is respectively disposed corresponding to each row of sub-pixels.
  • the line 30 is between the main area 10 and the sub-area 20, and one data line 40 is respectively disposed corresponding to each column sub-pixel; further includes a main-area thin film transistor 11 and a main area storage capacitor, The thin film transistor 21 and the sub-region storage capacitor; the main-region storage capacitor is formed by the main-region storage electrode 12 and the opposite common electrode 50 in the range of the main region 10; the sub-region storage capacitor is stored in the sub-region within the sub-region 20
  • the electrode 22 and the main-region storage electrode 13 in the range of the main region 10 are formed with the opposite common electrode 50, and the sub-region storage electrode 22 and the main-region storage electrode 13 are electrically connected to each other across the scanning line 30; the main-region thin film transistor 11
  • the gate is connected to the scan line 30, the source/drain is connected to the data line 40, the drain/source is connected to the main area storage electrode 12 or the pixel electrode 14 of the main area 10; and the gate connection scan of the sub-region thin film transistor 21 is performed.
  • the line 30 has
  • the main region 10 and the sub-region 20 correspond to liquid crystal molecules of four domains, respectively.
  • the main area storage electrode 12 may be connected to the pixel electrode 14 via a via; the sub-area storage electrode 22 may be connected to the pixel electrode 23 via a via.
  • the main area storage electrode 12, the sub-area storage electrode 22, and the main area storage electrode 13 can be fabricated by the same metal layer.
  • the gate of the main-region thin film transistor 11, the gate of the sub-region thin film transistor 21, and the scanning line 30 can be formed by the same metal layer.
  • the source and drain of the main-region thin film transistor 11, the source and drain of the sub-region thin film transistor 21, and the data line 40 can be formed by the same metal layer.
  • the pixel electrode 14 and the pixel electrode 23 may be made of indium tin oxide.
  • the eight-domain pixel structure of the present invention may be a PSVA pixel.
  • FIG. 2 is a circuit diagram of an eight-domain pixel structure of the present invention
  • the present invention can be further understood in conjunction with FIGS. 2 and 3.
  • a plurality of sub-pixels in the liquid crystal display panel are arranged in an array, and each sub-pixel can be divided into a main region and a sub-region, including a main-region thin film transistor TFT_m, a main-region liquid crystal capacitor Clc_m, a main-region storage capacitor Cst_m, and a sub-region thin film transistor TFT_s.
  • the sub-region liquid crystal capacitor Clc_s, the sub-region storage capacitor Cst_s, and the sub-region storage capacitor Cst_s1 respectively set a scan line Gate corresponding to each row of sub-pixels, and one data line Data is respectively corresponding to each column sub-pixel; the gate of the main-region thin film transistor TFT_m The pole is connected to the scan line Gate, and the source/drain is connected to the data line Data, and the main area liquid crystal capacitor Clc_m and the main area storage capacitor Cst_m are connected in parallel between the drain/source and the common electrode A_com (or C_com);
  • the gate of the thin film transistor TFT_s is connected to the scan line Gate, the source/drain is connected to the data line Data, and the sub-region liquid crystal capacitor Clc_s is connected in parallel between the drain/source and the common electrode A_com (or C_com), and the sub-area is stored.
  • the core idea of the present invention is to form a storage capacitor Cst_s1 over the common electrode A_com of the main region by crossing the scan line Gate according to the sub-region shown in FIG. 2, so that the storage capacitance of the sub-region is increased to the extreme, and the main memory is also relatively reduced.
  • the area storage capacitor can achieve the purpose of controlling the differential ratio of the main area and the sub-area; in addition, since the path of direct discharge with A_com is not formed like the circuit of the conventional 3T pixel structure of FIG. 1, there is no main area and sub-area. The problem of the best common voltage difference is too large.
  • the eight-domain pixel structure of the present invention can achieve the purpose of controlling the differential ratio of the main region and the sub-region by reducing the storage capacitance of the main region and increasing the storage capacitance of the sub-region;
  • the path in which the electrode A_com is directly discharged does not have a problem that the difference in the optimum common voltage between the main region and the sub-region is too large.

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Abstract

一种八畴像素结构。八畴像素结构包括多个子像素在液晶显示面板内呈阵列式排布，每个子像素分为主区（10）和次区（20），对应每一行子像素分别设置一条扫描线（30、Gate），扫描线（30、Gate）介于主区（10）和次区（20）之间，对应每一列子像素分别设置一条数据线（40、Data）；还包括主区薄膜晶体管（11、TFT_m）以及主区存储电容（Cst_m），次区薄膜晶体管（21、TFT_s）以及次区存储电容（Cst_s、Cst_s1）；主区存储电容（Cst_m）由主区（10）范围内的第一主区存储电极（12）与相对的公共电极（50、A_com）形成；次区存储电容（Cst_s、Cst_s1）由次区（20）范围内的次区存储电极（22）及主区（10）范围内的第二主区存储电极（13）与相对的公共电极（50、A_com）形成，次区存储电极（22）及第二主区存储电极（13）跨过扫描线（30、Gate）相互导通。可以达到控制主区（10）及次区（20）压差比的目的，不会存在主区（10）及次区（20）最佳公共电压差异太大的问题。

Description

八畴像素结构 技术领域
本发明涉及液晶显示器领域，尤其涉及一种八畴像素结构。
背景技术
液晶显示面板通常由彩色滤光片基板、薄膜晶体管阵列基板以及配置于两基板间的液晶层所构成，并分别在两基板的相对内侧设置像素电极、公共电极，通过施加电压控制液晶分子改变方向，将背光模组的光线折射出来产生画面。液晶显示器包括扭曲向列(TN)模式、电子控制双折射(ECB)模式、垂直配向(VA)等多种显示模式，其中，VA模式是一种具有高对比度、宽视角、无须摩擦配向等优势的常见显示模式。但由于VA模式采用垂直转动的液晶，液晶分子双折射率的差异比较大，导致大视角下的色偏(color shift)问题比较严重。
随着液晶显示技术的发展，显示屏幕的尺寸越来越大，传统采用4domain(4畴)的PSVA(聚合物稳定垂直配向)像素会凸显视角色偏的不良表现。为了提升面板视角表现，3T_8domain(8畴3晶体管)的PSVA像素逐渐应用于大尺寸电视面板的设计，使同一个子像素(sub pixel)内主(main)区的4个畴与次(sub)区的4个畴的液晶分子的转动角度不一样，从而改善色偏。如图1所示，其为现有的3T像素结构的电路示意图。液晶显示面板内多个子像素呈阵列式排布，每个子像素可分为主(main)区和次(sub)区，包括主区薄膜晶体管TFT_m，主区液晶电容Clc_m，主区存储电容Cst_m，次区薄膜晶体管TFT_s，次区液晶电容Clc_s，次区存储电容Cst_s，以及共享薄膜晶体管TFT_share，对应每一行子像素分别设置一条扫描线Gate，对应每一列子像素分别设置一条数据线Data；主区薄膜晶体管TFT_m的栅极连接扫描线Gate，其源极/漏极连接数据线Data，在其漏极/源极与公共电极A_com(或C_com)之间并联连接主区液晶电容Clc_m和主区存储电容Cst_m；次区薄膜晶体管TFT_s的栅极连接扫描线Gate，其源极/漏极连接数据线Data，在其漏极/源极与公共电极A_com(或C_com)之间并联连接次区液晶电容Clc_s和次区存储电容Cst_s；共享薄膜晶体管TFT_share的栅极连接扫描线Gate，其源极和漏极分别连接该次区薄膜晶体管TFT_s的漏极/源极和公共电极A_com。本领域技术人员可以理解，虽然公共电极A_com和C_com名称不同，但是在实际液晶面板中两者通常电位 相同，可以仅以公共电极A_com来表示；对于薄膜晶体管，由于其源极和漏极的特性一样，因此在电路中不对其源极和漏极进行特别限定；在液晶显示面板的立体结构中，液晶电容和存储电容的两极通常分别对应像素电极(或与像素电极电位相同的存储电极)和公共电极。
8畴像素已经成为大尺寸TV面板的像素设计趋势，但是在高分辨率高刷新频率下，为改善闪烁(Flicker)现象，主区与次区最佳公共电压(best vcom)的平衡始终是一个难点。如何解决这个难点是使用现有3T像素必须考虑的重要问题。
发明内容
因此，本发明的目的在于提供一种八畴像素结构，平衡主区和次区的压差比及最佳公共电压。
为实现上述目的，本发明提供了一种八畴像素结构，包括多个子像素在液晶显示面板内呈阵列式排布，每个子像素分为主区和次区，对应每一行子像素分别设置一条扫描线，该扫描线介于该主区和次区之间，对应每一列子像素分别设置一条数据线；还包括主区薄膜晶体管以及主区存储电容，次区薄膜晶体管以及次区存储电容；该主区存储电容由主区范围内的第一主区存储电极与相对的公共电极形成；该次区存储电容由次区范围内的次区存储电极及主区范围内的第二主区存储电极与相对的公共电极形成，该次区存储电极及第二主区存储电极跨过扫描线相互导通；该主区薄膜晶体管的栅极连接扫描线，其源极/漏极连接数据线，其漏极/源极连接第一主区存储电极或主区的像素电极；该次区薄膜晶体管的栅极连接扫描线，其源极/漏极连接数据线，其漏极/源极连接次区存储电极或次区的像素电极。
其中，所述主区和次区各自对应四个畴的液晶分子。
其中，所述第一主区存储电极经由过孔与主区的像素电极相连接。
其中，所述次区存储电极经由过孔与次区的像素电极相连接。
其中，所述第一主区存储电极，次区存储电极及第二主区存储电极通过同一金属层制作。
其中，所述主区薄膜晶体管的栅极，次区薄膜晶体管的栅极，以及扫描线通过同一金属层制作。
其中，所述主区薄膜晶体管的源极和漏极，次区薄膜晶体管的源极和漏极，以及数据线通过同一金属层制作。
其中，所述主区和次区的像素电极由氧化铟锡制成。
其中，其为PSVA像素。
本发明还提供一种八畴像素结构，包括多个子像素在液晶显示面板内呈阵列式排布，每个子像素分为主区和次区，对应每一行子像素分别设置一条扫描线，该扫描线介于该主区和次区之间，对应每一列子像素分别设置一条数据线；还包括主区薄膜晶体管以及主区存储电容，次区薄膜晶体管以及次区存储电容；该主区存储电容由主区范围内的第一主区存储电极与相对的公共电极形成；该次区存储电容由次区范围内的次区存储电极及主区范围内的第二主区存储电极与相对的公共电极形成，该次区存储电极及第二主区存储电极跨过扫描线相互导通；该主区薄膜晶体管的栅极连接扫描线，其源极/漏极连接数据线，其漏极/源极连接第一主区存储电极或主区的像素电极；该次区薄膜晶体管的栅极连接扫描线，其源极/漏极连接数据线，其漏极/源极连接次区存储电极或次区的像素电极；
其中，所述主区和次区各自对应四个畴的液晶分子；
其中，所述第一主区存储电极经由过孔与主区的像素电极相连接。
综上，本发明的八畴像素结构通过减小主区存储电容，增大次区存储电容，可以达到控制主区及次区压差比的目的；另外，由于未形成与公共电极A_com直接放电的通路，不会存在主区及次区最佳公共电压差异太大的问题。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其他有益效果显而易见。
附图中，
图1为现有的3T像素结构的电路示意图；
图2为本发明八畴像素结构的电路示意图；
图3为本发明八畴像素结构的示意图。
具体实施方式
参见图3，其为本发明八畴像素结构的示意图。本领域技术人员可以理解，本发明重点在于对八畴像素结构的改进，因此以下说明中对液晶显示面板及像素中包含的一般结构不再赘述。
本发明的八畴像素结构，包括多个子像素在液晶显示面板内呈阵列式排布，每个子像素分为主区10和次区20，对应每一行子像素分别设置一条扫描线30，该扫描线30介于该主区10和次区20之间，对应每一列子像素分别设置一条数据线40；还包括主区薄膜晶体管11以及主区存储电容，次 区薄膜晶体管21以及次区存储电容；该主区存储电容由主区10范围内的主区存储电极12与相对的公共电极50形成；该次区存储电容由次区20范围内的次区存储电极22及主区10范围内的主区存储电极13与相对的公共电极50形成，该次区存储电极22及主区存储电极13跨过扫描线30相互导通；该主区薄膜晶体管11的栅极连接扫描线30，其源极/漏极连接数据线40，其漏极/源极连接主区存储电极12或主区10的像素电极14；该次区薄膜晶体管21的栅极连接扫描线30，其源极/漏极连接数据线40，其漏极/源极连接次区存储电极22或次区20的像素电极23。
主区10和次区20分别对应四个畴的液晶分子。制程中，主区存储电极12可以经由过孔与像素电极14相连接；次区存储电极22可以经由过孔与像素电极23相连接。主区存储电极12，次区存储电极22及主区存储电极13可以通过同一金属层制作。主区薄膜晶体管11的栅极，次区薄膜晶体管21的栅极，以及扫描线30可以通过同一金属层制作。主区薄膜晶体管11的源极和漏极，次区薄膜晶体管21的源极和漏极，以及数据线40可以通过同一金属层制作。像素电极14和像素电极23可以由氧化铟锡制成。本发明的八畴像素结构可以为PSVA像素。
参见图2，其为本发明八畴像素结构的电路示意图，结合图2及图3可进一步理解本发明。液晶显示面板内多个子像素呈阵列式排布，每个子像素可分为主区和次区，包括主区薄膜晶体管TFT_m，主区液晶电容Clc_m，主区存储电容Cst_m，次区薄膜晶体管TFT_s，次区液晶电容Clc_s，次区存储电容Cst_s，以及次区存储电容Cst_s1，对应每一行子像素分别设置一条扫描线Gate，对应每一列子像素分别设置一条数据线Data；主区薄膜晶体管TFT_m的栅极连接扫描线Gate，其源极/漏极连接数据线Data，在其漏极/源极与公共电极A_com(或C_com)之间并联连接主区液晶电容Clc_m和主区存储电容Cst_m；次区薄膜晶体管TFT_s的栅极连接扫描线Gate，其源极/漏极连接数据线Data，在其漏极/源极与公共电极A_com(或C_com)之间并联连接次区液晶电容Clc_s，次区存储电容Cst_s，以及次区存储电容Cst_s1。本发明的核心思想就是按照图2所示次区通过跨过扫描线Gate，在主区的公共电极A_com上方形成存储电容Cst_s1，使次区存储电容增大到极致，同时还相对减小了主区存储电容，可以达到控制主区及次区压差比的目的；另外，由于未像图1现有的3T像素结构的电路一样形成与A_com直接放电的通路，不会存在主区及次区最佳公共电压差异太大的问题。
综上，本发明的八畴像素结构通过减小主区存储电容，增大次区存储电容，可以达到控制主区及次区压差比的目的；另外，由于未形成与公共 电极A_com直接放电的通路，不会存在主区及次区最佳公共电压差异太大的问题。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明后附的权利要求的保护范围。

Claims (16)

  1. 一种八畴像素结构，包括多个子像素在液晶显示面板内呈阵列式排布，每个子像素分为主区和次区，对应每一行子像素分别设置一条扫描线，该扫描线介于该主区和次区之间，对应每一列子像素分别设置一条数据线；还包括主区薄膜晶体管以及主区存储电容，次区薄膜晶体管以及次区存储电容；该主区存储电容由主区范围内的第一主区存储电极与相对的公共电极形成；该次区存储电容由次区范围内的次区存储电极及主区范围内的第二主区存储电极与相对的公共电极形成，该次区存储电极及第二主区存储电极跨过扫描线相互导通；该主区薄膜晶体管的栅极连接扫描线，其源极/漏极连接数据线，其漏极/源极连接第一主区存储电极或主区的像素电极；该次区薄膜晶体管的栅极连接扫描线，其源极/漏极连接数据线，其漏极/源极连接次区存储电极或次区的像素电极。
  2. 如权利要求1所述的八畴像素结构，其中，所述主区和次区各自对应四个畴的液晶分子。
  3. 如权利要求1所述的八畴像素结构，其中，所述第一主区存储电极经由过孔与主区的像素电极相连接。
  4. 如权利要求1所述的八畴像素结构，其中，所述次区存储电极经由过孔与次区的像素电极相连接。
  5. 如权利要求1所述的八畴像素结构，其中，所述第一主区存储电极，次区存储电极及第二主区存储电极通过同一金属层制作。
  6. 如权利要求1所述的八畴像素结构，其中，所述主区薄膜晶体管的栅极，次区薄膜晶体管的栅极，以及扫描线通过同一金属层制作。
  7. 如权利要求1所述的八畴像素结构，其中，所述主区薄膜晶体管的源极和漏极，次区薄膜晶体管的源极和漏极，以及数据线通过同一金属层制作。
  8. 如权利要求1所述的八畴像素结构，其中，所述主区和次区的像素电极由氧化铟锡制成。
  9. 如权利要求1所述的八畴像素结构，其中，其为PSVA像素。
  10. 一种八畴像素结构，包括多个子像素在液晶显示面板内呈阵列式排布，每个子像素分为主区和次区，对应每一行子像素分别设置一条扫描线，该扫描线介于该主区和次区之间，对应每一列子像素分别设置一条数据线；还包括主区薄膜晶体管以及主区存储电容，次区薄膜晶体管以及次 区存储电容；该主区存储电容由主区范围内的第一主区存储电极与相对的公共电极形成；该次区存储电容由次区范围内的次区存储电极及主区范围内的第二主区存储电极与相对的公共电极形成，该次区存储电极及第二主区存储电极跨过扫描线相互导通；该主区薄膜晶体管的栅极连接扫描线，其源极/漏极连接数据线，其漏极/源极连接第一主区存储电极或主区的像素电极；该次区薄膜晶体管的栅极连接扫描线，其源极/漏极连接数据线，其漏极/源极连接次区存储电极或次区的像素电极；
    其中，所述主区和次区各自对应四个畴的液晶分子；
    其中，所述第一主区存储电极经由过孔与主区的像素电极相连接。
  11. 如权利要求10所述的八畴像素结构，其中，所述次区存储电极经由过孔与次区的像素电极相连接。
  12. 如权利要求10所述的八畴像素结构，其中，所述第一主区存储电极，次区存储电极及第二主区存储电极通过同一金属层制作。
  13. 如权利要求10所述的八畴像素结构，其中，所述主区薄膜晶体管的栅极，次区薄膜晶体管的栅极，以及扫描线通过同一金属层制作。
  14. 如权利要求10所述的八畴像素结构，其中，所述主区薄膜晶体管的源极和漏极，次区薄膜晶体管的源极和漏极，以及数据线通过同一金属层制作。
  15. 如权利要求10所述的八畴像素结构，其中，所述主区和次区的像素电极由氧化铟锡制成。
  16. 如权利要求10所述的八畴像素结构，其中，其为PSVA像素。
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