WO2016187921A1 - 高画质液晶显示器像素电路 - Google Patents

高画质液晶显示器像素电路 Download PDF

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WO2016187921A1
WO2016187921A1 PCT/CN2015/082264 CN2015082264W WO2016187921A1 WO 2016187921 A1 WO2016187921 A1 WO 2016187921A1 CN 2015082264 W CN2015082264 W CN 2015082264W WO 2016187921 A1 WO2016187921 A1 WO 2016187921A1
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data signal
sub
capacitor
electrically connected
voltage
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PCT/CN2015/082264
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English (en)
French (fr)
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徐洪远
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深圳市华星光电技术有限公司
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Priority to US14/771,500 priority Critical patent/US9551912B2/en
Publication of WO2016187921A1 publication Critical patent/WO2016187921A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0443—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations
    • G09G2300/0447—Pixel structures with several sub-pixels for the same colour in a pixel, not specifically used to display gradations for multi-domain technique to improve the viewing angle in a liquid crystal display, such as multi-vertical alignment [MVA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a pixel circuit of a high-quality liquid crystal display.
  • LCD Liquid crystal display
  • PDAs personal digital assistants
  • digital cameras computer screens or laptop screens, etc.
  • liquid crystal displays which include a casing, a liquid crystal display panel disposed in the casing, and a backlight module disposed in the casing.
  • the liquid crystal display panel is the main component of the liquid crystal display, but the liquid crystal display panel itself does not emit light, and the light source provided by the backlight module needs to be used to display the image normally.
  • the liquid crystal display panel comprises a color filter substrate (CF), a thin film transistor array substrate (Thin Film Transistor Array Substrate, TFT Array Substrate), and a liquid crystal layer (Liquid Crystal Layer) disposed between the two substrates.
  • the pixel electrode and the common electrode are respectively disposed on opposite sides of the two substrates, and the liquid crystal molecules are controlled to change direction by applying a voltage, and the light of the backlight module is refracted to generate a picture.
  • the liquid crystal display includes a Twisted Nematic (TN) mode, an Electronically Controlled Birefringence (ECB) mode, a Vertical Alignment (VA), and the like, wherein the VA mode is high.
  • TN Twisted Nematic
  • EB Electronically Controlled Birefringence
  • VA Vertical Alignment
  • Common display modes such as contrast, wide viewing angle, and no need for friction alignment.
  • the VA mode uses vertically rotating liquid crystals, the difference in birefringence of liquid crystal molecules is relatively large, resulting in a serious color shift problem at a large viewing angle.
  • the mainstream method for solving the color shift of the VA mode liquid crystal display is to adopt a multi-domain, such as a pixel design of an 8-domain display, so that the four domains and the sub-regions of the main sub-pixel within the same sub-pixel (sub) 4
  • the liquid crystal molecules of the domains have different rotation angles, thereby improving the color shift.
  • the color shift improvement technologies mainly include capacitive coupling (CC) technology, charge sharing (CS) technology, common electrode voltage (Vcom) modulation technology, and 2D1G/2G1D technology.
  • CC capacitive coupling
  • CS charge sharing
  • Vcom common electrode voltage
  • 2D1G/2G1D technology common electrode voltage
  • FIG. 1 is a general architectural diagram of a conventional pixel circuit for improving the color shift problem of a VA mode liquid crystal display
  • FIG. 2 is a specific circuit diagram corresponding to FIG.
  • a plurality of sub-pixels are arranged in an array, and each sub-pixel is divided into a main area Main and a sub-area Sub, and a scan line is respectively disposed corresponding to each row of sub-pixels, and one sub-pixel is respectively set for each sub-pixel.
  • the data signal line, a voltage dividing unit 100, and a trace is respectively set for each sub-pixel.
  • the Mth scan line G(M) is electrically connected at the same time and provides a scan signal to the main area Main and sub-subsub of the M-th sub-pixel; the Nth data signal line D(N)
  • the main data signal voltage is electrically connected to the main area Main of the Nth column sub-pixel, and the Nth data signal line D(N) is electrically connected to the common electrode line Com via the voltage dividing unit 100, and the corresponding Nth
  • the strip line L(N) is led out by the voltage dividing unit 100, and is electrically connected and provides a sub-data signal voltage different from the main data signal voltage to the sub-region Sub of the N-th column sub-pixel.
  • the voltage dividing unit 100 includes a first capacitor C1 and a second capacitor C2 connected in series.
  • One end of the first capacitor C1 is electrically connected to the data signal line, and the other end is electrically connected to one end of the second capacitor C2.
  • the other end of the two capacitor C2 is electrically connected to the common electrode line Com.
  • the Nth trace L(N) is drawn between the capacitor C1 and the second capacitor C2.
  • the secondary data signal voltage is higher than the main
  • the data signal voltage is closer to the common electrode voltage, that is, the voltage difference between the secondary data signal voltage and the common voltage must be smaller than the voltage difference between the main data signal voltage and the common electrode voltage, so that the voltage applied to the main area Main and the sub-sub Sub in one pixel Different, to achieve the purpose of improving color cast.
  • the Nth data signal line D(N) corresponding to the Nth column sub-pixel and the corresponding Nth line L(N) The polarity of the main data signal voltage and the voltage of the sub-data signal are the same, so that the polarity of the voltage applied to the main area Main and the sub-sub Sub in one sub-pixel is the same in the same frame picture, and the liquid crystal display panel is still caused. The flicker is more noticeable and the display quality is lowered.
  • the object of the present invention is to provide a high-definition liquid crystal display pixel circuit capable of reducing the color shift of the VA mode liquid crystal display and realizing a sub-pixel main area without increasing the number of data signal lines and the number of COF terminals.
  • the sub-area displays the opposite polarity in one frame, reducing the flicker of the liquid crystal display panel and improving the display quality.
  • the present invention provides a pixel circuit of a high-quality liquid crystal display, in which a plurality of sub-pixels are arranged in an array, each sub-pixel is divided into a main area and a sub-area, and a scan is set for each sub-pixel.
  • a line, corresponding to each column of sub-pixels respectively set a data signal line, a voltage dividing unit, and a trace;
  • the Mth scan line is electrically connected at the same time and provides a scan signal to the main area and the sub-area of the Mth sub-pixel;
  • the Nth data signal line is electrically connected and provides the main data signal voltage to a main area of the Nth column of sub-pixels, and the Nth data signal line is electrically connected to the common electrode line via a voltage dividing unit, and the corresponding Nth line is led out by the voltage dividing unit, electrically connected and provided
  • the voltage dividing unit divides the secondary data signal voltage obtained by dividing the main data signal voltage to the sub-region of the N+1th column sub-pixel of the next column;
  • the main data signal voltage supplied from the Nth data signal line is opposite to the polarity of the main data signal voltage supplied from the next N+1th data signal line.
  • the voltage dividing unit includes a first capacitor and a second capacitor connected in series; one end of the first capacitor is electrically connected to the data signal line, and the other end is electrically connected to one end of the second capacitor; One end is electrically connected to the common electrode line; the trace is drawn between the first capacitor and the second capacitor.
  • the main area includes a first thin film transistor, a first liquid crystal capacitor, and a first storage capacitor; and the sub-region includes a second thin film transistor, a second liquid crystal capacitor, and a second storage capacitor;
  • the gate of the first thin film transistor is electrically connected to the Mth scan line, and the source is electrically connected to the Nth data signal line;
  • the first liquid crystal capacitor and the first The storage capacitors are connected in parallel with one end electrically connected to the drain of the first thin film transistor, and the other end is electrically connected to a constant voltage;
  • the gate of the second thin film transistor is electrically connected to the Mth scan line, and the source is electrically Connected to the N-1th trace corresponding to the N-1th column sub-pixel of the previous column;
  • the second liquid crystal capacitor and the second storage capacitor are connected in parallel, one end is electrically connected to the drain of the second thin film transistor, and the other end is electrically Sexually connected to a constant voltage;
  • the source of the first thin film transistor is electrically connected to the (N+1)th data signal line; and the source of the second thin film transistor is electrically connected to the Nth The Nth trace of the column subpixel.
  • the primary sub-regions respectively comprise four domains.
  • the Nth data signal line supplies a main data signal voltage to four domains in a main area of the Nth column sub-pixel, and the Nth line is downwardly arranged in four sub-regions of the N+1th column sub-pixel.
  • the domain provides a secondary data signal voltage; under the partial pressure of the first capacitor and the second capacitor, the relationship between the primary data signal voltage and the secondary data signal voltage is:
  • Vsub (C1/(C1+C2)) ⁇ (Vmain-Vcom)+Vcom
  • Vsub represents the secondary data signal voltage
  • Vmain represents the primary data signal voltage
  • C1 represents the first capacitance
  • C2 represents the second capacitance
  • Vcom represents the common electrode voltage
  • the first capacitor and the second capacitor are formed by the second metal layer and the first metal layer.
  • the first capacitor and the second capacitor are formed by the ITO pixel electrode and the first metal layer.
  • the sizes of the first capacitor and the second capacitor are respectively determined by the areas of the first capacitor and the second capacitor.
  • the difference between the primary data signal voltage and the secondary data signal voltage is varied by changing the area of the first capacitance and the second capacitance.
  • the invention also provides a high-definition liquid crystal display pixel circuit, wherein a plurality of sub-pixels are arranged in an array, each sub-pixel is divided into a main area and a sub-area, and a scan line is respectively arranged corresponding to each row of sub-pixels, corresponding to each The column sub-pixels respectively set a data signal line, a voltage dividing unit, and a routing line;
  • the Mth scan line is electrically connected at the same time and provides a scan signal to the main area and the sub-area of the Mth sub-pixel;
  • the Nth data signal line is electrically connected and provides the main data signal voltage to a main area of the Nth column of sub-pixels, and the Nth data signal line is electrically connected to the common electrode line via a voltage dividing unit, and the corresponding Nth line is led out by the voltage dividing unit, electrically connected and provided
  • the voltage dividing unit divides the secondary data signal voltage obtained by dividing the main data signal voltage to the sub-region of the N+1th column sub-pixel of the next column;
  • the polarity of the main data signal voltage provided by the Nth data signal line is opposite to the polarity of the main data signal voltage provided by the next N+1th data signal line;
  • the voltage dividing unit includes a first capacitor and a second capacitor connected in series; one end of the first capacitor is electrically connected to the data signal line, and the other end is electrically connected to one end of the second capacitor; the second capacitor The other end is electrically connected to the common electrode line; the trace is drawn between the first capacitor and the second capacitor;
  • the main area includes a first thin film transistor, a first liquid crystal capacitor, and a first storage capacitor; and the sub-region includes a second thin film transistor, a second liquid crystal capacitor, and a second storage capacitor;
  • the gate of the first thin film transistor is electrically connected to the Mth scan line, and the source is electrically connected to the Nth data signal line;
  • the first liquid crystal capacitor and the first The storage capacitors are connected in parallel with one end electrically connected to the drain of the first thin film transistor, and the other end is electrically connected to a constant voltage;
  • the gate of the second thin film transistor is electrically connected to the Mth scan line, and the source is electrically Connected to the N-1th trace corresponding to the N-1th column sub-pixel of the previous column;
  • the second liquid crystal capacitor and the second storage capacitor are connected in parallel, one end is electrically connected to the drain of the second thin film transistor, and the other end is electrically Sexually connected to a constant voltage;
  • the source of the first thin film transistor is electrically connected to The N+1th data signal line;
  • the source of the second thin film transistor is electrically connected to the Nth trace corresponding to the Nth column sub-pixel;
  • the first capacitor and the second capacitor are formed by the second metal layer and the first metal layer.
  • the invention provides a high-definition liquid crystal display pixel circuit, which electrically connects the Nth data signal line and provides a main data signal voltage to the main area of the Nth column sub-pixel, and the corresponding Nth
  • the strip trace is led out by the voltage dividing unit, electrically connected and provides a sub-data signal voltage obtained by dividing the main data signal voltage by the voltage dividing unit to the sub-region of the next column N+1 column sub-pixel, and setting the Nth strip
  • the main data signal voltage provided by the data signal line is opposite to the polarity of the main data signal voltage provided by the (N+1)th data signal line, thereby realizing the reduction of the VA mode liquid crystal without increasing the number of lines of the data signal and the number of COF ends.
  • the color shift of the display causes the sub-pixel main area and the sub-area to display opposite polarities in one frame, thereby reducing the flicker of the liquid crystal display panel and improving the display image quality.
  • FIG. 1 is a general architectural diagram of a conventional pixel circuit for improving a color shift problem of a VA mode liquid crystal display
  • Figure 2 is a specific circuit diagram corresponding to Figure 1;
  • FIG. 3 is a general architectural diagram of a pixel circuit of a high definition liquid crystal display of the present invention.
  • FIG. 4 is a specific circuit diagram corresponding to FIG. 3.
  • the present invention provides a pixel circuit of a high-quality liquid crystal display: a plurality of sub-pixels are arranged in an array, and each sub-pixel is divided into a main area Main and a sub-sub Sub, corresponding to each line.
  • Each of the pixels is provided with one scanning line, and one data signal line, one voltage dividing unit 10, and one routing line are respectively disposed corresponding to each column of sub-pixels.
  • the Mth scan line G(M) is electrically connected at the same time and provides a scan signal to the main area Main and sub-subsub of the M-th sub-pixel; the Nth data signal line D(N) Electrically connecting and providing a main data signal voltage to the main area Main of the Nth column sub-pixel, and the Nth data signal line D(N) is electrically connected to the common electrode line Com via the voltage dividing unit 10, correspondingly
  • the Nth trace L(N) is led out by the voltage dividing unit 10, and is electrically connected and provides a secondary data signal voltage obtained by dividing the voltage of the main data signal by the voltage dividing unit 10 to the next column N+1.
  • the sub-region Sub of the column sub-pixel is correspondingly.
  • the first data signal line D(1) is electrically connected and provides the main data signal voltage to the main area Main of the first column of sub-pixels, and the corresponding first line L(1) is taken out by the voltage dividing unit 10. Electrically connecting and providing a secondary data signal voltage obtained by dividing the main data signal voltage by the voltage dividing unit 10 to a sub-region Sub of the second column sub-pixel; the second data signal line D(2) is electrically connected and provided The main data signal voltage is to the main area Main of the second column sub-pixel, and the corresponding second line L(2) is taken out by the voltage dividing unit 10, electrically connected and provided by the voltage dividing unit 10 for the main data signal voltage.
  • the sub-data signal voltage obtained by dividing the voltage to the sub-region Sub of the third column sub-pixel; and so on.
  • the polarity of the main data signal voltage provided by the adjacent two data signal lines is opposite, and the polarity of the main data signal voltage provided by the Nth data signal line D(N) is negative.
  • the polarity of the main data signal voltage supplied from the N-1th data signal line D(N-1) and the (N+1)th data signal line D(N+1) is positive.
  • the main area Main of each sub-pixel receives the negative main data signal voltage provided by the Nth data signal line D(N), and the sub-area Sub receives the divided voltage.
  • the unit 10 divides the positive primary data signal voltage supplied from the N-1th data signal line D(N-1) into a secondary data signal voltage which is also positive polarity; for the N+1th column subpixel, The main area Main of one sub-pixel receives the positive main data signal voltage provided by the N+1th data signal line D(N+1), and the sub-area Sub receives the voltage division unit 10
  • the negative data data signal line D(N) provides a negative polarity secondary data signal voltage obtained by dividing the negative primary data signal voltage. It can be seen that the pixel circuit of the present invention realizes that one sub-pixel main area Main and the sub-area Sub display opposite polarities in one frame of the screen, thereby reducing flicker of the liquid crystal display panel and improving display image quality.
  • the voltage dividing unit 10 includes a first capacitor C1 and a second capacitor C2 connected in series.
  • One end of the first capacitor C1 is electrically connected to the data signal line, the other end is electrically connected to one end of the second capacitor C2; the other end of the second capacitor C2 is electrically connected to the common electrode line Com;
  • the line is drawn between the first capacitor C1 and the second capacitor C2.
  • the thin film transistor array substrate of the liquid crystal display panel includes a first metal layer, a second metal layer, and an indium tin oxide (ITO) pixel electrode, and the first capacitor C1 and the second capacitor C2 can pass through the second metal.
  • the layer is formed with the first metal layer, and may also be formed by the ITO pixel electrode and the first metal layer.
  • the structure and position of the specific first metal layer, the second metal layer, and the pixel electrode are prior art, and are not detailed herein. .
  • the sizes of the first capacitor C1 and the second capacitor C2 are respectively determined by the areas of the first capacitor C1 and the second capacitor C2.
  • the main area main includes a first thin film transistor T1, a first liquid crystal capacitor Cl1, and a first storage capacitor Cst1; and the sub-region Sub includes a second thin film transistor T2, a second liquid crystal capacitor Clc2, and a second storage capacitor Cst2.
  • the gate of the first thin film transistor T1 is electrically connected to the Mth scan line G(M), and the source is electrically connected to the Nth data signal line D(N);
  • the first liquid crystal capacitor Clc1 is electrically connected to the drain of the first thin film transistor T1 in parallel with the first storage capacitor Cst1, and the other end is electrically connected to a constant voltage;
  • the gate of the second thin film transistor T2 is electrically connected Connected to the Mth scan line G(M), the source is electrically connected to the N-1th trace D(N-1) corresponding to the N-1th column subpixel of the previous column;
  • the second liquid crystal capacitor One end of Clc2 is connected in parallel with the second storage capacitor Cst2, and one end is electrically connected to the drain of the second thin film transistor T2, and the other end is electrically connected to a constant voltage.
  • the source of the first thin film transistor T1 is electrically connected to the (N+1)th data signal line D(N+1); the source of the second thin film transistor T2 Electrically connected to the Nth trace D(N) corresponding to the Nth column of subpixels.
  • main area Main and the sub-area Sub respectively include multiple domains, for example, the main area Main and the sub-area Sub respectively include four domains, and the Nth data signal line D(N) to the Nth column sub-pixel
  • the four domains in the main area Main provide a main data signal voltage
  • the Nth line L(N) provides a sub-data signal voltage to four domains in the sub-region Sub of the next N+1 column sub-pixel.
  • the relationship between the main data signal voltage and the secondary data signal voltage is:
  • Vsub (C1/(C1+C2)) ⁇ (Vmain-Vcom)+Vcom (1)
  • Vsub represents the secondary data signal voltage
  • Vmain represents the primary data signal voltage
  • C1 represents the first capacitance
  • C2 represents the second capacitance
  • Vcom represents the common electrode voltage
  • the secondary data signal voltage is different from the primary data signal voltage, and the secondary data signal voltage is closer to the common electrode voltage than the primary data signal voltage, that is, the voltage difference between the secondary data signal voltage and the common voltage is smaller than the primary data signal voltage.
  • the voltage difference from the common electrode voltage is such that the main region Main applied to the Nth column sub-pixel is different from the voltage applied to the sub-region Sub of the N+1th column sub-pixel, enabling multi-domain display to improve the color shift of the VA mode liquid crystal display.
  • the problem is that the number of data signal lines and the number of COFs are not increased, and the manufacturing cost of the liquid crystal display panel is lowered.
  • the main data signal voltage and the secondary data signal voltage are The difference between the first capacitor C1 and the second capacitor C2 can be changed by changing the area of the first capacitor C1 and the second capacitor C2 to change the difference between the main data signal voltage and the secondary data signal voltage.
  • the high-definition liquid crystal display pixel circuit of the present invention electrically connects the Nth data signal line and provides the main data signal voltage to the main area of the Nth column sub-pixel, and the corresponding Nth trace is
  • the voltage dividing unit is led out, electrically connected and provides a secondary data signal voltage obtained by dividing the voltage of the main data signal by the voltage dividing unit to the sub-region of the N+1th column sub-pixel of the next column, and setting the Nth data signal line to provide
  • the main data signal voltage is opposite to the polarity of the main data signal voltage provided by the (N+1)th data signal line, thereby achieving the color shift of the VA mode liquid crystal display without increasing the number of lines of the data signal and the number of COF terminals.
  • one sub-pixel main area and the sub-area display opposite polarities in one frame thereby reducing flicker of the liquid crystal display panel and improving display quality.

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Abstract

一种高画质液晶显示器像素电路，多个子像素呈阵列式排布，每一子像素均分为主区(Main)与次区(Sub)，对应每一列子像素分别设置一条数据信号线、一分压单元(10)、与一条走线；第N条数据信号线(D(N))电性连接并提供主数据信号电压至第N列子像素的主区(Main)，相应的第N条走线(L(N))由分压单元(10)引出，电性连接并提供经分压单元(10)对主数据信号电压进行分压得到的次数据信号电压至下一列第N+1列子像素的次区(Sub)；第N条数据信号线(D(N))提供的主数据信号电压与下一条第N+1条数据信号线(D(N+1))提供的主数据信号电压的极性相反。该像素电路能够降低色偏，减少液晶显示面板的闪烁，提高显示画质。

Description

高画质液晶显示器像素电路 技术领域
本发明涉及液晶显示技术领域，尤其涉及一种高画质液晶显示器像素电路。
背景技术
液晶显示器(Liquid Crystal Display，LCD)具有机身薄、省电、无辐射等众多优点，得到了广泛的应用。如：液晶电视、移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕等，在平板显示领域中占主导地位。
现有市场上的液晶显示器大部分为背光型液晶显示器，其包括壳体、设于壳体内的液晶显示面板及设于壳体内的背光模组。液晶显示面板是液晶显示器的主要组件，但液晶显示面板本身不发光，需要借由背光模组提供的光源来正常显示影像。
通常液晶显示面板由一彩色滤光片基板(Color Filter，CF)、一薄膜晶体管阵列基板(Thin Film Transistor Array Substrate，TFT Array Substrate)以及一配置于两基板间的液晶层(Liquid Crystal Layer)所构成，并分别在两基板的相对内侧设置像素电极、公共电极，通过施加电压控制液晶分子改变方向，将背光模组的光线折射出来产生画面。
液晶显示器包括扭曲向列(Twisted Nematic，TN)模式、电子控制双折射(Electrically Controlled Birefringence，ECB)模式、垂直配向(Vertical Alignment，VA)等多种显示模式，其中，VA模式是一种具有高对比度、宽视野角、无须摩擦配向等优势的常见显示模式。但由于VA模式采用垂直转动的液晶，液晶分子双折射率的差异比较大，导致大视角下的色偏(color shift)问题比较严重。
降低色偏是VA模式液晶显示器的发展要求。目前解决VA模式液晶显示器色偏的主流方法是采用多畴(multi domain)，如8畴显示的像素设计，使同一个子像素内主区(main)的4个畴与次区(sub)的4个畴的液晶分子转动角度不一样，从而改善色偏。色偏改善技术主要有电容耦合(CC)技术、电荷分享(CS)技术、公共电极电压(Vcom)调制技术、2D1G/2G1D技术等。但多数色偏改善技术使得一个子像素主区与次区的液晶翻转极性都是相同的，没办法实现一个子像素主区与次区在一帧画面内显示相反的 极性，导致液晶显示面板的闪烁(flicker)较明显，降低了显示画质。2D1G色偏改善技术虽然能够解决面板闪烁的问题，但需要将数据信号线的数目增加一倍，数据信号线的覆晶薄膜端(Chip on Film，COF)的数目也需增倍，造成面板成本增高。
图1所示为一种现有的改善VA模式液晶显示器色偏问题的像素电路的总体架构图，图2为对应于图1的具体电路图。结合图1与图2，多个子像素呈阵列式排布，每一子像素均分为主区Main与次区Sub，对应每一行子像素分别设置一条扫描线，对应每一列子像素分别设置一条数据信号线、一分压单元100、与一条走线。设M、N为正整数，第M条扫描线G(M)同时电性连接并提供扫描信号至第M行子像素的主区Main与次区Sub；第N条数据信号线D(N)电性连接并提供主数据信号电压至第N列子像素的主区Main，且所述第N条数据信号线D(N)经由分压单元100电性连接至公共电极线Com，相应的第N条走线L(N)由所述分压单元100引出，电性连接并提供不同于主数据信号电压的次数据信号电压至第N列子像素的次区Sub。
具体地，所述分压单元100包括串联的第一电容C1与第二电容C2，第一电容C1的一端电性连接于数据信号线，另一端电性连接于第二电容C2的一端，第二电容C2的另一端电性连接于公共电极线Com。所述第N条走线L(N)由所述一电容C1与第二电容C2之间引出，在所述第一电容C1与第二电容C2的分压作用下，次数据信号电压比主数据信号电压更接近于公共电极电压，即次数据信号电压与公共电压的压差一定小于主数据信号电压与公共电极电压的压差，使得施加给一个像素内主区Main与次区Sub的电压不同，达到改善色偏的目的。
上述现有的像素电路虽然能够解决VA模式液晶显示器的色偏问题，但是，由于对应于第N列子像素的第N条数据信号线D(N)与相应的第N条走线L(N)所提供的主数据信号电压与次数据信号电压的极性相同，使得在同一帧画面中，施加给一个子像素内主区Main与次区Sub的电压极性相同，仍会造成液晶显示面板的闪烁较明显，显示画质降低。
发明内容
本发明的目的在于提供一种高画质液晶显示器像素电路，在不增加数据信号线条数与COF端数目的前提下，既能够降低VA模式液晶显示器的色偏，又能够实现一个子像素主区与次区在一帧画面内显示相反的极性，减少液晶显示面板的闪烁，提高显示画质。
为实现上述目的，本发明提供了一种高画质液晶显示器像素电路，多个子像素呈阵列式排布，每一子像素均分为主区与次区，对应每一行子像素分别设置一条扫描线，对应每一列子像素分别设置一条数据信号线、一分压单元、与一条走线；
设M、N为正整数，第M条扫描线同时电性连接并提供扫描信号至第M行子像素的主区与次区；第N条数据信号线电性连接并提供主数据信号电压至第N列子像素的主区，且所述第N条数据信号线经由分压单元电性连接至公共电极线，相应的第N条走线由所述分压单元引出，电性连接并提供经分压单元对主数据信号电压进行分压得到的次数据信号电压至下一列第N+1列子像素的次区；
第N条数据信号线提供的主数据信号电压与下一条第N+1条数据信号线提供的主数据信号电压的极性相反。
所述分压单元包括串联的第一电容与第二电容；所述第一电容的一端电性连接于数据信号线，另一端电性连接于第二电容的一端；所述第二电容的另一端电性连接于公共电极线；所述走线由所述第一电容与第二电容之间引出。
所述主区中包括第一薄膜晶体管、第一液晶电容、及第一存储电容；所述次区中包括第二薄膜晶体管、第二液晶电容、及第二存储电容；
对于第M行第N列子像素，所述第一薄膜晶体管的栅极电性连接于第M条扫描线，源极电性连接于第N条数据信号线；所述第一液晶电容与第一存储电容并联后一端电性连接于第一薄膜晶体管的漏极，另一端电性连接于一恒定电压；所述第二薄膜晶体管的栅极电性连接于第M条扫描线，源极电性连接于对应于上一列第N-1列子像素的第N-1条走线；所述第二液晶电容与第二存储电容并联后一端电性连接于第二薄膜晶体管的漏极，另一端电性连接于一恒定电压；
对于第M行第N+1列子像素，所述第一薄膜晶体管的源极电性连接于第N+1条数据信号线；所述第二薄膜晶体管的源极电性连接于对应于第N列子像素的第N条走线。
所述主区次区分别包括4个畴。
所述第N条数据信号线向第N列子像素的主区内的4个畴提供主数据信号电压，所述第N条走线向下一列第N+1列子像素的次区内的4个畴提供次数据信号电压；在所述第一电容与第二电容的分压作用下，所述主数据信号电压与次数据信号电压的关系为：
Vsub＝(C1/(C1+C2))×(Vmain-Vcom)+Vcom
其中，Vsub表示次数据信号电压，Vmain表示主数据信号电压，C1表示第一电容，C2表示第二电容，Vcom表示公共电极电压。
通过第二金属层与第一金属层形成所述第一电容、及第二电容。
通过ITO像素电极与第一金属层形成所述第一电容、及第二电容。
所述第一电容、第二电容的大小分别由所述第一电容、第二电容的面积确定。
通过改变第一电容与第二电容的面积来改变主数据信号电压与次数据信号电压的差值。
本发明还提供一种高画质液晶显示器像素电路，多个子像素呈阵列式排布，每一子像素均分为主区与次区，对应每一行子像素分别设置一条扫描线，对应每一列子像素分别设置一条数据信号线、一分压单元、与一条走线；
设M、N为正整数，第M条扫描线同时电性连接并提供扫描信号至第M行子像素的主区与次区；第N条数据信号线电性连接并提供主数据信号电压至第N列子像素的主区，且所述第N条数据信号线经由分压单元电性连接至公共电极线，相应的第N条走线由所述分压单元引出，电性连接并提供经分压单元对主数据信号电压进行分压得到的次数据信号电压至下一列第N+1列子像素的次区；
第N条数据信号线提供的主数据信号电压与下一条第N+1条数据信号线提供的主数据信号电压的极性相反；
其中，所述分压单元包括串联的第一电容与第二电容；所述第一电容的一端电性连接于数据信号线，另一端电性连接于第二电容的一端；所述第二电容的另一端电性连接于公共电极线；所述走线由所述第一电容与第二电容之间引出；
其中，所述主区中包括第一薄膜晶体管、第一液晶电容、及第一存储电容；所述次区中包括第二薄膜晶体管、第二液晶电容、及第二存储电容；
对于第M行第N列子像素，所述第一薄膜晶体管的栅极电性连接于第M条扫描线，源极电性连接于第N条数据信号线；所述第一液晶电容与第一存储电容并联后一端电性连接于第一薄膜晶体管的漏极，另一端电性连接于一恒定电压；所述第二薄膜晶体管的栅极电性连接于第M条扫描线，源极电性连接于对应于上一列第N-1列子像素的第N-1条走线；所述第二液晶电容与第二存储电容并联后一端电性连接于第二薄膜晶体管的漏极，另一端电性连接于一恒定电压；
对于第M行第N+1列子像素，所述第一薄膜晶体管的源极电性连接于 第N+1条数据信号线；所述第二薄膜晶体管的源极电性连接于对应于第N列子像素的第N条走线；
其中，通过第二金属层与第一金属层形成所述第一电容、及第二电容。
本发明的有益效果：本发明提供的一种高画质液晶显示器像素电路，将第N条数据信号线电性连接并提供主数据信号电压至第N列子像素的主区，将相应的第N条走线由分压单元引出，电性连接并提供经分压单元对主数据信号电压进行分压得到的次数据信号电压至下一列第N+1列子像素的次区，并设置第N条数据信号线提供的主数据信号电压与第N+1条数据信号线提供的主数据信号电压的极性相反，实现了在不增加数据信号线条数与COF端数目的前提下，既降低VA模式液晶显示器的色偏，又使得一个子像素主区与次区在一帧画面内显示相反的极性，从而减少液晶显示面板的闪烁，提高显示画质。
附图说明
下面结合附图，通过对本发明的具体实施方式详细描述，将使本发明的技术方案及其它有益效果显而易见。
附图中，
图1为一种现有的改善VA模式液晶显示器色偏问题的像素电路的总体架构图；
图2是对应于图1的具体电路图；
图3是本发明高画质液晶显示器像素电路的总体架构图；
图4是对应与图3的具体电路图。
具体实施方式
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。
请同时参阅图3与图4，本发明提供一种高画质液晶显示器像素电路：多个子像素呈阵列式排布，每一子像素均分为主区Main与次区Sub，对应每一行子像素分别设置一条扫描线，对应每一列子像素分别设置一条数据信号线、一分压单元10、与一条走线。
设M、N为正整数，第M条扫描线G(M)同时电性连接并提供扫描信号至第M行子像素的主区Main与次区Sub；第N条数据信号线D(N)电性连接并提供主数据信号电压至第N列子像素的主区Main，且所述第N条数据信号线D(N)经由分压单元10电性连接至公共电极线Com，相应 的第N条走线L(N)由所述分压单元10引出，电性连接并提供经分压单元10对主数据信号电压进行分压得到的次数据信号电压至下一列第N+1列子像素的次区Sub。即，第1条数据信号线D(1)电性连接并提供主数据信号电压至第1列子像素的主区Main，相应的第1条走线L(1)由所述分压单元10引出，电性连接并提供经分压单元10对主数据信号电压进行分压得到的次数据信号电压至第2列子像素的次区Sub；第2条数据信号线D(2)电性连接并提供主数据信号电压至第2列子像素的主区Main，相应的第2条走线L(2)由所述分压单元10引出，电性连接并提供经分压单元10对主数据信号电压进行分压得到的次数据信号电压至第3列子像素的次区Sub；依次类推。
特别值得一提的是，相邻的两条数据信号线提供的主数据信号电压的极性相反，设第N条数据信号线D(N)提供的主数据信号电压的极性为负，则第N-1条数据信号线D(N-1)与第N+1条数据信号线D(N+1)提供的主数据信号电压的极性为正。对于第N列子像素，每一个子像素的主区Main接收到的是第N条数据信号线D(N)提供的负极性的主数据信号电压，而次区Sub接收到的则是经分压单元10对第N-1条数据信号线D(N-1)提供的正极性的主数据信号电压进行分压得到的同样为正极性的次数据信号电压；对于第N+1列子像素，每一个子像素的主区Main接收到的是第N+1条数据信号线D(N+1)提供的正极性的主数据信号电压，而次区Sub接收到的则是经分压单元10对第N条数据信号线D(N)提供的负极性的主数据信号电压进行分压得到的同样为负极性的次数据信号电压。由此可见，本发明的像素电路实现了一个子像素主区Main与次区Sub在一帧画面内显示相反的极性，从而能够减少液晶显示面板的闪烁，提高显示画质。
具体地，所述分压单元10包括串联的第一电容C1与第二电容C2。所述第一电容C1的一端电性连接于数据信号线，另一端电性连接于第二电容C2的一端；所述第二电容C2的另一端电性连接于公共电极线Com；所述走线由所述第一电容C1与第二电容C2之间引出。由于液晶显示面板的薄膜晶体管阵列基板包括第一金属层、第二金属层、及氧化铟锡(Indium TinOxide，ITO)像素电极，所述第一电容C1、及第二电容C2可以通过第二金属层与第一金属层形成，也可以通过ITO像素电极与第一金属层形成，具体的第一金属层、第二金属层和像素电极的结构及位置为现有技术，此处不再详述。所述第一电容C1、第二电容C2的大小分别由所述第一电容C1、第二电容C2的面积确定。
所述主区Main中包括第一薄膜晶体管T1、第一液晶电容Clc1、及第一存储电容Cst1；所述次区Sub中包括第二薄膜晶体管T2、第二液晶电容Clc2、及第二存储电容Cst2。
对于第M行第N列子像素，所述第一薄膜晶体管T1的栅极电性连接于第M条扫描线G(M)，源极电性连接于第N条数据信号线D(N)；所述第一液晶电容Clc1与第一存储电容Cst1并联后一端电性连接于第一薄膜晶体管T1的漏极，另一端电性连接于一恒定电压；所述第二薄膜晶体管T2的栅极电性连接于第M条扫描线G(M)，源极电性连接于对应于上一列第N-1列子像素的第N-1条走线D(N-1)；所述第二液晶电容Clc2与第二存储电容Cst2并联后一端电性连接于第二薄膜晶体管T2的漏极，另一端电性连接于一恒定电压。
对于第M行第N+1列子像素，所述第一薄膜晶体管T1的源极电性连接于第N+1条数据信号线D(N+1)；所述第二薄膜晶体管T2的源极电性连接于对应于第N列子像素的第N条走线D(N)。
进一步地，所述主区Main与次区Sub分别包括多畴，例如所述主区Main与次区Sub分别包括4个畴，所述第N条数据信号线D(N)向第N列子像素的主区Main内的4个畴提供主数据信号电压，所述第N条走线L(N)向下一列第N+1列子像素的次区Sub内的4个畴提供次数据信号电压。在所述第一电容C1与第二电容C2的分压作用下，所述主数据信号电压与次数据信号电压的关系为：
Vsub＝(C1/(C1+C2))×(Vmain-Vcom)+Vcom    (1)
其中，Vsub表示次数据信号电压，Vmain表示主数据信号电压，C1表示第一电容，C2表示第二电容，Vcom表示公共电极电压。
由此可见，所述次数据信号电压不同于主数据信号电压，且次数据信号电压比主数据信号电压更接近于公共电极电压，即次数据信号电压与公共电压的压差小于主数据信号电压与公共电极电压的压差，使得施加给第N列子像素的主区Main与施加给第N+1列子像素的次区Sub的电压不同，能够进行多畴显示，改善VA模式液晶显示器的色偏问题，且不增加数据信号线的条数与COF数目，降低液晶显示面板的制造成本。
由于所述第一电容C1、第二电容C2的大小分别由所述第一电容C1、第二电容C2的面积确定，根据(1)式可知：所述主数据信号电压与次数据信号电压之间的差值受到第一电容C1与第二电容C2的大小的影响，可以通过改变第一电容C1与第二电容C2的面积来改变主数据信号电压与次数据信号电压的差值。
综上所述，本发明的高画质液晶显示器像素电路，将第N条数据信号线电性连接并提供主数据信号电压至第N列子像素的主区，将相应的第N条走线由分压单元引出，电性连接并提供经分压单元对主数据信号电压进行分压得到的次数据信号电压至下一列第N+1列子像素的次区，并设置第N条数据信号线提供的主数据信号电压与第N+1条数据信号线提供的主数据信号电压的极性相反，实现了在不增加数据信号线条数与COF端数目的前提下，既降低VA模式液晶显示器的色偏，又使得一个子像素主区与次区在一帧画面内显示相反的极性，从而减少液晶显示面板的闪烁，提高显示画质。
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。

Claims (14)

  1. 一种高画质液晶显示器像素电路，多个子像素呈阵列式排布，每一子像素均分为主区与次区，对应每一行子像素分别设置一条扫描线，对应每一列子像素分别设置一条数据信号线、一分压单元、与一条走线；
    设M、N为正整数，第M条扫描线同时电性连接并提供扫描信号至第M行子像素的主区与次区；第N条数据信号线电性连接并提供主数据信号电压至第N列子像素的主区，且所述第N条数据信号线经由分压单元电性连接至公共电极线，相应的第N条走线由所述分压单元引出，电性连接并提供经分压单元对主数据信号电压进行分压得到的次数据信号电压至下一列第N+1列子像素的次区；
    第N条数据信号线提供的主数据信号电压与下一条第N+1条数据信号线提供的主数据信号电压的极性相反。
  2. 如权利要求1所述的高画质液晶显示器像素电路，其中，所述分压单元包括串联的第一电容与第二电容；所述第一电容的一端电性连接于数据信号线，另一端电性连接于第二电容的一端；所述第二电容的另一端电性连接于公共电极线；所述走线由所述第一电容与第二电容之间引出。
  3. 如权利要求1所述的高画质液晶显示器像素电路，其中，所述主区中包括第一薄膜晶体管、第一液晶电容、及第一存储电容；所述次区中包括第二薄膜晶体管、第二液晶电容、及第二存储电容；
    对于第M行第N列子像素，所述第一薄膜晶体管的栅极电性连接于第M条扫描线，源极电性连接于第N条数据信号线；所述第一液晶电容与第一存储电容并联后一端电性连接于第一薄膜晶体管的漏极，另一端电性连接于一恒定电压；所述第二薄膜晶体管的栅极电性连接于第M条扫描线，源极电性连接于对应于上一列第N-1列子像素的第N-1条走线；所述第二液晶电容与第二存储电容并联后一端电性连接于第二薄膜晶体管的漏极，另一端电性连接于一恒定电压；
    对于第M行第N+1列子像素，所述第一薄膜晶体管的源极电性连接于第N+1条数据信号线；所述第二薄膜晶体管的源极电性连接于对应于第N列子像素的第N条走线。
  4. 如权利要求2所述的高画质液晶显示器像素电路，其中，所述主区与次区分别包括4个畴。
  5. 如权利要求4所述的高画质液晶显示器像素电路，其中，所述第N 条数据信号线向第N列子像素的主区内的4个畴提供主数据信号电压，所述第N条走线向下一列第N+1列子像素的次区内的4个畴提供次数据信号电压；在所述第一电容与第二电容的分压作用下，所述主数据信号电压与次数据信号电压的关系为：
    Vsub＝(C1/(C1+C2))×(Vmain-Vcom)+Vcom
    其中，Vsub表示次数据信号电压，Vmain表示主数据信号电压，C1表示第一电容，C2表示第二电容，Vcom表示公共电极电压。
  6. 如权利要求1所述的高画质液晶显示器像素电路，其中，通过第二金属层与第一金属层形成所述第一电容、及第二电容。
  7. 如权利要求1所述的高画质液晶显示器像素电路，其中，通过ITO像素电极与第一金属层形成所述第一电容、及第二电容。
  8. 如权利要求5所述的高画质液晶显示器像素电路，其中，所述第一电容、第二电容的大小分别由所述第一电容、第二电容的面积确定。
  9. 如权利要求8所述的高画质液晶显示器像素电路，其中，通过改变第一电容与第二电容的面积来改变主数据信号电压与次数据信号电压的差值。
  10. 一种高画质液晶显示器像素电路，多个子像素呈阵列式排布，每一子像素均分为主区与次区，对应每一行子像素分别设置一条扫描线，对应每一列子像素分别设置一条数据信号线、一分压单元、与一条走线；
    设M、N为正整数，第M条扫描线同时电性连接并提供扫描信号至第M行子像素的主区与次区；第N条数据信号线电性连接并提供主数据信号电压至第N列子像素的主区，且所述第N条数据信号线经由分压单元电性连接至公共电极线，相应的第N条走线由所述分压单元引出，电性连接并提供经分压单元对主数据信号电压进行分压得到的次数据信号电压至下一列第N+1列子像素的次区；
    第N条数据信号线提供的主数据信号电压与下一条第N+1条数据信号线提供的主数据信号电压的极性相反；
    其中，所述分压单元包括串联的第一电容与第二电容；所述第一电容的一端电性连接于数据信号线，另一端电性连接于第二电容的一端；所述第二电容的另一端电性连接于公共电极线；所述走线由所述第一电容与第二电容之间引出；
    其中，所述主区中包括第一薄膜晶体管、第一液晶电容、及第一存储电容；所述次区中包括第二薄膜晶体管、第二液晶电容、及第二存储电容；
    对于第M行第N列子像素，所述第一薄膜晶体管的栅极电性连接于第 M条扫描线，源极电性连接于第N条数据信号线；所述第一液晶电容与第一存储电容并联后一端电性连接于第一薄膜晶体管的漏极，另一端电性连接于一恒定电压；所述第二薄膜晶体管的栅极电性连接于第M条扫描线，源极电性连接于对应于上一列第N-1列子像素的第N-1条走线；所述第二液晶电容与第二存储电容并联后一端电性连接于第二薄膜晶体管的漏极，另一端电性连接于一恒定电压；
    对于第M行第N+1列子像素，所述第一薄膜晶体管的源极电性连接于第N+1条数据信号线；所述第二薄膜晶体管的源极电性连接于对应于第N列子像素的第N条走线；
    其中，通过第二金属层与第一金属层形成所述第一电容、及第二电容。
  11. 如权利要求10所述的高画质液晶显示器像素电路，其中，所述主区与次区分别包括4个畴。
  12. 如权利要求11所述的高画质液晶显示器像素电路，其中，所述第N条数据信号线向第N列子像素的主区内的4个畴提供主数据信号电压，所述第N条走线向下一列第N+1列子像素的次区内的4个畴提供次数据信号电压；在所述第一电容与第二电容的分压作用下，所述主数据信号电压与次数据信号电压的关系为：
    Vsub＝(C1/(C1+C2))×(Vmain-Vcom)+Vcom
    其中，Vsub表示次数据信号电压，Vmain表示主数据信号电压，C1表示第一电容，C2表示第二电容，Vcom表示公共电极电压。
  13. 如权利要求12所述的高画质液晶显示器像素电路，其中，所述第一电容、第二电容的大小分别由所述第一电容、第二电容的面积确定。
  14. 如权利要求13所述的高画质液晶显示器像素电路，其中，通过改变第一电容与第二电容的面积来改变主数据信号电压与次数据信号电压的差值。
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