WO2019192083A1 - 一种垂直取向型液晶显示器 - Google Patents

一种垂直取向型液晶显示器 Download PDF

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Publication number
WO2019192083A1
WO2019192083A1 PCT/CN2018/092354 CN2018092354W WO2019192083A1 WO 2019192083 A1 WO2019192083 A1 WO 2019192083A1 CN 2018092354 W CN2018092354 W CN 2018092354W WO 2019192083 A1 WO2019192083 A1 WO 2019192083A1
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Prior art keywords
thin film
film transistor
sub
pixel regions
liquid crystal
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PCT/CN2018/092354
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English (en)
French (fr)
Inventor
郝思坤
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深圳市华星光电半导体显示技术有限公司
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Priority to US16/112,502 priority Critical patent/US10755653B2/en
Publication of WO2019192083A1 publication Critical patent/WO2019192083A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/028—Improving the quality of display appearance by changing the viewing angle properties, e.g. widening the viewing angle, adapting the viewing angle to the view direction
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/068—Adjustment of display parameters for control of viewing angle adjustment
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels

Definitions

  • the present invention relates to the field of display technologies, and in particular, to a vertical alignment type liquid crystal display.
  • Liquid crystal display is currently the most widely used flat panel display, and has gradually become a high-resolution widely used in various electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or laptop screens. Rate display with color screen.
  • Currently used liquid crystal displays usually have an upper and lower substrate and an intermediate liquid crystal layer, and the substrate is composed of glass and electrodes. If the upper and lower substrates have electrodes, a vertical electric field mode display such as TN (Twist Nematic) mode, VA (Vertical Alignment) mode, and MVA (developed to solve the narrow viewing angle) can be formed. Multi-domain Vertical Alignment mode.
  • the electrodes are located only on one side of the substrate to form a display of a transverse electric field mode, such as an IPS (In-plane switching) mode, an FFS (Fringe Field Switching) mode, or the like.
  • a transverse electric field mode such as an IPS (In-plane switching) mode, an FFS (Fringe Field Switching) mode, or the like.
  • TFT-LCD Thin Film Transistor Liquid Crystal Display
  • the viewing angles of many products have been able to achieve horizontal viewing angles and vertical viewing angles of 85 ° / 85 °, or even larger viewing angles.
  • LCD wide viewing angle technology currently mainly includes Multi-domain Vertical Alignment technology and In Plane Switching (IPS) technology.
  • IPS In Plane Switching
  • the advantage of the vertical alignment mode is that the front contrast is high, usually up to 4000:1 and above; the IPS technology makes the liquid crystal molecules in the horizontal electric field by forming parallel and repeatedly distributed pixel electrodes and common electrodes on the TFT (thin film transistor) array substrate. Rotate under action to form a wide viewing angle, but the contrast is relatively low, usually below 2000:1.
  • FIG. 1 shows a driving circuit commonly used in liquid crystal displays.
  • the number of scanning lines is twice the horizontal resolution, and each row of sub-pixels needs two scanning lines to be driven; the number of data lines is vertical resolution. 1/2 times, each data line drives two columns of left and right sub-pixels.
  • Figure 2 shows the gamma curve of the vertical alignment type liquid crystal display at different viewing angles.
  • the lowermost one is the gamma curve corresponding to the 0° viewing angle
  • the uppermost one is the gamma curve corresponding to the 70° viewing angle.
  • the gamma curve corresponding to the 10° viewing angle, the 20° viewing angle, the 30° viewing angle, the 40° viewing angle, the 50° viewing angle, and the 60° viewing angle from bottom to top in the order of the gamma curve can be seen that the same gray level, 10°
  • the transmittance of the liquid crystal display corresponding to the viewing angle of the viewing angle of 70° is greater than the transmittance corresponding to the viewing angle of 0°, resulting in the color shift of the liquid crystal display corresponding to the viewing angle of the 10° viewing angle to the 70° viewing angle being greater than the color shift of the viewing angle of 0°.
  • the present invention provides a vertical alignment type liquid crystal display, which can improve disadvantages such as a change in visual character orientation and contrast of a liquid crystal display.
  • the present invention provides a vertical alignment type liquid crystal display, comprising: a plurality of data lines, a plurality of scan lines, and a plurality of common electrode lines;
  • the plurality of scan lines are disposed perpendicularly to the plurality of data lines and the plurality of common electrode lines to form a plurality of pixel regions arranged in an array; the plurality of scan lines and the plurality of data lines Arranged at intervals;
  • the plurality of pixel regions include a plurality of sub-pixel regions and a plurality of main pixel regions, and the plurality of sub-pixel regions and the plurality of main pixel regions are spaced apart from each other;
  • the sub-pixel region includes a first thin film transistor, a second thin film transistor, and a sub-pixel, and a gate of the first thin film transistor and a gate of the second thin film transistor are connected on a same scan line, and a drain of the first thin film transistor and a drain of the second thin film transistor are respectively connected to adjacent data lines and a common electrode line, a source of the first thin film transistor and a second thin film transistor The source is connected to the sub-pixel;
  • the main pixel region includes a third thin film transistor and one of the sub-pixels, a gate of the third thin film transistor is connected to the scan line, a drain of the third thin film transistor and the data line or The common electrode line is connected, and a source of the third thin film transistor is connected to the sub-pixel.
  • the first thin film transistor, the second thin film transistor, and the third thin film transistor in each row of pixel regions are commonly driven by scan lines on both sides of the row of pixel regions, and each scan line is used to drive a row of pixel regions.
  • a thin film transistor, a second thin film transistor, and a third thin film transistor are commonly driven by scan lines on both sides of the row of pixel regions, and each scan line is used to drive a row of pixel regions.
  • the plurality of pixel regions are divided into a plurality of rows of sub-pixel regions and a plurality of rows of main pixel regions, and the plurality of rows of sub-pixel regions and the plurality of rows of main pixel regions are spaced apart from each other.
  • the sub-pixels in the adjacent two sub-pixel regions in each row of sub-pixel regions are respectively connected to the scan lines on both sides of the row of sub-pixel regions through the first thin film transistor and the second thin film transistor;
  • the sub-pixels in the adjacent two main pixel regions in each row of the main pixel region are respectively connected to the scan lines on both sides of the main pixel region of the row through the third thin film transistor.
  • two adjacent third thin film transistors in each row of the main pixel region are respectively connected to adjacent data lines and common electrode lines.
  • each of the plurality of pixel regions includes a plurality of sub-pixel regions and a plurality of main pixel regions spaced apart from each other.
  • adjacent sub-pixel regions and sub-pixels in the main pixel region in each row of pixel regions are respectively connected to scan lines on both sides of the row of pixel regions.
  • the sub-pixel is a liquid crystal capacitor.
  • two adjacent data lines are used to access data signals having opposite waveforms.
  • the present invention also provides a vertical alignment type liquid crystal display, comprising: a plurality of data lines, a plurality of scan lines, and a plurality of common electrode lines;
  • the plurality of scan lines are disposed perpendicularly to the plurality of data lines and the plurality of common electrode lines to form a plurality of pixel regions arranged in an array; the plurality of scan lines and the plurality of data lines Arranged at intervals;
  • the plurality of pixel regions include a plurality of sub-pixel regions and a plurality of main pixel regions, and the plurality of sub-pixel regions and the plurality of main pixel regions are spaced apart from each other;
  • the sub-pixel region includes a first thin film transistor, a second thin film transistor, and a sub-pixel, wherein the sub-pixel is a liquid crystal capacitor, a gate of the first thin film transistor and a gate connection of the second thin film transistor On the same scan line, the drains of the first thin film transistor and the drains of the second thin film transistors are respectively connected to adjacent data lines and common electrode lines, the source of the first thin film transistor And a source of the second thin film transistor is connected to the sub-pixel;
  • the main pixel region includes a third thin film transistor and one of the sub-pixels, a gate of the third thin film transistor is connected to the scan line, a drain of the third thin film transistor and the data line or a common electrode line is connected, and a source of the third thin film transistor is connected to the sub-pixel;
  • the first thin film transistor, the second thin film transistor, and the third thin film transistor in each row of the pixel region are commonly driven by scan lines on both sides of the row of pixel regions, and each of the scan lines is used to drive the first thin film transistor of one row of pixel regions a second thin film transistor and a third thin film transistor.
  • the plurality of pixel regions are divided into a plurality of rows of sub-pixel regions and a plurality of rows of main pixel regions, and the plurality of rows of sub-pixel regions and the plurality of rows of main pixel regions are spaced apart from each other.
  • the sub-pixels in the adjacent two sub-pixel regions in each row of sub-pixel regions are respectively connected to the scan lines on both sides of the row of sub-pixel regions through the first thin film transistor and the second thin film transistor;
  • the sub-pixels in the adjacent two main pixel regions in each row of the main pixel region are respectively connected to the scan lines on both sides of the main pixel region of the row through the third thin film transistor.
  • two adjacent third thin film transistors in each row of the main pixel region are respectively connected to adjacent data lines and common electrode lines.
  • each of the plurality of pixel regions includes a plurality of sub-pixel regions and a plurality of main pixel regions spaced apart from each other.
  • adjacent sub-pixel regions and sub-pixels in the main pixel region in each row of pixel regions are respectively connected to scan lines on both sides of the row of pixel regions.
  • two adjacent data lines are used to access data signals having opposite waveforms.
  • the present invention also provides a vertical alignment type liquid crystal display, comprising: a plurality of data lines, a plurality of scanning lines, and a plurality of common electrode lines;
  • the plurality of scan lines are disposed perpendicularly to the plurality of data lines and the plurality of common electrode lines to form a plurality of pixel regions arranged in an array; the plurality of scan lines and the plurality of data lines Arranged at intervals;
  • the plurality of pixel regions include a plurality of sub-pixel regions and a plurality of main pixel regions, and the plurality of sub-pixel regions and the plurality of main pixel regions are spaced apart from each other;
  • the sub-pixel region includes a first thin film transistor, a second thin film transistor, and a sub-pixel, and a gate of the first thin film transistor and a gate of the second thin film transistor are connected on a same scan line, and a drain of the first thin film transistor and a drain of the second thin film transistor are respectively connected to adjacent data lines and a common electrode line, a source of the first thin film transistor and a second thin film transistor The source is connected to the sub-pixel;
  • the main pixel region includes a third thin film transistor and one of the sub-pixels, a gate of the third thin film transistor is connected to the scan line, a drain of the third thin film transistor and the data line or a common electrode line is connected, and a source of the third thin film transistor is connected to the sub-pixel;
  • the first thin film transistor, the second thin film transistor, and the third thin film transistor in each row of the pixel region are commonly driven by scan lines on both sides of the row of pixel regions, and each of the scan lines is used to drive the first thin film transistor of one row of pixel regions a second thin film transistor and a third thin film transistor;
  • the plurality of pixel regions are divided into a plurality of rows of sub-pixel regions and a plurality of rows of main pixel regions, and the plurality of rows of sub-pixel regions and the plurality of rows of main pixel regions are spaced apart from each other.
  • the sub-pixels in the adjacent two sub-pixel regions in each row of sub-pixel regions are respectively connected to the scan lines on both sides of the row of sub-pixel regions through the first thin film transistor and the second thin film transistor;
  • the sub-pixels in the adjacent two main pixel regions in each row of the main pixel region are respectively connected to the scan lines on both sides of the main pixel region of the row through the third thin film transistor;
  • Two adjacent third thin film transistors in each row of the main pixel region are respectively connected to adjacent data lines and common electrode lines.
  • each of the plurality of pixel regions comprises a plurality of sub-pixel regions and a plurality of main pixel regions arranged at intervals;
  • the adjacent sub-pixel regions and the sub-pixels in the main pixel region in each row of pixel regions are respectively connected to scan lines on both sides of the row of pixel regions.
  • the sub-pixel is a liquid crystal capacitor
  • the present invention sets the voltage on the data line through the first thin film transistor and the second thin film transistor by disposing two thin film transistors, that is, the first thin film transistor and the second thin film transistor, in the sub-pixel region.
  • the driving voltage of the sub-pixel is greater than the driving voltage of the sub-pixel in the sub-pixel region, that is, the luminance of the sub-pixel illumination in the main pixel region is greater than the luminance of the sub-pixel illumination in the sub-pixel region, and the main pixel region and the sub-pixel region are Is spaced apart, the brightness of the main pixel area and the brightness of the sub-pixel area are mutually neutralized, which can reduce the apparent role of the vertical alignment type liquid crystal display, especially some large-view character bias, such
  • FIG. 1 is a schematic diagram of a driving circuit commonly used in a liquid crystal display according to the background art provided by the present invention.
  • FIG. 2 is a gamma graph of a vertical alignment type liquid crystal display provided by the present invention at different viewing angles.
  • FIG 3 is a schematic diagram of a driving circuit of a vertical alignment type liquid crystal display in the first embodiment provided by the present invention.
  • FIG. 4 is a schematic view showing the arrangement of pixels of a vertical alignment type liquid crystal display according to a first embodiment of the present invention.
  • FIG. 5 is a schematic diagram of a driving circuit of a vertical alignment type liquid crystal display according to a second embodiment of the present invention.
  • FIG. 6 is a schematic view showing the arrangement of pixels of a vertical alignment type liquid crystal display according to a second embodiment of the present invention.
  • Fig. 7 is a timing chart showing the driving of the vertical alignment type liquid crystal display provided by the present invention.
  • the invention provides a vertical alignment type liquid crystal display, which comprises: a plurality of data lines, a plurality of scanning lines, and a plurality of common electrode lines.
  • the plurality of scan lines are disposed perpendicularly to the plurality of data lines and the plurality of common electrode lines to form a plurality of pixel regions arranged in the array; the plurality of scan lines and the plurality of data lines are spaced apart from each other and uniformly arranged.
  • the plurality of pixel regions include a plurality of sub-pixel regions and a plurality of main pixel regions, and the plurality of sub-pixel regions and the plurality of main pixel regions are spaced apart from each other.
  • the sub-pixel region includes a first thin film transistor, a second thin film transistor, and a sub-pixel.
  • the gate of the first thin film transistor and the gate of the second thin film transistor are connected on the same scan line, and the drain of the first thin film transistor
  • the drains of the poles and the second thin film transistors are respectively connected to the adjacent data lines and the common electrode lines, and the sources of the first thin film transistors and the sources of the second thin film transistors are connected to the sub-pixels.
  • the main pixel region includes a third thin film transistor and a sub-pixel, the gate of the third thin film transistor is connected to the scan line, the drain of the third thin film transistor is connected to the data line or the common electrode line, and the source of the third thin film transistor Connected to a subpixel.
  • the gate of the first thin film transistor and the gate of the second thin film transistor are connected on the same scan line, and the first thin film transistor and the second thin film transistor can be controlled to be turned on or off at the same time.
  • first thin film transistor, the second thin film transistor, and the third thin film transistor in each row of pixel regions are commonly driven by scan lines on both sides of the row of pixel regions, and each scan line is used to drive a row of pixel regions.
  • the plurality of pixel regions are divided into a plurality of rows of sub-pixel regions and a plurality of rows of main pixel regions, and the plurality of rows of sub-pixel regions and the plurality of rows of main pixel regions are spaced apart from each other.
  • the pixel region of the nth row is the main pixel region, and then the pixel region of the n+1th row is the sub-pixel region, n>0.
  • sub-pixels in the adjacent two sub-pixel regions in each row of sub-pixel regions are respectively connected to the scan lines on both sides of the row of sub-pixel regions through the first thin film transistor and the second thin film transistor.
  • the sub-pixels in the adjacent two main pixel regions in each row of the main pixel region are respectively connected to the scan lines on both sides of the main pixel region of the row through the third thin film transistor.
  • two adjacent third thin film transistors in each row of the main pixel region are respectively connected to adjacent data lines and common electrode lines. That is, one of the two adjacent third thin film transistors is connected to the data line, and the other is connected to the common electrode line, and the common electrode line is connected to a common voltage, and the common voltage may be zero volts. It may not be zero volts.
  • each of the plurality of pixel regions includes a plurality of sub-pixel regions and a plurality of main pixel regions spaced apart from each other.
  • adjacent sub-pixel regions and sub-pixels in the main pixel region in each row of pixel regions are respectively connected to scan lines on both sides of the row of pixel regions.
  • the sub-pixels of the main pixel region are connected to one of the scan lines through the third thin film transistor, and the sub-pixels of the sub-pixel region are connected to the other scan line through the first thin film transistor and the second thin film transistor.
  • the sub-pixel is a liquid crystal capacitor including a pixel electrode and a common electrode disposed opposite to each other, and a liquid crystal sandwiched between the pixel electrode and the common electrode.
  • the source of the first thin film transistor and the source of the second thin film transistor are connected to the pixel electrode of the liquid crystal capacitor, and the source of the third thin film transistor is connected to the pixel electrode of the liquid crystal capacitor, and the common electrode of the liquid crystal capacitor is connected to the common electrode line.
  • two adjacent data lines are used to access data signals of opposite waveforms. For example, at any time, the nth data line is connected to the high potential signal, and the n+1th data line is connected to the low potential signal.
  • a plurality of data lines D1, D2, D3, a plurality of common electrode lines Com, and a plurality of scanning lines G0, G1, ..., G7 are intersected to form a plurality of pixel regions.
  • the plurality of data lines D1, D2, D3 and the plurality of common electrode lines Com are spaced apart from each other.
  • the pixel circuits corresponding to the pixel regions of the odd row and the even row are different, and only one third thin film transistor T3 and one liquid crystal capacitor C1 are in the pixel region of the odd row, so each pixel region of the odd row is the main pixel region;
  • the pixel area of the even rows has a first thin film transistor T1 and a second thin film transistor T2 and a liquid crystal capacitor C1. Therefore, each pixel region of the even rows is a sub-pixel region.
  • each liquid crystal capacitor C1 constitutes one sub-pixel
  • H represents a sub-pixel of a main pixel region
  • L represents a sub-pixel of a sub-pixel region
  • a first row of sub-pixels are sub-pixels of a main pixel region
  • a second The row sub-pixels are sub-pixels of the sub-pixel region, which are sequentially cross-distributed.
  • each row of pixel regions includes a main pixel region and a sub-pixel region which are spaced apart from each other.
  • each row of sub-pixels includes sub-pixels of sub-pixel regions and sub-pixel regions of the main pixel region that are spaced apart from each other.
  • the sub-pixel region includes two thin film transistors, that is, a first thin film transistor T1 and a second thin film transistor T2.
  • the two thin film transistors are connected in series, and The voltage on the data line is divided such that the voltage driving the liquid crystal capacitor C1 is less than the voltage on the data line.
  • There is only one thin film transistor in the main pixel area and the voltage on the data line can be completely applied to the liquid crystal capacitor C1, and the voltage of the driving liquid crystal capacitor is the same as the voltage on the data line. Therefore, the driving voltage of the liquid crystal capacitor C1 in the main pixel region is larger than the driving voltage of the liquid crystal capacitor C1 in the sub-pixel region.
  • the liquid crystal capacitor C1 is composed of a pixel electrode, a common electrode, and a liquid crystal sandwiched between the pixel electrode and the common electrode.
  • the driving voltage of the liquid crystal capacitor C1 is different, and the liquid crystal deflection in the main pixel region and the sub-pixel region is different.
  • the main pixel area and the sub-pixel area are spaced apart from each other, and the liquid crystal of the liquid crystal display is more uniformly dispersed as a whole, and the liquid crystal display has the same brightness angle as that of the liquid crystal display, and the area with low brightness on the liquid crystal display and the area with high surrounding brightness. Neutralization is performed, and therefore, the disadvantages of contrast reduction and color shift of the liquid crystal display in the case of a large viewing angle can be improved.
  • the waveforms of the data signals on the data lines D1, D3 are the same, the waveforms of the data signals on the data lines D2, D4 are the same, and the waveforms of the data lines D1 and D2 are opposite.
  • This can prevent the display failure of the liquid crystal display.
  • the display failure of the liquid crystal display can be avoided by avoiding signal crosstalk between adjacent data lines.
  • the present invention divides the voltage on the data line by the first thin film transistor and the second thin film transistor by disposing two thin film transistors, that is, the first thin film transistor and the second thin film transistor, in the sub-pixel region.
  • the driving sub-pixel emits light
  • the main pixel region has only one third thin film transistor, and the third thin film transistor is turned on to apply all the voltages on the data line to the sub-pixel; therefore, the sub-pixel in the main pixel region
  • the driving voltage is greater than the driving voltage of the sub-pixels in the sub-pixel region, that is, the luminance of the sub-pixels in the main pixel region is greater than the luminance of the sub-pixels in the sub-pixel region, and the main pixel region and the sub-pixel region are spaced apart.
  • the brightness of the main pixel area and the brightness of the sub-pixel area are mutually neutralized, which can reduce the apparent role deviation of the vertical alignment type liquid crystal display, especially some large-view character deviations, such as a 70° viewing angle, and the like, and improve the contrast reduction of the liquid crystal display. Disadvantages.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)

Abstract

本发明提供一种垂直取向型液晶显示器，其包括：多条数据线、多条扫描线、多条公共电极线；多条扫描线与多条数据线、以及多条公共电极线垂直交叉形成多个像素区域；多个次像素区域和多个主像素区域相互间隔分布；次像素区域包含第一薄膜晶体管、第二薄膜晶体管以及子像素，第一薄膜晶体管的栅极以及第二薄膜晶体管的栅极连接在同一条扫描线上，且第一薄膜晶体管的漏极以及第二薄膜晶体管的漏极分别连接在相邻的数据线和公共电极线上，第一薄膜晶体管的源极以及第二薄膜晶体管的源极均与子像素连接；主像素区域包含第三薄膜晶体管和子像素。本发明可以改善液晶显示器的视角色偏和对比度下降等缺点。

Description

一种垂直取向型液晶显示器
本申请要求于2018年4月2日提交中国专利局、申请号为201810284062.8、发明名称为“一种垂直取向型液晶显示器”的中国专利申请的优先权，上述专利的全部内容通过引用结合在本申请中。
技术领域
本发明涉及显示技术领域，尤其涉及一种垂直取向型液晶显示器。
背景技术
液晶显示器是目前使用最广泛的一种平板显示器，已经逐渐成为各种电子设备如移动电话、个人数字助理(PDA，Personal Digital Assistant)、数字相机、计算机屏幕或笔记本电脑屏幕所广泛应用具有高分辨率彩色屏幕的显示器。目前普遍采用的液晶显示器，通常有上下衬底和中间液晶层组成，衬底有玻璃和电极等组成。如果上下衬底都有电极，可以形成纵向电场模式的显示器，如TN(Twist Nematic，扭转向列型)模式，VA(Vertical Alignment，垂直取向型)模式，以及为了解决视角过窄开发的MVA(Multi-domain Vertical Alignment，多畴垂直取向)模式。另外一类与上述显示器不同，电极只位于衬底的一侧，形成横向电场模式的显示器，如IPS(In-plane switching，面内转换)模式、FFS(Fringe Field Switching，广视角技术)模式等。与阴极射线管显示器相比，薄膜晶体管显示器(Thin Film Transistor Liquid Crystal Display，TFT-LCD)的视角相对较窄，这就为其在对视角要求严格的高端显示领域的应用带来了很大局限，如航空航天、医疗等领域。随着LCD领域广视角技术的迅速发展，目前很多产品的视角已经可以达到水平视角和垂直视角分别为85°/85°，甚至更大的视角。
LCD广视角技术目前主要包括多畴垂直取向(Multi-domain Vertical Alignment)技术和面内转换(In Plane Switching，IPS)技术。垂直取向模式的优点是正面对比度高，通常可以达到4000:1及以上；IPS技术通过在TFT(薄膜晶体管)阵列基板上形成平行且重复分布的像素电极和公用电极， 使液晶分子在水平电场的作用下转动，从而形成广视角，但是其对比相对较低，通常在2000:1以下。
图1所示为目前液晶显示器常用的驱动电路，该种驱动电路中，扫描线的数量为水平解析度的2倍，每一行子像素需要两条扫描线驱动；数据线的数量为垂直解析度的1/2倍，每一条数据线驱动左右两列子像素。
图2所示为垂直取向型液晶显示器不同视角下的伽马曲线，最下面的一条曲线为0°视角对应的伽马曲线，最上面的一条曲线为70°视角对应的伽马曲线，这两条伽马曲线之间由下至上依次对应10°视角、20°视角、30°视角、40°视角、50°视角、60°视角对应的伽马曲线，可以看出相同灰阶下，10°视角至70°视角对应的液晶显示器的穿透率大于0°视角对应的穿透率，导致10°视角至70°视角对应的液晶显示器的色偏大于0°视角的色偏。
发明内容
为解决上述技术问题，本发明提供一种垂直取向型液晶显示器，可以改善液晶显示器的视角色偏和对比度下降等缺点。
本发明提供的一种垂直取向型液晶显示器，包括：多条数据线、多条扫描线、多条公共电极线；
所述多条扫描线与所述多条数据线、以及所述多条公共电极线垂直交叉设置，形成阵列排布的多个像素区域；所述多条扫描线与所述多条数据线之间相互间隔排布；
所述多个像素区域包含多个次像素区域和多个主像素区域，所述多个次像素区域和所述多个主像素区域相互间隔分布；
所述次像素区域包含一个第一薄膜晶体管、一个第二薄膜晶体管以及一个子像素，所述第一薄膜晶体管的栅极以及所述第二薄膜晶体管的栅极连接在同一条扫描线上，且所述第一薄膜晶体管的漏极以及所述第二薄膜晶体管的漏极分别连接在相邻的数据线和公共电极线上，所述第一薄膜晶体管的源极以及所述第二薄膜晶体管的源极均与所述子像素连接；
所述主像素区域包含一个第三薄膜晶体管和一个所述子像素，所述第三薄膜晶体管的栅极与所述扫描线连接，所述第三薄膜晶体管的漏极与所述数 据线或者所述公共电极线连接，且所述第三薄膜晶体管的源极与所述子像素连接。
优选地，每一行像素区域中的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均通过该行像素区域两侧的扫描线共同驱动，且每一条扫描线用于驱动一行像素区域的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管。
优选地，所述多个像素区域分为多行次像素区域和多行主像素区域，且所述多行次像素区域和所述多行主像素区域相互间隔排布。
优选地，每一行次像素区域中相邻两个次像素区域中的子像素均通过所述第一薄膜晶体管和所述第二薄膜晶体管分别连接在该行次像素区域两侧的扫描线上；
每一行主像素区域中相邻两个主像素区域中的子像素均通过所述第三薄膜晶体管分别连接在该行主像素区域两侧的扫描线上。
优选地，每一行主像素区域中相邻的两个第三薄膜晶体管分别连接在相邻的数据线和公共电极线上。
优选地，所述多个像素区域中的每一行像素区域均包含相互间隔排布的多个次像素区域和多个主像素区域。
优选地，每一行像素区域中相邻的次像素区域和主像素区域中的子像素分别连接在该行像素区域两侧的扫描线上。
优选地，所述子像素为液晶电容。
优选地，在所述液晶显示器工作时，相邻的两条数据线用于接入波形相反的数据信号。
本发明还提供一种垂直取向型液晶显示器，包括：多条数据线、多条扫描线、多条公共电极线；
所述多条扫描线与所述多条数据线、以及所述多条公共电极线垂直交叉设置，形成阵列排布的多个像素区域；所述多条扫描线与所述多条数据线之间相互间隔排布；
所述多个像素区域包含多个次像素区域和多个主像素区域，所述多个次像素区域和所述多个主像素区域相互间隔分布；
所述次像素区域包含一个第一薄膜晶体管、一个第二薄膜晶体管以及一个子像素，所述子像素为液晶电容，所述第一薄膜晶体管的栅极以及所述第二薄膜晶体管的栅极连接在同一条扫描线上，且所述第一薄膜晶体管的漏极以及所述第二薄膜晶体管的漏极分别连接在相邻的数据线和公共电极线上，所述第一薄膜晶体管的源极以及所述第二薄膜晶体管的源极均与所述子像素连接；
所述主像素区域包含一个第三薄膜晶体管和一个所述子像素，所述第三薄膜晶体管的栅极与所述扫描线连接，所述第三薄膜晶体管的漏极与所述数据线或者所述公共电极线连接，且所述第三薄膜晶体管的源极与所述子像素连接；
每一行像素区域中的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均通过该行像素区域两侧的扫描线共同驱动，且每一条扫描线用于驱动一行像素区域的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管。
优选地，所述多个像素区域分为多行次像素区域和多行主像素区域，且所述多行次像素区域和所述多行主像素区域相互间隔排布。
优选地，每一行次像素区域中相邻两个次像素区域中的子像素均通过所述第一薄膜晶体管和所述第二薄膜晶体管分别连接在该行次像素区域两侧的扫描线上；
每一行主像素区域中相邻两个主像素区域中的子像素均通过所述第三薄膜晶体管分别连接在该行主像素区域两侧的扫描线上。
优选地，每一行主像素区域中相邻的两个第三薄膜晶体管分别连接在相邻的数据线和公共电极线上。
优选地，所述多个像素区域中的每一行像素区域均包含相互间隔排布的多个次像素区域和多个主像素区域。
优选地，每一行像素区域中相邻的次像素区域和主像素区域中的子像素分别连接在该行像素区域两侧的扫描线上。
优选地，在所述液晶显示器工作时，相邻的两条数据线用于接入波形相反的数据信号。
本发明还提供一种垂直取向型液晶显示器，包括：多条数据线、多条扫 描线、多条公共电极线；
所述多条扫描线与所述多条数据线、以及所述多条公共电极线垂直交叉设置，形成阵列排布的多个像素区域；所述多条扫描线与所述多条数据线之间相互间隔排布；
所述多个像素区域包含多个次像素区域和多个主像素区域，所述多个次像素区域和所述多个主像素区域相互间隔分布；
所述次像素区域包含一个第一薄膜晶体管、一个第二薄膜晶体管以及一个子像素，所述第一薄膜晶体管的栅极以及所述第二薄膜晶体管的栅极连接在同一条扫描线上，且所述第一薄膜晶体管的漏极以及所述第二薄膜晶体管的漏极分别连接在相邻的数据线和公共电极线上，所述第一薄膜晶体管的源极以及所述第二薄膜晶体管的源极均与所述子像素连接；
所述主像素区域包含一个第三薄膜晶体管和一个所述子像素，所述第三薄膜晶体管的栅极与所述扫描线连接，所述第三薄膜晶体管的漏极与所述数据线或者所述公共电极线连接，且所述第三薄膜晶体管的源极与所述子像素连接；
每一行像素区域中的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均通过该行像素区域两侧的扫描线共同驱动，且每一条扫描线用于驱动一行像素区域的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；
所述多个像素区域分为多行次像素区域和多行主像素区域，且所述多行次像素区域和所述多行主像素区域相互间隔排布。
优选地，每一行次像素区域中相邻两个次像素区域中的子像素均通过所述第一薄膜晶体管和所述第二薄膜晶体管分别连接在该行次像素区域两侧的扫描线上；
每一行主像素区域中相邻两个主像素区域中的子像素均通过所述第三薄膜晶体管分别连接在该行主像素区域两侧的扫描线上；
每一行主像素区域中相邻的两个第三薄膜晶体管分别连接在相邻的数据线和公共电极线上。
优选地，所述多个像素区域中的每一行像素区域均包含相互间隔排布的多个次像素区域和多个主像素区域；
每一行像素区域中相邻的次像素区域和主像素区域中的子像素分别连接在该行像素区域两侧的扫描线上。
优选地，所述子像素为液晶电容；
在所述液晶显示器工作时，相邻的两条数据线用于接入波形相反的数据信号。
实施本发明，具有如下有益效果：本发明通过在次像素区域中设置两个薄膜晶体管，即第一薄膜晶体管和第二薄膜晶体管，通过第一薄膜晶体管和第二薄膜晶体管将数据线上的电压进行分压后施加到子像素上，驱动子像素发光，而主像素区域只有一个第三薄膜晶体管，第三薄膜晶体管打开可以将数据线上的电压全部施加到子像素上；因此，主像素区域中的子像素的驱动电压大于次像素区域中的子像素的驱动电压，即主像素区域中子像素发光的亮度大于次像素区域中的子像素发光的亮度，而主像素区域和次像素区域又是间隔分布的，主像素区域的亮度和子像素区域的亮度会相互中和，可以降低垂直取向型液晶显示器的视角色偏，尤其是一些大视角色偏，例如70°视角等，以及改善液晶显示器的对比度下降的缺点。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本发明提供的背景技术中液晶显示器常用的驱动电路示意图。
图2是本发明提供的垂直取向型液晶显示器在不同视角下的伽马曲线图。
图3是本发明提供的第一实施例中垂直取向型液晶显示器的驱动电路示意图。
图4是本发明提供的第一实施例中垂直取向型液晶显示器的像素排列示意图。
图5是本发明提供的第二实施例中垂直取向型液晶显示器的驱动电路示意图。
图6是本发明提供的第二实施例中垂直取向型液晶显示器的像素排列示意图。
图7是本发明提供的垂直取向型液晶显示器的驱动时序图。
具体实施方式
本发明提供一种垂直取向型液晶显示器，该液晶显示器包括：多条数据线、多条扫描线、多条公共电极线。
多条扫描线与多条数据线、以及多条公共电极线垂直交叉设置，形成阵列排布的多个像素区域；多条扫描线与多条数据线之间相互间隔且均匀的排布。
多个像素区域包含多个次像素区域和多个主像素区域，多个次像素区域和多个主像素区域相互间隔分布。
次像素区域包含一个第一薄膜晶体管、一个第二薄膜晶体管以及一个子像素，第一薄膜晶体管的栅极以及第二薄膜晶体管的栅极连接在同一条扫描线上，且第一薄膜晶体管的漏极以及第二薄膜晶体管的漏极分别连接在相邻的数据线和公共电极线上，第一薄膜晶体管的源极以及第二薄膜晶体管的源极均与子像素连接。
主像素区域包含一个第三薄膜晶体管和一个子像素，第三薄膜晶体管的栅极与扫描线连接，第三薄膜晶体管的漏极与数据线或者公共电极线连接，且第三薄膜晶体管的源极与子像素连接。
其中，第一薄膜晶体管的栅极和第二薄膜晶体管的栅极连接在同一条扫描线上，可以控制第一薄膜晶体管和第二薄膜晶体管同时打开或关断。
进一步地，每一行像素区域中的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均通过该行像素区域两侧的扫描线共同驱动，且每一条扫描线用于驱动一行像素区域的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管。
进一步地，多个像素区域分为多行次像素区域和多行主像素区域，且多行次像素区域和多行主像素区域相互间隔排布。例如，第n行像素区域为主像素区域，那么第n+1行像素区域则为次像素区域，n>0。
进一步地，每一行次像素区域中相邻两个次像素区域中的子像素均通过 第一薄膜晶体管和第二薄膜晶体管分别连接在该行次像素区域两侧的扫描线上。
每一行主像素区域中相邻两个主像素区域中的子像素均通过第三薄膜晶体管分别连接在该行主像素区域两侧的扫描线上。
进一步地，每一行主像素区域中相邻的两个第三薄膜晶体管分别连接在相邻的数据线和公共电极线上。也即是，相邻的两个第三薄膜晶体管中，有一个连接在数据线上，而另一个则连接在公共电极线上，公共电极线上接入公共电压，公共电压可以是零伏也可以不是零伏。
进一步地，多个像素区域中的每一行像素区域均包含相互间隔排布的多个次像素区域和多个主像素区域。
进一步地，每一行像素区域中相邻的次像素区域和主像素区域中的子像素分别连接在该行像素区域两侧的扫描线上。具体地，主像素区域的子像素通过第三薄膜晶体管连接在其中一条扫描线上，次像素区域的子像素则通过第一薄膜晶体管和第二薄膜晶体管连接在其中的另一条扫描线上。
进一步地，子像素为液晶电容，液晶电容包括相对设置的像素电极和公共电极，以及夹持在像素电极和公共电极之间的液晶。第一薄膜晶体管的源极以及第二薄膜晶体管的源极与液晶电容的像素电极连接，且第三薄膜晶体管的源极与液晶电容的像素电极连接，液晶电容的公共电极与公共电极线连接。
进一步地，在液晶显示器工作时，相邻的两条数据线用于接入波形相反的数据信号。例如，在任一时刻，第n条数据线接入高电位信号，第n+1条数据线则接入低电位信号。
如图3所示，在第一实施例中，多条数据线D1、D2、D3，多条公共电极线Com，以及多条扫描线G0、G1……G7之间交叉形成多个像素区域，多条数据线D1、D2、D3与多条公共电极线Com之间相互间隔排布。其中，奇数行和偶数行的像素区域对应的像素电路不相同，奇数行的像素区域中只有一个第三薄膜晶体管T3以及一个液晶电容Cl，因此奇数行的每一个像素区域均为主像素区域；偶数行的像素区域中有一个第一薄膜晶体管T1和一个第二薄膜晶体管T2以及一个液晶电容Cl，因此，偶数行的每一个像素区 域均为次像素区域。
如图4所示，每一个液晶电容Cl构成一个子像素，H代表主像素区域的子像素，L代表次像素区域的子像素，第一行子像素均为主像素区域的子像素，第二行子像素均为次像素区域的子像素，依次交叉分布。
如图5所示，在第二实施例中，每一行像素区域中都包含相互间隔分布的主像素区域和次像素区域。
如图6所示，每一行子像素都包含相互间隔分布的主像素区域的子像素和次像素区域的子像素。
在上述的第一实施例和第二实施例中，次像素区域中包含有两个薄膜晶体管，即第一薄膜晶体管T1和一个第二薄膜晶体管T2，这两个薄膜晶体管之间串联连接，可以将数据线上的电压进行分压，使得驱动液晶电容Cl的电压小于数据线上的电压。而主像素区域上只有一个薄膜晶体管，可以将数据线上的电压完全施加到液晶电容Cl上，驱动液晶电容的电压和数据线上的电压相同。因此，主像素区域中的液晶电容Cl的驱动电压大于次像素区域中液晶电容Cl的驱动电压。
液晶电容Cl是由像素电极、公共电极以及夹持在像素电极与公共电极之间的液晶构成，液晶电容Cl的驱动电压不一样，导致主像素区域和次像素区域中的液晶偏转不一样，而主像素区域和次像素区域是相互间隔分布的，液晶显示器的液晶在整体上分散更加均匀，不会出现液晶显示器的所有液晶偏转角度一样，液晶显示器上亮度低的区域会与周围亮度高的区域进行中和，因此，可以改善液晶显示器在大视角情形下对比度下降和色偏的缺点。
如图7所示，数据线D1、D3上的数据信号的波形相同，数据线D2、D4上的数据信号的波形相同，数据线D1和D2的波形则相反。这样可以避免液晶显示器出现显示不良，例如，可以通过避免相邻的数据线之间出现信号串扰的情形而避免液晶显示器出现显示不良。
综上所述，本发明通过在次像素区域中设置两个薄膜晶体管，即第一薄膜晶体管和第二薄膜晶体管，通过第一薄膜晶体管和第二薄膜晶体管将数据线上的电压进行分压后施加到子像素上，驱动子像素发光，而主像素区域只有一个第三薄膜晶体管，第三薄膜晶体管打开可以将数据线上的电压全部施 加到子像素上；因此，主像素区域中的子像素的驱动电压大于次像素区域中的子像素的驱动电压，即主像素区域中子像素发光的亮度大于次像素区域中的子像素发光的亮度，而主像素区域和次像素区域又是间隔分布的，主像素区域的亮度和子像素区域的亮度会相互中和，可以降低垂直取向型液晶显示器的视角色偏，尤其是一些大视角色偏，例如70°视角等，以及改善液晶显示器的对比度下降的缺点。
以上内容是结合具体的优选实施方式对本发明所作的进一步详细说明，不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干简单推演或替换，都应当视为属于本发明的保护范围。

Claims (20)

  1. 一种垂直取向型液晶显示器，其中，包括：多条数据线、多条扫描线、多条公共电极线；
    所述多条扫描线与所述多条数据线、以及所述多条公共电极线垂直交叉设置，形成阵列排布的多个像素区域；所述多条扫描线与所述多条数据线之间相互间隔排布；
    所述多个像素区域包含多个次像素区域和多个主像素区域，所述多个次像素区域和所述多个主像素区域相互间隔分布；
    所述次像素区域包含一个第一薄膜晶体管、一个第二薄膜晶体管以及一个子像素，所述第一薄膜晶体管的栅极以及所述第二薄膜晶体管的栅极连接在同一条扫描线上，且所述第一薄膜晶体管的漏极以及所述第二薄膜晶体管的漏极分别连接在相邻的数据线和公共电极线上，所述第一薄膜晶体管的源极以及所述第二薄膜晶体管的源极均与所述子像素连接；
    所述主像素区域包含一个第三薄膜晶体管和一个所述子像素，所述第三薄膜晶体管的栅极与所述扫描线连接，所述第三薄膜晶体管的漏极与所述数据线或者所述公共电极线连接，且所述第三薄膜晶体管的源极与所述子像素连接。
  2. 根据权利要求1所述的垂直取向型液晶显示器，其中，每一行像素区域中的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均通过该行像素区域两侧的扫描线共同驱动，且每一条扫描线用于驱动一行像素区域的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管。
  3. 根据权利要求1所述的垂直取向型液晶显示器，其中，所述多个像素区域分为多行次像素区域和多行主像素区域，且所述多行次像素区域和所述多行主像素区域相互间隔排布。
  4. 根据权利要求3所述的垂直取向型液晶显示器，其中，每一行次像素区域中相邻两个次像素区域中的子像素均通过所述第一薄膜晶体管和所述第二薄膜晶体管分别连接在该行次像素区域两侧的扫描线上；
    每一行主像素区域中相邻两个主像素区域中的子像素均通过所述第三 薄膜晶体管分别连接在该行主像素区域两侧的扫描线上。
  5. 根据权利要求4所述的垂直取向型液晶显示器，其中，每一行主像素区域中相邻的两个第三薄膜晶体管分别连接在相邻的数据线和公共电极线上。
  6. 根据权利要求1所述的垂直取向型液晶显示器，其中，所述多个像素区域中的每一行像素区域均包含相互间隔排布的多个次像素区域和多个主像素区域。
  7. 根据权利要求6所述的垂直取向型液晶显示器，其中，每一行像素区域中相邻的次像素区域和主像素区域中的子像素分别连接在该行像素区域两侧的扫描线上。
  8. 根据权利要求1所述的垂直取向型液晶显示器，其中，所述子像素为液晶电容。
  9. 根据权利要求1所述的垂直取向型液晶显示器，其中，在所述液晶显示器工作时，相邻的两条数据线用于接入波形相反的数据信号。
  10. 一种垂直取向型液晶显示器，其中，包括：多条数据线、多条扫描线、多条公共电极线；
    所述多条扫描线与所述多条数据线、以及所述多条公共电极线垂直交叉设置，形成阵列排布的多个像素区域；所述多条扫描线与所述多条数据线之间相互间隔排布；
    所述多个像素区域包含多个次像素区域和多个主像素区域，所述多个次像素区域和所述多个主像素区域相互间隔分布；
    所述次像素区域包含一个第一薄膜晶体管、一个第二薄膜晶体管以及一个子像素，所述子像素为液晶电容，所述第一薄膜晶体管的栅极以及所述第二薄膜晶体管的栅极连接在同一条扫描线上，且所述第一薄膜晶体管的漏极以及所述第二薄膜晶体管的漏极分别连接在相邻的数据线和公共电极线上，所述第一薄膜晶体管的源极以及所述第二薄膜晶体管的源极均与所述子像素连接；
    所述主像素区域包含一个第三薄膜晶体管和一个所述子像素，所述第三薄膜晶体管的栅极与所述扫描线连接，所述第三薄膜晶体管的漏极与所述数 据线或者所述公共电极线连接，且所述第三薄膜晶体管的源极与所述子像素连接；
    每一行像素区域中的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均通过该行像素区域两侧的扫描线共同驱动，且每一条扫描线用于驱动一行像素区域的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管。
  11. 根据权利要求10所述的垂直取向型液晶显示器，其中，所述多个像素区域分为多行次像素区域和多行主像素区域，且所述多行次像素区域和所述多行主像素区域相互间隔排布。
  12. 根据权利要求11所述的垂直取向型液晶显示器，其中，每一行次像素区域中相邻两个次像素区域中的子像素均通过所述第一薄膜晶体管和所述第二薄膜晶体管分别连接在该行次像素区域两侧的扫描线上；
    每一行主像素区域中相邻两个主像素区域中的子像素均通过所述第三薄膜晶体管分别连接在该行主像素区域两侧的扫描线上。
  13. 根据权利要求12所述的垂直取向型液晶显示器，其中，每一行主像素区域中相邻的两个第三薄膜晶体管分别连接在相邻的数据线和公共电极线上。
  14. 根据权利要求10所述的垂直取向型液晶显示器，其中，所述多个像素区域中的每一行像素区域均包含相互间隔排布的多个次像素区域和多个主像素区域。
  15. 根据权利要求14所述的垂直取向型液晶显示器，其中，每一行像素区域中相邻的次像素区域和主像素区域中的子像素分别连接在该行像素区域两侧的扫描线上。
  16. 根据权利要求10所述的垂直取向型液晶显示器，其中，在所述液晶显示器工作时，相邻的两条数据线用于接入波形相反的数据信号。
  17. 一种垂直取向型液晶显示器，其中，包括：多条数据线、多条扫描线、多条公共电极线；
    所述多条扫描线与所述多条数据线、以及所述多条公共电极线垂直交叉设置，形成阵列排布的多个像素区域；所述多条扫描线与所述多条数据线之间相互间隔排布；
    所述多个像素区域包含多个次像素区域和多个主像素区域，所述多个次像素区域和所述多个主像素区域相互间隔分布；
    所述次像素区域包含一个第一薄膜晶体管、一个第二薄膜晶体管以及一个子像素，所述第一薄膜晶体管的栅极以及所述第二薄膜晶体管的栅极连接在同一条扫描线上，且所述第一薄膜晶体管的漏极以及所述第二薄膜晶体管的漏极分别连接在相邻的数据线和公共电极线上，所述第一薄膜晶体管的源极以及所述第二薄膜晶体管的源极均与所述子像素连接；
    所述主像素区域包含一个第三薄膜晶体管和一个所述子像素，所述第三薄膜晶体管的栅极与所述扫描线连接，所述第三薄膜晶体管的漏极与所述数据线或者所述公共电极线连接，且所述第三薄膜晶体管的源极与所述子像素连接；
    每一行像素区域中的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管均通过该行像素区域两侧的扫描线共同驱动，且每一条扫描线用于驱动一行像素区域的第一薄膜晶体管、第二薄膜晶体管以及第三薄膜晶体管；
    所述多个像素区域分为多行次像素区域和多行主像素区域，且所述多行次像素区域和所述多行主像素区域相互间隔排布。
  18. 根据权利要求17所述的垂直取向型液晶显示器，其中，每一行次像素区域中相邻两个次像素区域中的子像素均通过所述第一薄膜晶体管和所述第二薄膜晶体管分别连接在该行次像素区域两侧的扫描线上；
    每一行主像素区域中相邻两个主像素区域中的子像素均通过所述第三薄膜晶体管分别连接在该行主像素区域两侧的扫描线上；
    每一行主像素区域中相邻的两个第三薄膜晶体管分别连接在相邻的数据线和公共电极线上。
  19. 根据权利要求17所述的垂直取向型液晶显示器，其中，所述多个像素区域中的每一行像素区域均包含相互间隔排布的多个次像素区域和多个主像素区域；
    每一行像素区域中相邻的次像素区域和主像素区域中的子像素分别连接在该行像素区域两侧的扫描线上。
  20. 根据权利要求17所述的垂直取向型液晶显示器，其中，所述子像 素为液晶电容；
    在所述液晶显示器工作时，相邻的两条数据线用于接入波形相反的数据信号。
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