CN108899329A - 像素阵列及其制备方法、显示面板、显示装置 - Google Patents

像素阵列及其制备方法、显示面板、显示装置 Download PDF

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CN108899329A
CN108899329A CN201810716653.8A CN201810716653A CN108899329A CN 108899329 A CN108899329 A CN 108899329A CN 201810716653 A CN201810716653 A CN 201810716653A CN 108899329 A CN108899329 A CN 108899329A
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thin film
film transistor
gate
pixel array
forming
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苏同上
王东方
成军
刘军
王庆贺
李广耀
闫梁臣
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei Xinsheng Optoelectronics Technology Co Ltd
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Priority to US16/405,126 priority patent/US10971523B2/en
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Abstract

本发明提供一种像素阵列及其制备方法、显示面板、显示装置，属于显示技术领域。本发明的像素阵列包括交叉且绝缘设置的多条栅线和多条数据线，以及栅线和数据线交叉位置处限定出的像素单元；每个像素单元均包括薄膜晶体管，位于同一行的像素单元中的薄膜晶体管的有源层的宽长比，沿栅线的扫描方向依次增大；和/或，位于同一列的像素单元中的薄膜晶体管的有源层的宽长比，沿数据线的数据写入方向依次增大。

Description

像素阵列及其制备方法、显示面板、显示装置
技术领域
本发明属于显示技术领域，具体涉及一种像素阵列及其制备方法、显示面板、显示装置。
背景技术
现有的阵列基板的示意图如图1所示，其工作原理如下：在对栅线逐行进行扫描时，每一行的薄膜晶体管将会被打开，此时，数据线上写入的数据电压信号会存储至存储电容Cst里；在停止对栅线进行扫描时，存储电容Cst用于为与其电连接的液晶电容Clc两端提供电压，以使液晶电容Clc两端的电压在停止扫描后仍保持不变，以达到显示画面的目的。
但是，发明人发现：由于传输栅极电压信号的栅线和传输数据电压信号的数据线本身存在电压降，故在使用栅线、数据线分别对栅极电压信号、数据电压信号进行传输的过程中，栅极电压信号、数据电压信号会分别随着栅线、数据线长度的增加而不断减小，从而造成不同行、列的薄膜晶体管所连接的存储电容中存储的电荷不一样，进而使得由该阵列基板所制备的显示面板的均匀性较差，显示面板的显示质量低。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一，提供一种提高显示面板的显示效果的像素阵列及其制备方法、显示面板、显示装置。
解决本发明技术问题所采用的技术方案是一种像素阵列，包括交叉且绝缘设置的多条栅线和多条数据线，以及所述栅线和所述数据线交叉位置处限定出的像素单元；每个所述像素单元均包括薄膜晶体管，位于同一行的所述像素单元中的薄膜晶体管的有源层的宽长比，沿所述栅线的扫描方向依次增大；和/或，位于同一列的所述像素单元中的薄膜晶体管的有源层的宽长比，沿所述数据线的数据写入方向依次增大。
优选的是，每条所述栅线包括相对设置的第一端、第二端；
对于任意两相邻的所述栅线的扫描方向，其中，一者的所述扫描方向为由第一端指向所述第二端的方向，另一者的所述扫描方向为由第二端指向所述第一端的方向。
优选的是，每条所述栅线包括相对设置的第一端、第二端；
每条所述栅线的所述扫描方向包括由第一端指向所述第二端的方向；或者，
每条所述栅线的所述扫描方向包括由第二端指向所述第一端的方向。
优选的是，每个所述像素单元还包括：存储电容、液晶电容；
所述存储电容的第一极片与薄膜晶体管的漏极、液晶电容的第一极片电连接；
所述存储电容的第二极片、液晶电容的第二极片均与地线电连接。
优选的是，所述薄膜晶体管包括：顶栅顶接触型薄膜晶体管、顶栅底接触型薄膜晶体管、底栅顶接触型薄膜晶体管、底栅底接触型薄膜晶体管中的任意一种。
解决本发明技术问题所采用的技术方案是一种像素阵列的制备方法，包括在第一基底上形成交叉且绝缘设置的多条栅线和多条数据线，其中，所述栅线和所述数据线的交叉位置处限定的区域为像素单元，其特征在于，形成所述像素单元的步骤包括：
形成薄膜晶体管各层结构的步骤；其中，所形成的同一行的所述像素单元中的薄膜晶体管的有源层的宽长比，沿所述栅线的扫描方向依次增大；和/或，所形成的同一列的所述像素单元中的薄膜晶体管的有源层的宽长比，沿所述数据线的数据写入方向依次增大。
优选的是，当所述薄膜晶体管为顶栅顶接触型薄膜晶体管时，所述形成薄膜晶体管各层结构的步骤具体包括：
通过构图工艺，在所述第一基底上形成包括薄膜晶体管的有源层的图形；
通过构图工艺，在所述有源层背离所述第一基底的一侧依次形成包括栅极绝缘层和栅极的图形；其中，所述栅极与所述栅线电连接；
形成层间绝缘层，并在所述层间绝缘层中形成源极接触过孔和漏极接触过孔；
通过构图工艺，形成包括薄膜晶体管的源极、漏极的图形；其中，所述源极通过所述源极接触过孔与所述有源层的源极接触区电连接，所述源极还与所述数据线电连接；所述漏极通过所述漏极接触过孔与所述有源层的漏极接触区电连接。
优选的是，所述像素阵列的制备方法还包括：
形成存储电容、液晶电容的步骤；其中，所述存储电容的第一极片与薄膜晶体管的漏极、液晶电容的第一极片电连接；
所述存储电容的第二极片、液晶电容的第二极片均与地线电连接。
解决本发明技术问题所采用的技术方案是一种显示面板，其包括上述的像素阵列。
解决本发明技术问题所采用的技术方案是一种显示装置，其包括上述的显示面板。
附图说明
图1为现有的阵列基板的示意图；
图2为本发明的实施例1的薄膜晶体管的结构示意图；
图3为本发明的实施例2的像素阵列的制备方法的流程图；
其中附图标记为：1、第一基底；2、有源层；3、源极；4、漏极；5、栅极绝缘层；6、栅极；7、源极接触过孔；8、层间绝缘层；9、钝化层；10、漏极接触过孔。
具体实施方式
为使本领域技术人员更好地理解本发明的技术方案，下面结合附图和具体实施方式对本发明作进一步详细描述。
实施例1：
本实施例提供一种像素阵列，包括交叉且绝缘设置的多条栅线和多条数据线，以及栅线和数据线交叉位置处限定出的像素单元；其中，每个像素单元均包括薄膜晶体管，位于同一行的像素单元中的薄膜晶体管的有源层2的宽长比，沿栅线的扫描方向依次增大，和/或位于同一列的像素单元中的薄膜晶体管的有源层2的宽长比，沿数据线的数据写入方向依次增大。
其中，每个像素单元中的薄膜晶体管包括：顶栅顶接触型薄膜晶体管、顶栅底接触型薄膜晶体管、底栅顶接触型薄膜晶体管、底栅底接触型薄膜晶体管中的任意一种。
为便于理解本实施例的意图，如图2所示，以下以顶栅顶接触型薄膜晶体管为例进行说明。
具体的，根据IDS＝1/2×μ×C×W/L×(VGS-VTH)2公式(其中，IDS为流过薄膜晶体管的源极3与漏极4的电流；μ为有源层2的迁移率；C为薄膜晶体管的栅极6与有源层2形成的单位面积电容值；W/L为像素单元的薄膜晶体管的有源层2的宽长比；VGS为栅极与源极之间的电压差，VTH为薄膜晶体管的阈值电压)，可以看出，有源层2的宽长比W/L与流过薄膜晶体管的源极3与漏极4的电流IDS成正比，也即有源层2的宽长比W/L越大，流过薄膜晶体管的源极3与漏极4的电流IDS也会越大。这样一来，当位于同一行的像素单元中的薄膜晶体管的有源层2的宽长比，沿栅线的扫描方向依次增大，和/或位于同一列的像素单元中的薄膜晶体管有源层2的宽长比，沿数据线的数据写入方向依次增大时，流过位于同一行和/或位于同一列的像素单元中的薄膜晶体管的源极3与漏极4的电流IDS也会依次增大，增大的电流IDS即可用以弥补栅线和/或数据线在传输过程中损耗的电压降，从而保证不同行和/或不同列的薄膜晶体管所连接的存储电容中存储的电荷量相同，以使液晶电容Clc两端的电压也相同，以提高由本实施例所提供的像素阵列所制备的显示面板的均匀性，提高显示面板的显示效果。
其中，作为本实施例的第一种优选方式，当位于第x行的像素单元的薄膜晶体管的有源层2的宽长比，沿栅线的扫描方向依次增大时，也即当(W/L)(x，1)<(W/L)(x，2)<……<(W/L)(x，n)时，流过第x行的像素单元中的薄膜晶体管的源极3与漏极4的电流IDS(x，1)<IDS(x，2)<……<IDS(x，n)，由此可以看出，即便栅线上写入的栅极电压信号会随着栅线长度的增加而不断减小，然而，沿着栅线的扫描方向依次增大的电流IDS能够将栅线在传输栅极电压信号过程中所损耗的电压降弥补过来，以使第x行的薄膜晶体管所连接的存储电容中存储的电荷量相同，从而使得在停止对栅线进行扫描时，液晶电容CLC两端的电压仍保持不变，以提高由本实施例所提供的像素阵列所制备的显示面板的均匀性，提高显示面板的显示效果。
其中，作为本实施例的第二种优选方式，当位于第y列的像素单元中的薄膜晶体管的有源层2的宽长比，沿数据线的数据写入方向依次增大时，也即当(W/L)(1，y)<(W/L)(2，y)<……<(W/L)(m，y)时，流过第y列的像素单元中的薄膜晶体管的源极3与漏极4的电流IDS(1，y)<IDS(2，y)<……<IDS(m，y)，由此可以看出，即便数据线上写入的数据电压信号会随着数据线长度的增加而不断减小，然而，沿着数据线的数据写入方向依次增大的电流IDS能够将数据线在传输过程中所损耗的电压降弥补过来，以使第y列的薄膜晶体管所连接的存储电容中存储的电荷量相同，从而使得液晶电容Clc两端的电压也相同，以提高由本实施例所提供的像素阵列所制备的显示面板的均匀性，提高显示面板的显示效果。
其中，作为本实施例的第三种优选方式，当位于第x行的像素单元中的薄膜晶体管的有源层2的宽长比，沿栅线的扫描方向依次增大，以及位于第y列的像素单元中的薄膜晶体管的有源层2的宽长比，沿数据线的数据写入方向依次增大时，也即当(W/L)(x，1)<(W/L)(x，2)<……<(W/L)(x，n)，以及(W/L)(1，y)<(W/L)(2，y)<……<(W/L)(m，y)时，流过第x行的像素单元中的薄膜晶体管的源极3与漏极4的电流IDS(x，1)<IDS(x，2)<……<IDS(x，n)，以及流过第y列的像素单元中的薄膜晶体管的源极3与漏极4的电流IDS(1，y)<IDS(2，y)<……<IDS(m，y)，由此可以看出，即便栅线和数据线上的信号会随着金属导线长度的增加而不断减小，然而，沿着栅线的扫描方向依次增大，以及沿数据线的数据写入方向依次增大的电流IDS能够将栅线、数据线在传输过程中所损耗的电压降弥补过来，以使第x行、第y列的薄膜晶体管所连接的存储电容中存储的电荷量相同，从而使得液晶电容Clc两端的电压也相同，以提高由本实施例所提供的像素阵列所制备的显示面板的均匀性，提高显示面板的显示效果。
为便于理解本实施的意图，以下对本实施例中的栅线的扫描方向进行具体说明。
其中，作为本实施例的一种优选方式，每条栅线包括相对设置的第一端、第二端；每条栅线的扫描方向包括由第一端指向第二端的方向；或者，每条栅线的扫描方向包括第二端指向第一端的方向。
作为本实施例的另一种优选方式，每条栅线仍包括相对设置的第一端、第二端；对于任意两相邻的栅线的扫描方向，其中，一者的扫描方向为由第一端指向第二端的方向，另一者的扫描方向为由第二端指向第一端的方向。通过这种扫描方式，可以使得扫描更加均匀。
其中，本实施例优选的，每个像素单元还包括：存储电容、液晶电容；存储电容的第一极片与薄膜晶体管的漏极4、液晶电容的第一极片电连接；存储电容的第二极片、液晶电容的第二极片均与地线电连接。
综上，由于本实施例所提供的像素阵列中，位于同一行的像素单元中的薄膜晶体管的有源层2的宽长比，沿栅线的扫描方向依次增大，和/或位于同一列的像素单元中的薄膜晶体管的有源层2的宽长比，沿数据线的数据写入方向依次增大，故流过像素单元中的薄膜晶体管的源极3、漏极4之间的电流也会依次增大，从而保证不同行和/或不同列的薄膜晶体管所连接的存储电容中存储的电荷量相同，以使液晶电容Clc两端的电压也相同，以提高由本实施例所提供的像素阵列所制备的显示面板的均匀性，提高显示面板的显示效果。
实施例2：
如图3所示，本实施例提供一种像素阵列的制备方法，其中，该像素阵列可以为实施例1中所述的像素阵列。
为便于理解本实施例的意图，本实施例以顶栅顶接触型薄膜晶体管，且所形成的同一行的像素单元中的薄膜晶体管的有源层2的宽长比，沿栅线的扫描方向依次增大，以及所形成的同一列的像素单元中的薄膜晶体管的有源层2的宽长比，沿数据线的数据写入方向依次增大为例进行说明。具体的，该制备方法包括如下步骤：
S1、通过构图工艺，在第一基底1上形成包括薄膜晶体管的有源层2的图形。其中，所形成的同一行的像素单元中的薄膜晶体管的有源层2的宽长比，沿栅线的扫描方向依次增大，以及所形成的同一列的像素单元中的薄膜晶体管的有源层2的宽长比，沿数据线的数据写入方向依次增大。当然，在本实施例中，也可以仅限定所形成的同一行的像素单元中的薄膜晶体管的有源层2的宽长比，沿栅线的扫描方向依次增大即可，或者仅限定所形成的同一列的像素单元中的薄膜晶体管的有源层2的宽长比，沿数据线的数据写入方向依次增大，在此不再一一赘述。
S2、通过一次构图工艺，在步骤S1中形成的有源层2背离第一基底1的一侧依次形成包括栅极绝缘层5和栅极6的图形，以及栅线、存储电容的第二极片；其中，薄膜晶体管的栅极6与栅线电连接，存储电容的第二极片与地线电连接。
S3、在完成上述步骤S2的第一基底上形成层间绝缘层8，并通过刻蚀工艺，在层间绝缘层8中形成源极接触过孔7和漏极接触过孔10。
S4、通过构图工艺，在完成上述步骤S3的第一基底上形成包括薄膜晶体管的源极3和漏极4的图形，与此同时，还会在完成上述步骤S3的第一基底上形成数据线、存储电容的第一极片。其中，薄膜晶体管的源极3通过源极接触过孔7与有源层2的源极接触区电连接，且该薄膜晶体管的源极3还与数据线电连接，薄膜晶体管的漏极4通过和漏极接触过孔10与有源层2的漏极接触区，且该薄膜晶体管的漏极4还与存储电容的第一极片、液晶电容的第一极片电连接。
S5、通过构图工艺，在完成上述步骤S4的第一基底上形成钝化层9。
S6、通过构图工艺，在第二基底靠近第一基底1的一侧形成包括液晶电容的第二极片的图形；通常情况下，该液晶电容的第二极片也即公共电极。
需要说明的是，步骤S6可以在步骤S1之前执行，也可以与步骤S1同时执行，在此不做限定。
S7、将完成上述步骤S5的第一基底和完成上述步骤S6的第二基底对盒，形成液晶盒，并在液晶盒中填充液晶。
至此完成像素阵列的制备。
综上，采用本实施例所提供的制备方法制备像素阵列时，由于制备所形成的同一行的像素单元中的薄膜晶体管的有源层2的宽长比，沿栅线的扫描方向依次增大，以及所形成的同一列的像素单元中的薄膜晶体管的有源层2的宽长比，沿数据线的数据写入方向依次增大，故流过像素单元中的薄膜晶体管的源极3、漏极4之间的电流也会依次增大，从而使得不同行和不同列的薄膜晶体管所连接的存储电容中存储的电荷量相同，以使液晶电容Clc两端的电压也相同，以提高由本实施例所提供的像素阵列所制备的显示面板的均匀性，提高显示面板的显示效果。
实施例3：
本实施例提供一种显示面板和显示装置，其中，显示面板包括实施例1中的像素阵列。
由于本实施例中显示面板包括上述的像素阵列，故其显示效果较佳。
本实施例的显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
当然，本实施例的显示装置中还可以包括其他常规结构，如背光源、电源单元、显示驱动单元等。
可以理解的是，以上实施方式仅仅是为了说明本发明的原理而采用的示例性实施方式，然而本发明并不局限于此。对于本领域内的普通技术人员而言，在不脱离本发明的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本发明的保护范围。

Claims (10)

1.一种像素阵列，包括交叉且绝缘设置的多条栅线和多条数据线，以及所述栅线和所述数据线交叉位置处限定出的像素单元；每个所述像素单元均包括薄膜晶体管，其特征在于，位于同一行的所述像素单元中的薄膜晶体管的有源层的宽长比，沿所述栅线的扫描方向依次增大；和/或，位于同一列的所述像素单元中的薄膜晶体管的有源层的宽长比，沿所述数据线的数据写入方向依次增大。
2.根据权利要求1所述的像素阵列，其特征在于，每条所述栅线包括相对设置的第一端、第二端；
对于任意两相邻的所述栅线的扫描方向，其中，一者的所述扫描方向为由第一端指向所述第二端的方向，另一者的所述扫描方向为由第二端指向所述第一端的方向。
3.根据权利要求1所述的像素阵列，其特征在于，每条所述栅线包括相对设置的第一端、第二端；
每条所述栅线的所述扫描方向包括由第一端指向所述第二端的方向；或者，
每条所述栅线的所述扫描方向包括由第二端指向所述第一端的方向。
4.根据权利要求1所述的像素阵列，其特征在于，每个所述像素单元还包括：存储电容、液晶电容；
所述存储电容的第一极片与薄膜晶体管的漏极、液晶电容的第一极片电连接；
所述存储电容的第二极片、液晶电容的第二极片均与地线电连接。
5.根据权利要求1所述的像素阵列，其特征在于，所述薄膜晶体管包括：顶栅顶接触型薄膜晶体管、顶栅底接触型薄膜晶体管、底栅顶接触型薄膜晶体管、底栅底接触型薄膜晶体管中的任意一种。
6.一种如权利要求1-5中任一所述的像素阵列的制备方法，包括在第一基底上形成交叉且绝缘设置的多条栅线和多条数据线，其中，所述栅线和所述数据线的交叉位置处限定的区域为像素单元，其特征在于，形成所述像素单元的步骤包括：
形成薄膜晶体管各层结构的步骤；其中，所形成的同一行的所述像素单元中的薄膜晶体管的有源层的宽长比，沿所述栅线的扫描方向依次增大；和/或，所形成的同一列的所述像素单元中的薄膜晶体管的有源层的宽长比，沿所述数据线的数据写入方向依次增大。
7.根据权利要求6所述的像素阵列的制备方法，其特征在于，当所述薄膜晶体管为顶栅顶接触型薄膜晶体管时，所述形成薄膜晶体管各层结构的步骤具体包括：
通过构图工艺，在所述第一基底上形成包括薄膜晶体管的有源层的图形；
通过构图工艺，在所述有源层背离所述第一基底的一侧依次形成包括栅极绝缘层和栅极的图形；其中，所述栅极与所述栅线电连接；
形成层间绝缘层，并在所述层间绝缘层中形成源极接触过孔和漏极接触过孔；
通过构图工艺，形成包括薄膜晶体管的源极、漏极的图形；其中，所述源极通过所述源极接触过孔与所述有源层的源极接触区电连接，所述源极还与所述数据线电连接；所述漏极通过所述漏极接触过孔与所述有源层的漏极接触区电连接。
8.根据权利要求6所述的像素阵列的制备方法，其特征在于，所述像素阵列的制备方法还包括：
形成存储电容、液晶电容的步骤；其中，所述存储电容的第一极片与薄膜晶体管的漏极、液晶电容的第一极片电连接；
所述存储电容的第二极片、液晶电容的第二极片均与地线电连接。
9.一种显示面板，其特征在于，所述显示面板包括权利要求1-5中任一项所述的像素阵列。
10.一种显示装置，其特征在于，包括权利要求9所述的显示面板。
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