WO2014023010A1 - 一种阵列基板及液晶显示面板 - Google Patents

一种阵列基板及液晶显示面板 Download PDF

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Publication number
WO2014023010A1
WO2014023010A1 PCT/CN2012/079905 CN2012079905W WO2014023010A1 WO 2014023010 A1 WO2014023010 A1 WO 2014023010A1 CN 2012079905 W CN2012079905 W CN 2012079905W WO 2014023010 A1 WO2014023010 A1 WO 2014023010A1
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pixel
pixel unit
array substrate
thin film
liquid crystal
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PCT/CN2012/079905
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English (en)
French (fr)
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罗时勲
陈世烽
韩丙
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深圳市华星光电技术有限公司
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Priority to US13/640,935 priority Critical patent/US8976329B2/en
Priority to DE201211006704 priority patent/DE112012006704T5/de
Publication of WO2014023010A1 publication Critical patent/WO2014023010A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/40—Arrangements for improving the aperture ratio

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to an array substrate and a liquid crystal display panel.
  • HVA wide viewing angle technology is one of the wide viewing angle technologies of liquid crystal VA.
  • a monomer molecule (Monomer) sensitive to light between liquid crystal molecules, and then applying an electric signal to the liquid crystal molecules, the liquid crystal molecules have a pretilt angle, and then the liquid crystal The molecules are irradiated with ultraviolet light to cure their pretilt angle.
  • the liquid crystal molecules having a certain pretilt angle are solidified on the surface of the alignment film (PI, Polyimide) by the above-mentioned light alignment and power-on, and the conventional rubbing alignment structure can be omitted.
  • the pixel electrode 1 in order to realize a wide viewing angle of the liquid crystal display in the HVA type display panel, the pixel electrode 1 is generally designed as a multi-region m-shaped structure, as shown in the figure, as a four-region m-shaped mechanism. Specifically, referring to a specific schematic diagram of the pixel structure shown in FIG. 2, the pixel electrode 1 includes a stem electrode 11 and a branch electrode 12, wherein the stem electrode 11 is located at the boundary of the branch electrodes 12 of the respective regions. In the RGB sub-pixel arrangement of the HVA type display panel, the three sub-pixels of RGB are changed from the conventional horizontal arrangement to the vertical arrangement.
  • the scanning line 2 is located on the long side of the pixel electrode 1 and is disposed between the adjacent pixel electrodes 1.
  • the scanning line 2 is disposed on the long side of the pixel electrode 1 so that the scanning line 2 occupies more space, thereby reducing the aperture ratio of the liquid crystal display panel and reducing The brightness of the LCD panel.
  • the technical problem to be solved by the present invention is to provide an array substrate and a liquid crystal display panel, which can improve the transmittance and aperture ratio of the liquid crystal display panel.
  • a technical solution adopted by the present invention is to provide an array substrate, comprising: a plurality of pixel units arranged in a matrix array, each pixel unit including a pixel electrode and a color resist layer, and the pixel electrode includes at least one Corresponding to a main portion of the opaque dark area; a plurality of scan lines, the scan line being disposed within a vertical projection range of the trunk portion to input a scan signal to the pixel unit; wherein the color resist layer is located between the trunk portion and the scan line;
  • the substrate includes a display area, the plurality of pixel units are divided into a first pixel unit and a second pixel unit, the first pixel unit is located in the display area, and the second pixel unit is located outside the display area and adjacent to the edge of the display area; In the line, at least one scan line is disposed in a vertical projection range of a trunk portion of the corresponding opaque dark area of the second pixel unit.
  • the pixel unit has a long side and a short side, the long side is parallel to the row direction, the short side is parallel to the column direction, and the scanning line is parallel to the long side.
  • the array substrate includes a plurality of data lines and a plurality of thin film transistors, wherein the data lines are parallel to the short sides of the pixel units to input data signals to the pixel units; the thin film transistor includes a gate, a source and a drain, and a gate of the thin film transistor
  • the scan line is electrically connected, the source is electrically connected to the data line, and the drain is electrically connected to the pixel electrode.
  • an array substrate comprising: a plurality of pixel units arranged in a matrix array, each pixel unit including a pixel electrode, and the pixel electrode includes at least one corresponding impervious a main portion of the dark region; a plurality of scan lines disposed within a vertical projection range of the trunk portion to input a scan signal to the pixel unit.
  • the pixel unit has a long side and a short side, the long side is parallel to the row direction, the short side is parallel to the column direction, and the scanning line is parallel to the long side.
  • the array substrate includes a plurality of data lines and a plurality of thin film transistors, wherein the data lines are parallel to the short sides of the pixel units to input data signals to the pixel units; the thin film transistor includes a gate, a source and a drain, and a gate of the thin film transistor
  • the scan line is electrically connected, the source is electrically connected to the data line, and the drain is electrically connected to the pixel electrode.
  • each data line inputs a data signal to all pixel units in a column of pixel units through respective thin film transistors.
  • the at least one data line inputs a data signal to a part of the pixel units of the two columns of pixel units adjacent to the data line through respective thin film transistors.
  • the array substrate includes a display area, the plurality of pixel units are divided into a first pixel unit and a second pixel unit, the first pixel unit is located in the display area, and the second pixel unit is located outside the display area and adjacent to the edge of the display area; At least one of the plurality of scan lines is disposed within a vertical projection range of the trunk portion of the corresponding opaque dark region of the second pixel unit.
  • the pixel unit further includes a color resist layer disposed between the main portion of the pixel electrode corresponding to the opaque dark region and the scan line.
  • a liquid crystal display panel comprising: an array substrate, a color filter substrate, and a liquid crystal layer between the array substrate and the color filter substrate;
  • the array substrate includes a plurality of pixel units arranged in a matrix array, each pixel unit comprising a pixel electrode, the pixel electrode comprising at least one trunk portion corresponding to the opaque dark region; and a plurality of scan lines, the scan line being disposed within a vertical projection range of the trunk portion To input a scan signal to the pixel unit.
  • the pixel unit has a long side and a short side, the long side is parallel to the row direction, the short side is parallel to the column direction, and the scanning line is parallel to the long side.
  • the array substrate includes a plurality of data lines and a plurality of thin film transistors, wherein the data lines are parallel to the short sides of the pixel units to input data signals to the pixel units; the thin film transistor includes a gate, a source and a drain, and a gate of the thin film transistor
  • the scan line is electrically connected, the source is electrically connected to the data line, and the drain is electrically connected to the pixel electrode.
  • each data line inputs a data signal to all pixel units in a column of pixel units through respective thin film transistors.
  • the at least one data line inputs a data signal to a part of the pixel units of the two columns of pixel units adjacent to the data line through respective thin film transistors.
  • the array substrate includes a display area, the plurality of pixel units are divided into a first pixel unit and a second pixel unit, the first pixel unit is located in the display area, and the second pixel unit is located outside the display area and adjacent to the edge of the display area; At least one of the plurality of scan lines is disposed within a vertical projection range of the trunk portion of the corresponding opaque dark region of the second pixel unit.
  • the pixel unit further includes a color resist layer disposed between the main portion of the pixel electrode corresponding to the opaque dark region and the scan line.
  • the invention has the beneficial effects that, different from the prior art, in the array substrate of the present invention, the pixel electrode of each pixel unit includes at least one trunk portion corresponding to the opaque dark region, and the scan line is disposed on the trunk portion.
  • the vertical projection range rather than the area between the two pixel units, so that the pixel electrode can be enlarged to the space between the two pixel units, and the line layout area originally serving as the scan line is changed into the penetration area, The penetration area of the liquid crystal display panel is increased, whereby the transmittance and aperture ratio of the liquid crystal display panel can be improved.
  • FIG. 1 is a schematic plan view showing a pixel structure of an array substrate in the prior art
  • FIG. 2 is a schematic structural view of the pixel electrode of FIG. 1;
  • FIG. 3 is a plan view showing an embodiment of an array substrate of the present invention.
  • FIG. 4 is a schematic cross-sectional view of the pixel unit of FIG. 3 along the AB direction;
  • Figure 5 is a plan view showing another embodiment of the array substrate of the present invention.
  • Fig. 6 is a plan view showing an embodiment of a liquid crystal display panel of the present invention, in which a color filter substrate is not shown.
  • an embodiment of the array substrate of the present invention includes a plurality of pixel units 101 and a plurality of scan lines 102 arranged in a matrix array.
  • Each of the pixel units 101 includes a pixel electrode 1011, and the pixel electrode 1011 includes at least one stem portion 10111 corresponding to an opaque dark region (not shown).
  • the scan line 102 is disposed within the vertical projection range of the trunk portion 10111 to input a scan signal to the pixel unit 101.
  • ITO Indium Tin Oxide, indium tin oxide
  • ITO Indium Tin Oxide, indium tin oxide
  • the junction will form an opaque dark area.
  • the trunk portion 10111 of the pixel electrode 1011 corresponds to the opaque dark region.
  • the scan line 102 is located below the pixel electrode 101 and is disposed within the vertical projection range of the stem portion 10111 of the pixel electrode 101.
  • the pixel unit 101 has a long side and a short side.
  • the long sides are parallel to the row arrangement direction of the pixel unit 101, and the short sides are parallel to the column arrangement direction of the pixel unit 101.
  • the scanning line 102 is parallel to the long side.
  • the array substrate includes a plurality of data lines 103 and a plurality of thin film transistors 104.
  • the data line 103 is parallel to the short side of the pixel unit 101 to input a data signal to the pixel unit 101.
  • the thin film transistor 104 includes a gate 1041, a source 1042, and a drain 1043.
  • the gate 1041 is electrically connected to the scan line 102
  • the source 1042 is electrically connected to the data line 103
  • the drain 1043 is electrically connected to the pixel electrode 1011.
  • the scan line 102 inputs a scan signal to the gate 1041 of the thin film transistor 104 to turn on the thin film transistor 104, then the data line 103 inputs a data signal to the source 1042, and enters the pixel electrode 1011 through the drain 1043 to Realize the screen display.
  • one data line 103 corresponds to one column of pixel units 1031, and each pixel unit 101 corresponds to one thin film transistor 104.
  • Each of the data lines 103 inputs a data signal to all of the pixel units 101 in one column of pixel units 1031 through respective thin film transistors 104.
  • the trunk portion 10111 of the pixel electrode 1011 corresponds to the opaque dark region, and the space corresponding to the opaque dark region is fully utilized, and the scan line 102 is disposed within the vertical projection range of the trunk portion 10111 instead of being set.
  • the penetration region of the pixel unit 101 is increased, whereby the penetration of the liquid crystal display panel can be improved.
  • the rate and aperture ratio increase the brightness of the liquid crystal display panel.
  • the pixel unit 101 of the present embodiment may further include a color resist layer 106.
  • the color resist layer 106 is located between the stem portion 10111 of the corresponding opaque dark region (not shown) of the pixel electrode 1011 and the scan line 102.
  • the color resist layer 106 is added between the pixel electrode 1011 and the scan line 102, so that the distance between the pixel electrode 1011 and the scan line 102 is increased, and the capacitive load of the scan line 102 is effectively reduced, so that the color shift can be reduced to some extent. Improve the display.
  • the array substrate includes a display area 200 (a dotted frame portion in the drawing), and divides the plurality of pixel units into a first pixel unit 201 and a second pixel unit 202.
  • the first pixel unit 201 is located in the display area 200 of the array substrate to implement display of the screen;
  • the second pixel unit 202 is located outside the display area 200 and adjacent to the edge of the display area 200, that is, the first row of pixels. All of the pixel units in unit 2011 and tail row pixel unit 2012 are second pixel unit 202.
  • the second scan line 2032 is disposed within a vertical projection range of the stem portion 20211 of the pixel electrode 2021 of the second pixel unit 202, and the first scan line 2031 is disposed in the pixel of the first pixel unit 201.
  • the vertical projection range of the stem portion 20111 of the electrode 2011 is within.
  • the second pixel unit 202 is not used for display, and is defined as a "false" pixel unit as an auxiliary pixel unit having the same structure as that of the first pixel unit 201.
  • the arrangement of the second pixel unit 202 enables the second scan line 2032 to be disposed within the vertical projection range of the stem portion 20211 of the pixel electrode 2021, so that all the scan lines of the array substrate can be laid out in the same structure, and have structurally Consistency can improve the uniformity of brightness and chromaticity of the liquid crystal display panel.
  • one data line can be associated with a pixel unit of a different column to input a data signal.
  • the first to fourth data lines 2041-2044 are included.
  • the second data line 2042 inputs a data signal to the first pixel unit 2061 adjacent to the second data line 2042 and a portion of the first pixel unit 201 in the second column pixel unit 2062 through the corresponding thin film transistor 205.
  • the third data line 2043 inputs a data signal to the second column unit 2062 adjacent to the third data line 2043 and a portion of the first pixel unit 201 in the third column pixel unit 2063 through the corresponding thin film transistor 205, respectively.
  • the first data line 2041 and the fourth data line 2044 input data signals to the remaining first pixel units 201 of the first column of pixel units 2061 and the third column of pixel units 2063.
  • the second data line 2042 and the third data line 2043 are respectively input with data signals to the adjacent two columns of pixel units through the corresponding thin film transistors 205, thereby contributing to reducing the power consumption of the data lines.
  • an embodiment of the liquid crystal display panel of the present invention includes an array substrate 301, a color filter substrate (not shown), and a liquid crystal layer 302 between the array substrate 301 and the color filter substrate.
  • the display area of the liquid crystal display panel corresponding to each pixel unit includes at least one opaque dark area.
  • the liquid crystal layer 302 is divided into a plurality of liquid crystal inverted regions. In different liquid crystal inverted regions, the liquid crystal molecules 3021 are turned differently, so that opaque portions are formed at the boundary of different liquid crystal inverted regions.
  • the dark area 3022 is such that the liquid crystal display panel has an opaque dark area corresponding to the display area of each pixel unit.
  • the array substrate 301 is the array substrate in each of the above embodiments. Taking the array substrate shown in FIG. 3 as an example, the array substrate includes a plurality of pixel units 101 and a plurality of scanning lines 102 arranged in a matrix array.
  • Each of the pixel units 101 includes a pixel electrode 1011, and the pixel unit 101 has a long side and a short side, the long side is parallel to the row direction, and the short side is parallel to the column direction.
  • the pixel electrode 1011 at least one stem portion 10111 corresponding to the opaque dark region 3022 of the liquid crystal layer 302 is provided.
  • the scan line 102 is disposed within a vertical projection range of the stem portion 10111 of the pixel electrode 1011 and is parallel to the direction of the long side of the pixel unit 101 to input a scan signal to the pixel unit 101.
  • the array substrate further includes a plurality of data lines 103 and a plurality of thin film transistors 104.
  • the data line 103 is parallel to the short side of the pixel unit 101 to input a data signal to the pixel unit 101.
  • the thin film transistor 104 includes a gate 1041, a source 1042, and a drain 1043.
  • One pixel unit 101 is connected to one scanning line 102, one data line 103, and one thin film transistor 104.
  • the thin film transistor 104 corresponding to one pixel unit 101 has a gate 1041 electrically connected to a corresponding scan line 102, a source 1042 electrically connected to a corresponding data line 103, and a drain 1043 electrically connected to a corresponding pixel electrode 1011.
  • corresponding electrical signals are input to the scan line 102 and the data line 103, respectively, so that the pixel electrode 1011 displays the corresponding picture.
  • the liquid crystal display panel of the present embodiment is disposed in the vertical projection range of the stem portion 10111 of the pixel electrode 1011 instead of the region 105 between the two pixel units 101, so that the pixel electrode 1011 can be
  • the enlargement of the space between the two pixel units 101 increases the penetration area of the pixel unit 101, whereby the transmittance and aperture ratio of the liquid crystal display panel can be improved, and the brightness of the liquid crystal display panel is increased.

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Abstract

一种阵列基板，包括：呈行列阵列排列的多个像素单元（101），每个所述像素单元（101）包括像素电极（1011），所述像素电极（1011）包括至少一个对应不透光暗区的主干部分（10111）；多条扫描线（102），所述扫描线（102）设置在所述主干部分（10111）的垂直投影范围内，以对像素单元（101）输入扫描信号。还提供了了一种液晶显示面板。通过上述方式，能够提高液晶显示面板的穿透率和开口率。

Description

一种阵列基板及液晶显示面板
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种阵列基板及液晶显示面板。
【背景技术】
HVA广视角技术作为液晶VA广视角技术中的一种，通过在液晶分子间掺入对光线敏感的单体分子（Monomer），然后对液晶分子施加电信号使液晶分子具有预倾角，再对液晶分子进行紫外光照射以固化其预倾角。通过上述光配向加电的方式，实现在配向膜（PI，Polyimide）表面固化出带有一定预倾角的液晶分子，可以省略传统的摩擦取向结构。
参阅图1和图2，在HVA型显示面板中为了实现液晶显示的广视角，通常将像素电极1设计为多区域米字形结构，如图所示为四区域米字形机构。具体地，参阅图2所示的像素结构的具体示意图，像素电极1包括主干电极11和分支电极12，其中主干电极11位于各区域分支电极12的交界处。在HVA型显示面板的RGB子像素排列中，将RGB三个子像素由传统的横向排列改为纵向排列。因此，扫描线2位于像素电极1的长边侧，并且设置在相邻像素电极1之间。但是，由于扫描线2的线宽和阻值等因素的影响，将扫描线2设置在像素电极1的长边侧使得扫描线2占用更多的空间，从而减少液晶显示面板的开口率，降低液晶显示面板的亮度。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及液晶显示面板，能够提高液晶显示面板的穿透率和开口率。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，包括：呈行列阵列排列的多个像素单元，每个像素单元包括像素电极和色阻层，像素电极包括至少一个对应不透光暗区的主干部分；多条扫描线，扫描线设置在主干部分的垂直投影范围内，以对像素单元输入扫描信号；其中，色阻层位于主干部分和扫描线之间；阵列基板包括显示区域，多个像素单元分为第一像素单元和第二像素单元，第一像素单元位于显示区域中，第二像素单元位于显示区域之外并邻近显示区域的边缘；在多条扫描线中，至少有一条扫描线设置于第二像素单元的对应不透光暗区的主干部分的垂直投影范围内。
其中，像素单元具有长边和短边，长边与行方向平行，短边与列方向平行；扫描线与长边平行。
其中，阵列基板包括多条数据线和多个薄膜晶体管，数据线与像素单元的短边平行以对像素单元输入数据信号；薄膜晶体管包括栅极、源极以及漏极，薄膜晶体管的栅极与扫描线电连接，源极与数据线电连接，漏极与像素电极电连接。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，包括：呈行列阵列排列的多个像素单元，每个像素单元包括像素电极，像素电极包括至少一个对应不透光暗区的主干部分；多条扫描线，扫描线设置在主干部分的垂直投影范围内，以对像素单元输入扫描信号。
其中，像素单元具有长边和短边，长边与行方向平行，短边与列方向平行；扫描线与长边平行。
其中，阵列基板包括多条数据线和多个薄膜晶体管，数据线与像素单元的短边平行以对像素单元输入数据信号；薄膜晶体管包括栅极、源极以及漏极，薄膜晶体管的栅极与扫描线电连接，源极与数据线电连接，漏极与像素电极电连接。
其中，每条数据线通过相应的薄膜晶体管分别对一列像素单元中的所有像素单元输入数据信号。
其中，至少有一条数据线通过相应的薄膜晶体管分别对与该条数据线相邻的两列像素单元中的部分像素单元输入数据信号。
其中，阵列基板包括显示区域，多个像素单元分为第一像素单元和第二像素单元，第一像素单元位于显示区域中，第二像素单元位于显示区域之外并邻近显示区域的边缘；在多条扫描线中，至少有一条扫描线设置于第二像素单元的对应不透光暗区的主干部分的垂直投影范围内。
其中，像素单元还包括色阻层，色阻层位于像素电极的对应不透光暗区的主干部分和扫描线之间。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板，包括：阵列基板、彩色滤光基板以及位于阵列基板和彩色滤光基板之间的液晶层；阵列基板包括：呈行列阵列排列的多个像素单元，每个像素单元包括像素电极，像素电极包括至少一个对应不透光暗区的主干部分；多条扫描线，扫描线设置在主干部分的垂直投影范围内，以对像素单元输入扫描信号。
其中，像素单元具有长边和短边，长边与行方向平行，短边与列方向平行；扫描线与长边平行。
其中，阵列基板包括多条数据线和多个薄膜晶体管，数据线与像素单元的短边平行以对像素单元输入数据信号；薄膜晶体管包括栅极、源极以及漏极，薄膜晶体管的栅极与扫描线电连接，源极与数据线电连接，漏极与像素电极电连接。
其中，每条数据线通过相应的薄膜晶体管分别对一列像素单元中的所有像素单元输入数据信号。
其中，至少有一条数据线通过相应的薄膜晶体管分别对与该条数据线相邻的两列像素单元中的部分像素单元输入数据信号。
其中，阵列基板包括显示区域，多个像素单元分为第一像素单元和第二像素单元，第一像素单元位于显示区域中，第二像素单元位于显示区域之外并邻近显示区域的边缘；在多条扫描线中，至少有一条扫描线设置于第二像素单元的对应不透光暗区的主干部分的垂直投影范围内。
其中，像素单元还包括色阻层，色阻层位于像素电极的对应不透光暗区的主干部分和扫描线之间。
本发明的有益效果是：区别于现有技术的情况，本发明的阵列基板，每个像素单元的像素电极包括至少一个对应不透光暗区的主干部分，通过将扫描线设置在主干部分的垂直投影范围内，而不是设置在两个像素单元之间的区域，从而使得像素电极可以向两个像素单元之间的空间扩大，将原本作为扫描线的线路布局区域变为穿透区域，以增加液晶显示面板的穿透区域，由此能够提高液晶显示面板的穿透率和开口率。
【附图说明】
图1是现有技术中一种阵列基板的像素结构平面示意图；
图2是图1中的像素电极的结构示意图；
图3是本发明阵列基板的一实施方式的平面示意图；
图4是图3的像素单元沿AB方向的截面示意图；
图5是本发明阵列基板的另一实施方式的平面示意图；
图6是本发明液晶显示面板的一实施方式的平面示意图，图中未显示彩色滤光基板。
【具体实施方式】
下面将结合附图和实施方式对本发明进行详细描述。
参阅图3，本发明阵列基板的一实施方式包括：呈行列阵列排列的多个像素单元101和多条扫描线102。其中，每个像素单元101包括像素电极1011，像素电极1011包括至少一个对应不透光暗区（图未示）的主干部分10111。扫描线102设置在主干部分10111的垂直投影范围内，以对像素单元101输入扫描信号。
在HVA型液晶显示面板中，利用ITO（Indium Tin Oxide，氧化铟锡）裂缝分区形成多个液晶倒向区域。通过对不同的液晶倒向区域施加不同的电信号和进行紫外光照射，使得在不同的液晶倒向区域的液晶分子具有不同的倾倒角，而液晶分子的不同倒向使在不同液晶倒向区域的交界处会形成不透光暗区。而像素电极1011的主干部分10111则对应该不透光暗区。扫描线102位于像素电极101的下层，并且布局在像素电极101的主干部分10111的垂直投影范围内。
其中，像素单元101具有长边和短边。长边与像素单元101的行排列方向平行，短边与像素单元101的列排列方向平行。本实施方式中扫描线102与长边平行。
进一步地，阵列基板包括多条数据线103和多个薄膜晶体管104。数据线103与像素单元101的短边平行以对像素单元101输入数据信号。薄膜晶体管104包括栅极1041、源极1042以及漏极1043。其中栅极1041与扫描线102电连接，源极1042与数据线103电连接，漏极1043与像素电极1011电连接。在需要显示画面时，扫描线102输入扫描信号至薄膜晶体管104的栅极1041，以打开薄膜晶体管104，然后数据线103输入数据信号至源极1042，并经过漏极1043输入像素电极1011，以实现画面显示。
本实施方式中，一条数据线103对应着一列像素单元1031，每个像素单元101对应一个薄膜晶体管104。每条数据线103通过相应的薄膜晶体管104分别对一列像素单元1031中的所有像素单元101输入数据信号。
本实施方式的阵列基板，像素电极1011的主干部分10111对应不透光暗区，充分利用不透光暗区对应的空间，将扫描线102布局在主干部分10111的垂直投影范围内，而不是设置在两个像素单元101之间的区域105处，以使得像素电极1011可以向两个像素单元101之间的空间扩大，增加像素单元101的穿透区域，由此能够提高液晶显示面板的穿透率和开口率，增加了液晶显示面板的亮度。
此外，一并参阅图4，本实施方式的像素单元101还可以包括色阻层106。色阻层106位于像素电极1011的对应不透光暗区（图未示）的主干部分10111和扫描线102之间。在像素电极1011和扫描线102之间增加色阻层106，使得像素电极1011和扫描线102之间的距离变大，有效降低扫描线102的电容负载，从而能够在一定程度上降低色偏，提高显示效果。
参阅图5，在本发明阵列基板的另一实施方式中，阵列基板包括显示区域200（图中虚线框部分），并将多个像素单元分为第一像素单元201和第二像素单元202。如图5所示，第一像素单元201位于阵列基板的显示区域200中，用以实现画面的显示；第二像素单元202位于显示区域200之外并邻近显示区域200的边缘，即首行像素单元2011和尾行像素单元2012中的所有像素单元为第二像素单元202。在阵列基板的多条扫描线中，第二扫描线2032布局在第二像素单元202的像素电极2021的主干部分20211的垂直投影范围内，第一扫描线2031布局在第一像素单元201的像素电极2011的主干部分20111的垂直投影范围内。第二像素单元202不用于进行显示，定义为“假”像素单元，作为辅助像素单元，其结构与第一像素单元201的结构相同。第二像素单元202的设置使得第二扫描线2032能够设置在像素电极2021的主干部分20211的垂直投影范围内，从而使得阵列基板的所有扫描线均能布局在相同的结构中，在结构上具有一致性，能够提高液晶显示面板亮度和色度的均匀性。
本实施方式的阵列基板的数据线，可以使一条数据线对应不同列的像素单元以输入数据信号。具体地，在多条数据线中，包括第一至第四数据线2041-2044。其中，第二数据线2042通过相应的薄膜晶体管205分别对与该第二数据线2042相邻的第一列像素单元2061和第二列像素单元2062中的部分第一像素单元201输入数据信号。第三数据线2043通过相应的薄膜晶体管205分别对与该第三数据线2043相邻的第二列像素单元2062和第三列像素单元2063中的部分第一像素单元201输入数据信号。而第一数据线2041和第四数据线2044则对第一列像素单元2061和第三列像素单元2063其余的第一像素单元201输入数据信号。通过上述方式，使第二数据线2042和第三数据线2043分别通过相应的薄膜晶体管205分别对与其相邻的两列像素单元输入数据信号，有助于减少数据线的耗能。
为了解决上述技术问题，本发明还提供一种液晶显示面板的实施方式。具体地，参阅图6，本发明液晶显示面板的一实施方式包括：阵列基板301、彩色滤光基板（图未示）以及位于阵列基板301和彩色滤光基板之间的液晶层302。
其中，液晶显示面板对应于每个像素单元的显示区域包括至少一个不透光暗区。为了实现液晶显示面板的广视角，液晶层302分为多个液晶倒向区域，在不同的液晶倒向区域，液晶分子3021的转向不同，使得在不同液晶倒向区域的交界处形成不透光暗区3022，从而在液晶显示面板对应于每个像素单元的显示区域具有不透光暗区。
其中，阵列基板301为上述各实施方式中的阵列基板。以图3所示的阵列基板为例，阵列基板包括呈行列阵列排列的多个像素单元101和多条扫描线102。每个像素单元101包括像素电极1011，并且像素单元101具有长边和短边，长边与行方向平行，短边与列方向平行。在像素电极1011中，至少有一个对应液晶层302的不透光暗区3022的主干部分10111。扫描线102设置在像素电极1011的主干部分10111的垂直投影范围内，并与像素单元101的长边的方向平行，以对像素单元101输入扫描信号。
进一步地，阵列基板还包括多条数据线103和多个薄膜晶体管104。数据线103与像素单元101的短边平行以对像素单元101输入数据信号。薄膜晶体管104包括栅极1041、源极1042以及漏极1043。一个像素单元101对应与一条扫描线102、一条数据线103以及一个薄膜晶体管104连接。其中，一个像素单元101对应的薄膜晶体管104，其栅极1041与对应的扫描线102电连接，源极1042与对应的数据线103电连接，漏极1043与对应的像素电极1011电连接。在需要进行画面显示时，分别对扫描线102和数据线103输入相应的电信号，以使像素电极1011显示相应画面。
本实施方式的液晶显示面板，通过将扫描线102设置在像素电极1011的主干部分10111的垂直投影范围内，而不是设置在两个像素单元101之间的区域105处，以使得像素电极1011可以向两个像素单元101之间的空间扩大，增加了像素单元101的穿透区域，由此能够提高液晶显示面板的穿透率和开口率，增加了液晶显示面板的亮度。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (17)

  1. 一种阵列基板，其中，包括：
    呈行列阵列排列的多个像素单元，每个所述像素单元包括像素电极和色阻层，所述像素电极包括至少一个对应不透光暗区的主干部分；
    多条扫描线，所述扫描线设置在所述主干部分的垂直投影范围内，以对像素单元输入扫描信号；
    其中，所述色阻层位于所述主干部分和所述扫描线之间；
    所述阵列基板包括显示区域，所述多个像素单元分为第一像素单元和第二像素单元，所述第一像素单元位于显示区域中，所述第二像素单元位于显示区域之外并邻近显示区域的边缘；
    在所述多条扫描线中，至少有一条扫描线设置于所述第二像素单元的对应不透光暗区的主干部分的垂直投影范围内。
  2. 根据权利要求1所述的阵列基板，其中，
    所述像素单元具有长边和短边，所述长边与行方向平行，所述短边与列方向平行；
    所述扫描线与所述长边平行。
  3. 根据权利要求2所述的阵列基板，其中，
    所述阵列基板包括多条数据线和多个薄膜晶体管，所述数据线与所述像素单元的短边平行以对像素单元输入数据信号；
    所述薄膜晶体管包括栅极、源极以及漏极，所述薄膜晶体管的栅极与扫描线电连接，所述源极与数据线电连接，所述漏极与像素电极电连接。
  4. 一种阵列基板，其中，包括：
    呈行列阵列排列的多个像素单元，每个所述像素单元包括像素电极，所述像素电极包括至少一个对应不透光暗区的主干部分；
    多条扫描线，所述扫描线设置在所述主干部分的垂直投影范围内，以对像素单元输入扫描信号。
  5. 根据权利要求4所述的阵列基板，其中，
    所述像素单元具有长边和短边，所述长边与行方向平行，所述短边与列方向平行；
    所述扫描线与所述长边平行。
  6. 根据权利要求5所述的阵列基板，其中，
    所述阵列基板包括多条数据线和多个薄膜晶体管，所述数据线与所述像素单元的短边平行以对像素单元输入数据信号；
    所述薄膜晶体管包括栅极、源极以及漏极，所述薄膜晶体管的栅极与扫描线电连接，所述源极与数据线电连接，所述漏极与像素电极电连接。
  7. 根据权利要求6所述的阵列基板，其中，
    每条所述数据线通过相应的薄膜晶体管分别对一列像素单元中的所有像素单元输入数据信号。
  8. 根据权利要求6所述的阵列基板，其中，
    至少有一条数据线通过相应的薄膜晶体管分别对与该条数据线相邻的两列像素单元中的部分像素单元输入数据信号。
  9. 根据权利要求6所述的阵列基板，其中，
    所述阵列基板包括显示区域，所述多个像素单元分为第一像素单元和第二像素单元，所述第一像素单元位于显示区域中，所述第二像素单元位于显示区域之外并邻近显示区域的边缘；
    在所述多条扫描线中，至少有一条扫描线设置于所述第二像素单元的对应不透光暗区的主干部分的垂直投影范围内。
  10. 根据权利要求6所述的阵列基板，其中，
    所述像素单元还包括色阻层，所述色阻层位于像素电极的对应不透光暗区的主干部分和扫描线之间。
  11. 一种液晶显示面板，其中，包括：
    阵列基板、彩色滤光基板以及位于阵列基板和彩色滤光基板之间的液晶层；
    所述阵列基板包括：
    呈行列阵列排列的多个像素单元，每个所述像素单元包括像素电极，所述像素电极包括至少一个对应不透光暗区的主干部分；
    多条扫描线，所述扫描线设置在所述主干部分的垂直投影范围内，以对像素单元输入扫描信号。
  12. 根据权利要求11所述的液晶显示面板，其中，
    所述像素单元具有长边和短边，所述长边与行方向平行，所述短边与列方向平行；
    所述扫描线与所述长边平行。
  13. 根据权利要求12所述的液晶显示面板，其中，
    所述阵列基板包括多条数据线和多个薄膜晶体管，所述数据线与所述像素单元的短边平行以对像素单元输入数据信号；
    所述薄膜晶体管包括栅极、源极以及漏极，所述薄膜晶体管的栅极与扫描线电连接，所述源极与数据线电连接，所述漏极与像素电极电连接。
  14. 根据权利要求13所述的液晶显示面板，其中，
    每条所述数据线通过相应的薄膜晶体管分别对一列像素单元中的所有像素单元输入数据信号。
  15. 根据权利要求13所述的液晶显示面板，其中，
    至少有一条数据线通过相应的薄膜晶体管分别对与该条数据线相邻的两列像素单元中的部分像素单元输入数据信号。
  16. 根据权利要求13所述的液晶显示面板，其中，
    所述阵列基板包括显示区域，所述多个像素单元分为第一像素单元和第二像素单元，所述第一像素单元位于显示区域中，所述第二像素单元位于显示区域之外并邻近显示区域的边缘；
    在所述多条扫描线中，至少有一条扫描线设置于所述第二像素单元的对应不透光暗区的主干部分的垂直投影范围内。
  17. 根据权利要求13所述的液晶显示面板，其中，
    所述像素单元还包括色阻层，所述色阻层位于像素电极的对应不透光暗区的主干部分和扫描线之间。
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