WO2023272505A1 - 显示基板及其制备方法、显示装置 - Google Patents
显示基板及其制备方法、显示装置 Download PDFInfo
- Publication number
- WO2023272505A1 WO2023272505A1 PCT/CN2021/103218 CN2021103218W WO2023272505A1 WO 2023272505 A1 WO2023272505 A1 WO 2023272505A1 CN 2021103218 W CN2021103218 W CN 2021103218W WO 2023272505 A1 WO2023272505 A1 WO 2023272505A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- substrate
- electrode layer
- electrode
- display
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 290
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 239000010410 layer Substances 0.000 claims description 510
- 239000000463 material Substances 0.000 claims description 43
- 239000010409 thin film Substances 0.000 claims description 42
- 239000011229 interlayer Substances 0.000 claims description 38
- 238000002161 passivation Methods 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 25
- 239000004020 conductor Substances 0.000 claims description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- 229920005591 polysilicon Polymers 0.000 claims description 9
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 7
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 230000000903 blocking effect Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 description 16
- 238000002834 transmittance Methods 0.000 description 13
- 230000008569 process Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 239000007769 metal material Substances 0.000 description 7
- 239000010408 film Substances 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 2
- 230000003190 augmentative effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000009832 plasma treatment Methods 0.000 description 2
- 238000002310 reflectometry Methods 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- -1 ITO) Chemical compound 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1237—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a different composition, shape, layout or thickness of the gate insulator in different devices
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
- G02F1/13685—Top gates
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
Definitions
- the present disclosure relates to the field of display technology, in particular to a display substrate, a manufacturing method thereof, and a display device.
- a display panel in a liquid crystal display generally includes an array substrate, a cell-matching substrate, and liquid crystals filled between the array substrate and the cell-matching substrate.
- the size of a single pixel unit becomes smaller and smaller, and a lower and lower pixel aperture ratio is an urgent problem to be solved in this field.
- the present disclosure provides a display substrate, the display substrate comprising:
- a substrate a first electrode layer disposed on one side of the substrate, the first electrode layer including a first electrode pattern;
- a second electrode layer, a second flat layer, and a third electrode layer disposed on the side of the first flat layer facing away from the substrate are laminated, wherein the second electrode layer is disposed close to the substrate, and the first electrode layer is disposed close to the substrate.
- the orthographic projection of the second electrode layer on the substrate covers the orthographic projection of the through hole on the substrate, the second electrode layer connects the first electrode pattern and the third electrode layer, the The second planarization layer is filled in the via hole to planarize the via hole.
- the orthographic projection of the through hole on the substrate completely falls within the orthographic projection of the second electrode layer on the substrate.
- the orthographic projection of the second electrode layer on the substrate completely falls within the orthographic projection of the third electrode layer on the substrate.
- the orthographic projection of the second flat layer on the substrate completely falls within the orthographic projection of the third electrode layer on the substrate.
- the shape of the through hole and the second electrode layer is rectangle, circle or ellipse.
- the display substrate includes a display area and a non-display area, and the display area includes an opening area and a non-opening area;
- the display substrate further includes: a first thin film transistor disposed between the substrate and the first electrode layer, the first thin film transistor is located in the display area, and the first thin film transistor includes stacked a first active layer, a first gate insulating layer, and a first gate, the first active layer including a drain contact region;
- the first electrode layer further includes a second electrode pattern integrally formed with the first electrode pattern, the second electrode pattern is connected to the drain contact region, and the first electrode pattern is located in the non-opening region .
- the first active layer is arranged close to the substrate, and a first interlayer dielectric layer, a second A source electrode and a first passivation layer, the first electrode layer is arranged on the side of the first passivation layer away from the substrate, the second electrode pattern and the drain contact region are arranged on the The via holes on the first passivation layer, the first interlayer dielectric layer and the first gate insulating layer are connected.
- the material of the first electrode layer is a transparent conductive material.
- the drain contact region is located in the non-opening region, and the material of the first electrode layer is metal.
- the drain contact region is located in the non-opening region, and the first gate insulating layer, the first interlayer dielectric layer, and the first passivation layer are located in the non-opening region.
- the orthographic projection on the substrate has no overlap with the opening area.
- the first active layer is arranged close to the substrate, and a first interlayer dielectric layer and a second interlayer dielectric layer are stacked on the side of the first gate away from the substrate.
- a source-drain electrode layer, the first source-drain electrode layer includes a first source electrode and a first drain electrode arranged in the same layer, and the first drain electrode and the drain electrode contact region are arranged on the first layer
- the interlayer and the via hole on the first gate insulating layer are connected, the first electrode layer is arranged on the side of the first drain away from the substrate, and the second electrode pattern is connected to the The first drain contact is connected.
- the drain contact region is located in the non-opening region, and the material of the first drain is metal.
- the display substrate includes a display area and a non-display area, and the display area includes an opening area and a non-opening area;
- the display substrate further includes: a first thin film transistor disposed on a side of the substrate close to the first electrode layer, the first thin film transistor is located in the display area, and the first thin film transistor includes stacked A first active layer, a first gate insulating layer, a first gate, a first interlayer dielectric layer, and a first source, the first active layer is disposed close to the substrate, and the first active a layer comprising a drain contact region located in the opening region;
- Orthographic projections of the first gate insulating layer and the first interlayer dielectric layer on the substrate do not overlap with the opening area; the drain contact area is the first electrode pattern.
- the material of the first active layer includes metal oxide.
- the display region further includes data lines and scan lines
- the first source extends along a first direction to form the data line
- the first gate is A second direction intersecting with one direction extends to form the scan lines
- the orthographic projections of the data lines and the scan lines on the substrate both cover the channel region of the first active layer on the substrate. Orthographic projection on the bottom.
- the material of the first active layer includes polysilicon
- the orthographic projection of the data line on the substrate covers the first active layer on the substrate. orthographic projection.
- a shielding layer and a second interlayer dielectric layer are stacked between the first active layer and the substrate, the shielding layer is disposed close to the substrate,
- the orthographic projection of the blocking layer on the substrate covers the orthographic projection of the channel region of the first active layer on the substrate.
- the display area further includes data lines and scan lines, and the orthographic projection of the shielding layer on the substrate covers the data lines and the scan lines on the substrate. Orthographic projection on .
- the shielding layer is connected to a fixed potential input terminal.
- the shielding layer and the first source are arranged between the second interlayer dielectric layer, the first gate insulating layer and the first interlayer dielectric layer Via connections on the .
- the material of the shielding layer includes at least one of the following: molybdenum, aluminum and silver.
- the display substrate further includes a second thin film transistor located in the non-display area, and an active layer material of the second thin film transistor includes polysilicon.
- the channel region of the first active layer includes a first channel region, a first resistance region and a second channel region sequentially arranged along a first direction
- the first channel region A gate includes a first sub-gate and a second sub-gate separately arranged
- the orthographic projection of the first sub-gate on the substrate covers the first channel region on the substrate.
- Orthographic projection, the orthographic projection of the second sub-gate on the substrate covers the orthographic projection of the second channel region on the substrate.
- a second passivation layer and a fourth electrode layer are stacked on the side of the first electrode layer away from the substrate, and the fourth electrode layer is transparent and connected to the first electrode layer.
- a fixed potential input terminal, the second passivation layer is disposed close to the substrate, and the orthographic projections of the first electrode layer and the fourth electrode layer on the substrate overlap;
- the first flat layer is disposed on the side of the fourth electrode layer away from the substrate, the through hole penetrates through the second passivation layer, and the through hole and the fourth electrode layer are on the
- the orthographic projection on the substrate has no overlap.
- the display substrate includes an opening area, and a color-resist layer is further provided on the side of the first electrode layer away from the substrate, and the color-resist layer is on the substrate The orthographic projection of covers the opening area;
- the first flat layer is disposed on the side of the color-resist layer away from the substrate, and the orthographic projection of the through hole on the substrate is the same as the orthographic projection of the color-resist layer on the substrate No overlap.
- a third passivation layer and a common electrode layer are stacked on the side of the third electrode layer away from the substrate, and the third passivation layer is close to the substrate configuration, wherein the common electrode layer includes a plurality of strip electrodes, and the material of the common electrode layer is metal.
- an isolation column is further provided on a side of the first planar layer away from the substrate, and the isolation column is formed synchronously with the second planar layer.
- the present disclosure provides a display device, including the display substrate described in any embodiment.
- the present disclosure provides a preparation method of a display substrate, the preparation method comprising:
- first electrode layer on one side of the substrate, the first electrode layer including a first electrode pattern
- a first planar layer is sequentially formed on the side of the first electrode layer away from the substrate, and a through hole is arranged on the first planar layer, and the through hole penetrates through the first planar layer, so that the The first electrode pattern is exposed;
- a second electrode layer, a second flat layer, and a third electrode layer are sequentially formed on the side of the first flat layer away from the substrate, wherein the orthographic projection of the second electrode layer on the substrate covers Orthographic projection of the through hole on the bottom, the second electrode layer is used to connect the first electrode pattern and the third electrode layer, and the second planar layer is used to planarize the through hole .
- FIG. 1 shows a schematic cross-sectional structure diagram of a display substrate provided by an embodiment of the present disclosure
- FIG. 2 shows a schematic cross-sectional structure diagram of a display substrate provided by an embodiment of the present disclosure
- FIG. 3 shows a schematic cross-sectional structure diagram of a display substrate provided by an embodiment of the present disclosure
- FIG. 4 shows a schematic plan view of a display substrate provided by an embodiment of the present disclosure
- FIG. 5 shows a schematic plan view of a first thin film transistor provided by an embodiment of the present disclosure
- FIG. 6 shows a schematic cross-sectional structure diagram of a first thin film transistor provided by an embodiment of the present disclosure
- FIG. 7 shows a schematic plan view of the shielding layer provided by an embodiment of the present disclosure.
- FIG. 8 shows a schematic cross-sectional structure diagram of a display substrate on which a second electrode layer has been fabricated according to an embodiment of the present disclosure
- FIG. 9 shows a schematic cross-sectional structure diagram of a display substrate that has completed the fabrication of a second flat material layer provided by an embodiment of the present disclosure
- FIG. 10 shows a schematic cross-sectional structure of a display substrate provided by an embodiment of the present disclosure after the fabrication of the second flat layer is completed;
- FIG. 11 shows a schematic cross-sectional structure diagram of a display substrate provided by an embodiment of the present disclosure after the fabrication of the third electrode layer is completed;
- FIG. 12 shows a schematic cross-sectional structure of a display substrate provided by an embodiment of the present disclosure after the third passivation layer has been fabricated
- FIG. 13 shows a schematic cross-sectional structure diagram of a display substrate that has completed the fabrication of a common electrode layer provided by an embodiment of the present disclosure
- FIG. 14 shows a schematic plan view of the display substrate with the first active layer fabricated according to an embodiment of the present disclosure
- FIG. 15 shows a schematic plan view of the display substrate with the first gate fabricated according to an embodiment of the present disclosure
- FIG. 16 shows a schematic plan view of the display substrate provided by an embodiment of the present disclosure after the fabrication of the first interlayer dielectric layer is completed;
- FIG. 17 shows a schematic plan view of a display substrate with data lines fabricated according to an embodiment of the present disclosure
- FIG. 18 shows a schematic plan view of the display substrate provided by an embodiment of the present disclosure after the fabrication of the first electrode layer is completed;
- FIG. 19 shows a schematic plan view of the structure of the display substrate provided by the embodiment of the present disclosure after the manufacture of the color-resist layer is completed;
- FIG. 20 shows a schematic plan view of the display substrate provided by an embodiment of the present disclosure after the fabrication of the first flat layer is completed;
- FIG. 21 shows a schematic plan view of the display substrate provided by an embodiment of the present disclosure after the fabrication of the third electrode layer is completed;
- FIG. 22 shows a schematic plan view of the structure of the display substrate provided by an embodiment of the present disclosure after the fabrication of the common electrode layer is completed.
- An embodiment of the present disclosure provides a display substrate. Referring to FIG. 1 to FIG. Electrode pattern 121; the first flat layer 13 arranged on the side of the first electrode layer 12 facing away from the substrate 11, the first flat layer 13 is provided with a through hole, the through hole penetrates the first flat layer 13, so that the first electrode pattern 121 naked.
- the second electrode layer 14, the second flat layer 15, and the third electrode layer 16 arranged on the side of the first flat layer 13 facing away from the substrate 11 are laminated, wherein the second electrode layer 14 is arranged close to the substrate 11, and the second electrode layer
- the orthographic projection of 14 on the substrate 11 covers the orthographic projection of the through hole on the substrate 11, the second electrode layer 14 is connected to the first electrode pattern 121 and the third electrode layer 16, and the second flat layer 15 is filled in the through hole to Planarized vias.
- the through hole on the first flat layer 13 is filled and leveled, the deep hole structure on the first flat layer 13 is eliminated, and the light leakage caused by the deep hole structure is eliminated, thereby There is no need to set a large light-shielding layer to block light leakage, so the pixel aperture ratio of the display area can be increased.
- the third electrode layer 16 is arranged on a flat surface, when the third electrode layer 16 is used as a pixel electrode layer, it can ensure that the distance between the pixel electrode layer and the common electrode layer remains consistent, so that the electric field is uniform, and the liquid crystal The deflection is normal, avoiding light leakage caused by abnormal liquid crystal deflection, and there is no need to set a large light-shielding layer to block light leakage, so the pixel aperture ratio of the display area can be increased.
- the materials of the first electrode layer 12 , the second electrode layer 14 and the third electrode layer 16 may be, for example, transparent conductive materials or metal materials, which are not limited in this embodiment.
- the materials of the first electrode layer 12 , the second electrode layer 14 and the third electrode layer 16 are all transparent conductive materials, the transmittance of the display area can be further improved.
- the first electrode layer 12 and the second electrode layer 14 are made of the same material, they can be deposited at the same time and formed by one patterning process, thus saving one mask process.
- the transparent conductive material may include at least one of transparent metal oxides such as indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO) and graphene oxide, for example.
- transparent metal oxides such as indium tin oxide (Indium Tin Oxide, ITO), indium zinc oxide (Indium Zinc Oxide, IZO) and graphene oxide, for example.
- the orthographic projection of the through hole on the first planar layer 13 on the substrate 11 completely falls within the orthographic projection of the second electrode layer 14 on the substrate 11 .
- the orthographic projection of the second electrode layer 14 on the substrate 11 completely falls within the orthographic projection of the third electrode layer 16 on the substrate 11.
- the orthographic projection of the second flat layer 15 on the substrate 11 completely falls within the orthographic projection of the third electrode layer 16 on the substrate 11 .
- the shapes of the through holes on the first flat layer 13 and the second electrode layer 14 are rectangular, circular or elliptical. This is not limited.
- the display substrate includes a display area and a non-display area, and the display area includes an opening area and a non-opening area; the display substrate may also include: The first thin film transistor 17 between the electrode layers 12, the first thin film transistor 17 is located in the display area, and the first thin film transistor 17 includes a stacked first active layer 171, a first gate insulating layer 172 and a first gate 173 .
- the first active layer 171 includes the drain contact region 21 .
- the first electrode layer 12 may further include a second electrode pattern 122 integrally formed with the first electrode pattern 121 , the second electrode pattern 122 is connected to the drain contact region 21 , and the first electrode pattern 121 is located in the non-opening region.
- the first thin film transistor 17 may have a top-gate structure (as shown in FIGS. 1 to 2 ) or a bottom-gate structure, which is not limited in this embodiment.
- the first gate 173 may be a single gate structure (as shown in FIG. 1 ), a double gate structure (as shown in FIG. 2 ) or a multi-gate structure, etc., which is not limited in this embodiment.
- the material of the first active layer 171 may include amorphous silicon, polysilicon, or metal oxide, which is not limited in this embodiment.
- the drain contact region 21 may be formed by conducting the material of the first active layer 171 . Conductorization can be achieved by ion doping, plasma treatment and other processes.
- a first interlayer dielectric layer 18, a first source electrode 19 and a first passivation layer 110 are stacked on the side away from the substrate 11, and the first electrode layer 12 is arranged on a side of the first passivation layer 110 away from the substrate 11.
- the second electrode pattern 122 is connected to the drain contact region 21 through the via holes provided on the first passivation layer 110 , the first interlayer dielectric layer 18 and the first gate insulating layer 172 .
- the material of the first electrode layer 12 can be a transparent conductive material, which can improve the transmittance of the display area.
- the material of the first active layer 171 can include metal oxide, which can reduce the contact resistance between the second electrode pattern 122 and the drain contact region 21 .
- the material of the first electrode layer 12 can also be a metal material, and the second electrode pattern 122 and the drain contact region 21 connected to the second electrode pattern 122 can be located in a non-opening area, further increasing the pixel aperture ratio.
- the material of the first electrode layer 12 can be a metal material, the contact resistance between the second electrode pattern 122 and the drain contact region 21 can be reduced.
- the second electrode pattern 122 in the first electrode layer 12 is multiplexed as the drain of the first thin film transistor, and is connected to the drain contact region 21 through a via hole.
- the orthographic projections of the first gate insulating layer 172 , the first interlayer dielectric layer 18 and the first passivation layer 110 on the substrate 11 may not overlap with the opening area.
- the first active layer 171 is disposed close to the substrate 11, and the 173 is stacked with a first interlayer dielectric layer 18 and a first source-drain electrode layer on the side away from the substrate 11.
- the first source-drain electrode layer includes a first source electrode 19 and a first drain electrode 111 arranged in the same layer.
- a drain 111 is connected to the drain contact region 21 through a via hole arranged on the first interlayer dielectric layer 18 and the first gate insulating layer 172, and the first electrode layer 12 is arranged on the first drain 111 facing away from the substrate 11 On one side of the drain electrode 111 , the second electrode pattern 122 is in contact with the first drain electrode 111 .
- the material of the first drain electrode 111 is metal.
- the first drain 111 made of metal material can reduce the contact resistance between the first drain 111 and the drain contact region 21 .
- the drain contact region 21 and the first drain 111 connected to the drain contact region 21 may be located in the non-opening area.
- the first electrode layer 12 functions as a transfer layer, and the material of the first electrode layer 12 can be a transparent conductive material, which can increase the aperture ratio and transmittance.
- the first thin film transistor 17 When the first active layer 171 is arranged close to the substrate 11, the first thin film transistor 17 has a top-gate structure. Compared with the traditional bottom-gate structure, since the first gate 173 does not need to block the backlight, the size can be reduced, thereby reducing the The parasitic capacitance formed between the first gate 173 and other film layers is reduced to reduce power consumption.
- the orthographic projections of the first gate insulating layer 172 and the first interlayer dielectric layer 18 on the substrate 11 may not overlap with the opening area.
- the display substrate includes a display area and a non-display area, and the display area includes an opening area and a non-opening area; the display substrate further includes: The first thin film transistor 17 on one side, the first thin film transistor 17 is located in the display area, and the first thin film transistor 17 includes a first active layer 171, a first gate insulating layer 172, a first gate 173, a first The interlayer dielectric layer 18 and the first source 19, the first active layer 171 is disposed close to the substrate 11, the first active layer 171 includes a drain contact region 21, and the drain contact region 21 is located in the opening area; the drain contact region 21 is the first electrode pattern 121 .
- the orthographic projections of the first gate insulating layer 172 and the first interlayer dielectric layer 18 on the substrate 11 may not overlap with the opening area.
- the drain contact area is located in the opening area, the drain contact area can overlap with the first electrode layer located in the opening area, without making a transfer electrode or a drain, so the aperture ratio and transmittance of the display area can be improved.
- the material of the first active layer 171 is a transparent metal oxide, even if the drain contact region 21 of the first active layer 171 is arranged in the opening region, it will not affect the aperture ratio and the transmittance of the display region. Rate.
- the display area further includes data lines 41 and scan lines 42.
- the second intersecting direction extends to form the scan line 42 , and the orthographic projections of the data line 41 and the scan line 42 on the substrate 11 cover the orthographic projection of the channel region of the first active layer 171 on the substrate 11 .
- the second direction may be perpendicular to the first direction, as shown in FIG. 4 .
- the orthographic projection of the data line 41 on the substrate 11 covers the orthographic projection of the first active layer 171 on the substrate 11 . Since the first active layer 171 made of polysilicon is opaque, disposing the first active layer 171 in the non-opening area corresponding to the data line 41 can increase the aperture ratio of the pixel.
- FIGS. 1 to 3 A shielding layer 112 and a second interlayer dielectric layer 113 are stacked between the first active layer 171 and the substrate 11, the shielding layer 112 is disposed close to the substrate 11, and the orthographic projection of the shielding layer 112 on the substrate 11 An orthographic projection of the channel region covering the first active layer 171 on the substrate 11 .
- the orthographic projection of the second interlayer dielectric layer 113 on the substrate 11 may not overlap with the opening area.
- the orthographic projection of the shielding layer 112 on the substrate 11 may cover the orthographic projections of the data lines 41 and the scan lines 42 on the substrate 11 . That is, the shielding layer 126 is a mesh structure.
- the shielding layer with a mesh structure can increase the area of the shielding layer without affecting the aperture ratio, so that more backlight can be reflected and the transmittance of the backlight can be improved.
- the shielding layer 112 is connected to a fixed potential input terminal. This implementation can prevent display abnormality caused by threshold voltage drift of the first thin film transistor 17 and improve display uniformity.
- the shielding layer 112 and the first source electrode 19 are arranged on the second interlayer dielectric layer 113, the first gate insulating layer 172 and the first interlayer dielectric layer. 18 through-hole connections.
- the shielding layer 126 can be made of a metal material with high reflectivity, and the metal material can include at least one of the following: molybdenum, aluminum, silver and tin.
- the shielding layer made of high-reflectivity material can reflect the backlight irradiated on the shielding layer, and the reflected backlight can be reused, thereby increasing the transmittance of the backlight.
- the material of the shielding layer can be, for example, Al/top TIN, Al/top Mo, Al alloy/top TIN or Al alloy/top Mo. These materials have good high temperature resistance and stability, and the reflectance before and after high temperature annealing is stable.
- the material of the first active layer 171 includes metal oxide
- the display substrate further includes a second thin film transistor 114
- the second thin film transistor 114 is located in the non-display area
- the second thin film transistor 114 has
- the source layer material includes polysilicon.
- the second thin film transistor 114 can be formed using a low temperature polysilicon (Low Temperature Poly-Silicon, LTPS) process to improve the circuit driving capability of the non-display area.
- the first thin film transistor 17 can be formed by using an indium gallium zinc oxide (IGZO) process, which can reduce the leakage current, improve the voltage retention rate, and improve the display effect of the display area.
- IGZO indium gallium zinc oxide
- the channel region 22 of the first active layer 171 may include a first channel region 61 and a first resistance region 62 sequentially arranged along the first direction. and the second channel region 63, the first gate 173 includes a first sub-gate 64 and a second sub-gate 65 which are separately arranged, and the orthographic projection of the first sub-gate 64 on the substrate 11 covers the first channel The orthographic projection of the region 61 on the substrate 11 , the orthographic projection of the second sub-gate 65 on the substrate 11 covers the orthographic projection of the second channel region 63 on the substrate 11 .
- the first channel region 61 , the first resistance region 62 and the second channel region 63 are sequentially arranged along the first direction to form an I-type channel.
- the first channel region 61 and the second channel region 63 may be equivalent to two TFT switches connected in series, and the first resistor region 62 may be equivalent to a resistor connected in series between the two TFT switches.
- the first resistance region 62 may be formed by performing ion doping, plasma treatment and other processes on the material of the first active layer 171 .
- the first resistance region 62 between the first channel region 61 and the second channel region 63, it is equivalent to connecting a resistor in series between two TFT switches, and the setting of the resistance can suppress leakage.
- the current generation can reduce the leakage current of the thin film transistor and improve the stability of the threshold voltage.
- the first sub-gate 64 is used for receiving a signal for controlling the first channel region 61 to be turned on or off.
- the second sub-gate 65 is used for receiving a signal for controlling the turn-on or turn-off of the second channel region 63 .
- the signals received by the first sub-gate 64 and the second sub-gate 65 may be the same, which is not limited in this embodiment.
- the first thin film transistor since the first thin film transistor has a double-gate structure, it has high electrical stability and a good voltage retention rate, so the display effect and reliability of the display substrate can be improved.
- the channel of the first thin film transistor is an I-type channel, it occupies a small area in the pixel unit of the display substrate, so the aperture ratio of the display substrate can be increased, especially for a display substrate with a high pixel density. Increase opening rate.
- the display substrate can be applied to virtual reality display technology (Virtual Reality, VR), augmented reality (Augmented Reality, AR) display technology, and the like.
- the source contact region 20 in the first active layer 171 may include a first conductor region 66 and a second resistance region 67 disposed close to the first channel region 61 .
- the drain contact region 21 may include a second conductor region 69 and a third resistance region 68 disposed close to the second channel region 63 .
- a second passivation layer 115 and a fourth electrode layer 116 are stacked on the side of the first electrode layer 12 away from the substrate 11, the fourth electrode layer 116 is transparent and connected to the first fixed potential input terminal, the second The passivation layer 115 is arranged close to the substrate 11, and the orthographic projections of the first electrode layer 12 and the fourth electrode layer 116 on the substrate 11 overlap; the first flat layer 13 is arranged on the side of the fourth electrode layer 116 away from the substrate 11 On one side, the through hole penetrates the second passivation layer 115 , and the through hole does not overlap with the orthographic projection of the fourth electrode layer 116 on the substrate 11 .
- first electrode layer 12 and the fourth electrode layer 116 may extend into the opening area, as shown in FIG. 2 .
- Both the first electrode layer 12 and the fourth electrode layer 116 can be made of transparent conductive material, which can improve the transmittance of the opening area.
- a storage capacitor can be formed to increase the pixel storage capacitor and ensure that there is still enough storage capacity in a smaller pixel space. Capacitor, improve voltage retention rate, ensure normal display.
- the voltage on the fourth electrode layer 116 may be, for example, a common voltage.
- an insulating layer 121 is further disposed on the side of the fourth electrode layer 116 away from the substrate 11 , and the data line 41 is disposed on the side of the insulating layer 121 away from the substrate 11 .
- the first flat layer 13 is disposed on the side of the data line 41 facing away from the substrate 11 , the through hole penetrates through the insulating layer 121 , and the through hole does not overlap with the orthographic projection of the data line 41 on the substrate 11 .
- the fourth electrode layer 116 By arranging the fourth electrode layer 116 between the data line 41 and the first electrode layer 12 , it is possible to avoid the formation of coupling capacitance between the data line 41 and the first electrode layer 12 due to too close a distance. Since the fourth electrode layer 116 is connected to a fixed potential, even if the signal on the data line 41 changes at a high frequency, the influence of the signal on the data line 41 on the first electrode layer 12 can be shielded, thereby shielding the influence of the data line 41 on the pixels on the pixel electrode layer. The influence of the voltage, so as to realize the normal display of the pixel.
- the display substrate includes an opening area, and a color-resist layer 117 is also provided on the side of the first electrode layer 12 facing away from the substrate 11.
- the orthographic projection of the color-resist layer 117 on the substrate 11 covers the opening area; the first flat layer 13 is disposed on the side of the color resist layer 117 away from the substrate 11 , and the orthographic projection of the through hole on the substrate 11 does not overlap with the orthographic projection of the color resist layer 117 on the substrate 11 .
- the first electrode layer 12 and the color-resist layer 117 may be sequentially patterned on the side of the first passivation layer 110 away from the substrate 11, and then the color-resist layer 117 and the first electrode layer 12 are away from the substrate.
- One side of the base 11 forms a first flat layer 13 .
- the color-resist layer 117 may include a red color-resist layer, a green color-resist layer and a blue color-resist layer, and each color-resist layer is arranged in a different sub-pixel unit to realize color display.
- the display substrate is relatively close to the backlight source in the display device, which can reduce the crosstalk of light between adjacent sub-pixel units and affect the display effect.
- a third passivation layer 118 and a common electrode layer 119 are stacked on the side of the third electrode layer 16 facing away from the substrate 11 , and the third passivation layer 118 is disposed close to the substrate 11 .
- the material of the common electrode layer 118 may be a transparent conductive material or a metal material, which is not limited in this embodiment.
- the common electrode layer 118 may include a plurality of strip electrodes, and the plurality of strip electrodes may form a horizontal electric field with the pixel electrode layer 19 .
- the width and spacing of the strip electrodes can be designed according to actual requirements, which is not limited in this embodiment.
- the material of the common electrode layer 118 can be metal.
- an isolation column 120 is further provided on a side of the first planar layer 13 facing away from the substrate 11 , and the isolation column 120 is formed synchronously with the second planar layer 15 .
- the isolation column 120 is made of the same material as the second planar layer 15, and both are formed in the same process, which can simplify the process steps and reduce the cost.
- Another embodiment of the present disclosure further provides a display device, which may include the display substrate described in any embodiment.
- the display device in this embodiment can be any product or component with 2D or 3D display function, such as display panel, electronic paper, mobile phone, tablet computer, television, notebook computer, digital photo frame, and navigator.
- Another embodiment of the present disclosure also provides a method for preparing a display substrate, the method comprising:
- Step 11 providing a substrate
- Step 12 forming a first electrode layer on one side of the substrate, the first electrode layer including a first electrode pattern;
- Step 13 sequentially forming a first flat layer on the side of the first electrode layer away from the substrate, the first flat layer is provided with a through hole, and the through hole penetrates the first flat layer, so that the first electrode pattern is exposed;
- Step 14 Form a second electrode layer, a second flat layer, and a third electrode layer sequentially on the side of the first flat layer away from the substrate, wherein the orthographic projection of the second electrode layer on the substrate covers the through hole on the bottom Orthographic projection of , the second electrode layer is used to connect the first electrode pattern and the third electrode layer, and the second planar layer is used to planarize the through hole.
- the display substrate described in any of the above embodiments can be prepared.
- the method for preparing a display substrate may include the following steps:
- Step 21 Firstly, the fabrication of the first thin film transistor 17 and the second thin film transistor 114 is completed on the substrate 11, and then the first electrode layer 12 and the first flat layer are sequentially formed on the side of the first passivation layer 110 facing away from the substrate 11. 13 and a second electrode layer 14, wherein the first flat layer 13 is provided with a through hole, and the second electrode layer 14 covers the through hole to form a display substrate as shown in FIG. 8 ;
- Step 22 making a second flat material layer, and filling the through holes on the first flat layer 13 to form a display substrate as shown in FIG. 9 ;
- Step 23 pattern the second flat material layer, and form the spacer columns 120 and the second flat layer 15 respectively by controlling the exposure energy in different regions, forming the display substrate as shown in FIG. 10; wherein, the second flat layer 15 For filling the through holes on the first flat layer 13, the materials of the second flat layer 15 and the first flat layer 13 can be the same or different;
- Step 24 Depositing ITO and patterning to form a third electrode layer to obtain a display substrate as shown in Figure 11;
- Step 25 Depositing and forming a third passivation layer 118 to form a display substrate as shown in FIG. 12 ;
- Step 26 Patterning and forming the common electrode layer 119 to form the display substrate as shown in FIG. 1 .
- the method for preparing a display substrate may include the following steps:
- Step 31 making a shielding layer, which shields the channel region of the first TFT to prevent backlight from affecting the characteristics of the TFT.
- FIG. 13 it shows a schematic plan view of the structure of the display substrate after the shielding layer has been fabricated.
- Step 32 Fabricate a buffer layer and a first active layer made of metal oxide.
- the drain contact area is located in the opening area. Since the metal oxide is transparent, it will not affect the pixel aperture ratio.
- FIG. 14 a schematic plan view of the structure of the display substrate after the fabrication of the first active layer is shown.
- Step 33 making a first gate insulating layer and a first gate, the first gate is located in the shielding layer region, ensuring that the channel region in the first active layer is shielded by the shielding layer.
- FIG. 15 a schematic plan view of the structure of the display substrate after the fabrication of the first gate is shown.
- Step 34 Fabricate the first interlayer dielectric layer, and drill holes at the positions corresponding to the source contact regions of the first active layer, such as 161 in FIG. 16 , so that subsequent film layers overlap the first active layer.
- FIG. 16 a schematic plan view of the structure of the display substrate after the fabrication of the first interlayer dielectric layer is shown.
- Step 35 making a data line, the data line is connected to the source contact area through a via hole provided on the first interlayer dielectric layer.
- FIG. 17 it shows a schematic plan view of the structure of the display substrate on which the data lines have been fabricated.
- Step 36 Make the first passivation layer and the first electrode layer, and drill holes on the first passivation layer corresponding to the drain contact area of the first active layer, as shown in 181 in Figure 18, the first electrode layer It is connected with the drain contact region through the via hole arranged on the first passivation layer.
- FIG. 18 a schematic plan view of the structure of the display substrate after the fabrication of the first electrode layer is shown.
- Step 37 Fabricate a color-resist layer, and disposing the color-resist layer on the display substrate can effectively reduce the crosstalk between lights of different colors; referring to FIG. 19 , it shows a schematic plan view of the display substrate with the color-resist layer fabricated.
- Step 38 Fabricate the first flat layer and form through holes, as shown in 201 in FIG. 20 .
- FIG. 20 it shows a schematic plan view of the display substrate after the first flat layer is fabricated.
- Step 39 Forming the second electrode layer, the second flat layer and the third electrode layer in sequence, wherein the second electrode layer and the third electrode layer are formed respectively, and the second flat layer is used to fill and level the through holes on the first flat layer , this structure not only ensures the electrical connection between the third electrode layer and the first electrode layer, but also ensures the flatness of the entire surface of the third electrode layer, and ensures the formation of a uniform electric field with the common electrode layer.
- FIG. 21 a schematic plan view of the structure of the display substrate after the third electrode layer is shown.
- Step 310 Fabricate a third passivation layer and a common electrode layer.
- the common electrode layer and the third electrode layer together form an electric field to drive the liquid crystal to deflect.
- FIG. 22 a schematic plan view of the structure of the display substrate after the common electrode layer has been fabricated is shown. In this way, the display substrate shown in FIG. 1 can be prepared.
- references herein to "one embodiment,” “an embodiment,” or “one or more embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Additionally, please note that examples of the word “in one embodiment” herein do not necessarily all refer to the same embodiment.
- any reference signs placed between parentheses shall not be construed as limiting the claim.
- the word “comprising” does not exclude the presence of elements or steps not listed in a claim.
- the word “a” or “an” preceding an element does not exclude the presence of a plurality of such elements.
- the disclosure can be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means can be embodied by one and the same item of hardware.
- the use of the words first, second, and third, etc. does not indicate any order. These words can be interpreted as names.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
Description
Claims (29)
- 一种显示基板,其中,所述显示基板包括:衬底,设置在所述衬底一侧的第一电极层,所述第一电极层包括第一电极图案;设置在所述第一电极层背离所述衬底一侧的第一平坦层,所述第一平坦层上设置有通孔,所述通孔贯穿所述第一平坦层,以使所述第一电极图案裸露;层叠设置在所述第一平坦层背离所述衬底一侧的第二电极层、第二平坦层以及第三电极层,其中,所述第二电极层靠近所述衬底设置,所述第二电极层在所述衬底上的正投影覆盖所述通孔在所述衬底上的正投影,所述第二电极层连接所述第一电极图案以及所述第三电极层,所述第二平坦层填充于所述通孔内以平坦化所述通孔。
- 根据权利要求1所述的显示基板,其中,所述通孔在所述衬底上的正投影完全落入所述第二电极层在所述衬底上的正投影内。
- 根据权利要求1所述的显示基板,其中,所述第二电极层在所述衬底上的正投影完全落入第三电极层在所述衬底上的正投影内。
- 根据权利要求1所述的显示基板,其中,所述第二平坦层在所述衬底上的正投影完全落入第三电极层在所述衬底上的正投影内。
- 根据权利要求1所述的显示基板,其中,所述通孔和所述第二电极层的形状为矩形、圆形或椭圆形。
- 根据权利要求1所述的显示基板,其中,所述显示基板包括显示区和非显示区,所述显示区包括开口区域和非开口区域;所述显示基板还包括:设置在所述衬底与所述第一电极层之间的第一薄膜晶体管,所述第一薄膜晶体管位于所述显示区,所述第一薄膜晶体管包括层叠设置的第一有源层、第一栅极绝缘层和第一栅极,所述第一有源层包括漏极接触区;所述第一电极层还包括与所述第一电极图案一体形成的第二电极图案,所述第二电极图案与所述漏极接触区连接,所述第一电极图案位于所述非开口区域。
- 根据权利要求6所述的显示基板,其中,所述第一有源层靠近所述衬底设置,在所述第一栅极背离所述衬底的一侧层叠设置有第一层间介质层、第一源极和第一钝化层,所述第一电极层设置在所述第一钝化层背离所述衬底的一侧,所述第二电极图案与所述漏极接触区通过设置在所述第一钝化层、所述第一层间介质层以及所述第一栅极绝缘层上的过孔连接。
- 根据权利要求7所述的显示基板,其中,所述第一电极层的材料为透明导电材料。
- 根据权利要求7所述的显示基板,其中,所述漏极接触区位于所述非开口区域,所述第一电极层的材料为金属。
- 根据权利要求7所述的显示基板,其中,所述漏极接触区位于所述非开口区域,所述第一栅极绝缘层、所述第一层间介质层以及所述第一钝化层在所述衬底上的正投影与所述开口区域无交叠。
- 根据权利要求6所述的显示基板,其中,所述第一有源层靠近所述衬底设置,在所述第一栅极背离所述衬底的一侧层叠设置有第一层间介质层和第一源漏电极层,所述第一源漏电极层包括同层设置的第一源极和第一漏极,所述第一漏极与所述漏极接触区通过设置在所述第一层间介质层以及所述第一栅极绝缘层上的过孔连接,所述第一电极层设置在所述第一漏极背离所述衬底的一侧,所述第二电极图案与所述第一漏极接触连接。
- 根据权利要求11所述的显示基板,其中,所述漏极接触区位于所述非开口区域,所述第一漏极的材料为金属。
- 根据权利要求1所述的显示基板,其中,所述显示基板包括显示区和非显示区,所述显示区包括开口区域和非开口区域;所述显示基板还包括:设置在所述衬底靠近所述第一电极层一侧的第一薄膜晶体管,所述第一薄膜晶体管位于所述显示区,所述第一薄膜晶体管包括层叠设置的第一有源层、第一栅极绝缘层、第一栅极、第一层间介质层和第一源极,所述第一有源层靠近所述衬底设置,所述第一有源层包括漏极接触区,所述漏极接触区位于所述开口区域;所述第一栅极绝缘层以及所述第一层间介质层在所述衬底上的正投影与所述开口区域无交叠;所述漏极接触区为所述第一电极图案。
- 根据权利要求13所述的显示基板,其中,所述第一有源层的材料包 括金属氧化物。
- 根据权利要求7或13所述的显示基板,其中,所述显示区域还包括数据线和扫描线,所述第一源极沿第一方向延伸构成所述数据线,所述第一栅极沿与所述第一方向相交的第二方向延伸构成所述扫描线,所述数据线以及所述扫描线分别在所述衬底上的正投影均覆盖所述第一有源层的沟道区在所述衬底上的正投影。
- 根据权利要求15所述的显示基板,其中,所述第一有源层的材料包括多晶硅,所述数据线在所述衬底上的正投影覆盖所述第一有源层在所述衬底上的正投影。
- 根据权利要求7、11或13所述的显示基板,其中,在所述第一有源层与所述衬底之间还层叠设置有遮挡层和第二层间介质层,所述遮挡层靠近所述衬底设置,所述遮挡层在所述衬底上的正投影覆盖所述第一有源层的沟道区在所述衬底上的正投影。
- 根据权利要求17所述的显示基板,其中,所述显示区还包括数据线和扫描线,所述遮挡层在所述衬底上的正投影覆盖所述数据线以及所述扫描线在所述衬底上的正投影。
- 根据权利要求17所述的显示基板,其中,所述遮挡层连接固定电位输入端。
- 根据权利要求17所述的显示基板,其中,所述遮挡层与所述第一源极通过设置在所述第二层间介质层、所述第一栅极绝缘层以及所述第一层间介质层上的过孔连接。
- 根据权利要求17所述的显示基板,其中,所述遮挡层的材料包括以下至少之一:钼、铝和银。
- 根据权利要求7、11或13所述的显示基板,其中,所述显示基板还包括第二薄膜晶体管,所述第二薄膜晶体管位于所述非显示区,所述第二薄膜晶体管的有源层材料包括多晶硅。
- 根据权利要求7、11或13所述的显示基板,其中,所述第一有源层的沟道区包括沿第一方向依次排布的第一沟道区、第一电阻区和第二沟道区,所述第一栅极包括分立设置的第一子栅极和第二子栅极,所述第一子栅极在所述衬底上的正投影覆盖所述第一沟道区在所述衬底上的正投影,所述第二 子栅极在所述衬底上的正投影覆盖所述第二沟道区在所述衬底上的正投影。
- 根据权利要求1所述的显示基板,其中,在所述第一电极层背离所述衬底的一侧层叠设置有第二钝化层和第四电极层,所述第四电极层透明并且连接第一固定电位输入端,所述第二钝化层靠近所述衬底设置,所述第一电极层与所述第四电极层在所述衬底上的正投影有交叠;所述第一平坦层设置在所述第四电极层背离所述衬底的一侧,所述通孔贯穿所述第二钝化层,所述通孔与所述第四电极层在所述衬底上的正投影无交叠。
- 根据权利要求1所述的显示基板,其中,所述显示基板包括开口区域,在所述第一电极层背离所述衬底的一侧还设置有色阻层,所述色阻层在所述衬底上的正投影覆盖所述开口区域;所述第一平坦层设置在所述色阻层背离所述衬底的一侧,所述通孔在所述衬底上的正投影与所述色阻层在所述衬底上的正投影无交叠。
- 根据权利要求1所述的显示基板,其中,在所述第三电极层背离所述衬底的一侧层叠设置有第三钝化层和公共电极层,所述第三钝化层靠近所述衬底设置,其中,所述公共电极层包括多个条状电极,所述公共电极层的材料为金属。
- 根据权利要求1所述的显示基板,其中,在所述第一平坦层背离所述衬底的一侧还设置有隔离柱,所述隔离柱与所述第二平坦层同步形成。
- 一种显示装置,其中,包括权利要求1至27任一项所述的显示基板。
- 一种显示基板的制备方法,其中,所述制备方法包括:提供衬底;在所述衬底的一侧形成第一电极层,所述第一电极层包括第一电极图案;在所述第一电极层背离所述衬底的一侧依次形成第一平坦层,所述第一平坦层上设置有通孔,所述通孔贯穿所述第一平坦层,以使所述第一电极图案裸露;在所述第一平坦层背离所述衬底的一侧依次形成第二电极层、第二平坦层以及第三电极层,其中,所述第二电极层在所述衬底上的正投影覆盖所述通孔在所述底上的正投影,所述第二电极层用于连接所述第一电极图案以及所述第三电极层,所述第二平坦层用于平坦化所述通孔。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/765,769 US20240103328A1 (en) | 2021-06-29 | 2021-06-29 | Displaying base plate and manufacturing method thereof, and displaying device |
PCT/CN2021/103218 WO2023272505A1 (zh) | 2021-06-29 | 2021-06-29 | 显示基板及其制备方法、显示装置 |
CN202180001747.7A CN115735156A (zh) | 2021-06-29 | 2021-06-29 | 显示基板及其制备方法、显示装置 |
EP21947462.4A EP4270105A4 (en) | 2021-06-29 | 2021-06-29 | DISPLAY SUBSTRATE AND PRODUCTION METHOD THEREOF AND DISPLAY DEVICE |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/CN2021/103218 WO2023272505A1 (zh) | 2021-06-29 | 2021-06-29 | 显示基板及其制备方法、显示装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2023272505A1 true WO2023272505A1 (zh) | 2023-01-05 |
Family
ID=84689830
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CN2021/103218 WO2023272505A1 (zh) | 2021-06-29 | 2021-06-29 | 显示基板及其制备方法、显示装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20240103328A1 (zh) |
EP (1) | EP4270105A4 (zh) |
CN (1) | CN115735156A (zh) |
WO (1) | WO2023272505A1 (zh) |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1405610A (zh) * | 2001-09-20 | 2003-03-26 | 精工爱普生株式会社 | 电光装置及其制造方法 |
CN1641450A (zh) * | 2004-01-17 | 2005-07-20 | 统宝光电股份有限公司 | 液晶显示器及其制作方法及其晶体管数组基板及制作方法 |
US20060012742A1 (en) * | 2004-07-16 | 2006-01-19 | Yaw-Ming Tsai | Driving device for active matrix organic light emitting diode display and manufacturing method thereof |
CN101009333A (zh) * | 2006-01-25 | 2007-08-01 | 爱普生映象元器件有限公司 | 半导体装置 |
CN102778797A (zh) * | 2012-08-07 | 2012-11-14 | 深圳市华星光电技术有限公司 | 一种阵列基板及液晶显示面板 |
CN105575978A (zh) * | 2016-02-25 | 2016-05-11 | 昆山龙腾光电有限公司 | 薄膜晶体管阵列基板及其制造方法以及液晶显示装置 |
CN105576036A (zh) * | 2016-01-04 | 2016-05-11 | 京东方科技集团股份有限公司 | 薄膜晶体管和像素结构及制备方法、阵列基板、显示装置 |
CN111381411A (zh) * | 2020-04-30 | 2020-07-07 | 厦门天马微电子有限公司 | 阵列基板、显示面板和显示装置 |
CN112965310A (zh) * | 2021-02-26 | 2021-06-15 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示面板 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4285158B2 (ja) * | 2003-08-29 | 2009-06-24 | セイコーエプソン株式会社 | 電気光学装置及び電子機器 |
KR100614332B1 (ko) * | 2004-03-30 | 2006-08-18 | 엘지.필립스 엘시디 주식회사 | 액정표시장치 및 그 제조방법 |
WO2010032386A1 (ja) * | 2008-09-17 | 2010-03-25 | シャープ株式会社 | 半導体装置 |
CN104965365A (zh) * | 2015-07-14 | 2015-10-07 | 深圳市华星光电技术有限公司 | 液晶显示面板及其阵列基板 |
WO2018180617A1 (ja) * | 2017-03-27 | 2018-10-04 | シャープ株式会社 | アクティブマトリクス基板、液晶表示装置および有機el表示装置 |
CN208013633U (zh) * | 2018-04-19 | 2018-10-26 | 合肥鑫晟光电科技有限公司 | 显示基板和显示装置 |
CN111665668B (zh) * | 2019-03-08 | 2023-07-07 | 夏普株式会社 | 显示装置 |
-
2021
- 2021-06-29 CN CN202180001747.7A patent/CN115735156A/zh active Pending
- 2021-06-29 EP EP21947462.4A patent/EP4270105A4/en active Pending
- 2021-06-29 WO PCT/CN2021/103218 patent/WO2023272505A1/zh active Application Filing
- 2021-06-29 US US17/765,769 patent/US20240103328A1/en active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1405610A (zh) * | 2001-09-20 | 2003-03-26 | 精工爱普生株式会社 | 电光装置及其制造方法 |
CN1641450A (zh) * | 2004-01-17 | 2005-07-20 | 统宝光电股份有限公司 | 液晶显示器及其制作方法及其晶体管数组基板及制作方法 |
US20060012742A1 (en) * | 2004-07-16 | 2006-01-19 | Yaw-Ming Tsai | Driving device for active matrix organic light emitting diode display and manufacturing method thereof |
CN101009333A (zh) * | 2006-01-25 | 2007-08-01 | 爱普生映象元器件有限公司 | 半导体装置 |
CN102778797A (zh) * | 2012-08-07 | 2012-11-14 | 深圳市华星光电技术有限公司 | 一种阵列基板及液晶显示面板 |
CN105576036A (zh) * | 2016-01-04 | 2016-05-11 | 京东方科技集团股份有限公司 | 薄膜晶体管和像素结构及制备方法、阵列基板、显示装置 |
CN105575978A (zh) * | 2016-02-25 | 2016-05-11 | 昆山龙腾光电有限公司 | 薄膜晶体管阵列基板及其制造方法以及液晶显示装置 |
CN111381411A (zh) * | 2020-04-30 | 2020-07-07 | 厦门天马微电子有限公司 | 阵列基板、显示面板和显示装置 |
CN112965310A (zh) * | 2021-02-26 | 2021-06-15 | 京东方科技集团股份有限公司 | 一种阵列基板及其制作方法、显示面板 |
Non-Patent Citations (1)
Title |
---|
See also references of EP4270105A4 * |
Also Published As
Publication number | Publication date |
---|---|
EP4270105A1 (en) | 2023-11-01 |
EP4270105A4 (en) | 2024-02-28 |
US20240103328A1 (en) | 2024-03-28 |
CN115735156A (zh) | 2023-03-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11199750B2 (en) | Display panel having black matrix comprising extension portions | |
US8692756B2 (en) | Liquid crystal display device and method for manufacturing same | |
WO2014190727A1 (zh) | 阵列基板及其制造方法、显示装置 | |
CN103904086A (zh) | 一种薄膜晶体管阵列基板 | |
EP2991121B1 (en) | Array substrate, method for manufacturing array substrate and display device | |
CN112965310B (zh) | 一种阵列基板及其制作方法、显示面板 | |
CN104576747A (zh) | 薄膜晶体管、具有其的显示面板及其制造方法 | |
CN102929060B (zh) | 阵列基板及其制作方法、显示装置 | |
US10381384B2 (en) | Array substrate, method for manufacturing array substrate, display panel and display device | |
US9791755B2 (en) | Color filter-on-array substrate, display device, and method for manufacturing the color filter-on-array substrate | |
CN104007574A (zh) | 一种阵列基板、显示装置及其制造方法 | |
TW201518827A (zh) | 顯示面板及包含該顯示面板的顯示裝置 | |
US10782580B2 (en) | Array substrate, liquid crystal display device having the same, and method for manufacturing array substrate | |
CN103137555B (zh) | 薄膜晶体管液晶显示器件及其制造方法 | |
WO2017143660A1 (zh) | 阵列基板、显示面板以及液晶显示装置 | |
WO2023272503A1 (zh) | 薄膜晶体管及其制备方法、显示基板、显示装置 | |
CN113690256B (zh) | 显示基板及其制备方法、显示装置 | |
WO2023272505A1 (zh) | 显示基板及其制备方法、显示装置 | |
CN113985662B (zh) | 显示面板、阵列基板及其制造方法 | |
WO2023272504A1 (zh) | 显示基板及其制备方法、显示装置 | |
TW201608314A (zh) | 畫素結構及其製造方法 | |
JP2008040123A (ja) | 液晶表示装置 | |
US20240178234A1 (en) | Display panel and method for fabricating same | |
WO2023184426A1 (zh) | 阵列基板、显示面板及显示装置 | |
CN116224666A (zh) | 阵列基板及其制备方法、显示面板和显示装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 17765769 Country of ref document: US |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 21947462 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2023546317 Country of ref document: JP Kind code of ref document: A |
|
ENP | Entry into the national phase |
Ref document number: 2021947462 Country of ref document: EP Effective date: 20230728 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |