WO2017117827A1 - 液晶显示面板、tft基板及其制造方法 - Google Patents

液晶显示面板、tft基板及其制造方法 Download PDF

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Publication number
WO2017117827A1
WO2017117827A1 PCT/CN2016/072549 CN2016072549W WO2017117827A1 WO 2017117827 A1 WO2017117827 A1 WO 2017117827A1 CN 2016072549 W CN2016072549 W CN 2016072549W WO 2017117827 A1 WO2017117827 A1 WO 2017117827A1
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Prior art keywords
layer
disposed
tft substrate
common electrode
liquid crystal
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PCT/CN2016/072549
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English (en)
French (fr)
Inventor
郝思坤
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深圳市华星光电技术有限公司
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Priority to US14/914,260 priority Critical patent/US20180039143A1/en
Publication of WO2017117827A1 publication Critical patent/WO2017117827A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133345—Insulating layers
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H01L23/5223—Capacitor integral with wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134318—Electrodes characterised by their geometrical arrangement having a patterned common electrode
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/121—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode common or background

Definitions

  • the present invention relates to the field of liquid crystal technology, and in particular to a liquid crystal display panel, a TFT substrate, and a method of fabricating the same.
  • the liquid crystal display panel is currently the most widely used flat panel display panel, and it has gradually become widely used in various electronic devices such as mobile phones, personal digital assistants (PDAs), digital cameras, computer screens or notebook screens, and has high resolution. Rate display panel for color screens.
  • PDAs personal digital assistants
  • Rate display panel for color screens With the development of liquid crystal display panel technology, people have put forward higher requirements on the display quality, design, low cost and high transmittance of liquid crystal display panels.
  • the IPS (Plane Control) mode LCD panel allows the observer to see only the short axis of the liquid crystal molecules at any time, so the images viewed at various angles are not much different, which improves the IPS perfectly.
  • the angle of view of the mode of the liquid crystal display panel in the internal structure of the IPS mode liquid crystal display panel of the prior art, the ITO layer includes a pixel electrode layer 128 and a common electrode layer 129, and the pixel electrode layer 128 and the common electrode layer 129 are both disposed on the resin. On the layer, this causes a small capacity of the storage capacitor, and therefore requires a large breakdown voltage to break down, thereby affecting the picture quality of the IPS mode liquid crystal display panel.
  • the commonly used method is to additionally increase the capacity of the storage capacitor, but this will cause the aperture ratio to decrease, so that the transmittance of the IPS mode liquid crystal display panel becomes lower, which also affects the IPS mode.
  • the picture quality of the LCD panel is to additionally increase the capacity of the storage capacitor, but this will cause the aperture ratio to decrease, so that the transmittance of the IPS mode liquid crystal display panel becomes lower, which also affects the IPS mode.
  • the technical problem to be solved by the present invention is to provide a liquid crystal display panel, a TFT substrate, and a method of manufacturing the same, which can avoid the problem that the aperture ratio is lowered due to an increase in the capacity of the storage capacitor.
  • a technical solution adopted by the present invention is to provide a method for manufacturing a TFT substrate, the method comprising: forming a first metal layer on a substrate layer; forming a first insulating layer on the first metal layer; Forming a semiconductor active layer on the first insulating layer; forming a second metal layer, wherein the second metal layer comprises a drain and a source disposed on the semiconductor active layer and a first common electrode layer disposed on the first insulating layer; Forming a second insulating layer on the second metal layer; forming a resin layer on the second insulating layer; forming an ITO layer on the resin layer, wherein the ITO layer includes a second common electrode layer; wherein, the first common electrode layer and the first The two common electrode layers are respectively disposed corresponding to the light-transmitting regions of the TFT substrate.
  • the method further includes: providing a recess on the resin layer exposing the second insulating layer, wherein the recess is disposed corresponding to the light transmissive area of the TFT substrate.
  • the second common electrode layer disposed on the light transmitting region of the TFT substrate is disposed on the recess.
  • the ITO layer further includes a pixel electrode layer disposed on the non-transparent region of the TFT substrate.
  • the method further includes: providing a via hole exposing the second metal layer on the resin layer, wherein the via hole is disposed corresponding to the non-transmissive region of the TFT substrate, and the pixel electrode layer is disposed on the via hole.
  • a TFT substrate including a substrate layer, a first metal layer disposed on the substrate layer, and a first layer disposed on the first metal layer.
  • the layer and the second common electrode layer are respectively disposed corresponding to the light-transmitting regions of the TFT substrate.
  • the resin layer is provided with a recess for exposing the second insulating layer, the recess is disposed corresponding to the light-transmitting region of the TFT substrate, and the second common electrode layer disposed at the light-transmitting region of the TFT substrate is disposed on the recess.
  • the ITO layer further includes a pixel electrode layer disposed on the non-transparent region of the TFT substrate.
  • the resin layer is provided with a via hole exposing the second metal layer, wherein the via hole is disposed corresponding to the non-transmissive region of the TFT substrate, and the pixel electrode layer is disposed on the via hole.
  • the resin layer is a flat passivation layer.
  • the depth of the groove is proportional to the capacity value of the storage capacitor.
  • a liquid crystal display panel including a TFT substrate, the TFT substrate including a substrate layer, a first metal layer disposed on the substrate layer, and disposed on a first insulating layer on the first metal layer, a semiconductor active layer disposed on the first insulating layer, a second metal layer, a second insulating layer disposed on the second metal layer, and a resin disposed on the second insulating layer a layer and an ITO layer disposed on the resin layer, wherein the second metal layer includes a drain and a source disposed on the semiconductor active layer and a first common electrode layer disposed on the first insulating layer,
  • the ITO layer includes a second common electrode layer, and the first common electrode layer and the second common electrode layer are respectively disposed corresponding to the light-transmitting regions of the TFT substrate.
  • the resin layer is provided with a recess for exposing the second insulating layer, the recess is disposed corresponding to the light-transmitting region of the TFT substrate, and the second common electrode layer disposed at the light-transmitting region of the TFT substrate is disposed on the recess.
  • the ITO layer further includes a pixel electrode layer disposed on the non-transparent region of the TFT substrate.
  • the resin layer is provided with a via hole exposing the second metal layer, wherein the via hole is disposed corresponding to the non-transmissive region of the TFT substrate, and the pixel electrode layer is disposed on the via hole.
  • the resin layer is a flat passivation layer.
  • the depth of the groove is proportional to the capacity value of the storage capacitor.
  • the liquid crystal display panel is an IPS mode liquid crystal display panel.
  • the manufacturing method of the TFT substrate of the present invention comprises: forming a first metal layer on the substrate layer; forming a first insulating layer on the first metal layer; Forming a semiconductor active layer on the layer; forming a second metal layer, wherein the second metal layer comprises a drain and a source disposed on the semiconductor active layer and a first common electrode layer disposed on the first insulating layer; Forming a second insulating layer on the metal layer; forming a resin layer on the second insulating layer; forming an ITO layer on the resin layer, wherein the ITO layer includes a second common electrode layer; wherein, the first common electrode layer and the second common electrode
  • the layers are respectively disposed corresponding to the light-transmitting regions of the TFT substrate.
  • the present invention can increase the capacity of the storage capacitor, avoid the problem of a decrease in the aperture ratio caused by increasing the capacity of the storage capacitor, and can increase the transmittance of the liquid crystal display panel, thereby effectively improving the liquid crystal display panel. Picture quality.
  • FIG. 1 is a schematic structural view of a prior art liquid crystal display panel
  • FIG. 2 is a schematic structural view of a liquid crystal display panel of the present invention.
  • FIG. 3 is a flow chart showing a method of manufacturing a TFT substrate of the present invention.
  • the present invention discloses a display device including a liquid crystal display panel, wherein the liquid crystal display panel is preferably an IPS mode liquid crystal display panel.
  • the liquid crystal display panel may be a liquid crystal display panel with a new liquid crystal alignment mode adopted by the first generation IPS technology for the defect of the TN mode, which can achieve a better viewing angle; the liquid crystal display panel can also be adopted.
  • the second-generation IPS technology (S-IPS or Super-IPS) adopts a chevron-shaped electrode to introduce a dual-domain mode liquid crystal display panel, which can improve the gray-scale reversal phenomenon of the liquid crystal display panel at certain specific angles; the liquid crystal display panel also Third-generation IPS technology (AS-IPS or Advanced) Super-IPS) liquid crystal display panel, which can increase the aperture ratio and obtain higher brightness by reducing the distance between liquid crystal molecules.
  • AS-IPS or Advanced Third-generation IPS technology
  • FIG. 2 is a schematic structural view of a liquid crystal display panel of the present invention.
  • the liquid crystal display panel includes a first substrate 21 and a second substrate 22 which are spaced apart from each other, and a liquid crystal layer 23 disposed between the first substrate 21 and the second substrate 22.
  • the first substrate 21 is a CF substrate (color filter array substrate)
  • the second substrate 22 is a TFT substrate (thin film transistor array substrate).
  • the TFT substrate includes a substrate layer 221, a first metal layer 222, a first insulating layer 223, a semiconductor active layer 224, a second metal layer 225, a second insulating layer 226, a resin layer 227, and an ITO (conductive glass) layer (228, 229). ).
  • the first metal layer 222 is disposed on the substrate layer 221, the first insulating layer 223 is disposed on the first metal layer 222, the semiconductor active layer 224 is disposed on the first insulating layer 223, and the second metal 225 is respectively disposed on the semiconductor active layer On the 224 and first insulating layer 223, the second insulating layer 226 is disposed on the second metal layer 225, the resin layer 227 is disposed on the second insulating layer 226, and the ITO layer 257 is disposed on the resin layer 226.
  • the second metal layer 225 includes a source 2251, a drain 2252, and a first common electrode layer 2253.
  • the source 2251 and the drain 2252 are respectively disposed on the semiconductor active layer 224, and the first common electrode layer 2253 is disposed on the first insulating layer 223.
  • the first common electrode layer 2253 is disposed corresponding to the light-transmitting area A-A of the TFT substrate.
  • the resin layer 227 is provided with a recess 2271 exposing the second insulating layer 226 and a via 2272 provided with the exposed second metal layer 225.
  • the groove 2271 is disposed corresponding to the light-transmitting area A-A of the TFT substrate, that is, the groove 2271 is disposed at a position corresponding to the light-transmitting area A-A of the liquid crystal display panel.
  • the via 2272 is provided corresponding to the non-transmissive region of the TFT substrate.
  • the resin layer 227 is a flat passivation layer, that is, a polytetrafluoroethylene layer.
  • the ITO layer (228, 229) includes a pixel electrode layer 228 and a second common electrode layer 229.
  • the second common electrode layer 229 is disposed corresponding to the light-transmitting region A-A of the TFT substrate.
  • the pixel electrode layer 228 is disposed in the non-transmissive region of the TFT substrate; the second common electrode layer 229 is partially disposed in the light transmissive region of the TFT substrate, and the second common electrode layer 229 is partially disposed in the non-transparent region of the TFT substrate.
  • the second common electrode layer 229 disposed on the light-transmitting region A-A of the TFT substrate is disposed on the recess 2270, and the pixel electrode layer 229 is disposed on the via 2272.
  • the first common electrode layer 2253 is provided with a plurality of spacers 223 disposed on the first insulating layer 223 corresponding to the transparent region AA, and the second common electrode layer 229 is also disposed at a plurality of intervals.
  • the area AA corresponds to the second insulating layer 226.
  • the first common electrode layer 2253 and the second common electrode layer 229 are disposed in one-to-one correspondence.
  • the first common electrode layer 2253 is disposed correspondingly to the second common electrode layer 229.
  • the present invention is not limited to expose the second insulating layer 226 through the recess 2271.
  • the recess 2271 may not pass through the resin layer 227, and the depth of the recess 2271 may be set according to actual needs, as long as The groove 2271 can satisfy the reduction of the distance between the first common electrode layer 2253 and the second common electrode layer 229.
  • the depth of the groove 2271 is related to the capacity value of the storage capacitor of the liquid crystal display panel, that is, the depth of the groove 2271 is proportional to the capacity value of the storage capacitor, that is, the deeper the depth of the groove 2271, the first common
  • the capacity value of the storage capacitor formed by the electrode layer 2253 and the second common electrode layer 229 the larger the capacity value of the storage capacitor of the liquid crystal display panel.
  • a new first common electrode layer 2253 is formed by the second metal layer 225, and a new storage capacitor is formed with the second common electrode layer 229 of the original ITO layer.
  • the present invention can increase the liquid crystal display panel. The capacity of the storage capacitor.
  • the recess 2271 is formed by digging holes in the light-transmissive area AA corresponding to the resin layer 227, and the second common electrode layer 229 is disposed on the recess 2271, thereby reducing the first common electrode layer 2253 and The distance between the second common electrode layers 229 further increases the capacity of the storage capacitor, while the thickness of the non-transmissive region corresponding to the resin layer 227 remains unchanged, and does not affect the capacity of the parasitic capacitance of the liquid crystal display panel.
  • FIG. 3 is a schematic flow chart of a method of manufacturing a TFT substrate of the present invention. The method includes the following steps:
  • Step S101 forming a first metal layer 222 on the substrate layer 221.
  • Step S102 forming a first insulating layer 223 on the first metal layer 222.
  • Step S103 forming a semiconductor active layer 224 on the first insulating layer 223.
  • Step S104 forming a second metal layer 225, wherein the second metal layer 225 includes a drain 2252 and a source 2251 disposed on the semiconductor active layer 224 and a first common electrode layer 2253 disposed on the first insulating layer 223.
  • step S104 when the second metal layer 225 is formed to form the drain 2252 and the source 2251, the second metal layer 225 is also required to form the first common electrode layer 2253. Forming the drain 2252, the source 2251, and the first common electrode layer 2253 by the step of forming the second metal layer 225 can save manufacturing costs.
  • Step S105 forming a second insulating layer 226 on the second metal layer 225.
  • Step S106 A resin layer 227 is formed on the second insulating layer 226.
  • step S106 a step of providing the recess 2271 exposing the second insulating layer 226 on the resin layer 227 is further included.
  • the recess 2251 is disposed corresponding to the light-transmitting area A-A of the TFT substrate. It should be understood that the present invention is not limited to expose the second insulating layer 226 through the recess 2271.
  • the recess 2271 may not pass through the resin layer 227, and the depth of the recess 2271 may be set according to actual needs, as long as The groove 2271 can satisfy the reduction of the distance between the first common electrode layer 2253 and the second common electrode layer 229.
  • the depth of the groove 2271 is related to the capacity value of the storage capacitor of the liquid crystal display panel, that is, the depth of the groove 2271 is proportional to the capacity value of the storage capacitor, that is, the deeper the depth of the groove 2271, the first common
  • the capacity value of the storage capacitor formed by the electrode layer 2253 and the second common electrode layer 229 the larger the capacity value of the storage capacitor of the liquid crystal display panel.
  • step S106 a step of providing a via hole 2272 exposing the second metal layer 225 is further provided on the resin layer 227.
  • the via 2272 is disposed corresponding to the non-transparent area of the TFT substrate,
  • Step S107 An ITO layer (228, 229) is formed on the resin layer 227, wherein the ITO layer (228, 229) includes the second common electrode layer 229.
  • the second common electrode layer 226 disposed in the light-transmitting region A-A of the TFT substrate is disposed on the recess 2271. It should be understood that the second common electrode layer 229 is partially disposed in the light-transmitting region of the TFT substrate, and the second common electrode layer 229 is also partially disposed in the non-transmissive region of the TFT substrate.
  • the ITO layer (228, 229) further includes a pixel electrode layer 228 disposed on the non-transmissive region of the TFT substrate, and the pixel electrode layer 228 is disposed on the via 2272.
  • a new first common electrode layer 2253 is formed by the second metal layer 225, and a new storage capacitor is formed with the second common electrode layer 229 of the original ITO layer.
  • the present invention can increase the liquid crystal display panel. The capacity of the storage capacitor.
  • the recess 2271 is formed by digging holes in the light-transmissive area AA corresponding to the resin layer 227, and the second common electrode layer 229 is disposed on the recess 2271, thereby reducing the first common electrode layer 2253 and The distance between the second common electrode layers 229 further increases the capacity of the storage capacitor, while the thickness of the non-transmissive region corresponding to the resin layer 227 remains unchanged, and does not affect the capacity of the parasitic capacitance of the liquid crystal display panel.
  • the method for fabricating a TFT substrate of the present invention includes: forming a first metal layer on a substrate layer; forming a first insulating layer on the first metal layer; forming a semiconductor active layer on the first insulating layer; forming a second metal layer
  • the second metal layer includes a drain and a source disposed on the semiconductor active layer and a first common electrode layer disposed on the first insulating layer; a second insulating layer formed on the second metal layer;
  • a resin layer is formed on the insulating layer; an ITO layer is formed on the resin layer, wherein the ITO layer includes a second common electrode layer; wherein the first common electrode layer and the second common electrode layer are respectively disposed corresponding to the light-transmitting regions of the TFT substrate.
  • the present invention can increase the capacity of the storage capacitor, avoid the problem of a decrease in the aperture ratio caused by increasing the capacity of the storage capacitor, and can increase the transmittance of the liquid crystal display panel, thereby effectively improving the liquid crystal display panel. Picture quality.

Abstract

一种TFT基板的制造方法，包括：在衬底层形成第一金属层（S101）；在第一金属层上形成第一绝缘层（S102）；在第一绝缘层上形成半导体活性层（S103）；形成第二金属层，其中，第二金属层包括第一公共电极层（S104）；在第二金属层上形成第二绝缘层（S105）；在第二绝缘层上形成树脂层（S106）；在树脂层上形成ITO层，其中，ITO层包括第二公共电极层（S107）；第一公共电极层和第二公共电极层分别与TFT基板的透光区域对应设置。通过上述方式，能够增大存储电容的容量，避免因增加存储电容的容量而造成的开口率下降的问题发生。

Description

液晶显示面板、TFT基板及其制造方法
【技术领域】
本发明涉及液晶技术领域，特别是涉及一种液晶显示面板、TFT基板及其制造方法。
【背景技术】
液晶显示面板是目前使用最广泛的一种平板显示面板，其已经逐渐成为各种电子设备如移动电话、个人数字助理(PDA)、数字相机、计算机屏幕或笔记本电脑屏幕所广泛应用且具有高分辨率彩色屏幕的显示面板。随着液晶显示面板技术的发展进步，人们对液晶显示面板的显示品质、外观设计、低成本和高穿透率等提出了更高的要求。
IPS（平面控制）模式的液晶显示面板让观察者任何时候都只能看到液晶分子的短轴，因此在各个角度上观看的画面都不会有太大差别，这样就比较完美地改善了IPS模式的液晶显示面板的视角。然而，如图1所示，现有技术中的IPS模式的液晶显示面板的内部结构中，ITO层包括像素电极层128和公共电极层129，像素电极层128和公共电极层129均设置在树脂层上，这样会造成存储电容的容量小，因此需要较大的击穿电压来击穿，从而影响IPS模式的液晶显示面板的画面品质。而为了保证IPS模式的液晶显示面板的画面品质，常用的方法是额外增加存储电容的容量，但是这样会导致开口率下降，使得IPS模式的液晶显示面板的穿透率变低，同样影响IPS模式的液晶显示面板的画面品质。
综上所述，有必要提供一种液晶显示面板、TFT基板及其制造方法以解决上述问题。
【发明内容】
本发明主要解决的技术问题是提供一种液晶显示面板、TFT基板及其制造方法，能够避免因增加存储电容的容量而造成的开口率下降的问题发生。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种TFT基板的制造方法，该方法包括：在衬底层形成第一金属层；在第一金属层上形成第一绝缘层；在第一绝缘层上形成半导体活性层；形成第二金属层，其中，第二金属层包括设置在半导体活性层上的漏极和源极以及设置在第一绝缘层上的第一公共电极层； 在第二金属层上形成第二绝缘层；在第二绝缘层上形成树脂层；在树脂层上形成ITO层，其中，ITO层包括第二公共电极层；其中，第一公共电极层和第二公共电极层分别与TFT基板的透光区域对应设置。
其中，该方法还包括：在树脂层上设置有露出第二绝缘层的凹槽，其中，凹槽与TFT基板的透光区域对应设置。
其中，设置在TFT基板的透光区域的第二公共电极层设置在凹槽上。
其中，ITO层还包括像素电极层，像素电极层设置在TFT基板的非透光区域。
其中，该方法还包括：在树脂层上设置有露出第二金属层的过孔，其中，过孔与TFT基板的非透光区域对应设置，像素电极层设置在过孔上。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种TFT基板，该TFT基板包括衬底层、设置在衬底层上的第一金属层、设置在第一金属层上的第一绝缘层、设置在第一绝缘层上的半导体活性层、第二金属层、设置在第二金属层上的第二绝缘层、设置在第二绝缘层上的树脂层以及设置在树脂层上的ITO层，其中，第二金属层包括设置在半导体活性层上的漏极和源极以及设置在第一绝缘层上的第一公共电极层，ITO层包括第二公共电极层，第一公共电极层和第二公共电极层分别与TFT基板的透光区域对应设置。
其中，树脂层设置有露出第二绝缘层的凹槽，凹槽与TFT基板的透光区域对应设置，设置在TFT基板的透光区域的第二公共电极层设置在凹槽上。
其中，ITO层还包括像素电极层，像素电极层设置在TFT基板的非透光区域。
其中，树脂层上设置有露出第二金属层的过孔，其中，过孔与TFT基板的非透光区域对应设置，像素电极层设置在过孔上。
其中，树脂层为平坦钝化层。
其中，凹槽的深度与存储电容的容量值成正比例关系。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种液晶显示面板，该液晶显示面板包括TFT基板，TFT基板包括衬底层、设置在衬底层上的第一金属层、设置在第一金属层上的第一绝缘层、设置在第一绝缘层上的半导体活性层、第二金属层、设置在第二金属层上的第二绝缘层、设置在第二绝缘层上的树脂层以及设置在树脂层上的ITO层，其中，第二金属层包括设置在半导体活性层上的漏极和源极以及设置在第一绝缘层上的第一公共电极层， ITO层包括第二公共电极层，第一公共电极层和第二公共电极层分别与TFT基板的透光区域对应设置。
其中，树脂层设置有露出第二绝缘层的凹槽，凹槽与TFT基板的透光区域对应设置，设置在TFT基板的透光区域的第二公共电极层设置在凹槽上。
其中，ITO层还包括像素电极层，像素电极层设置在TFT基板的非透光区域。
其中，树脂层上设置有露出第二金属层的过孔，其中，过孔与TFT基板的非透光区域对应设置，像素电极层设置在过孔上。
其中，树脂层为平坦钝化层。
其中，凹槽的深度与存储电容的容量值成正比例关系。
其中，液晶显示面板为IPS模式液晶显示面板。
本发明的有益效果是：区别于现有技术的情况，本发明的TFT基板的制造方法包括：在衬底层形成第一金属层；在第一金属层上形成第一绝缘层；在第一绝缘层上形成半导体活性层；形成第二金属层，其中，第二金属层包括设置在半导体活性层上的漏极和源极以及设置在第一绝缘层上的第一公共电极层；在第二金属层上形成第二绝缘层；在第二绝缘层上形成树脂层；在树脂层上形成ITO层，其中，ITO层包括第二公共电极层；其中，第一公共电极层和第二公共电极层分别与TFT基板的透光区域对应设置。通过上述方式，本发明能够增大存储电容的容量，避免因增加存储电容的容量而造成的开口率下降的问题发生，同时能够使得液晶显示面板的穿透率变大，有效提升液晶显示面板的画面品质。
【附图说明】
图1是现有技术液晶显示面板的结构示意图；
图2是本发明液晶显示面板的结构示意图；
图3是本发明TFT基板的制造方法的流程示意图。
【具体实施方式】
下面结合附图和实施方式对本发明进行详细说明。
本发明公开一种显示装置，该显示装置包括液晶显示面板，其中，液晶显示面板优选为IPS模式液晶显示面板。具体地，该液晶显示面板可以是采用第一代IPS技术针对TN模式的弊病提出了全新的液晶排列方式的液晶显示面板，其可以实现较好的可视角度；该液晶显示面板也可以是采用第二代IPS技术（S-IPS即Super-IPS）采用人字形电极，引入双畴模式的液晶显示面板，其可以改善液晶显示面板在某些特定角度的灰阶逆转现象；该液晶显示面板还可以采用第三代IPS技术（AS-IPS即Advanced Super-IPS）的液晶显示面板，其通过减小液晶分子间距离，从而可以提高开口率，获得更高亮度。
如图2所示，图2是本发明液晶显示面板的结构示意图。该液晶显示面板包括间隔设置的第一基板21和第二基板22以及设置在第一基板21和第二基板22之间的液晶层23。在本实施例中，第一基板21为CF基板（彩色滤光阵列基板），第二基板22为TFT基板（薄膜晶体管阵列基板）。
TFT基板包括衬底层221、第一金属层222、第一绝缘层223、半导体活性层224、第二金属层225、第二绝缘层226、树脂层227和ITO（导电玻璃）层（228、229）。第一金属层222设置在衬底层221上，第一绝缘层223设置在第一金属层222上，半导体活性层224设置在第一绝缘层223上的，第二金属225分别设置在半导体活性层224和第一绝缘层223上，第二绝缘层226设置在第二金属层225上，树脂层227设置在第二绝缘层226上，ITO层257设置在树脂层226上。
其中，第二金属层225包括源极2251、漏极2252和第一公共电极层2253。源极2251和漏极2252分别设置在半导体活性层224上，第一公共电极层2253设置在第一绝缘层223上。在本实施例中，第一公共电极层2253与TFT基板的透光区域A-A对应设置。
树脂层227设置有露出第二绝缘层226的凹槽2271和设置有露出第二金属层225的过孔2272。凹槽2271与TFT基板的透光区域A-A对应设置，即凹槽2271设置液晶显示面板的透光区域A-A对应的位置。过孔2272与TFT基板的非透光区域对应设置。具体地，树脂层227为平坦钝化层，即聚四氟乙烯层。
ITO层（228、229）包括像素电极层228和第二公共电极层229。在本实施例中，第二公共电极层229与TFT基板的透光区域A-A对应设置。具体地，像素电极层228设置在TFT基板的非透光区域；第二公共电极层229部分设置在TFT基板的透光区域，第二公共电极层229部分设置在TFT基板的非透光区域。优选地，设置在TFT基板的透光区域A-A的第二公共电极层229设置在凹槽2270上，像素电极层229设置在过孔2272上。
在本实施例中，第一公共电极层2253设有多个，间隔设置在透光区域A-A对应的第一绝缘层223上，第二公共电极层229也设有多个，间隔设置在透光区域A-A对应的第二绝缘层226上。其中，第一公共电极层2253与第二公共电极层229是一一对应设置的。当然，在一些实施例中，第一公共电极层2253与第二公共电极层229交叉对应设置。
应理解，本发明并不限定通过凹槽2271露出第二绝缘层226，在一些实施例中，凹槽2271可以不穿过树脂层227，凹槽2271的深度可以根据实际需要而设定，只要凹槽2271能够满足降低第一公共电极层2253与第二公共电极层229之间的距离即可。值得注意的是，凹槽2271的深度跟液晶显示面板的存储电容的容量值有关，即凹槽2271的深度与存储电容的容量值成正比例关系，即凹槽2271的深度越深，第一公共电极层2253与第二公共电极层229形成的存储电容的容量值越大，使得液晶显示面板的存储电容的容量值越大。
本实施例通过第二金属层225形成新的第一公共电极层2253，与原ITO层的第二公共电极层229形成新的存储电容，相比现有技术，本发明能够增加液晶显示面板的存储电容的容量。进一步地，本实施例通过在树脂层227所对应的透光区域A-A上挖孔形成凹槽2271，且第二公共电极层229设置在凹槽2271上，从而降低了第一公共电极层2253与第二公共电极层229之间的距离，进一步加大了存储电容的容量，同时树脂层227所对应的非透光区域的厚度保持不变，不影响液晶显示面板的寄生电容的容量。
如图3所示，图3是本发明TFT基板的制造方法的流程示意图。该方法包括以下步骤：
步骤S101：在衬底层221形成第一金属层222。
步骤S102：在第一金属层222上形成第一绝缘层223。
步骤S103：在第一绝缘层223上形成半导体活性层224。
步骤S104：形成第二金属层225，其中，第二金属层225包括设置在半导体活性层224上的漏极2252和源极2251以及设置在第一绝缘层223上的第一公共电极层2253。
应理解，在步骤S104中，在形成第二金属层225时，需要将第二金属层225形成漏极2252和源极2251时，还需要将第二金属层225形成第一公共电极层2253，通过形成第二金属层225的步骤形成具有漏极2252、源极2251和第一公共电极层2253，能够节省制造成本。
步骤S105：在第二金属层225上形成第二绝缘层226。
步骤S106：在第二绝缘层226上形成树脂层227。
在步骤S106中，还包括在树脂层227上设置有露出第二绝缘层226的凹槽2271的步骤。其中，凹槽2251与TFT基板的透光区域A-A对应设置。应理解，本发明并不限定通过凹槽2271露出第二绝缘层226，在一些实施例中，凹槽2271可以不穿过树脂层227，凹槽2271的深度可以根据实际需要而设定，只要凹槽2271能够满足降低第一公共电极层2253与第二公共电极层229之间的距离即可。值得注意的是，凹槽2271的深度跟液晶显示面板的存储电容的容量值有关，即凹槽2271的深度与存储电容的容量值成正比例关系，即凹槽2271的深度越深，第一公共电极层2253与第二公共电极层229形成的存储电容的容量值越大，使得液晶显示面板的存储电容的容量值越大。
在步骤S106中，还包括在树脂层227上设置有露出第二金属层225的过孔2272的步骤。其中，过孔2272与TFT基板的非透光区域对应设置，
步骤S107：在树脂层227上形成ITO层（228、229），其中，ITO层（228、229）包括第二公共电极层229。
在本实施例中，设置在TFT基板的透光区域A-A的第二公共电极层226设置在凹槽2271上。应理解，第二公共电极层229是部分设置在TFT基板的透光区域的，第二公共电极层229还有部分是设置在TFT基板的非透光区域的。另外，ITO层（228、229）还包括像素电极层228，像素电极层228设置在TFT基板的非透光区域，像素电极层228设置在过孔2272上。
本实施例通过第二金属层225形成新的第一公共电极层2253，与原ITO层的第二公共电极层229形成新的存储电容，相比现有技术，本发明能够增加液晶显示面板的存储电容的容量。进一步地，本实施例通过在树脂层227所对应的透光区域A-A上挖孔形成凹槽2271，且第二公共电极层229设置在凹槽2271上，从而降低了第一公共电极层2253与第二公共电极层229之间的距离，进一步加大了存储电容的容量，同时树脂层227所对应的非透光区域的厚度保持不变，不影响液晶显示面板的寄生电容的容量。
综上，本发明的TFT基板的制造方法包括：在衬底层形成第一金属层；在第一金属层上形成第一绝缘层；在第一绝缘层上形成半导体活性层；形成第二金属层，其中，第二金属层包括设置在半导体活性层上的漏极和源极以及设置在第一绝缘层上的第一公共电极层；在第二金属层上形成第二绝缘层；在第二绝缘层上形成树脂层；在树脂层上形成ITO层，其中，ITO层包括第二公共电极层；其中，第一公共电极层和第二公共电极层分别与TFT基板的透光区域对应设置。通过上述方式，本发明能够增大存储电容的容量，避免因增加存储电容的容量而造成的开口率下降的问题发生，同时能够使得液晶显示面板的穿透率变大，有效提升液晶显示面板的画面品质。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (18)

  1. 一种TFT基板的制造方法，其中，所述方法包括：
    在衬底层形成第一金属层；
    在所述第一金属层上形成第一绝缘层；
    在所述第一绝缘层上形成半导体活性层；
    形成第二金属层，其中，所述第二金属层包括设置在所述半导体活性层上的漏极和源极以及设置在所述第一绝缘层上的第一公共电极层；
    在所述第二金属层上形成第二绝缘层；
    在所述第二绝缘层上形成树脂层；
    在所述树脂层上形成ITO层，其中，所述ITO层包括第二公共电极层；
    其中，所述第一公共电极层和所述第二公共电极层分别与所述TFT基板的透光区域对应设置。
  2. 根据权利要求1所述的方法，其中，所述方法还包括：
    在所述树脂层上设置有露出所述第二绝缘层的凹槽，其中，所述凹槽与所述TFT基板的透光区域对应设置。
  3. 根据权利要求2所述的方法，其中，设置在所述TFT基板的透光区域的所述第二公共电极层设置在所述凹槽上。
  4. 根据权利要求1所述的方法，其中，所述ITO层还包括像素电极层，所述像素电极层设置在所述TFT基板的非透光区域。
  5. 根据权利要求4所述的方法，其中，所述方法还包括：
    在所述树脂层上设置有露出所述第二金属层的过孔，其中，所述过孔与所述TFT基板的非透光区域对应设置，所述像素电极层设置在所述过孔上。
  6. 一种TFT基板，其中，所述TFT基板包括衬底层、设置在所述衬底层上的第一金属层、设置在所述第一金属层上的第一绝缘层、设置在所述第一绝缘层上的半导体活性层、第二金属层、设置在所述第二金属层上的第二绝缘层、设置在所述第二绝缘层上的树脂层以及设置在所述树脂层上的ITO层，其中，所述第二金属层包括设置在所述半导体活性层上的漏极和源极以及设置在所述第一绝缘层上的第一公共电极层，所述ITO层包括第二公共电极层，所述第一公共电极层和所述第二公共电极层分别与所述TFT基板的透光区域对应设置。
  7. 根据权利要求6所述的TFT基板，其中，所述树脂层设置有露出所述第二绝缘层的凹槽，所述凹槽与所述TFT基板的透光区域对应设置，设置在所述TFT基板的透光区域的所述第二公共电极层设置在所述凹槽上。
  8. 根据权利要求6所述的TFT基板，其中，所述ITO层还包括像素电极层，所述像素电极层设置在所述TFT基板的非透光区域。
  9. 根据权利要求8所述的TFT基板，其中，所述树脂层上设置有露出所述第二金属层的过孔，其中，所述过孔与所述TFT基板的非透光区域对应设置，所述像素电极层设置在所述过孔上。
  10. 根据权利要求6所述的TFT基板，其中，所述树脂层为平坦钝化层。
  11. 根据权利要求7所述的TFT基板，其中，所述凹槽的深度与存储电容的容量值成正比例关系。
  12. 一种液晶显示面板，其中，所述液晶显示面板包括TFT基板，所述TFT基板包括衬底层、设置在所述衬底层上的第一金属层、设置在所述第一金属层上的第一绝缘层、设置在所述第一绝缘层上的半导体活性层、第二金属层、设置在所述第二金属层上的第二绝缘层、设置在所述第二绝缘层上的树脂层以及设置在所述树脂层上的ITO层，其中，所述第二金属层包括设置在所述半导体活性层上的漏极和源极以及设置在所述第一绝缘层上的第一公共电极层，所述ITO层包括第二公共电极层，所述第一公共电极层和所述第二公共电极层分别与所述TFT基板的透光区域对应设置。
  13. 根据权利要求12所述的液晶显示面板，其中，所述树脂层设置有露出所述第二绝缘层的凹槽，所述凹槽与所述TFT基板的透光区域对应设置，设置在所述TFT基板的透光区域的所述第二公共电极层设置在所述凹槽上。
  14. 根据权利要求12所述的液晶显示面板，其中，所述ITO层还包括像素电极层，所述像素电极层设置在所述TFT基板的非透光区域。
  15. 根据权利要求14所述的液晶显示面板，其中，所述树脂层上设置有露出所述第二金属层的过孔，其中，所述过孔与所述TFT基板的非透光区域对应设置，所述像素电极层设置在所述过孔上。
  16. 根据权利要求12所述的液晶显示面板，其中，所述树脂层为平坦钝化层。
  17. 根据权利要求13所述的液晶显示面板，其中，所述凹槽的深度与存储电容的容量值成正比例关系。
  18. 根据权利要求12所述的液晶显示面板，其中，所述液晶显示面板为IPS模式液晶显示面板。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020244100A1 (zh) * 2019-06-04 2020-12-10 武汉华星光电半导体显示技术有限公司 一种显示器件及其制备方法

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107402487A (zh) * 2017-08-31 2017-11-28 武汉天马微电子有限公司 阵列基板及其制造方法、显示面板
CN107706199B (zh) * 2017-09-30 2020-05-05 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管阵列基板的制作方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101847641A (zh) * 2009-03-27 2010-09-29 京东方科技集团股份有限公司 阵列基板及其制造方法和宽视角液晶显示器
CN103066069A (zh) * 2011-10-20 2013-04-24 上海天马微电子有限公司 Tft阵列基板、电子纸显示面板及其形成方法
CN103278986A (zh) * 2013-04-01 2013-09-04 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制造方法
CN103295959A (zh) * 2012-09-14 2013-09-11 上海中航光电子有限公司 阵列基板及其制造方法、液晶显示面板

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5641974A (en) * 1995-06-06 1997-06-24 Ois Optical Imaging Systems, Inc. LCD with bus lines overlapped by pixel electrodes and photo-imageable insulating layer therebetween
KR100336886B1 (ko) * 1998-08-24 2003-06-09 주식회사 현대 디스플레이 테크놀로지 고개구율및고투과율을갖는반사형액정표시장치및그제조방법
KR100443902B1 (ko) * 1999-03-25 2004-08-09 엘지.필립스 엘시디 주식회사 엑스레이 영상 감지소자 및 그 제조방법
TW460731B (en) * 1999-09-03 2001-10-21 Ind Tech Res Inst Electrode structure and production method of wide viewing angle LCD
US6342572B1 (en) * 1999-12-28 2002-01-29 Honeywell International Inc. Flame retardant benzocyclobutene resin with reduced brittleness
KR100736114B1 (ko) * 2000-05-23 2007-07-06 엘지.필립스 엘시디 주식회사 횡전계 방식의 액정표시장치 및 그 제조방법
TW471181B (en) * 2000-12-27 2002-01-01 Ind Tech Res Inst Manufacturing method of wide view angle flat panel display cell
JP4380648B2 (ja) * 2005-05-25 2009-12-09 エプソンイメージングデバイス株式会社 液晶装置及び電子機器
KR101795549B1 (ko) * 2010-06-25 2017-11-09 엘지디스플레이 주식회사 프린지 필드 스위칭 모드 액정표시장치용 어레이 기판 및 이의 제조 방법
US8647919B2 (en) * 2010-09-13 2014-02-11 Semiconductor Energy Laboratory Co., Ltd. Light-emitting display device and method for manufacturing the same
CN102243401B (zh) * 2011-07-11 2013-05-29 昆山龙腾光电有限公司 液晶显示装置
US8895428B2 (en) * 2012-02-07 2014-11-25 Shenzhen China Star Optoelectronics Technology Co., Ltd. Manufacture method of thin film transistor array substrate
CN103064224A (zh) * 2013-01-28 2013-04-24 京东方科技集团股份有限公司 阵列基板及显示装置
WO2014181494A1 (ja) * 2013-05-09 2014-11-13 パナソニック液晶ディスプレイ株式会社 液晶表示装置及びその製造方法
CN103605244B (zh) * 2013-11-25 2016-03-30 深圳市华星光电技术有限公司 像素结构
CN203941365U (zh) * 2014-07-09 2014-11-12 京东方科技集团股份有限公司 阵列基板、显示面板及显示装置
CN105655292B (zh) * 2016-01-05 2019-03-15 深圳市华星光电技术有限公司 液晶显示面板、阵列基板及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101847641A (zh) * 2009-03-27 2010-09-29 京东方科技集团股份有限公司 阵列基板及其制造方法和宽视角液晶显示器
CN103066069A (zh) * 2011-10-20 2013-04-24 上海天马微电子有限公司 Tft阵列基板、电子纸显示面板及其形成方法
CN103295959A (zh) * 2012-09-14 2013-09-11 上海中航光电子有限公司 阵列基板及其制造方法、液晶显示面板
CN103278986A (zh) * 2013-04-01 2013-09-04 京东方科技集团股份有限公司 一种阵列基板、显示装置及阵列基板的制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020244100A1 (zh) * 2019-06-04 2020-12-10 武汉华星光电半导体显示技术有限公司 一种显示器件及其制备方法

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