WO2021208643A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2021208643A1
WO2021208643A1 PCT/CN2021/079911 CN2021079911W WO2021208643A1 WO 2021208643 A1 WO2021208643 A1 WO 2021208643A1 CN 2021079911 W CN2021079911 W CN 2021079911W WO 2021208643 A1 WO2021208643 A1 WO 2021208643A1
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WIPO (PCT)
Prior art keywords
substrate
orthographic projection
wiring area
spacer
sub
Prior art date
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PCT/CN2021/079911
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English (en)
French (fr)
Inventor
苏秋杰
王小元
孙志华
田丽
李承珉
刘建涛
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/636,148 priority Critical patent/US20220291558A1/en
Publication of WO2021208643A1 publication Critical patent/WO2021208643A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G02F1/13394—Gaskets; Spacers; Sealing of cells spacers regularly patterned on the cell subtrate, e.g. walls, pillars
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133514—Colour filters
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1339—Gaskets; Spacers; Sealing of cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136222—Colour filters incorporated in the active matrix substrate
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel and a display device.
  • the purpose of the present disclosure is to provide a display panel and a display device, which have a good display effect.
  • a display panel which includes:
  • the array substrate includes a first substrate, a gate line, a data line, and a plurality of sub-pixel units.
  • the first substrate has a plurality of sub-pixel regions arranged in an array, and a first substrate located between two adjacent rows of sub-pixel regions.
  • a spacer is arranged on the side of the alignment portion away from the array substrate, and the orthographic projection of the spacer on the first substrate is located on the alignment portion on the first substrate Within the orthographic projection.
  • the data line further has main line portions located on opposite sides of the alignment portion in the column direction, and the orthographic projection of the main line portion on the first substrate It does not overlap with the orthographic projection of the first wiring area on the first substrate, and the size of the main line portion in the row direction is smaller than the size of the alignment portion in the row direction.
  • the size of the alignment portion in the row direction Gradually increase.
  • the edge of the orthographic projection of the spacer on the first substrate is different from the edge of the orthographic projection of the alignment portion on the first substrate.
  • the distance between is the first distance
  • the ratio between the first pitch and the size of the main line portion of the data line in the row direction is 50% to 100%.
  • two of the gate lines are provided on the first wiring area, and each of the gate lines and at least part of the sub-pixel units in a row of sub-pixel units adjacent thereto Electrical connection
  • the orthographic projection of the alignment portion on the first substrate is located between the orthographic projections of the two grid lines on the first substrate.
  • retaining walls located on opposite sides of the spacer in the column direction are further formed on the first substrate;
  • the distance between the retaining wall and the spacer is a second distance
  • the ratio between the second pitch and the size of the main line portion of the data line in the row direction is 2.5 to 8.
  • the data line further has a transition part located between the main line part and the alignment part; the transition part and the gate line are connected to the first liner.
  • the orthographic projections on the bottom overlap, and the overlap position is defined as the blocking position;
  • the retaining wall includes a part of the transition part located at the blocking position and a part of the gate line located at the blocking position.
  • the alignment portion is electrically connected to the sub-pixel units in two adjacent columns.
  • a color filter substrate is further included.
  • the color filter substrate includes a second substrate located on a side of the spacer away from the array substrate and a second substrate located on the side of the array substrate.
  • the orthographic projection of the cross shielding portion on the first substrate at least covers the intersection area of the first wiring area and the second wiring area, and the first shielding portion is on the first substrate.
  • the orthographic projection covers at least the first wiring area and does not overlap the second wiring area, and the orthographic projection of the second shielding portion on the first substrate at least covers the second wiring area and does not overlap with the second wiring area.
  • the first wiring areas overlap;
  • the size of the cross shielding portion in the column direction is larger than the size of the first shielding portion in the column direction, and the size of the cross shielding portion in the row direction is larger than the size of the second shielding portion in the row direction.
  • the orthographic projection of the spacer on the second substrate is located in a central area of the orthographic projection of the cross shielding portion on the second substrate
  • the distance between the edge of the orthographic projection of the spacer on the first substrate and the edge of the orthographic projection of the cross shielding portion on the first substrate is a third distance
  • the ratio between the third pitch and the size of the main line portion of the data line in the row direction is 6.5-12.
  • the shielding layer further has a transition shielding portion located between the cross shielding portion and the first shielding portion; the transition shielding portion and the first shielding portion The two opposite end faces completely overlap each other, and the opposite end faces between the transition shielding part and the cross shielding part completely overlap.
  • a display device which includes the display panel described in any one of the above.
  • FIG. 1 shows a schematic diagram of a part of the structure of a display panel according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic diagram of the positional relationship between the array substrate and the spacers in the display panel according to an embodiment of the present disclosure
  • FIG. 3 shows a schematic diagram of the structure of a thin film transistor in the array substrate shown in FIG. 2;
  • FIG. 4 shows a schematic diagram of a part of the structure of a display panel according to another embodiment of the present disclosure
  • FIG. 5a shows a schematic structural diagram of a shielding layer in the display panel shown in FIG. 4;
  • FIG. 5b shows a schematic diagram of an enlarged structure of part A in the display panel shown in FIG. 4;
  • Fig. 6 shows a schematic cross-sectional view of the display panel shown in Fig. 5b in the B-B direction;
  • FIG. 7 shows a schematic diagram of the positional relationship between the shielding layer and the spacers in the display panel according to an embodiment of the present disclosure
  • FIG. 8 shows a schematic diagram of a part of the structure of a display panel in the related art
  • FIG. 9a shows a schematic structural diagram of a shielding layer in the display panel shown in FIG. 8;
  • FIG. 9b shows a schematic diagram of the positional relationship between the shielding layer of the display panel and the spacer in the related art.
  • Array substrate 10, first substrate; 10a, sub-pixel area; 10b, first wiring area; 10c, second wiring area; 11, data line; 110, alignment part; 111, main line part; 112, Transition part; 12, gate line; 13, sub-pixel unit; 130, common electrode; 131, pixel electrode; 1310, slit; 132, thin film transistor; 1320, gate; 1321, active layer; 1322, source electrode; 1323. Drain electrode; 14, common line, 15, first insulating layer; 16, second insulating layer; 17, orientation film layer; 18, retaining wall.
  • Color film substrate 20, second substrate; 21, color film layer; 22, shielding layer; 220, first shielding part; 221, second shielding part; 222, cross shielding part; 223, transitional shielding part; 224.
  • Light-transmitting holes
  • on can mean that one layer is directly formed or disposed on another layer, or can mean a layer A layer is formed indirectly or arranged on another layer, that is, there are other layers between the two layers.
  • first may be used herein to describe various components, components, elements, regions, layers and/or parts, these components, components, elements, regions, and layers And/or part should not be limited by these terms. Rather, these terms are used to distinguish one component, member, element, region, layer, and/or section from another.
  • the term “same layer arrangement” used means that two layers, parts, components, elements or parts can be formed by the same patterning process, and the two layers, parts, components , Components or parts are generally formed of the same material.
  • patterning process generally includes the steps of photoresist coating, exposure, development, etching, and photoresist stripping.
  • one-time patterning process means a process of forming patterned layers, parts, components, etc., using one mask.
  • the display panel may be a liquid crystal display panel.
  • the display panel may include an array substrate 1 and spacers 3; in addition, the display panel may also include a color filter substrate 2, and the color filter substrate 2 is located on the side of the spacer 3 away from the array substrate 1.
  • the spacer 3 can be located between the color filter substrate 2 and the array substrate 1 to support the color filter substrate 2 and the array substrate 1, and the liquid crystal 4 can be located in the space where the spacer 3 supports it.
  • the array substrate 1 may include a first substrate 10, data lines 11, gate lines 12 and a plurality of sub-pixel units 13 formed on the first substrate 10.
  • the first substrate 10 has a plurality of sub-pixel regions 10a arranged in an array, a first wiring region 10b between adjacent rows of sub-pixel regions 10a, and a second wiring region between adjacent columns of sub-pixel regions 10a.
  • Area 10c, the first wiring area 10b and the second wiring area 10c intersect; wherein at least part of each sub-pixel unit 13 is located on a sub-pixel area 10a; the gate line 12 is located on the first wiring area 10b and is connected to the sub-pixel unit 13 is electrically connected.
  • the data line 11 is located on the second wiring area 10c and is electrically connected to the sub-pixel unit 13.
  • the data line 11 and the gate line 12 are insulated from each other and the orthographic projection on the first substrate 10 intersects.
  • the orthographic projection of the line 11 and the gate line 12 on the first substrate 10 intersects in the area where the first wiring area 10b and the second wiring area 10c intersect; it should be understood that the extension directions of the data line 11 and the gate line 12 are different Specifically, the data line 11 extends in the column direction Y, and the gate line 12 extends in the row direction X; wherein, the data line 11 has an alignment portion 110, and the orthographic projection of the alignment portion 110 on the first substrate 10 is located In the area where the first wiring area 10b and the second wiring area 10c intersect.
  • the first substrate 10 is mainly used to form structures such as sub-pixel units 13, gate lines 12, and data lines 11.
  • the The first substrate 10 is divided into regions corresponding to these structures.
  • the sub-pixel region 10a, the first wiring region 10b, and the second wiring region 10c can be divided on the first substrate 10 first, and then the first substrate 10
  • the sub-pixel unit 13 is formed on the sub-pixel area 10a of the substrate 10, the first wiring area 10b is used to form at least the gate line 12, and the second wiring area 10c is used to form at least the data line 11.
  • the first wiring area 10b and the second wiring area 10c are also provided with multiple; in addition, the first substrate 10 may also be provided with other wiring areas except the first wiring area 10b and the second wiring area 10c, As the case may be.
  • the spacer 3 is arranged on the side of the alignment portion 110 of the data line 11 away from the array substrate 1, and the orthographic projection of the spacer 3 on the first substrate 10 is located
  • the alignment portion 110 is in the orthographic projection of the first substrate 10; that is, the outer contour of the orthographic projection of the spacer 3 on the first substrate 10 is located on the alignment portion 110 on the first substrate 10.
  • the inner side of the outer contour of the orthographic projection to ensure that the spacer 3 is stably supported on the array substrate 1.
  • the color filter substrate 2 may include a second substrate 20 and a shielding layer 22.
  • the second substrate 20 is located on the side of the spacer 3 away from the array substrate 1
  • the shielding layer 22 is located on the side of the spacer 3 away from the array substrate 1.
  • the second substrate 200 is close to one side of the array substrate.
  • the shielding layer 22 has a cross shielding portion 222, a first shielding portion 220 located on opposite sides of the cross shielding portion 222 in the row direction X, and two opposite first shielding portions 220 located on the cross shielding portion 222 in the column direction Y.
  • the second shielding portion 221 on the side.
  • the orthographic projection of the cross shielding portion 222 on the first substrate 10 covers at least the intersection area of the first wiring area 10b and the second wiring area 10c, and the first shielding portion 220 is on the first substrate 10
  • the orthographic projection on 10 covers at least the first wiring area 10b and does not overlap with the second wiring area 10c, and the orthographic projection of the second shielding portion 221 on the first substrate 10 at least covers the second wiring area 10c and does not overlap with the first wiring area 10c.
  • the wiring areas 10b overlap.
  • the first shielding portion 220, the second shielding portion 221, and the cross shielding portion 222 in the shielding layer 22 may be arranged in an array.
  • the second shielding portion 221 and the cross shielding portion 222 may enclose a light-transmitting hole 224, the orthographic projection of the light-transmitting hole 224 on the first substrate is located in the sub-pixel area 10a, and the light-transmitting hole 224 is used to allow light to pass through .
  • the area of the entire display panel is constant, the larger the total area of the light-transmitting holes 224, that is, the smaller the total area of the shielding portion, the higher the light transmittance of the display panel and the better the display effect.
  • the first shielding portion 220, the second shielding portion 221, and the cross shielding portion 222 in the shielding layer 22 can be formed on the first substrate.
  • the orthographic projection can also cover part of the sub-pixel area 10a, as shown in FIG. 4.
  • the spacer 3 by disposing the spacer 3 on the alignment part 110 in the intersection area of the first wiring area 10b and the second wiring area 10c in the data line 11, when the spacer 3 is in the row When movement occurs in the direction X and the column direction Y, the scratches formed on the alignment film layer 17 will also be shielded by the first shielding portion 220, the second shielding portion 221 and the cross shielding of the first wiring area 10b and the second wiring area 10c.
  • the part 222 is shielded, and this design can alleviate the situation that the spacer 3 slips out of the original shading range during the pressure test, thereby alleviating the light leakage that easily occurs, and then improving the display effect.
  • the spacer 3 in the embodiment of the present disclosure Located on the alignment portion 110 in the intersection area of the first wiring area 10b and the second wiring area 10c in the data line 11, compared to the related art shown in FIG. 8, the spacers 3 are arranged in the same column.
  • the scheme on the gate line 12 between the two adjacent sub-pixel units 13 is also to ensure that the scratches generated during the movement of the spacer 3 can be completely covered, but the increased area of the shielding part in the embodiment of the present disclosure is much smaller than the related The increased area of the shielding part in the technology.
  • the area enclosed by the S frame in Figures 7 and 9b is the moving area of the spacer 3, and the spacer 3 moves around in the related technical solution
  • the distance is the same as the distance that the spacer 3 moves to the surroundings in the solution described in the embodiment of the present disclosure; in order to ensure that the scratches generated during the movement of the spacer 3 can be completely blocked by the shielding layer 22, the related technical solutions
  • the area of the shielding portion of the shielding layer 22 is increased; among them, the sum of the areas of Q1, Q2, Q3, and Q4 in FIG. 7 is the shielding portion in the embodiment of the present disclosure.
  • the area of the Q part in Figure 9b is the increased area of the shielding part in the related art, and the area of the Q part is larger than the sum of the areas of the Q1 part, Q2 part, Q3 part and Q4 part. Therefore, in the embodiment of the present disclosure, The loss of aperture ratio caused is significantly less than the loss of related technical solutions.
  • the solution of the embodiment of the present disclosure is It is ensured that the scratches generated during the movement of the spacer 3 can be completely blocked by the shielding layer 22, and the pixel aperture ratio can also be increased.
  • the pixel aperture ratio refers to the total area of the light-transmitting holes 224 in the shielding layer 22 and the display The ratio between the entire area of the panel.
  • the data line 11 is usually closer to the spacer 3 than the gate line 12, for example, the data line 11 is usually arranged in the same layer as the source and drain of the thin film transistor in the array substrate 1, and the gate line 12 is usually arranged in the same layer as the source and drain of the thin film transistor in the array substrate 1.
  • the gates of the thin film transistors in the array substrate 1 are arranged in the same layer. Therefore, in the embodiment of the present disclosure, the spacer 3 is aligned with the data line 11, that is, the spacer 3 is arranged above the data line 11. Compared with the solution in the related art in which the spacer 3 is arranged above the gate line 12, the alignment accuracy can be improved, thereby ensuring the assembly yield of the display panel.
  • the first substrate 10 in the array substrate 1 may have a single-layer structure, and the material of the first substrate 10 may be glass. But not limited to this, the first substrate 10 may also have a multilayer structure; and the material of the first substrate 10 is not limited to glass, and may also be other materials, such as polyimide, etc., depending on the specific situation.
  • the sub-pixel unit 13 may include a common electrode 130, a pixel electrode 131, and a thin film transistor 132.
  • the thin film transistor 132 may include a gate 1320, an active layer 1321, a source electrode 1322, and a drain electrode 1323.
  • the gate 1320 may belong to a part of the gate line 12, but it is not limited to this.
  • the gate 1320 may also be arranged independently of the gate line 12, and the gate 1320 of the thin film transistor 132 may be connected to the gate Line 12 is set on the same layer. It should be noted that the number of thin film transistors 132 in the sub-pixel unit 13 may be provided in multiples, and the sub-pixel unit 13 may also include a capacitor structure, which is not shown in the figure.
  • a first insulating layer 15 may be further provided between the gate 1320 and the active layer 1321, so that the gate 1320 and the active layer 1321 are insulated from each other.
  • the insulating layer 15 can be made of inorganic materials, for example, silicon oxide, silicon nitride and other inorganic materials.
  • the thin film transistor 132 may be a top gate type or a bottom gate type. In the embodiments of the present disclosure, the thin film transistor 132 is a bottom-gate type as an example for description. As shown in FIG. 5b and FIG. 6, when the thin film transistor 132 is of a bottom gate type, the gate 1320 is formed on the first substrate 10.
  • the gate 1320 may include metal materials or alloy materials, such as molybdenum, aluminum, and titanium. Etc. to ensure its good electrical conductivity; the first insulating layer 15 is formed on the first substrate 10 and covers the gate 1320.
  • the first insulating layer 15 can be made of inorganic materials, such as silicon oxide, nitride Inorganic materials such as silicon; the active layer 1321 is formed on the side of the first insulating layer 15 away from the first substrate 10, the source electrode 1322 and the drain electrode 1323 are respectively connected to the two doped regions of the active layer 1321, the source electrode 1322
  • the drain electrode 1323 may include a metal material or an alloy material, such as a metal single-layer or multi-layer structure formed of molybdenum, aluminum, titanium, etc., for example, the multi-layer structure is a multi-metal laminated layer, such as three layers of titanium, aluminum, and titanium. Metal laminate (Al/Ti/Al), etc.
  • the common electrode 130 can be made of transparent materials such as ITO (Indium Tin Oxide), Indium Zinc Oxide (IZO), and Zinc Oxide (ZnO); that is, because the common electrode 130
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • ZnO Zinc Oxide
  • the materials used are different from those of the gate 1320 and source electrode 1322 of the thin film transistor 132 and the drain electrode 1323. Therefore, the common electrode 130 and the gate 1320 and source electrode 1322 of the thin film transistor 132 and the drain electrode 1323 can adopt different patterning processes. Made.
  • the common electrode 130 of this embodiment can be formed on the first substrate 10 before the gate 1320 of the thin film transistor 132 is formed. That is to say, when the array substrate 1 is fabricated, a patterning process can be used first. A common electrode 130 is formed on a substrate 10, and then a gate 1320 of the thin film transistor 132 is formed on the first substrate 10 by another patterning process. It should be noted that although the common electrode 130 and the gate 1320 are both formed on the first substrate 10, the common electrode 130 and the gate 1320 are disconnected from each other, that is, there is no electricity between the common electrode 130 and the gate 1320. Sexual connection.
  • the gate 1320 and the common electrode 130 can also be formed on the first substrate 10 at the same time by using a patterning process.
  • the common electrode 130 may not only be formed on the first substrate 10 before the gate 1320 of the thin film transistor 132 is formed, but also may be formed after it, depending on the specific situation.
  • the pixel electrode 131 can also be made of transparent materials such as ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), etc.; the pixel electrode 131 can It is formed on the side of the source electrode 1322, the drain electrode 1323 away from the first substrate 10; as shown in FIG. 5b and FIG. 6, the pixel electrode 131 can be connected to the drain electrode 1323. After the drain electrode 1323 and before the pixel electrode 131 is formed, a second insulating layer 16 can be formed.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • ZnO zinc oxide
  • a hole can be made on the second insulating layer 16 and the hole can be The surface of the drain electrode 1323 is exposed, and the pixel electrode 131 can be electrically connected to the drain electrode 1323 through the opening.
  • the pixel electrode 131 and the common electrode 130 may be oppositely designed in a direction perpendicular to the first substrate 10.
  • the pixel electrode 131 may be a slit electrode, that is, on the electrode.
  • a slit 1310 is provided, and the common electrode 130 can be a plate electrode (that is, the electrode is a single piece without slits); it is formed by the electric field generated by the pixel electrode 131 and the electric field between the common electrode 130 in the same plane It is mostly an electric field, which deflects all the liquid crystal molecules between the electrodes and directly above the electrodes, which can improve the working efficiency of the liquid crystal and increase the light transmission efficiency.
  • the pixel electrode 131 and the common electrode 130 can also be arranged in other structures, depending on the specific situation.
  • the positional relationship between the common electrode 130 and the pixel electrode 131 is not limited to being located on the same substrate as mentioned above, and may not be on the same substrate.
  • the pixel electrode 131 may be located on the array substrate 1.
  • the common electrode 130 may be located on the color filter substrate 2 and so on, depending on the specific situation.
  • the data line 11 can be arranged in the same layer as the source electrode 1322 of the thin film transistor 132 and the drain electrode 1323 and electrically connected to the source electrode 1322, but it is not limited to this.
  • the data line 11 can also be connected to other electrodes.
  • the same layer setting depends on the specific situation.
  • the data line 11 may include metal materials or alloy materials, such as molybdenum, aluminum, titanium, etc., to ensure good electrical conductivity.
  • the data line 11 may also have main line portions 111 located on opposite sides of the alignment portion 110 in the column direction Y, and the main line portions 111 are located in two adjacent columns of sub-pixel units 13 4 and 5b, the orthographic projection of the main line portion 111 on the first substrate 10 is located outside the intersection of the first wiring area 10b and the second wiring area 10c, that is, the main line portion
  • the orthographic projections of 111 and the first wiring area 10b on the first substrate 10 do not overlap; wherein the size of the main line portion 111 in the row direction X is smaller than the size of the alignment portion 110 in the row direction X.
  • the size of the alignment portion 110 in the data line 11 in the row direction X is designed to be larger, so that the spacer 3 and the data line 11 can be aligned.
  • the size of the main line portion 111 in the row direction X is designed to be small, which can reduce the area covered by the shielding portion, thereby increasing the pixel aperture ratio.
  • the size of the alignment portion 110 in the row direction X gradually increases.
  • This design ensures that the alignment portion 110 has sufficient While aligning with the spacer 3, the area of the aligning portion 110 can be prevented from being too large, thereby affecting the arrangement of other structures.
  • the orthographic projection shape of the alignment portion 110 on the first substrate 10 may be similar to a rhombus, an ellipse, or other polygons, etc., depending on the specific situation.
  • the size of the main line portion 111 of the data line 11 in the row direction X is basically unchanged.
  • the distance between the edge of the orthographic projection of the spacer 3 on the first substrate 10 and the edge of the orthographic projection of the alignment portion 110 on the first substrate 10 may be a first distance.
  • the ratio between the pitch and the size of the main line portion 111 of the data line 11 in the row direction X is 50% to 100%; for example, the size of the main line portion 111 of the data line 11 in the row direction X is 5 ⁇ m to 6 ⁇ m.
  • the distance between the edges of the orthographic projection on the substrate 10 (ie, the first distance) may be 3 ⁇ m to 5 ⁇ m, such as 3 ⁇ m, 4 ⁇ m, 5 ⁇ m, etc., to meet the requirements of alignment deviation.
  • the distance between the edge of the orthographic projection of the spacer 3 on the first substrate 10 and the edge of the orthographic projection of the alignment portion 110 on the first substrate 10 is not limited to 3 ⁇ m to 5 ⁇ m, and may be More than 5 ⁇ m, etc., depending on the alignment deviation of the color filter substrate 2 and the array substrate 1 in the production line.
  • the data line 11 also has a transition portion 112 between the main line portion 111 and the alignment portion 110.
  • the orthographic projection of the transition portion 112 on the first substrate 10 can be located on the first substrate 10.
  • the wiring area 10b and the second wiring area 10c are located on the intersection area, but not limited to this.
  • the orthographic projection of the transition portion 112 on the first substrate 10 may also be located in the second wiring area 10c and not with the first wiring area 10b. overlap.
  • the size of the transition portion 112 in the row direction X may be slightly larger than the size of the main line portion 111 in the row direction X, and smaller than the size of the alignment portion 110 in the row direction X, but is not limited to this.
  • the size of the transition portion 112 in the row direction X may also be equal to the size of the main line portion 111 in the row direction X.
  • the orthographic projection of the alignment portion 110 of the data line 11 on the first substrate 10 and the gate line 12 located on the first wiring area 10b are on the first substrate 10.
  • the orthographic projections on the first substrate 10 do not overlap, and the orthographic projection of the transition portion 112 on the first substrate 10 overlaps with the orthographic projection of the gate line 12 located on the first wiring area 10b on the first substrate 10.
  • the size in the row direction X is smaller than the size of the alignment portion 110 in the row direction X. Therefore, this design can reduce the overlap area between the data line 11 and the gate line 12, thereby reducing the gate line 12 and the data line 11 The capacitance between them can then ensure the performance of the array substrate 1.
  • the sub-pixel units 13 are electrically connected. This design ensures reliable electrical connection between the data line 11 and the sub-pixel units 13 in two adjacent columns, and also reduces the process difficulty.
  • two gate lines 12 may be provided on the first wiring area 10b on the first substrate 10; each gate line and its adjacent row At least some of the sub-pixel units 13 are electrically connected.
  • the first wiring area 10b can also be provided with a common line 14.
  • the common line 14 can be provided in the same layer as the gate line 12, and is similar to the sub-pixel unit 13 in a row.
  • the common electrode 130 of each sub-pixel unit 13 is overlapped to realize the electrical connection between the common line 14 and the common electrode 130.
  • the gate line 12 and the common line 14 part of the sub-pixel unit 13 may be located in the first wiring area 10b, as shown in FIGS. 2 and 4.
  • the orthographic projection of the alignment portion 110 of the data line 11 on the first substrate 10 is located between the two gate lines. Between the orthographic projections on the first substrate 10, this design reduces the overlap area between the data line 11 and the two gate lines 12, while also making the alignment portion 110 of the data line 11 as close to the first wiring as possible.
  • the center position of the intersecting area of the area 10b and the second wiring area 10c that is, ensure that the spacer 3 is as close as possible to the center of the intersecting area of the first wiring area 10b and the second wiring area 10c, so as to prevent the spacer 3 from being in the pressure test.
  • the shielding range of the cross shielding portion 222 is slid out.
  • the first substrate 10 when the spacer 3 is formed on the color filter substrate 2, the first substrate 10 is also formed with two spacers 3 opposite to each other in the column direction Y.
  • the surface of the retaining wall 18 that is far away from the first substrate 10 is farther from the first substrate 10 than the surface of the spacer 3 that is close to the first substrate 10, and is compared to the surface of the spacer 3
  • the surface away from the first substrate 10 is close to the first substrate 10.
  • the sliding displacement of the spacer 3 in the column direction Y can be limited by setting the retaining wall 18, so as to prevent the spacer 3 from sliding out of the blocked area during the pressure test.
  • retaining walls 18 are not limited to providing retaining walls 18 on opposite sides of the spacer 3 in the column direction Y, and retaining walls 18 may also be provided in the row direction X or other directions.
  • the distance between the retaining wall 18 and the spacer 3 is a second distance, and the ratio between the second distance and the size of the main line portion 111 of the data line 11 in the row direction X is 2.5 to 8; for example, :
  • the size of the main line portion 111 of the data line 11 in the row direction X is 5 ⁇ m to 6 ⁇ m;
  • the distance between the barrier wall 18 and the spacer 3 (ie, the second distance) may be 15 ⁇ m to 40 ⁇ m, for example: 15 ⁇ m, 20 ⁇ m , 25 ⁇ m, 30 ⁇ m, 35 ⁇ m, 40 ⁇ m, by designing the distance between the retaining wall 18 and the spacer 3 to be greater than or equal to 15 ⁇ m, it can avoid the situation that the retaining wall 18 cannot prevent the spacer 3 from sliding due to the too small distance;
  • By designing the distance between the retaining wall 18 and the spacer 3 to be less than or equal to 40 ⁇ m, it can be avoided that the distance is too large and the setting of the retaining wall 18
  • the retaining wall 18 may include a portion of the transition portion 112 at the barrier position and a portion of the gate line 12 at the barrier position. That is to say, the retaining wall 18 of the embodiment of the present disclosure may be a part where the data line 11 and the gate line 12 overlap. It is formed, and this design does not need to set the retaining wall 18 through other processes, which can reduce the processing cost.
  • the retaining wall 18 includes, in addition to the part at the barrier position in the transition portion 112, and the gate line 12 (common line 14 In addition to the part in the blocking position in ), it may also include the part in the blocking position in the first insulating layer 15; in addition, it may also include the part in the blocking position in the second insulating layer 16.
  • the size of the cross shielding portion 222 of the shielding layer 22 in the color filter substrate 2 in the column direction Y is larger than the size of the first shielding portion 220 in the row direction Y, and the cross shielding portion
  • the size of 222 in the row direction X is larger than the size of the second shielding portion 221 in the row direction X; this design can prevent the spacer 3 from sliding out of the blocked area during the pressure test.
  • the orthographic projection of the spacer 3 on the second substrate 20 is located in the central area of the orthographic projection of the cross-shielding portion on the second substrate 20 at 222, and the spacer 3 is
  • the distance between the edge of the orthographic projection on the first substrate 10 and the edge of the orthographic projection of the cross shielding portion 222 on the first substrate 10 is a third distance, and the third distance is at a distance from the main line portion 111 of the data line 11
  • the ratio between the dimensions in the row direction X is 6.5 to 12; for example: the size of the main line portion 111 of the data line 11 in the row direction X is 5 ⁇ m to 6 ⁇ m; the orthographic projection of the spacer 3 on the first substrate 10
  • the distance between the edge of and the edge of the orthographic projection of the cross shielding portion 222 on the first substrate 10 may be 40 ⁇ m to 60 ⁇ m, such as 40 ⁇ m, 45 ⁇ m, 50 ⁇ m, 55 ⁇ m,
  • the shielding layer 22 also has a transition shielding portion 223 located between the cross shielding portion 222 and the first shielding portion 220.
  • the transition shielding portion 223 In the direction from the first shielding portion 220 to the cross shielding portion 222, the transition shielding portion 223 is in the row direction Y
  • the size of the transitional shielding portion 223 and the first shielding portion 220 are completely overlapped, and the opposite end surfaces of the transitional shielding portion 223 and the cross-shielding portion 222 are completely overlapped; by setting the transitional shielding portion Therefore, while preventing the spacer 3 from sliding out of the blocked area during the pressure test, the blocking area of the blocking layer 22 can be reduced, thereby increasing the pixel aperture ratio.
  • the color filter substrate 2 may also be provided with a color filter layer 21, which may be formed on the side of the shielding layer 22 away from the second substrate 20, and the color filter layer 21 may include red, green, and red colors arranged in an array. Filter structure of blue and other colors.
  • the spacer 3 may be formed on the color filter substrate 2 first, and then the color filter substrate 2 and the array substrate 1 are aligned, but it is not limited to this.
  • the spacer 3 may also be formed on the array first. On the substrate 1, then the color filter substrate 2 and the array substrate 1 are boxed together.
  • the plurality of spacers may include a main spacer and an auxiliary spacer.
  • the main spacer may be a spacer 3 as shown in FIG. 6.
  • the main spacer Both ends can be in contact with the array substrate 1 and the color filter substrate 2 respectively, and mainly play a supporting role; and the auxiliary spacer (not shown in the figure) when the display panel does not receive external pressure, if the auxiliary spacer is formed On the color filter substrate 2, there is a certain distance between the auxiliary spacer and the array substrate 1, that is to say, there is a step (height difference) between the main spacer and the auxiliary spacer.
  • the gap between the spacer and the auxiliary spacer can fine-tune the thickness of the display panel. For example, the height of the main spacer is greater than the height of the auxiliary spacer.
  • the main spacer When the display panel is subjected to external pressure, the main spacer first bears all the pressure and is compressed. When the main spacer is compressed to the main spacer and the auxiliary spacer When the step difference between the objects drops to 0, the main spacer and the auxiliary spacer can bear the external pressure together.
  • the position of the spacers 3 is selectively arranged, and it is not necessary that the spacers 3 are correspondingly arranged in each intersection area of the first wiring area 10b and the second wiring area 10c in the array substrate 1. Not every part of the data line located at the intersection of the first wiring area 10b and the second wiring area 10c is provided with the alignment portion 110, and the specific number and position of the spacers 3 can be determined according to actual requirements.
  • An embodiment of the present disclosure also provides a display device, which includes the display panel described in any of the above embodiments.
  • the display device may be a liquid crystal display device.
  • the specific type of the display device is not particularly limited.
  • the types of display devices commonly used in the field can be used, such as liquid crystal displays, mobile devices such as mobile phones and notebook computers, wearable devices such as watches, and VR devices.
  • the device, etc. can be selected by those skilled in the art according to the specific purpose of the display device, which will not be repeated here.
  • the display device also includes other necessary components and components. Taking the display as an example, it may also include a backlight module, a housing, a main circuit board, a power cord, etc., those skilled in the art Corresponding supplements can be made according to the specific use requirements of the display device, which will not be repeated here.

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Abstract

一种显示面板及显示装置。显示面板包括：阵列基板（1），包括第一衬底（10）、栅线（12）、数据线（11）及多个子像素单元（13），第一衬底（10）具有呈阵列排布的多个子像素区（10a）、位于相邻两行子像素区（10a）之间的第一布线区（10b）及位于相邻两列子像素区（10a）之间并与第一布线区（10b）相交的第二布线区（10c），每一子像素单元（13）的至少部分位于一子像素区（10a）上；栅线（12）和数据线（11）分别位于第一布线区（10b）和第二布线区（10c）上并与子像素单元（13）电连接，数据线（11）与栅线（12）相互绝缘且相交，数据线（11）具有对位部（110），对位部（110）在第一衬底（10）上的正投影位于第一布线区（10b）和第二布线区（10c）相交叉的区域内；隔垫物（3），设置在对位部（110）背离阵列基板（1）的一侧，隔垫物（3）在第一衬底（10）上的正投影位于对位部（110）在第一衬底（10）上的正投影内。显示产品具有良好的显示效果。

Description

显示面板及显示装置
交叉引用
本公开要求于2020年04月14日提交的申请号为202010291154.6名称为“显示面板及显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及显示装置。
背景技术
随着液晶面板的不断发展，高分辨率的产品被不断开发，但随着像素的增多，容易导致一系列的问题发生，例如：在对液晶面板进行某些压力测试时，会使彩膜基板相对阵列基板发生滑动，导致彩膜基板上的隔垫物划伤阵列基板的取向(PI)膜层，使液晶配向异常，发生不可控的漏光，从影响显示效果。
需要说明的是，在上述背景技术部分发明的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
公开内容
本公开的目的在于提供一种显示面板及显示装置，具有良好的显示效果。
根据本公开的一个方面，提供一种显示面板，其中，包括：
阵列基板，包括第一衬底、栅线、数据线及多个子像素单元，所述第一衬底具有呈阵列排布的多个子像素区、位于相邻两行子像素区之间的第一布线区及位于相邻两列子像素区之间的第二布线区，所述第一布线区与所述第二布线区相交；每一所述子像素单元的至少部分位于一所述子像素区上；所述栅线位于所述第一布线区上并与所述子像素单元电连接，所述数据线位于所述第二布线区上并与所述子像素单元电连接，所述数据线与所述栅线相互绝缘且在所述第一衬底上的正投影相交，所述数据线具有对位部，所述对位部在所述第一衬底上的正投影位于所述第一布线区和所述第二布线区相交叉的区域内；
隔垫物，设置在所述对位部背离所述阵列基板的一侧，所述隔垫物在所述第一衬底上的正投影位于所述对位部在所述第一衬底上的正投影内。
在本公开的一种示例性实施例中，所述数据线还具有位于所述对位部在列方向上相对两侧的主线部，所述主线部在所述第一衬底上的正投影与所述第一布线区在所述第一衬底上的正投影不交叠，且所述主线部在行方向上的尺寸小于所述对位部在行方向上的尺寸。
在本公开的一种示例性实施例中，从所述对位部靠近所述主线部的一侧至所述对位部的中心的方向上，所述对位部在所述行方向上的尺寸逐渐增大。
在本公开的一种示例性实施例中，所述隔垫物在所述第一衬底上的正投影的边缘与所述对位部在所述第一衬底上的正投影的边缘之间的间距为第一间距；
其中，所述第一间距与所述数据线的主线部在行方向上的尺寸之间的比值为50％至100％。
在本公开的一种示例性实施例中，所述第一布线区上设置有两条所述栅线，每条所述栅线和与其相邻的一行子像素单元中的至少部分子像素单元电连接；
所述对位部在所述第一衬底上的正投影位于两条所述栅线在所述第一衬底上的正投影之间。
在本公开的一种示例性实施例中，所述第一衬底上还形成有位于所述隔垫物在所述列方向上相对两侧的挡墙；
所述挡墙与所述隔垫物之间的间距为第二间距；
其中，所述第二间距与所述数据线的主线部在行方向上的尺寸之间的比值为2.5至8。
在本公开的一种示例性实施例中，所述数据线还具有位于所述主线部和所述对位部之间的过渡部；所述过渡部和所述栅线在所述第一衬底上的正投影相交叠，其交叠位置定义为阻挡位；
所述挡墙包括所述过渡部中位于所述阻挡位的部分和所述栅线中位于所述阻挡位的部分。
在本公开的一种示例性实施例中，所述对位部与相邻两列的子像素单元电连接。
在本公开的一种示例性实施例中，还包括彩膜基板，所述彩膜基板包括位于所述隔垫物远离所述阵列基板一侧的第二衬底及位于所述第二衬底靠近所述阵列基板一侧的遮挡层，所述遮挡层具有交叉遮挡部、位于所述交叉遮挡部在行方向相对两侧的第一遮挡部、以及位于所述交叉遮挡部在列方向上相对两侧的第二遮挡部；其中，
所述交叉遮挡部在所述第一衬底上的正投影至少覆盖所述第一布线区与所述第二布线区的交叉区域，所述第一遮挡部在所述第一衬底上的正投影至少覆盖所述第一布线区且不与所述第二布线区交叠，所述第二遮挡部在所述第一衬底上的正投影至少覆盖所述第二布线区且不与所述第一布线区相交叠；
所述交叉遮挡部在列方向上的尺寸大于所述第一遮挡部在列方向上的尺寸，且所述交叉遮挡部在行方向上的尺寸大于所述第二遮挡部在行方向上的尺寸。
在本公开的一种示例性实施例中，所述隔垫物在所述第二衬底上的正投影位于所述交叉遮挡部在所述第二衬底上的正投影的中心区域内，
所述隔垫物在所述第一衬底上的正投影的边缘与所述交叉遮挡部在所述第一衬 底上的正投影的边缘之间的间距为第三间距；
其中，所述第三间距与所述数据线的主线部在行方向上的尺寸之间的比值为6.5至12。
在本公开的一种示例性实施例中，所述遮挡层还具有位于所述交叉遮挡部与所述第一遮挡部之间的过渡遮挡部；所述过渡遮挡部与所述第一遮挡部之间相对的两端面完全重叠，所述过渡遮挡部与所述交叉遮挡部之间相对的两端面完全重叠。
根据本公开的另一个方面，提供一种显示装置，其包括上述任一项所述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本公开一实施例所述的显示面板的部分结构示意图；
图2示出了本公开一实施例所述的显示面板中阵列基板与隔垫物的位置关系示意图；
图3示出了图2中所示的阵列基板中薄膜晶体管的结构示意图；
图4示出了本公开另一实施例所述的显示面板的部分结构示意图；
图5a示出了图4中所示的显示面板中遮挡层的结构示意图；
图5b示出了图4中所示的显示面板中A部的放大结构示意图；
图6示出了图5b中所示的显示面板在B-B方向上的截面示意图；
图7示出了本公开一实施例所述显示面板中遮挡层与隔垫物的位置关系示意图；
图8示出了相关技术中显示面板的部分结构示意图；
图9a示出了图8中所示的显示面板中遮挡层的结构示意图；
图9b示出了相关技术中显示面板的遮挡层与隔垫物的位置关系示意图。
附图标记：
1、阵列基板；10、第一衬底；10a、子像素区；10b、第一布线区；10c、第二布线区；11、数据线；110、对位部；111、主线部；112、过渡部；12、栅线；13、子像素单元；130、公共电极；131、像素电极；1310、狭缝；132、薄膜晶体管；1320、栅极；1321、有源层；1322、源电极；1323、漏电极；14、公共线、15、第一绝缘层；16、第二绝缘层；17、取向膜层；18、挡墙。
2、彩膜基板；20、第二衬底；21、彩膜层；22、遮挡层；220、第一遮挡部；221、第二遮挡部；222、交叉遮挡部；223、过渡遮挡部；224、透光孔；
3、隔垫物；
4、液晶。
具体实施方式
下面通过实施例，并结合附图，对本公开的技术方案作进一步具体的说明。在说明书中，相同或相似的附图标号指示相同或相似的部件。下述参照附图对本公开实施方式的说明旨在对本公开的总体发明构思进行解释，而不应当理解为对本公开的一种限制。
另外，在下面的详细描述中，为便于解释，阐述了许多具体的细节以提供对本披露实施例的全面理解。然而明显地，一个或多个实施例在没有这些具体细节的情况下也可以被实施。
需要说明的是，本文中所述的“在……上”、“在……上形成”和“设置在……上”可以表示一层直接形成或设置在另一层上，也可以表示一层间接形成或设置在另一层上，即两层之间还存在其它的层。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。
在本公开中，除非另有说明，所采用的术语“同层设置”指的是两个层、部件、构件、元件或部分可以通过同一构图工艺形成，并且，这两个层、部件、构件、元件或部分一般由相同的材料形成。
在本公开中，除非另有说明，表述“构图工艺”一般包括光刻胶的涂布、曝光、显影、刻蚀、光刻胶的剥离等步骤。表述“一次构图工艺”意指使用一块掩模板形成图案化的层、部件、构件等的工艺。
本公开的一实施例提供了一种显示面板，此显示面板可为液晶显示面板。如图1所示，显示面板可包括阵列基板1和隔垫物3；此外，该显示面板还可包括彩膜基板2，该彩膜基板2位于隔垫物3远离阵列基板1的一侧。也就是说，隔垫物3可位于彩膜基板2与阵列基板1之间，以起到支撑彩膜基板2与阵列基板1的作用，且液晶4可位于隔垫物3支撑其来的空间内。其中：
如图2、图4至图6所示，阵列基板1可包括第一衬底10及形成在第一衬底10上的数据线11、栅线12及多个子像素单元13。详细说明，第一衬底10具有呈阵列排布的多个子像素区10a、位于相邻行子像素区10a之间的第一布线区10b及位于相邻列子像素区10a之间的第二布线区10c，第一布线区10b与第二布线区10c相交；其中，每一子像素单元13的至少部分位于一子像素区10a上；栅线12位于第一布线区10b上并与子像素单元13电连接，数据线11位于第二布线区10c上并与子像素单元13电连接，数据线11与栅线12相互绝缘且在第一衬底10上的正投影相交，具体地，此数据线11与栅线12在第一衬底10上的正投影相交于第一布线区10b与第二布线区10c相交的区域内；理应了解的是，数据线11与栅线12的延伸方向不同，具体地，数据线11在列方向Y上延伸，栅线12在行方向X上延伸；其中，数据线11具有对位部110，对位部110在第一衬底10上的正投影位于第一布线区10b和第二布线区10c相交叉的区域内。
应当理解的是，第一衬底10上主要用来形成子像素单元13、栅线12和数据线11等结构，为了便于将这些结构加工至第一衬底10上的特定区域，可先在第一衬底10上划分出与这些结构对应的各区域，比如：可先在第一衬底10上划分出子像素区10a、第一布线区10b和第二布线区10c，然后在第一衬底10的子像素区10a上形成子像素单元13，第一布线区10b上至少用来形成有栅线12，第二布线区10c上至少用来形成数据线11。其中，第一布线区10b和第二布线区10c也设置有多个；此外，第一衬底10上还可设置有除了第一布线区10b和第二布线区10c之外的其他布线区，视具体情况而定。
如图2、图4至图6所示，隔垫物3设置在数据线11的对位部110背离阵列基板1的一侧，且隔垫物3在第一衬底10上的正投影位于对位部110在第一衬底10上的正投影内；也就是说，隔垫物3在第一衬底10上的正投影的外轮廓位于对位部110在第一衬底10上的正投影的外轮廓的内侧，以保证隔垫物3稳定地支撑在阵列基板1上。
如图2、图4至图6所示，彩膜基板2可包括第二衬底20和遮挡层22，第二衬底20位于隔垫物3远离阵列基板1的一侧，遮挡层22位于第二衬底200靠近阵列基板的一侧。
如图5a、图7所示，遮挡层22具有交叉遮挡部222、位于交叉遮挡部222在行方向X上相对两侧的第一遮挡部220以及位于交叉遮挡部222在列方向Y上相对两侧的第二遮挡部221。结合图4和图5a所示，交叉遮挡部222在第一衬底10上的正投影至少覆盖第一布线区10b与第二布线区10c的交叉区域，第一遮挡部220在第一衬底10上的正投影至少覆盖第一布线区10b且不与第二布线区10c交叠，第二遮挡部221在第一衬底10上的正投影至少覆盖第二布线区10c且不与第一布线区10b相交叠。
其中，遮挡层22中第一遮挡部220、第二遮挡部221和交叉遮挡部222可呈阵列排布，结合图4、图5a和图7所示，阵列排布的第一遮挡部220、第二遮挡部221和交叉遮挡部222可围成透光孔224，此透光孔224在第一衬底上的正投影位于子像素区10a内，该透光孔224用于允许光线透过。在整个显示面板的面积一定时，透光孔224的面积总和越大，也就是说，遮挡部的面积总和越小，则显示面板的光透过率越高，显示效果越好。
需要说明的是，为了保证遮挡层22能够将阵列基板1上布线区完全遮盖，可使遮挡层22中第一遮挡部220、第二遮挡部221和交叉遮挡部222在第一衬底上的正投影还可覆盖部分子像素区10a，如图4所示。
在本公开的实施例中，通过将隔垫物3设置在数据线11中位于第一布线区10b和第二布线区10c交叉区内的对位部110上，这样当隔垫物3在行方向X和列方向Y上产生移动时，取向膜层17上形成的划痕也会被遮挡第一布线区10b和第二布线区10c的第一遮挡部220、第二遮挡部221和交叉遮挡部222遮挡住，这样设计可缓解隔垫物3在压力测试过程中滑出原有遮光范围内的情况，从而可缓解容易发生的漏光情况，继而可提高显示效果。
应当理解的是，即使隔垫物3在压力测试过程中发生在其他方向(即：除了行方向X和列方向Y以外的方向)上的滑动，但由于本公开实施例中的隔垫物3位于数据线11中位于第一布线区10b和第二布线区10c交叉区内的对位部110上，相比于图8中所示出的相关技术中将隔垫物3设置在同列中相邻两个子像素单元13之间的栅线12上的方案，同样为了保证隔垫物3在移动过程中产生的划痕能够完全被覆盖，但本公开实施例中遮挡部增加的面积远小于相关技术中遮挡部增加的面积。
具体如图5a、图7和图9a、图9b所示，图7和图9b中S框所围住的区域为隔垫物3的移动区域，该相关技术方案中隔垫物3向周围移动的距离和本公开实施例所述的方案中隔垫物3向周围移动的距离相同；为了保证隔垫物3在移动过程中产生的划痕能够完全被遮挡层22遮挡，相关技术方案中与本公开实施例所描述的方案中，遮挡层22的遮挡部面积均有所增加；其中，图7中Q1部、Q2部、Q3部和Q4部的面积之和为本公开实施例中遮挡部增加的面积，图9b中Q部的面积为相关技术中遮挡部增加的面积，Q部的面积大于Q1部、Q2部、Q3部和Q4部的面积之和，因此，本公开实施例方案中引起的开口率损失明显小于相关技术方案的损失。
也就是说，相比于图8中所示出的相关技术中将隔垫物3设置在同列中相邻两个子像素单元13之间的栅线12上的方案，本公开实施例的方案在保证隔垫物3在移动过程中产生的划痕能够完全被遮挡层22遮挡的同时，还可提高像素开口率，此像素开口率指的是遮挡层22中透光孔224的面积总和与显示面板的整个面积之间的比值。
举例而言，对于55寸UHD(Ultra High Definition，超高清)显示产品来说，在 隔垫物3进行压力测试过程中向周围移动的距离为40μm至60μm时，且在一个子像素单元13的宽为105um，长为315um时，采用相关技术的方案，开口率为56.9％；采用本公开实施所描述的方案，开口率为60.9％，本公开实施例所描述的方案相比于相关技术的方案，开口率绝对值增加4％，相对值约提升10.7％。
需要说明的是，图7中粗体虚线、单点划线、双点划线和图9b中粗体虚线和双点划线均不具有实际含义，仅仅是为了方便本领域技术人员理解遮挡层22中各部分所对应的位置及隔垫物3的移动范围。
此外，如图6所示，由于数据线11通常比栅线12更靠近隔垫物3，例如：数据线11通常与阵列基板1中薄膜晶体管的源漏极同层设置，栅线12通常与阵列基板1中的薄膜晶体管的栅极同层设置，因此，本公开实施例中通过隔垫物3与数据线11进行对位，即：通过将隔垫物3设置在数据线11的上方，相比于相关技术中将隔垫物3设置在栅线12上方的方案，可提高对位准确性，从而保证显示面板的组装良率。
下面结合附图对本公开实施例所描述的显示面板进行详细描述。
在一些实施例中，如图6所示，阵列基板1中的第一衬底10可单层结构，该第一衬底10的材料可为玻璃。但不限于此，此第一衬底10还可多层结构；且第一衬底10的材料不限于玻璃，也可为其他材料，例如：聚酰亚胺等材料，视具体情况而定。
如图2至图6所示，子像素单元13可包括公共电极130、像素电极131及薄膜晶体管132，此薄膜晶体管132可包括栅极1320、有源层1321、源电极1322、漏电极1323，如图2、图3、图5b所示，栅极1320可属于栅线12的一部分，但不限于此，栅极1320也可相对栅线12独立设置，薄膜晶体管132中栅极1320可与栅线12同层设置。需要说明的是，子像素单元13中薄膜晶体管132的数量可设置有多个，且子像素单元13中还可包括电容结构，图中未示出。
此外，应当理解的是，如图6所示，栅极1320与有源层1321之间还可设置第一绝缘层15，以使栅极1320与有源层1321之间相互绝缘，此第一绝缘层15可采用无机材料制作而成，例如，氧化硅、氮化硅等无机材料。
其中薄膜晶体管132可为顶栅型，也可为底栅型。在本公开的实施例中主要以薄膜晶体管132为底栅型为例进行说明。如图5b和图6所示，在薄膜晶体管132为底栅型时，栅极1320形成在第一衬底10上，此栅极1320可包括金属材料或者合金材料，例如包括钼、铝及钛等，以保证其良好的导电性能；第一绝缘层15形成在第一衬底10上并覆盖栅极1320，此第一绝缘层15可采用无机材料制作而成，例如：氧化硅、氮化硅等无机材料；有源层1321形成在第一绝缘层15背离第一衬底10的一侧，源电极1322和漏电极1323分别与有源层1321的两掺杂区连接，该源电极1322和漏电极1323可包括金属材料或者合金材料，例如由钼、铝及钛等形成的金 属单层或多层结构，例如，该多层结构为多金属层叠层，例如钛、铝、钛三层金属叠层(Al/Ti/Al)等。
而为了保证阵列基板1的透光率，公共电极130可采用ITO(氧化铟锡)、氧化铟锌(IZO)、氧化锌(ZnO)等透明材料制作而成；也就是说，由于公共电极130采用的材料与薄膜晶体管132的栅极1320和源电极1322、漏电极1323的材料不同，因此，该公共电极130与薄膜晶体管132的栅极1320和源电极1322、漏电极1323可采用不同构图工艺制作而成。
举例而言，本实施例的公共电极130可在形成薄膜晶体管132的栅极1320之前形成在第一衬底10上，也就是说，在制作阵列基板1时，可先采用一构图工艺在第一衬底10上形成公共电极130，然后再采用另一构图工艺在第一衬底10上形成薄膜晶体管132的栅极1320。需要说明的是，公共电极130与栅极1320虽然都形成在第一衬底10上，但公共电极130与栅极1320之间相互断开，即：公共电极130与栅极1320之间无电性连接。
但应当理解的是，在栅极1320的材料与公共电极130的材料相同时，也可采用一次构图工艺同时在第一衬底10上形成栅极1320和公共电极130。此外，公共电极130不仅可在形成薄膜晶体管132的栅极1320之前形成在第一衬底10上，也可在其之后形成，视具体情况而定。
同理，为了保证阵列基板1的透光率，像素电极131也可采用ITO(氧化铟锡)、氧化铟锌(IZO)、氧化锌(ZnO)等透明材料制作而成；此像素电极131可形成在源电极1322、漏电极1323远离第一衬底10的一侧；如图5b和图6所示，像素电极131可与漏电极1323相连接，理应了解的是，在形成源电极1322、漏电极1323之后，且形成像素电极131之前，还可形成一层第二绝缘层16，为了实现像素电极131与漏电极1323的连接，可在第二绝缘层16上开孔，此开孔可露出漏电极1323的表面，而像素电极131可通过此开孔与漏电极1323电连接。
举例而言，此像素电极131可与公共电极130在垂直于第一衬底10的方向相对设计，其中，如图2和图4所示，像素电极131可为狭缝电极，即：电极上开设有狭缝1310，而公共电极130可为板状电极(即：电极为一整块并未开设狭缝)；通过同一平面内像素电极131所产生的电场和公共电极130间产生的电场形成多为电场，使在电极之间和电极正上方的所有液晶分子发生偏转，可提高液晶的工作效率，且增加了透光效率。但不限于此，像素电极131和公共电极130也可设置为其他结构，视具体情况而定。
此外，还需说明的是，公共电极130与像素电极131的位置关系不限于前述提到的位于在同一基板上，也可不在同一基板上，例如：像素电极131可位于阵列基板1上，而公共电极130可位于彩膜基板2上等等，视具体情况而定。
如图5b和图6所示，数据线11可与薄膜晶体管132的源电极1322、漏电极 1323同层设置，并与源电极1322电连接，但不限于此，数据线11也可与其他电极同层设置，视具体情况而定。举例而言，数据线11可包括金属材料或者合金材料，例如包括钼、铝及钛等，以保证其良好的导电性能。
如图5b所示，数据线11除了具有对位部110之外，还可具有位于对位部110在列方向Y上相对两侧的主线部111，主线部111位于相邻两列子像素单元13之间；结合图4和图5b所示，此主线部111在第一衬底10上的正投影位于第一布线区10b与第二布线区10c的交叉区之外，也就是说，主线部111与第一布线区10b在第一衬底10上的正投影不交叠；其中，主线部111在行方向X上的尺寸小于对位部110在行方向X上的尺寸。
在本公开的实施例中，通过将数据线11中对位部110在行方向X上的尺寸设计的较大，以便于隔垫物3与数据线11进行对位，通过将数据线11中主线部111在行方向X上的尺寸设计的较小，可减小遮挡部覆盖的面积，从而可提高像素开口率。
其中，从对位部110靠近主线部111的一侧至对位部110的中心的方向上，对位部110在行方向X上的尺寸逐渐增大，这样设计在保证对位部110具有足够的面积与隔垫物3进行对位的同时，还可避免对位部110的面积过大，从而影响其他结构的布置。举例而言，此对位部110在第一衬底10上的正投影形状可类似为菱形、椭圆形或其他多边形等，视具体情况而定。
需要说明的是，在列方向Y上，数据线11的主线部111在行方向X上的尺寸基本不变。
可选地，隔垫物3在第一衬底10上的正投影的边缘与对位部110在第一衬底10上的正投影的边缘之间的间距可为第一间距，此第一间距与数据线11的主线部111在行方向X上的尺寸之间的比值为50％至100％；比如：数据线11的主线部111在行方向X上的尺寸为5μm至6μm，第一衬底10上的正投影的边缘之间的间距(即：第一间距)可为3μm至5μm，比如：3μm、4μm、5μm等等，以满足对位偏差的需求。需要说明的是，隔垫物3在第一衬底10上的正投影的边缘与对位部110在第一衬底10上的正投影的边缘之间的间距不限于3μm至5μm，也可大于5μm等等，具体视产线中彩膜基板2与阵列基板1的对位偏差而定。
此外，如图4和图5b所示，数据线11还具有位于主线部111和对位部110之间的过渡部112，此过渡部112在第一衬底10上的正投影可位于第一布线区10b和第二布线区10c的交叉区上，但不限于此，过渡部112的部分在第一衬底10上的正投影也可位于第二布线区10c并不与第一布线区10b交叠。
其中，如图5b所示，过渡部112在行方向X上的尺寸可略大于主线部111在行方向X上的尺寸，并小于对位部110在行方向X上的尺寸，但不限于此，过渡部112在行方向X上的尺寸也可等于主线部111在行方向X上的尺寸。
需要说明的是，如图4和图5b所示，数据线11的对位部110在第一衬底10上的正投影与位于第一布线区10b上的栅线12在第一衬底10上的正投影不交叠，过渡部112在第一衬底10上的正投影与位于第一布线区10b上的栅线12在第一衬底10上的正投影交叠，由于过渡部112在行方向X上的尺寸小于对位部110在行方向X上的尺寸，因此，这样设计可减小数据线11与栅线12之间的重叠面积，从而可降低栅线12与数据线11之间的电容，继而可保证阵列基板1的性能。
由于对位部110的面积较大，因此，如图5b所示，通过对位部110与相邻两列的子像素单元13的漏电极1323电连接，以实现数据线11与相邻两列的子像素单元13电连接，这样设计在保证数据线11与相邻两列的子像素单元13电连接可靠的同时，还可降低工艺难度。
在一些实施例中，如图2、图4和图5b所示，第一衬底10上的第一布线区10b上可设置有两条栅线12；每条栅线和与其相邻的一行子像素单元13中的至少部分子像素单元电连接。
除此之外，如图2、图4、图5b所示，第一布线区10b还可设置公共线14，此公共线14可与栅线12同层设置，并与一行子像素单元13中各子像素单元13的公共电极130搭接，以实现公共线14与公共电极130之间的电性连接。
应当理解的是，为了方便子像素单元13与数据线11、栅线12和公共线14连接，子像素单元13的部分可位于第一布线区10b内，如图2和图4所示。
如图2、图4、图5b所示，在第一布线区10b设置两条栅线12时，数据线11的对位部110在第一衬底10上的正投影位于两条栅线在第一衬底10上的正投影之间，这样设计在减小数据线11与两条栅线12之间的重叠面积的同时，还可使得数据线11的对位部110尽量靠近第一布线区10b和第二布线区10c相交区域的中心位置，即：保证隔垫物3尽量靠近第一布线区10b和第二布线区10c相交区域的中心位置，从而可避免隔垫物3在压力测试过程中滑出交叉遮挡部222的遮挡范围。
在一些实施例中，如图5b和图6所示，当隔垫物3形成在彩膜基板2上时，第一衬底10上还形成有位于隔垫物3在列方向Y上相对两侧的挡墙18，挡墙18中远离第一衬底10的表面相较于隔垫物3中靠近第一衬底10的表面远离第一衬底10，且相较于隔垫物3中远离第一衬底10的表面靠近第一衬底10。本公开的实施例中，通过设置挡墙18可对隔垫物3在列方向Y上的滑动位移进行限定，从而可避免隔垫物3在压力测试过程中滑出被遮挡的区域。
应当理解的是，本公开的实施例中不限于在隔垫物3在列方向Y上的相对两侧设置挡墙18，也可在行方向X上或者其他方向上设置挡墙18。
可选地，挡墙18与隔垫物3之间的间距为第二间距，此第二间距与数据线11的主线部111在行方向X上的尺寸之间的比值为2.5至8；比如：数据线11的主线部111在行方向X上的尺寸为5μm至6μm；挡墙18与隔垫物3之间的间距(即： 第二间距)可为15μm至40μm，比如：15μm、20μm、25μm、30μm、35μm、40μm，通过将挡墙18与隔垫物3之间的间距设计为大于或等于15μm，可避免间距过小而导致挡墙18无法阻止隔垫物3滑动的情况；通过将挡墙18与隔垫物3之间的间距设计为小于或等于40μm，可避免间距过大而导致挡墙18的设置失去意义。
在一些实施例中，如图5b和图6所示，数据线11的过渡部112和栅线12在第一衬底10上的正投影相交叠，其交叠位置可定义为阻挡位；其中，挡墙18可包括过渡部112中位于阻挡位的部分和栅线12中位于阻挡位的部分，也就是说，本公开实施例的挡墙18可由数据线11与栅线12相交叠的部位形成，这样设计不需要在通过其他工艺设置挡墙18，可降低加工成本。
其中，如图5b和图6所示，数据线11的过渡部112和公共线14在第一衬底10上的正投影相交叠，其相交叠的部位也可形成挡墙18。
应当理解的是，由于数据线11与薄膜晶体管132的源电极1322、漏电极1323同层设置，栅线12、公共线14与薄膜晶体管132的栅极1320同层设置，因此，数据线11与栅线12、公共线14之间相交叠的部位之间还设置有第一绝缘层15，也就是说，挡墙18除了包括过渡部112中位于阻挡位的部分和栅线12(公共线14)中位于阻挡位的部分之外，还可包括第一绝缘层15中位于阻挡位的部分；此外，还可包括第二绝缘层16中位于阻挡为的部分。
在一些实施例中，如图7所示，彩膜基板2中遮挡层22的交叉遮挡部222在列方向Y上的尺寸大于第一遮挡部220在列方向Y上的尺寸，且交叉遮挡部222在行方向X上的尺寸大于第二遮挡部221在行方向X上的尺寸；这样设计可避免隔垫物3在压力测试过程中滑出被遮挡的区域。
可选地，如图7所示，隔垫物3在第二衬底20上的正投影位于交叉遮挡部在222在第二衬底20上的正投影的中心区域，且隔垫物3在第一衬底10上的正投影的边缘与交叉遮挡部222在第一衬底10上的正投影的边缘之间的间距为第三间距，此第三间距与数据线11的主线部111在行方向X上的尺寸之间的比值为6.5至12；比如：数据线11的主线部111在行方向X上的尺寸为5μm至6μm；隔垫物3在第一衬底10上的正投影的边缘与交叉遮挡部222在第一衬底10上的正投影的边缘之间的间距(即：第三间距)可为40μm至60μm，比如：40μm、45μm、50μm、55μm、60μm等等，以避免隔垫物3在压力测试过程中滑出被遮挡的区域。
其中，遮挡层22还具有位于交叉遮挡部222与第一遮挡部220之间的过渡遮挡部223，自第一遮挡部220至交叉遮挡部222的方向上，过渡遮挡部223在列方向Y上的尺寸逐渐增大；其中，过渡遮挡部223与第一遮挡部220之间相对的两端面完全重叠，过渡遮挡部223与交叉遮挡部222之间相对的两端面完全重叠；通过设置过渡遮挡部，在避免隔垫物3在压力测试过程中滑出被遮挡的区域的同时，还可减 小遮挡层22的遮挡面积，从而可提高像素开口率。
其中，彩膜基板2还可设置彩膜层21，此彩膜层21可形成在遮挡层22远离第二衬底20的一侧，此彩膜层21可包括阵列排布的红、绿、蓝等颜色的滤光结构。
在一些实施例中，隔垫物3可先形成在彩膜基板2上，然后再使彩膜基板2与阵列基板1进行对盒，但不限于此，隔垫物3也可先形成在阵列基板1上，然后再使彩膜基板2与阵列基板1进行对盒。
其中，隔垫物3可设置有多个，多个隔垫物3的设置可以提高显示面板整体厚度的均一性，提高显示面板对液晶4波动的容忍度，进而提高显示面板的良率。多个隔垫物中可包括主隔垫物和辅隔垫物，主隔垫物可如图6所示的隔垫物3，该主隔垫物在显示面板未收到外界压力时，其两端可分别与阵列基板1和彩膜基板2相接触，主要起到支撑作用；而辅隔垫物(图中未示出)在显示面板未收到外界压力时，辅隔垫物若形成在彩膜基板2上，该辅隔垫物与阵列基板1之间具有一定的间距，也就是说，主隔垫物与辅隔垫物之间存在段差(高度差)，通过调节主隔垫物与辅隔垫物之间的段差可以对显示面板的厚度进行微调。示例地，主隔垫物的高度大于辅隔垫物的高度，当显示面板受到外界压力时，主隔垫物先承受所有压力并压缩，当主隔垫物压缩至主隔垫物与辅隔垫物之间的段差降为0时，主隔垫物和辅隔垫物共同承受外界压力。
此外，还需要说明的是，隔垫物3的位置选择性设置，并非需要阵列基板1中每个第一布线区10b和第二布线区10c的交叉区域都对应设置隔垫物3，这样使得并非每个数据线中位于第一布线区10b和第二布线区10c的交叉区域的部位均设置对位部110，隔垫物3的具体数量、位置可根据实际需求而定。
本公开的实施例还提供了一种显示装置，其包括上述任一实施例所描述的显示面板。此显示装置可为液晶显示装置。
根据本公开的实施例，该显示装置的具体类型不受特别的限制，本领域常用的显示装置类型均可，具体例如液晶显示屏、手机、笔记本电脑等移动装置、手表等可穿戴设备、VR装置等等，本领域技术人员可根据该显示设备的具体用途进行相应地选择，在此不再赘述。
需要说明的是，该显示装置除了显示面板以外，还包括其他必要的部件和组成，以显示器为例，还可包括背光模组、外壳、主电路板、电源线，等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本公开旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (12)

  1. 一种显示面板，其中，包括：
    阵列基板，包括第一衬底、栅线、数据线及多个子像素单元，所述第一衬底具有呈阵列排布的多个子像素区、位于相邻两行子像素区之间的第一布线区及位于相邻两列子像素区之间的第二布线区，所述第一布线区与所述第二布线区相交；每一所述子像素单元的至少部分位于一所述子像素区上；所述栅线位于所述第一布线区上并与所述子像素单元电连接，所述数据线位于所述第二布线区上并与所述子像素单元电连接，所述数据线与所述栅线相互绝缘且在所述第一衬底上的正投影相交，所述数据线具有对位部，所述对位部在所述第一衬底上的正投影位于所述第一布线区和所述第二布线区相交叉的区域内；
    隔垫物，设置在所述对位部背离所述阵列基板的一侧，所述隔垫物在所述第一衬底上的正投影位于所述对位部在所述第一衬底上的正投影内。
  2. 根据权利要求1所述的显示面板，其中，
    所述数据线还具有位于所述对位部在列方向上相对两侧的主线部，所述主线部在所述第一衬底上的正投影与所述第一布线区在所述第一衬底上的正投影不交叠，且所述主线部在行方向上的尺寸小于所述对位部在行方向上的尺寸。
  3. 根据权利要求2所述的显示面板，其中，
    从所述对位部靠近所述主线部的一侧至所述对位部的中心的方向上，所述对位部在所述行方向上的尺寸逐渐增大。
  4. 根据权利要求2所述的显示面板，其中，
    所述隔垫物在所述第一衬底上的正投影的边缘与所述对位部在所述第一衬底上的正投影的边缘之间的间距为第一间距；
    其中，所述第一间距与所述数据线的主线部在行方向上的尺寸之间的比值为50％至100％。
  5. 根据权利要求2所述的显示面板，其中，
    所述第一布线区上设置有两条所述栅线，每条所述栅线和与其相邻的一行子像素单元中的至少部分子像素单元电连接；
    所述对位部在所述第一衬底上的正投影位于两条所述栅线在所述第一衬底上的正投影之间。
  6. 根据权利要求5所述的显示面板，其中，
    所述第一衬底上还形成有位于所述隔垫物在所述列方向上相对两侧的挡墙；
    所述挡墙与所述隔垫物之间的间距为第二间距；
    其中，所述第二间距与所述数据线的主线部在行方向上的尺寸之间的比值为2.5至8。
  7. 根据权利要求6所述的显示面板，其中，
    所述数据线还具有位于所述主线部和所述对位部之间的过渡部；所述过渡部和所述栅线在所述第一衬底上的正投影相交叠，其交叠位置定义为阻挡位；
    所述挡墙包括所述过渡部中位于所述阻挡位的部分和所述栅线中位于所述阻挡位的部分。
  8. 根据权利要求2所述的显示面板，其中，所述对位部与相邻两列的子像素单元电连接。
  9. 根据权利要求2所述的显示面板，其中，还包括彩膜基板，所述彩膜基板包括位于所述隔垫物远离所述阵列基板一侧的第二衬底及位于所述第二衬底靠近所述阵列基板一侧的遮挡层，所述遮挡层具有交叉遮挡部、位于所述交叉遮挡部在行方向相对两侧的第一遮挡部、以及位于所述交叉遮挡部在列方向上相对两侧的第二遮挡部；其中，
    所述交叉遮挡部在所述第一衬底上的正投影至少覆盖所述第一布线区与所述第二布线区的交叉区域，所述第一遮挡部在所述第一衬底上的正投影至少覆盖所述第一布线区且不与所述第二布线区交叠，所述第二遮挡部在所述第一衬底上的正投影至少覆盖所述第二布线区且不与所述第一布线区相交叠；
    所述交叉遮挡部在列方向上的尺寸大于所述第一遮挡部在列方向上的尺寸，且所述交叉遮挡部在行方向上的尺寸大于所述第二遮挡部在行方向上的尺寸。
  10. 根据权利要求9所述的显示面板，其中，所述隔垫物在所述第二衬底上的正投影位于所述交叉遮挡部在所述第二衬底上的正投影的中心区域内，
    所述隔垫物在所述第一衬底上的正投影的边缘与所述交叉遮挡部在所述第一衬底上的正投影的边缘之间的间距为第三间距；
    其中，所述第三间距与所述数据线的主线部在行方向上的尺寸之间的比值为6.5至12。
  11. 根据权利要求9所述的显示面板，其中，所述遮挡层还具有位于所述交叉遮挡部与所述第一遮挡部之间的过渡遮挡部；所述过渡遮挡部与所述第一遮挡部之间相对的两端面完全重叠，所述过渡遮挡部与所述交叉遮挡部之间相对的两端面完全重叠。
  12. 一种显示装置，其中，包括权利要求1至11中任一项所述的显示面板。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111338144B (zh) * 2020-04-14 2023-08-18 京东方科技集团股份有限公司 显示面板及显示装置
CN113985634A (zh) * 2020-07-27 2022-01-28 京东方科技集团股份有限公司 显示面板及显示装置
CN114981719B (zh) * 2020-10-30 2023-09-01 京东方科技集团股份有限公司 电极结构、显示面板及显示装置
US11984453B2 (en) 2021-01-29 2024-05-14 Boe Technology Group Co., Ltd. Array substrate, display panel and electronic device
US20240096902A1 (en) * 2021-04-27 2024-03-21 Beijing Boe Display Technology Co., Ltd. Dual gate array substrate and display panel
CN115373186A (zh) * 2021-05-21 2022-11-22 北京京东方显示技术有限公司 一种显示面板及显示装置
CN114280867B (zh) * 2021-12-29 2023-06-09 惠科股份有限公司 阵列基板、显示面板及显示装置
CN115509050B (zh) * 2022-10-09 2024-09-24 厦门天马微电子有限公司 显示面板和显示装置
WO2024182965A1 (zh) * 2023-03-06 2024-09-12 京东方科技集团股份有限公司 阵列基板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012124699A1 (ja) * 2011-03-17 2012-09-20 シャープ株式会社 液晶表示装置
CN103487994A (zh) * 2013-05-22 2014-01-01 友达光电股份有限公司 液晶显示面板
US20170192281A1 (en) * 2016-01-06 2017-07-06 Samsung Display Co. Ltd. Liquid crystal display device
CN110121675A (zh) * 2017-01-06 2019-08-13 夏普株式会社 弯曲显示面板
CN110119055A (zh) * 2018-02-05 2019-08-13 夏普株式会社 显示装置
CN111338144A (zh) * 2020-04-14 2020-06-26 京东方科技集团股份有限公司 显示面板及显示装置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003066433A (ja) * 2001-08-28 2003-03-05 Hitachi Ltd 液晶表示装置
JP4717533B2 (ja) * 2005-07-06 2011-07-06 株式会社 日立ディスプレイズ 表示装置
KR20070055301A (ko) * 2005-11-25 2007-05-30 삼성전자주식회사 컬러 필터용 블랙 매트릭스의 제조방법
CN100587571C (zh) * 2006-09-22 2010-02-03 北京京东方光电科技有限公司 一种薄膜晶体管在彩膜之上的液晶显示器件及其制造方法
CN101738787B (zh) * 2008-11-12 2013-01-23 北京京东方光电科技有限公司 液晶显示器阵列基板及其制造方法
KR101868036B1 (ko) * 2011-12-22 2018-06-18 엘지디스플레이 주식회사 노광 마스크 및 이를 이용한 액정표시장치의 제조방법
CN103336391B (zh) * 2013-06-28 2016-02-03 深圳市华星光电技术有限公司 液晶显示面板
KR20150146111A (ko) * 2014-06-20 2015-12-31 삼성디스플레이 주식회사 액정 표시 장치
TWI548911B (zh) * 2015-08-26 2016-09-11 友達光電股份有限公司 顯示面板
CN105572996B (zh) * 2016-02-02 2019-01-25 京东方科技集团股份有限公司 一种双栅极阵列基板及显示装置
CN106324923B (zh) * 2016-10-18 2020-02-14 上海中航光电子有限公司 阵列基板及显示面板
CN106855674B (zh) * 2017-03-23 2020-01-07 厦门天马微电子有限公司 阵列基板、显示面板和显示装置
CN110767661B (zh) * 2018-07-27 2023-07-07 京东方科技集团股份有限公司 阵列基板及其制备方法、显示装置
CN110824795A (zh) * 2019-10-18 2020-02-21 深圳市华星光电半导体显示技术有限公司 一种基板及液晶显示面板

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012124699A1 (ja) * 2011-03-17 2012-09-20 シャープ株式会社 液晶表示装置
CN103487994A (zh) * 2013-05-22 2014-01-01 友达光电股份有限公司 液晶显示面板
US20170192281A1 (en) * 2016-01-06 2017-07-06 Samsung Display Co. Ltd. Liquid crystal display device
CN110121675A (zh) * 2017-01-06 2019-08-13 夏普株式会社 弯曲显示面板
CN110119055A (zh) * 2018-02-05 2019-08-13 夏普株式会社 显示装置
CN111338144A (zh) * 2020-04-14 2020-06-26 京东方科技集团股份有限公司 显示面板及显示装置

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