WO2019033505A1 - 一种阵列基板及该阵列基板的制备方法 - Google Patents

一种阵列基板及该阵列基板的制备方法 Download PDF

Info

Publication number
WO2019033505A1
WO2019033505A1 PCT/CN2017/102614 CN2017102614W WO2019033505A1 WO 2019033505 A1 WO2019033505 A1 WO 2019033505A1 CN 2017102614 W CN2017102614 W CN 2017102614W WO 2019033505 A1 WO2019033505 A1 WO 2019033505A1
Authority
WO
WIPO (PCT)
Prior art keywords
conductive transparent
layer
data line
pixel electrode
transparent layer
Prior art date
Application number
PCT/CN2017/102614
Other languages
English (en)
French (fr)
Inventor
赵阳
陈剑鸿
Original Assignee
深圳市华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电半导体显示技术有限公司 filed Critical 深圳市华星光电半导体显示技术有限公司
Priority to US15/739,732 priority Critical patent/US10312265B2/en
Publication of WO2019033505A1 publication Critical patent/WO2019033505A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136227—Through-hole connection of the pixel electrode to the active element through an insulation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes

Definitions

  • the present invention relates to the field of display technologies, and in particular, to an array substrate and a method for preparing the array substrate.
  • the pixel electrode can only overlap or partially overlap the data line.
  • the inventors of the present application have found in the long-term research that in the current display panel structure, the pixel electrode is easily affected by the electric field coupling generated by the data line, so that the screen displayed on the display panel is prone to crosstalk.
  • the technical problem to be solved by the present invention is to provide an array substrate and a method for preparing the array substrate, which can reduce the interference of the pixel electrode in the array substrate by the electric field of the data line.
  • an array substrate comprising:
  • a thin film transistor disposed on the base substrate, a data line electrically connected to a source of the thin film transistor, and a pixel electrode electrically connected to a drain of the thin film transistor;
  • the data line and the pixel electrode are respectively disposed in different layers, and the data line overlaps with a vertical projection of the pixel electrode on the same plane, and further between the data line and the layer where the pixel electrode is located.
  • a conductive transparent layer is disposed, the conductive transparent layer is provided with a via hole, and the pixel electrode is electrically connected to the drain of the thin film transistor through the via hole, the data line, the conductive transparent layer, the The pixel electrodes are stacked and insulated from each other.
  • an array substrate comprising:
  • a thin film transistor disposed on the base substrate, a data line electrically connected to a source of the thin film transistor, and a pixel electrode electrically connected to a drain of the thin film transistor;
  • the data line and the pixel electrode are respectively disposed in different layers, and a conductive transparent layer is further disposed between the data line and the layer where the pixel electrode is located, the data line, the conductive transparent layer, and the The pixel electrodes are stacked and insulated from each other.
  • another technical solution adopted by the present invention is to provide a method for preparing an array substrate, the method comprising:
  • the data line and the pixel electrode are respectively disposed in different layers, and the conductive transparent layer is located between the data line and the layer where the pixel electrode is located, the data line, the conductive transparent layer, and the The pixel electrodes are stacked and insulated from each other.
  • the array substrate in the present invention has a conductive transparent layer disposed between the data line and the layer where the pixel electrode is located, and the conductive transparent layer functions as a metal shield to reduce the data line. Interference with the electric field generated by the pixel electrode.
  • FIG. 1 is a schematic plan view showing a plan view of an embodiment of an array substrate of the present invention
  • FIG. 2 is a partial cross-sectional structural view of the array substrate of FIG. 1 taken along the A-B direction;
  • FIG. 3 is a partial cross-sectional structural view of the array substrate of FIG. 1 taken along the A-B direction of FIG. 1 in an application scenario;
  • FIG. 4 is a partial cross-sectional view of the array substrate of the present invention taken along the line A-B of FIG. 1; Figure.
  • FIG. 5 is a schematic flow chart of an embodiment of a method for preparing an array substrate of the present invention.
  • FIG. 1 is a schematic plan view showing a structure of an array substrate according to an embodiment of the present invention
  • FIG. 2 is a partial cross-sectional structural view of the array substrate of FIG. 1 along the A-B direction.
  • the array substrate includes a base substrate 100, a thin film transistor 200, a data line 300, a pixel electrode 400, and a conductive transparent layer 500.
  • the base substrate 100 has excellent optical properties, and high transparency and low reflectance can be made, for example, of a glass material.
  • the source 201 of the thin film transistor 200 is electrically connected to the data line 300, and the drain 202 of the thin film transistor 200 is electrically connected to the pixel electrode 400.
  • the data line 300 inputs a data signal to the source 201 and is input to the pixel electrode 400 through the drain 201.
  • the data line 300 and the pixel electrode 400 are respectively disposed in different layers.
  • the data line 300 is located in the same layer as the source 201 of the thin film transistor 200, and is made of the same metal material.
  • the conductive transparent layer 500 is located between the data line 300 and the layer where the pixel electrode 400 is located. Since the conductive transparent layer 500 shields the pixel electrode 400, it can reduce the electric field interference generated by the data line 300 on the pixel electrode 400.
  • the data line 300, the conductive transparent layer 500, and the pixel electrode 400 are stacked and insulated from each other, that is, the data line 300, the conductive transparent layer 500, and the pixel electrode 400 are not in the same layer.
  • the data line 300 is disposed under the pixel electrode 400 for illustration, that is, the data line 300 is disposed on a side relatively close to the substrate 100, and the pixel electrode 400 is disposed relatively far from the substrate.
  • the data line 300 may be disposed above the pixel electrode 400 according to the design requirements.
  • the electric field effect of the data line 300 can be reduced to the pixel electrode due to the shielding effect of the conductive transparent layer 500 on the pixel electrode 400. 400 effect, mitigating data line 300 to pixel electrode 400
  • the generated electric field interference can reduce the image crosstalk and flicker phenomenon on the screen when the array substrate is applied to the display device, and improve the display picture quality.
  • the material of the conductive transparent layer 500 is indium tin oxide (ITO).
  • ITO indium tin oxide
  • the material of the conductive transparent layer 500 may also be other conductive transparent materials, such as: indium zinc oxide (TZO), indium oxide (In 2 O 3 ), etc., where the conductive transparent layer 500 is Materials are not restricted.
  • the data line 300 overlaps with the vertical projection of the pixel electrode 400 on the same plane.
  • the pixel width is only 18.75 ⁇ m, in order to ensure a sufficient aperture ratio, the data line 300
  • the vertical projection of the same plane as the pixel electrode 400 overlaps. It can be understood that the size of the overlapping area between the data line 300 and the pixel electrode 400 is not limited herein, and the data line 300 can completely overlap the pixel electrode 400. It is also possible to overlap only a part.
  • a via hole (not shown) is provided in the conductive transparent layer 500, and the pixel electrode 400 is electrically connected to the drain 201 of the thin film transistor 200 through the via hole.
  • the array substrate further includes a common electrode (not shown), and the conductive transparent layer 500 is electrically connected to the common electrode and has the same potential as the common electrode, that is, the conductive transparent layer 500 and the common electrode. It has a zero potential as well, so it can shield the pixel electrode 400 and can prevent charges from accumulating on the conductive transparent layer 500.
  • the common electrode can also be disposed on the color filter substrate opposite to the array substrate, and the common electrode line is disposed on the array substrate, and the conductive transparent layer 500 can pass through the common electrode line. It is electrically connected to the common electrode so as to have the same potential as the common electrode.
  • the conductive transparent layers 500 corresponding to the different pixel electrodes 400 may be the same conductive transparent layer or may not be the same conductive transparent layer.
  • the conductive transparent layer 500 corresponding to the different pixel electrodes 400 is the same conductive transparent layer.
  • the conductive transparent layer 500 corresponding to the different pixel electrodes 400 is in the same layer, and the conductive transparent layer 500 corresponding to the different pixel electrodes 400 is continuous.
  • Uninterrupted that is, the vertical projection of the conductive transparent layer 400 covers an entire surface of the array substrate; the conductive transparent layer 500 corresponding to the different pixel electrodes 400 is not the same conductive transparent layer: the conductive transparent layer 500 corresponding to the different pixel electrodes 400 The interval is broken, not a continuous whole layer.
  • the different conductive transparent layers 500 are electrically connected to each other and have the same potential.
  • the conductive transparent layer 500 is between the data line 300 and the layer where the pixel electrode 400 is located, and in particular, for a single pixel unit, the vertical projection of the conductive transparent layer 500 completely covers the pixel electrode 400 in the same plane.
  • the vertical projection that is, the vertical projection of the conductive transparent layer 500 completely covers the vertical projection of the pixel opening area, and functions to optimize the liquid crystal reversal.
  • the array substrate further includes: a color photoresist layer 600 and a planar protective layer 700 .
  • the color photoresist layer 600 and the flat protective layer 700 are located between the conductive transparent layer 500 and the layer where the pixel electrode 400 is located.
  • the color photoresist layer 600 is located on a side of the conductive transparent layer 500 away from the data line 300, and the flat protective layer 700 is located on a side of the color photoresist layer 600 away from the conductive transparent layer 500.
  • the flat protective layer 700 is an organic material coating having a thickness of 2-3 ⁇ m, which serves to protect and flatten the color photoresist layer 600.
  • the material of the planar protective layer 700 is good. Chemically resistant, high temperature resistant soluble polytetrafluoroethylene (PFA).
  • the color resist layer 600 is formed on the array substrate, which can effectively solve the problem of light leakage caused by the alignment deviation in the process of the liquid crystal display device, and can also significantly increase the aperture ratio.
  • FIG. 5 is a schematic flow chart of an embodiment of a method for fabricating an array substrate according to the present invention.
  • the preparation method includes:
  • the base substrate 100 has excellent optical properties, and high transparency and low reflectance can be made, for example, of a glass material.
  • a thin film transistor 200, a data line 300 electrically connected to the source 201 of the thin film transistor 200, a conductive transparent layer 500, and a pixel electrode 400 electrically connected to the drain 202 of the thin film transistor 200 are formed on the base substrate.
  • the data line 300 and the pixel electrode 400 are respectively disposed in different layers, and the conductive transparent layer 500 is located between the data line 300 and the layer where the pixel electrode 400 is located.
  • the data line 300, the conductive transparent layer 500, and the pixel electrode layer 400 are stacked and mutually connected. Insulation between.
  • the material of the conductive transparent layer 500 is indium tin oxide (ITO).
  • forming a pixel Before the pole 400 also includes:
  • a color photoresist layer 600 and a flat protective layer 700 covering the color photoresist layer 600 are sequentially formed.
  • the color photoresist layer 600 is located on a side of the conductive transparent layer 500 away from the data line 300, and the flat protective layer 700 is located on a side of the color photoresist layer 600 away from the conductive transparent layer 500.
  • the flat protective layer 700 protects and flattens the color photoresist layer 600.
  • the material of the flat protective layer 700 is a soluble polytetrafluoroethylene having good chemical resistance and high temperature resistance. Ethylene (PFA).
  • the method for fabricating the array substrate of the present invention is the method for preparing the array substrate according to any of the above embodiments.
  • the structure of the array substrate refer to the above embodiments, and details are not described herein again.
  • the array substrate of the present invention can reduce the electric field interference generated by the data line to the pixel electrode by providing a conductive transparent layer between the data line and the layer where the pixel electrode is located.
  • each layer is not limited to one element, and can be various; in addition, it can be understood that when an element or layer is referred to as being "on one another" On the component, there may be an intermediate layer.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)

Abstract

一种阵列基板及阵列基板的制备方法，阵列基板包括：衬底基板（100）；设置在衬底基板（100）上的薄膜晶体管（200）、与薄膜晶体管（200）的源极（201）电连接的数据线（300）、与薄膜晶体管（200）的漏极（202）电连接的像素电极（400）；其中，数据线（300）与像素电极（400）分别设置在不同层中，数据线（300）与像素电极（400）所在层之间进一步设有导电透明层（500），数据线（300）、导电透明层（500）、像素电极层（400）叠设置且相互之间绝缘。能够减少阵列基板中像素电极受到数据线电场的干扰。

Description

一种阵列基板及该阵列基板的制备方法 【技术领域】
本发明涉及显示技术领域，特别是涉及一种阵列基板及该阵列基板的制备方法。
【背景技术】
随着显示技术的发展，液晶显示器等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛的应用于手机、电视、个人数字助理、数字相机、笔记本电脑等各种消费性电子产品，成为显示装置中的主流。
目前，随着液晶显示器分辨率的不断提高，单个像素的尺寸越来越小，这就使得像素电极与数据线之间的距离越来越小，甚至对于超高解析度的面板来说，为了保证足够的开口率以及液晶电容的大小，像素电极只能与数据线交叠或者部分重叠。
本申请的发明人在长期的研究中发现，目前的显示面板结构，像素电极容易受到数据线产生的电场耦合影响，从而显示面板显示的画面容易发生串扰(Crosstalk)现象。
【发明内容】
本发明主要解决的技术问题是提供一种阵列基板及该阵列基板的制备方法，能够减少阵列基板中像素电极受到数据线电场的干扰。
为解决上述技术问题，本发明采用的一个技术方案是：提供一种阵列基板，该阵列基板包括：
衬底基板；
设置在衬底基板上的薄膜晶体管、与所述薄膜晶体管的源极电连接的数据线、与所述薄膜晶体管的漏极电连接的像素电极；
其中，所述数据线与所述像素电极分别设置在不同层中，所述数据线与所述像素电极在同一平面的垂直投影有重叠，所述数据线与所述像素电极所在层之间进一步设有导电透明层，所述导电透明层上设有过孔，所述像素电极通过所述过孔与所述薄膜晶体管的漏极电连接，所述数据线、所述导电透明层、所述像素电极层叠设置且相互之间绝缘。
为解决上述技术问题，本发明采用的另一个技术方案是：提供一种阵列基板，该阵列基板包括：
衬底基板；
设置在衬底基板上的薄膜晶体管、与所述薄膜晶体管的源极电连接的数据线、与所述薄膜晶体管的漏极电连接的像素电极；
其中，所述数据线与所述像素电极分别设置在不同层中，所述数据线与所述像素电极所在层之间进一步设有导电透明层，所述数据线、所述导电透明层、所述像素电极层叠设置且相互之间绝缘。
为解决上述技术问题，本发明采用的又一个技术方案是：提供一种阵列基板的制备方法，该方法包括：
提供一衬底基板；
在所述衬底基板上形成薄膜晶体管、与所述薄膜晶体管的源极电连接的数据线、导电透明层、与所述薄膜晶体管的漏极电连接的像素电极；
其中，所述数据线与所述像素电极分别设置在不同层中，所述导电透明层位于所述数据线与所述像素电极所在层之间，所述数据线、所述导电透明层、所述像素电极层叠设置且相互之间绝缘。
本发明的有益效果是：区别于现有技术的情况，本发明中的阵列基板通过在数据线与像素电极所在层之间设置导电透明层，导电透明层起到金属屏蔽作用，能够减轻数据线对像素电极产生的电场干扰。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是本发明阵列基板一实施方式的俯面结构示意图；
图2是图1中阵列基板沿A-B方向的部分剖面结构示意图；
图3是图1中阵列基板在一应用场景下沿图1中A-B方向的部分剖面结构示意图；
图4是本发明阵列基板另一实施方式沿图1中A-B方向的部分剖面结构示意 图。
图5是本发明阵列基板的制备方法一实施方式的流程示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
参阅图1和图2，图1是本发明阵列基板一实施方式的俯面结构示意图，图2是图1中阵列基板沿A-B方向的部分剖面结构示意图。该阵列基板包括：衬底基板100、薄膜晶体管200、数据线300、像素电极400以及导电透明层500。
衬底基板100具有优良的光学性能，较高的透明度和较低的反射率例如，可采用玻璃材料制成。
薄膜晶体管200的源极201与数据线300电连接、薄膜晶体管200的漏极202与像素电极400电连接。当薄膜晶体管200被打开时，数据线300输入数据信号至源极201，并经过漏极201输入像素电极400。
数据线300与像素电极400分别设置在不同层中，一般而言，数据线300与薄膜晶体管200的源极201位于同一层，采用相同的金属材料制成。导电透明层500位于数据线300与像素电极400所在层之间，由于导电透明层500对像素电极400产生屏蔽作用，因此，其可减少数据线300对像素电极400产生的电场干扰。
数据线300、导电透明层500、像素电极400层叠设置且相互之间绝缘，即数据线300、导电透明层500、像素电极400均不在同一层。
需要说明的是，在本实施方式中以数据线300设置在像素电极400的下面进行示意说明，即数据线300设置在相对靠近衬底基板100的一侧，像素电极400设置在相对远离衬底基板100的同一侧，但本发明实施方式并不限制于此，数据线300也可根据设计的需要而设置在像素电极400的上方。
上述实施方式中，通过在像素电极400所在层与数据线300所在层之间设置导电透明层500，由于导电透明层500对像素电极400的屏蔽作用，可减少数据线300的电场效应对像素电极400的影响，减轻数据线300对像素电极400 产生的电场干扰，当阵列基板应用于显示装置的情况下，可减少画面出现图像串扰和闪烁现象，提高显示画面质量。
在上述实施方式的一个应用场景中，导电透明层500的材料为铟锡氧化物(ITO)。当然，在其他应用场景中，导电透明层500的材料也可以为其他导电透明材料，如：铟锌氧化物(TZO)、氧化铟(In2O3)等，在此对导电透明层500的材料不做限制。
参阅图3，在上述实施例的另一个应用场景中，数据线300与像素电极400在同一平面的垂直投影有重叠。
对于超高解析度的面板，例如目前正在开发的39”16K8K HVA(High Vertical Alignment，高垂直排列)液晶模式的面板来说，其像素宽度只有18.75μm，为了保证足够的开口率，数据线300与像素电极400在同一平面的垂直投影有重叠。可以理解的是，在此对数据线300与像素电极400之间重叠面积的大小不做任何限制，数据线300既可以与像素电极400完全重叠，也可以只重叠一部分。
其中，在本实施方式中，导电透明层500上设有过孔(图未示)，像素电极400通过该过孔与薄膜晶体管200的漏极201电连接。
其中，在本实施方式中，阵列基板进一步还包括公共电极(图未示)，导电透明层500与公共电极电连接，具有和公共电极一样的电位，也就是说，导电透明层500与公共电极一样具有零电位，因此其能够对像素电极400产生屏蔽作用，且能避免电荷聚集在导电透明层500上。此外，本领域的技术人员也可以理解的是，公共电极也可以设置在与阵列基板相对的彩色滤光片基板上，而阵列基板上设有公共电极线，导电透明层500可通过公共电极线而与公共电极电连接，从而具有和公共电极一样的电位。
可选地，在本实施方式中，当阵列基板包括多个薄膜晶体管200时，不同像素电极400对应的导电透明层500既可以是同一个导电透明层，也可以不是同一个导电透明层。其中，不同像素电极400对应的导电透明层500是同一个导电透明层指的是：不同像素电极400对应的导电透明层500在同一层，且不同像素电极400对应的导电透明层500之间连续不间断，即导电透明层400的垂直投影覆盖阵列基板的一整面；不同像素电极400对应的导电透明层500不是同一个导电透明层指的是：不同像素电极400对应的导电透明层500之间被间隔断开，不是连续的一个整层。当不同像素电极400对应的导电透明层500 不是同一个导电透明层时，不同的导电透明层500之间电连接，具有相同的电位。
同时在本实施方式中，导电透明层500在数据线300与像素电极400所在层之间，具体对于单个的像素单元来说，在同一平面内，导电透明层500的垂直投影完全覆盖像素电极400的垂直投影，即，导电透明层500的垂直投影完全覆盖像素开口区的垂直投影，起到优化液晶倒向的作用。
参阅图4，在本发明阵列基板另一实施方式中，该阵列基板进一步还包括：彩色光阻层600以及平坦保护层700。
彩色光阻层600以及平坦保护层700位于导电透明层500与像素电极400所在层之间。
彩色光阻层600位于导电透明层500远离数据线300的一侧，平坦保护层700位于彩色光阻层600远离导电透明层500的一侧。
具体地，平坦保护层700为有机材料涂层，其厚度为2-3μm，起到对彩色光阻层600进行保护和平坦的作用，在一个应用场景下，平坦保护层700的材料为具有良好的耐化学腐蚀性、耐高温性的可溶性聚四氟乙烯(PFA)。
在本实施方式中，将彩色光阻层600制作在阵列基板上，能够有效解决液晶显示装置对盒工艺中因对位偏差造成的漏光等问题，同时也能显著提高开口率。
参阅图5，图5是本发明阵列基板的制备方法一实施方式的流程示意图，该制备方法包括：
S101：提供一衬底基板100。
衬底基板100具有优良的光学性能，较高的透明度和较低的反射率例如可采用玻璃材料制成。
S102：在衬底基板上形成薄膜晶体管200、与薄膜晶体管200的源极201电连接的数据线300、导电透明层500、与薄膜晶体管200的漏极202电连接的像素电极400。
其中，数据线300与像素电极400分别设置在不同层中，导电透明层500位于数据线300与像素电极400所在层之间，数据线300、导电透明层500、像素电极层400叠设置且相互之间绝缘。
可选地，在本实施方式中导电透明层500的材料为铟锡氧化物(ITO)。
可选地，在一个应用场景中，在形成导电透明层500之后，在形成像素电 极400之前还包括：
S103：依次形成彩色光阻层600以及覆盖彩色光阻层600的平坦保护层700。
具体地，彩色光阻层600位于导电透明层500远离数据线300的一侧，平坦保护层700位于彩色光阻层600远离导电透明层500的一侧。
可选地，平坦保护层700对彩色光阻层600进行保护和平坦的作用，在一个应用场景下，平坦保护层700的材料为具有良好的耐化学腐蚀性、耐高温性的可溶性聚四氟乙烯(PFA)。
本发明中的阵列基板制备方法为上述任一项实施方式中的阵列基板的制备方法，具体的阵列基板结构请参见上述实施方式，在此不再赘述。
总而言之，区别于现有技术，本发明中的阵列基板通过在数据线与像素电极所在层之间设置导电透明层，能够减轻数据线对像素电极产生的电场干扰。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，每一层并不局限于一种元件，可以为多种；另外，可以理解的是当元件或层被称为在另一元件或层“一侧”时，它可以直接在其他元件上，或者可以存在中间的层。
以上所述仅为本发明的实施方式，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (15)

  1. 一种阵列基板，其中，包括：
    衬底基板；
    设置在衬底基板上的薄膜晶体管、与所述薄膜晶体管的源极电连接的数据线、与所述薄膜晶体管的漏极电连接的像素电极；
    其中，所述数据线与所述像素电极分别设置在不同层中，所述数据线与所述像素电极在同一平面的垂直投影有重叠，所述数据线与所述像素电极所在层之间进一步设有导电透明层，所述导电透明层上设有过孔，所述像素电极通过所述过孔与所述薄膜晶体管的漏极电连接，所述数据线、所述导电透明层、所述像素电极层叠设置且相互之间绝缘。
  2. 根据权利要求1所述的阵列基板，其中，
    所述阵列基板进一步还包括公共电极，所述导电透明层与所述公共电极电连接。
  3. 根据权利要求1所述的阵列基板，其中，
    所述导电透明层与所述像素电极所在层之间还包括彩色光阻层以及覆盖所述光阻层的平坦保护层，
    所述彩色光阻层位于所述导电透明层远离所述数据线的一侧，所述平坦保护层位于所述彩色光阻层远离所述导电透明层的一侧。
  4. 根据权利要求1所述的阵列基板，其中，
    所述导电透明层的材料为铟锡氧化物。
  5. 根据权利要求3所述的阵列基板，其中，
    所述平坦保护层的材料为可溶性聚四氟乙烯。
  6. 一种阵列基板，其中，包括：
    衬底基板；
    设置在衬底基板上的薄膜晶体管、与所述薄膜晶体管的源极电连接的数据线、与所述薄膜晶体管的漏极电连接的像素电极；
    其中，所述数据线与所述像素电极分别设置在不同层中，所述数据线与所述像素电极所在层之间进一步设有导电透明层，所述数据线、所述导电透明层、所述像素电极层叠设置且相互之间绝缘。
  7. 根据权利要求6所述的阵列基板，其中，
    所述数据线与所述像素电极在同一平面的垂直投影有重叠。
  8. 根据权利要求6所述的阵列基板，其中，
    所述导电透明层上设有过孔，所述像素电极通过所述过孔与所述薄膜晶体管的漏极电连接。
  9. 根据权利要求6所述的阵列基板，其中，
    所述阵列基板进一步还包括公共电极，所述导电透明层与所述公共电极电连接。
  10. 根据权利要求6所述的阵列基板，其中，
    所述导电透明层与所述像素电极所在层之间还包括彩色光阻层以及覆盖所述光阻层的平坦保护层，
    所述彩色光阻层位于所述导电透明层远离所述数据线的一侧，所述平坦保护层位于所述彩色光阻层远离所述导电透明层的一侧。
  11. 根据权利要求6所述的阵列基板，其中，
    所述导电透明层的材料为铟锡氧化物。
  12. 根据权利要求10所述的阵列基板，其中，
    所述平坦保护层的材料为可溶性聚四氟乙烯。
  13. 一种阵列基板的制备方法，其中，所述方法包括：
    提供一衬底基板；
    在所述衬底基板上形成薄膜晶体管、与所述薄膜晶体管的源极电连接的数据线、导电透明层、与所述薄膜晶体管的漏极电连接的像素电极；
    其中，所述数据线与所述像素电极分别设置在不同层中，所述导电透明层位于所述数据线与所述像素电极所在层之间，所述数据线、所述导电透明层、所述像素电极层叠设置且相互之间绝缘。
  14. 根据权利要求13所述的制备方法，其中，在形成所述导电透明层之后，在形成所述像素电极之前还包括：
    依次形成彩色光阻层以及覆盖所述彩色光阻层的平坦保护层，
    其中，所述彩色光阻层位于所述导电透明层远离所述数据线的一侧，所述平坦保护层位于所述彩色光阻层远离所述导电透明层的一侧。
  15. 根据权利要求13所述的制备方法，其中，
    所述导电透明层的材料为铟锡氧化物。
PCT/CN2017/102614 2017-08-17 2017-09-21 一种阵列基板及该阵列基板的制备方法 WO2019033505A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US15/739,732 US10312265B2 (en) 2017-08-17 2017-09-21 Array substrate and manufacturing method of array substrate for reducing electric field interference

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201710709567.XA CN107479280A (zh) 2017-08-17 2017-08-17 一种阵列基板及该阵列基板的制备方法
CN201710709567.X 2017-08-17

Publications (1)

Publication Number Publication Date
WO2019033505A1 true WO2019033505A1 (zh) 2019-02-21

Family

ID=60600878

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2017/102614 WO2019033505A1 (zh) 2017-08-17 2017-09-21 一种阵列基板及该阵列基板的制备方法

Country Status (2)

Country Link
CN (1) CN107479280A (zh)
WO (1) WO2019033505A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116449615B (zh) * 2023-06-13 2023-10-03 Tcl华星光电技术有限公司 显示面板及显示面板的驱动方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103715206A (zh) * 2013-12-31 2014-04-09 信利半导体有限公司 一种像素单元、阵列基板及显示面板
CN104142592A (zh) * 2013-05-07 2014-11-12 友达光电股份有限公司 液晶显示面板及其制造方法
CN105116582A (zh) * 2015-09-07 2015-12-02 昆山龙腾光电有限公司 液晶显示装置及其制作方法
CN105336747A (zh) * 2015-10-28 2016-02-17 深圳市华星光电技术有限公司 阵列基板及其修复方法
JP2016053637A (ja) * 2014-09-03 2016-04-14 セイコーエプソン株式会社 有機エレクトロルミネッセンス装置および電子機器
CN106773403A (zh) * 2016-12-29 2017-05-31 深圳市华星光电技术有限公司 像素单元结构及显示装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103676373A (zh) * 2013-11-27 2014-03-26 北京京东方光电科技有限公司 一种阵列基板及其制备方法、显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104142592A (zh) * 2013-05-07 2014-11-12 友达光电股份有限公司 液晶显示面板及其制造方法
CN103715206A (zh) * 2013-12-31 2014-04-09 信利半导体有限公司 一种像素单元、阵列基板及显示面板
JP2016053637A (ja) * 2014-09-03 2016-04-14 セイコーエプソン株式会社 有機エレクトロルミネッセンス装置および電子機器
CN105116582A (zh) * 2015-09-07 2015-12-02 昆山龙腾光电有限公司 液晶显示装置及其制作方法
CN105336747A (zh) * 2015-10-28 2016-02-17 深圳市华星光电技术有限公司 阵列基板及其修复方法
CN106773403A (zh) * 2016-12-29 2017-05-31 深圳市华星光电技术有限公司 像素单元结构及显示装置

Also Published As

Publication number Publication date
CN107479280A (zh) 2017-12-15

Similar Documents

Publication Publication Date Title
US9638975B2 (en) Method for manufacturing COA liquid crystal panel comprising color resist blocks having first and second intersection zones and COA liquid crystal panel
CN103293802B (zh) 液晶显示器件及其制造方法
US10503290B2 (en) Color filtering substrate and display apparatus
US9874795B2 (en) Array substrate, manufacturing method, and display device thereof
WO2017031908A1 (zh) 阵列基板及其制作方法和显示装置
US10295873B2 (en) Array substrate, and liquid crystal display device
CN203894515U (zh) 一种阵列基板及显示装置
US20160306220A1 (en) A color filter on array substrate and fabricating method thereof as well as a display device
JP2010190933A (ja) 液晶表示装置及びそれを用いた電子機器
TW201445228A (zh) 顯示面板與其製造方法
TWI469360B (zh) 顯示面板及顯示裝置
WO2017016014A1 (zh) Coa阵列基板及液晶面板
WO2021184506A1 (zh) 液晶显示面板
TW201435438A (zh) 液晶顯示面板及包含其之液晶顯示裝置
WO2020097959A1 (zh) 一种显示面板、制程方法和显示装置
CN105093756A (zh) 液晶显示像素结构及其制作方法
WO2020124896A1 (zh) 液晶显示面板
TWI570492B (zh) 畫素結構
US20200301215A1 (en) Array substrate, liquid crystal display panel and display device
WO2015180302A1 (zh) 阵列基板及其制备方法、显示装置
WO2018176809A1 (zh) 阵列基板及其制作方法、显示装置
TWI692089B (zh) 顯示裝置
WO2019051971A1 (zh) 阵列基板及显示面板
US8866142B2 (en) Display device and manufacturing method thereof
WO2017143660A1 (zh) 阵列基板、显示面板以及液晶显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 17921848

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 17921848

Country of ref document: EP

Kind code of ref document: A1