CN203941365U - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
CN203941365U
CN203941365U CN201420378231.1U CN201420378231U CN203941365U CN 203941365 U CN203941365 U CN 203941365U CN 201420378231 U CN201420378231 U CN 201420378231U CN 203941365 U CN203941365 U CN 203941365U
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pixel
electrode
public electrode
sub
array base
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程鸿飞
乔勇
先建波
李文波
李盼
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to CN201420378231.1U priority Critical patent/CN203941365U/zh
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Priority to US14/769,405 priority patent/US9773819B2/en
Priority to PCT/CN2014/092319 priority patent/WO2016004722A1/zh
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    • H—ELECTRICITY
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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Abstract

本实用新型提供一种阵列基板、显示面板及显示装置，所述阵列基板包括：衬底基板；形成于所述衬底基板上的多条栅线和多条数据线，多条所述栅线和多条所述数据线相互交叉形成多个子像素；设置于所述子像素内的像素电极；设置于所述子像素内与所述像素电极相对设置且相互绝缘的公共电极；设置于所述子像素内的薄膜晶体管，与对应的数据线、栅线及像素电极连接；至少一个所述子像素内还设置有公共电极线，且至少所述一个子像素内的所述公共电极线和与其位于同一子像素内的所述公共电极连接。本实用新型所提供的阵列基板可以减小公共电极的电阻，降低公共电极信号的压降，提高显示均匀性。

Description

阵列基板、显示面板及显示装置
技术领域
本实用新型涉及显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
背景技术
薄膜晶体管液晶显示装置(Thin Film Transistor Liquid Crystal Display，简称TFT-LCD)以轻薄、节约空间、低能耗、低辐射等特点已经成为了市场上的主流产品。液晶显示技术广泛应用于电视、手机以及公共信息显示，是目前使用最为广泛的显示技术。液晶显示的画面质量是这些产品成功的重要条件。在诸多的因素中，液晶显示均匀性是一个重要参数。
液晶显示装置包括阵列基板、彩膜基板以及设置在两基板之间的液晶层。在阵列基板上包括纵横交错的数据线和栅线，这些数据线和栅线交错，从而在阵列基板的显示区域形成一个个的子像素，在每一子像素都设置有一个TFT，其中TFT的栅极与栅线连接，漏极与像素电极连接，源极与数据线连接，在栅线传输的栅极驱动信号和数据线传输的数据信号的共同作用下，通过像素电极和公共电极在液晶层形成电场，进而通过电场控制液晶分子的偏转来实现显示。
传统的水平电场模式(Fringe Field Switching-FFS)的液晶显示装置中，像素电极和公共电极均设置在阵列基板上，其中每一子像素内设置一像素电极，公共电极与像素电极相互绝缘设置，并覆盖整个显示区域，在阵列基板的显示区域外围设置有公共电极线，公共电极与公共电极线连接，由公共电极线提供信号。这种传统的水平电场模式的液晶显示装置存在以下问题：
公共电极采用一整块的ITO(氧化铟锡)电极，由于其自身电阻的存在，其靠近公共电极线的区域和远离公共电极线的区域会产生公共电极压降大的问题，从而影响显示均匀性。
实用新型内容
本实用新型的目的是提供一种阵列基板、显示面板及显示装置，能够降低公共电极信号的压降，提高显示均匀性。
本实用新型所提供的技术方案如下：
一种阵列基板，包括：
衬底基板；
形成于所述衬底基板上的多条栅线和多条数据线，多条所述栅线和多条所述数据线相互交叉形成多个子像素；
设置于所述子像素内的像素电极；
设置于所述子像素内与所述像素电极相对设置且相互绝缘的公共电极；
设置于所述子像素内的薄膜晶体管，与对应的数据线、栅线及像素电极连接；
至少一个所述子像素内还设置有公共电极线，且至少一个所述子像素内的所述公共电极线和与其位于同一子像素内的所述公共电极连接。
进一步的，所述公共电极线与所述栅线同层设置且相互绝缘，且所述公共电极线与所述公共电极处于不同层，并通过位于所述公共电极线与所述公共电极之间的绝缘层上的过孔相连接。
进一步的，所述阵列基板还包括第一屏蔽电极；
其中，所述第一屏蔽电极与所述数据线在所述衬底基板上的投影完全重合；
或者，所述第一屏蔽电极与所述数据线在所述衬底基板上的投影部分重合；
或者，所述第一屏蔽电极与所述数据线在所述衬底基板上的投影不重合。
进一步的，所述第一屏蔽电极与所述公共电极线同层设置，并与所述公共电极线直接连接。
进一步的，所述阵列基板还包括第二屏蔽电极；
其中，所述第二屏蔽电极与所述栅线在所述衬底基板上的投影完全重合；
或者，所述第二屏蔽电极与所述栅线在所述衬底基板上的投影部分重合；
或者，所述第二屏蔽电极与所述栅线在所述衬底基板上的投影不重合。
进一步的，所述第二屏蔽电极与所述公共电极线同层设置，且所述第二屏
蔽电极与所述公共电极线连接。
进一步的，设置有所述公共电极线的子像素内的所述公共电极完全覆盖形成对应的子像素的所述数据线和/或所述栅线；
或者，设置有所述公共电极线的子像素内的所述公共电极部分覆盖形成对应的子像素的所述数据线和/或所述栅线；
或者，设置有所述公共电极线的子像素内的所述公共电极未覆盖形成对应的子像素的所述数据线和/或所述栅线。
进一步的，所述公共电极在与同一子像素内的所述薄膜晶体管所对应的位置上形成有切口部。
进一步的，所述公共电极上设有第一狭缝；
所述像素电极上设有第二狭缝或者所述像素电极为板状电极。
一种显示面板，包括彩膜基板，还包括如上所述的阵列基板。
一种显示装置，包括如上所述的阵列基板。
本实用新型的有益效果如下：
本实用新型所提供的阵列基板中，至少一部分子像素内分别单独设置有公共电极，并且该公共电极由与其位于同一子像素内的公共电极线来提供信号，与传统的阵列基板相比，可减小公共电极的电阻，降低公共电极信号的压降，提高显示均匀性。
附图说明
图1为本实用新型所提供的阵列基板的第一种实施例的一个子像素的结构示意图；
图2为图1中A-A向的结构示意图；
图3为图1中B-B向的结构示意图；
图4表示为本实用新型所提供的阵列基板的第二种实施例的一个子像素的结构示意图；
图5为本实用新型所提供的阵列基板的第三种实施例的一个子像素的结构示意图；
图6为本实用新型所提供的阵列基板的第三种实施例的一个子像素的结构示意图；
图7为图6中A-A向结构示意图；
图8为本实用新型所提供的阵列基板的第四种实施例的一个子像素的结构示意图。
具体实施方式
以下结合附图对本实用新型的原理和特征进行描述，所举实例只用于解释本实用新型，并非用于限定本实用新型的范围。
针对现有技术中阵列基板的公共电极为一整块ITO电极覆盖在阵列基板的显示区，并由位于显示区外围的公共电极线来提供信号，公共电极压降大，会影响显示均匀性的问题，本实用新型提供了一种阵列基板，能够减少公共电极压降，提高显示均匀性。
如图1至图3所示，本实用新型所提供的阵列基板包括：
衬底基板100；
形成于所述衬底基板100上的多条栅线200和多条数据线300，多条栅线200和多条数据线300相互交叉形成多个子像素；
设置于所述子像素内的像素电极400；
设置于所述子像素内与所述像素电极400相对设置且相互绝缘的公共电极700；
设置于所述子像素内的薄膜晶体管，与对应的数据线300、栅线200及像素电极400连接，其中所述薄膜晶体管的栅极501与对应的栅线200连接，所述薄膜晶体管的源极502与对应的数据线300连接，所述薄膜晶体管的漏极503与对应的像素电极400连接；
至少一个所述子像素内还设置有公共电极线600，且至少一个所述子像素内的所述公共电极线600和与其位于同一子像素内的所述公共电极700连接。
上述方案中，阵列基板的公共电极线600可以布置在子像素内，并且布置有公共电极线600的子像素内可以单独设置公共电极700，且公共电极700和与其同一子像素内的公共电极线600连接，从而每一子像素内的公共电极700可以分别由该子像素内的公共电极线600来提供信号，降低了由于公共电极700的电阻存在导致的公共电极700信号的压降，提高了显示均匀性。
需要说明的是，在本实用新型的阵列基板中，可以是，在该阵列基板的任一子像素内均单独设置公共电极700与公共电极线600，并且同一子像素内的公共电极700与公共电极线600相连接，不同子像素内的公共电极700之间相互绝缘；
还可以是，在该阵列基板的仅一部分子像素内采用上述单独设置公共电极700与公共电极线600的结构，例如：
多个子像素可以间隔地设置上述公共电极线600及公共电极700的结构，也就是说，多个子像素中相邻两个子像素中一个子像素内单独设置公共电极700与公共电极线600，所述公共电极700与所述公共电极线600连接，与其相邻的另一个子像素内不设置公共电极线600，所述相邻的另一个子像素内的公共电极与所述相邻两个子像素中一个子像素内的公共电极为一体结构且相互连接。
此外，在本实用新型的一实施例中，优选的，如图1至图3所示，所述公共电极线600与所述栅线200同层设置且相互绝缘，所述公共电极线600与所述公共电极700处于不同层，并通过位于所述公共电极线600与所述公共电极700之间的的绝缘层上的过孔900相连接，所述绝缘层包括栅极绝缘层101、钝化层801和平坦层802。
采用上述方案，所述公共电极线600与所述栅线200可以制作在同一层，并且，优选的，所述公共电极线600可以与所述栅线200采用同一材质，从而，可以通过一次构图工艺在衬底基板100上形成栅线200、薄膜晶体管的栅极501的同时，在子像素内形成所述公共电极线600，可以简化制造步骤。
当然可以理解的是，在本发明的其他实施例中，所述公共电极线600与所述栅线200也可以处于不同层，所述公共电极线600与所述栅线200也可以采用不同材质形成，例如：所述公共电极线600也可以与数据线同层设置，所述公共电极线600与所述数据线可以采用相同材质形成；在此仅提供一种公共电极线600的优选布线方式，但并不对此进行限定。
此外，上述方案中，所述公共电极线600与所述公共电极700通过过孔900连接，在实际应用中，可以根据实际需要，采用其他方式实现所述公共电极线600与所述公共电极700之间的连接，例如：所述公共电极700与所述公共电极线600也可以同层设置，并直接连接。
此外，本实用新型的一实施例中，优选的，如图1所示，所述公共电极线600与所述栅线200平行设置，且设置有所述公共电极线600的子像素内的所述公共电极线600和所述栅线200分别位于同一子像素内的所述像素电极400的相对两侧。
采用上述方案，阵列基板的布线方式更为简单。当然可以理解的是，在实际应用中，所述公共电极线600的布线方式不仅局限于此，还可以是其他方式，例如：所述公共电极线600与所述栅线200位于同一子像素内的所述像素电极400的同侧。
此外，TFT-LCD的显示性能和电场密切相关，但真正与显示相关的电场是由像素电极400和公共电极700产生的电场，除此之外的电场都应该视为是干扰信号，会对显示造成不利影响。
有鉴于此，本实用新型的一实施例中，优选的，所述阵列基板还包括第一屏蔽电极601，所述第一屏蔽电极601位于所述数据线300所在区域，并与所述数据线300处于不同层且相互绝缘，所述数据线300所在区域是指数据线300所在位置及周边区域。
上述方案，第一屏蔽电极601设置在数据线300所在区域，即，在阵列基板上布设有所述数据线300的区域对应地设置与所述数据线300绝缘的所述第一屏蔽电极601，数据线300作为感应源，而像素电极400作为受感器，在感应源和受感器之间增加一个屏蔽电极，能够阻挡数据线300上电信号产生的电场传输到像素电极400，也就是说，可以屏蔽数据线300的电压变化对像素电极400的电压造成的干扰，提高显示质量。
上述方案中，所述第一屏蔽电极601只要位于数据线300所在区域内，同时第一屏蔽电极601位于数据线300和像素电极400之间即可。具体地，所述第一屏蔽电极601与所述数据线300的位置关系可以有以下几种：
所述第一屏蔽电极601位于所述数据线300的正下方或正上方，即，所述第一屏蔽电极601与所述数据线300在所述衬底基板100上的投影完全重合；
或者，所述第一屏蔽电极601中一部分位于所述数据线300的正下方或正上方，即，所述第一屏蔽所述第一屏蔽电极601与所述数据线300在所述衬底基板100上的投影部分重合；
或者，所述第一屏蔽电极601位于所述数据线300的侧上方或侧下方，即，所述第一屏蔽电极601与所述数据线300在所述衬底基板100上的投影不重合。
优选的，所述第一屏蔽电极601位于所述数据线300的正下方或正上方，这样，所述第一屏蔽电极601可以同时屏蔽所述数据线300对与其相邻的两个所述像素电极400所产生的干扰信号，结构更为简化。
进一步优选的，所述第一屏蔽电极601位于所述数据线300的正下方。采用上述方案，如图2所示，通常，所述像素电极400与所述数据线300都位于栅极绝缘层101上，将所述第一屏蔽电极601设置在所述数据线300的正下方，屏蔽干扰信号效果更好。
需要说明的是，所述第一屏蔽电极601还可以位于所述数据线300所在区域，并与所述数据线300处于同层且相互绝缘。
此外，本实用新型的一实施例中，优选的，所述第一屏蔽电极601与所述公共电极线600连接，可以是通过过孔方式连接或直接连接。采用上述方案，可以由所述公共电极线600直接为所述第一屏蔽电极601提供信号，所述第一屏蔽电极601可以将其与所述数据线300之间产生的耦合信号导入公共信号线，而不会对像素电极400产生信号干扰。
当然可以理解的是，所述第一屏蔽电极601也可以是由其他信号线来提供信号，例如：所述第一屏蔽电极601可以接地，而将其与所述数据线300之间产生的寄生电容短接到地。
此外，进一步优选的，如图1所示，所述第一屏蔽电极601与所述公共电极线600同层设置，并与所述公共电极线600直接连接。采用上述方案，所述第一屏蔽电极601可以与所述公共电极线600采用同一次构图工艺形成，工艺简化，且结构更加简单。
当然可以理解的是，所述第一屏蔽电极601与所述公共电极线600也可以是处于不同层，而通过过孔进行连接。
此外，本实用新型的一实施例中，优选的，所述阵列基板还可以包括：
第二屏蔽电极，所述第二屏蔽电极位于所述栅线200所在区域，并与所述栅线200处于不同层，并且相互绝缘，所述栅线200所在区域是指栅线200所在位置及周边区域。
上述方案，第二屏蔽电极设置在所述栅线200所在区域，即，在阵列基板上布设有所述栅线200的区域对应地设置有与所述栅线200绝缘的所述第二屏蔽电极，所述栅线200作为感应源，而所述像素电极400作为受感器，在感应源和受感器之间增加一个屏蔽电极，能够阻挡所述栅线200上电信号产生的电场传输到所述像素电极400，通过抑制寄生电容的耦合达到了电场屏蔽的目的，提高显示质量。
上述方案中，所述第二屏蔽电极只要位于栅线200所在区域内，同时第二屏蔽电极位于栅线200和像素电极400之间即可。具体地，所述第二屏蔽电极与所述栅线200的位置关系可以有以下几种：
所述第二屏蔽电极位于所述栅线200的正下方或正上方，即，所述第二屏蔽电极与所述栅线200在所述衬底基板100上的投影完全重合；
或者，所述第二屏蔽电极中一部分位于所述栅线200的正下方或正上方，即，所述第二屏蔽电极与所述栅线200在所述衬底基板100上的投影部分重合；
或者，所述第二屏蔽电极位于所述栅线200的侧上方或侧下方，即，所述第二屏蔽电极与所述栅线200在所述衬底基板100上的投影不重合。
优选的，所述第二屏蔽电极位于所述栅线200的正下方或正上方，由此所述第二屏蔽电极可以同时屏蔽所述栅线200对与其相邻的两个所述像素电极400所产生的干扰信号，结构更为简化。
进一步优选的，所述第二屏蔽电极位于所述栅线200的正上方。采用上述方案，通常，如图所示，所述像素电极400制作在所述栅线200的侧上方位置，将所述第二屏蔽电极设置在所述栅线200的正上方，屏蔽干扰信号效果更好。
需要说明的是，所述第二屏蔽电极还可以位于所述栅线200所在区域，并与所述栅线200处于同层，并且相互绝缘。
此外，本实用新型的一实施例中，优选的，所述第二屏蔽电极可以与所述公共电极线600连接，可以是通过过孔方式连接或直接连接。采用上述方案，可以由所述公共电极线600直接为所述第二屏蔽电极提供信号，所述第二屏蔽电极可以将其与所述栅线200之间产生的耦合信号导入公共信号线，而不会对像素电极400产生信号干扰。
当然可以理解的是，所述第二屏蔽电极也可以是由其他信号线来提供信号，例如：所述第二屏蔽电极可以接地，而将其与所述栅线200之间产生的寄生电容短接到地。
此外，在本实用新型的一实施例中，所述第一屏蔽电极601与所述公共电极线600同层设置且直接连接，所述公共电极线600与所述栅线200同层设置，所述第二屏蔽电极可与所述数据线300同层设置，且所述第二屏蔽电极通过所述第一屏蔽电极601与所述第二屏蔽电极之间的栅极绝缘层101上的过孔与第一屏蔽电极601相连接，从而实现所述第二屏蔽电极与所述公共电极线600的连接。
当然可以理解的是，在实际应用中，所述第二屏蔽电极的布线方式并不仅局限于此，还可以采用其他布线方式，例如：所述第一屏蔽电极601与所述第二屏蔽电极通过同一次构图工艺形成，且所述第一屏蔽电极601与所述第二屏蔽电极直接连接。
优选的，所述第一屏蔽电极601与所述公共电极线600同层设置且直接连接，所述公共电极线600与所述栅线200同层设置，所述第二屏蔽电极可与所述公共电极线600同层设置，且所述第二屏蔽电极与所述第一屏蔽电极601相连接，从而实现所述第二屏蔽电极与所述公共电极线600的连接。
此外，本实用新型中，设置有所述公共电极线600的子像素内的所述公共电极700与形成对应的数据线300和/或栅线200之间可以有几下几种位置关系：
如图1所示，设置有所述公共电极线600的子像素内的所述公共电极700完全覆盖形成对应的子像素的所述数据线300和/或所述栅线200，即，所述公共电极700完全覆盖其周边的数据线300和/或栅线200；
或者，如图5所示，设置有所述公共电极线600的子像素内的所述公共电极700部分覆盖形成对应的子像素的所述数据线300和/或所述栅线200，即，所述公共电极700部分覆盖其周边的数据线300和/或栅线200；
或者，如图4所示，设置有所述公共电极线600的子像素内的所述公共电极700未覆盖形成对应的子像素的所述数据线300和/或所述栅线200，即，所述公共电极700不覆盖其周边的数据线300和/或栅线200。
优选的，公共电极700完全覆盖其周边的数据线300和/或栅线200，从而所述公共电极700也可以同时起到屏蔽数据线300和/或栅线200的电压变化对像素电极400的电压造成的干扰，进一步提高显示质量。
此外，本实用新型的一实施例中，优选的，如图8所示，所述公共电极700在与同一子像素内的所述薄膜晶体管所对应的位置上形成有切口部702。
采用上述方案，在所述薄膜晶体管的上方，公共电极700设置有切口部702，可以降低公共电极700和薄膜晶体管之间的寄生电容，进一步提高显示质量。
此外，本实用新型所提供的阵列基板优选为FFS阵列基板，所述公共电极700上设有第一狭缝；所述像素电极400上设有第二狭缝401(如图6和图7所示)，或者，所述像素电极400也可以为板状电极(如图1至图5所示)。
以下说明本实用新型的阵列基板的一优选实施例。
如图1至图3所示，本实施例中，所述阵列基板包括：
衬底基板100；
形成于所述衬底基板100上的同层设置的栅线200、栅极501、公共电极线600及第一屏蔽电极601，其中所述栅线200与所述栅极501连接，所述公共电极线600与所述第一屏蔽电极601连接；
覆盖在所述栅线200、所述栅极501、所述公共电极线600及所述第一屏蔽电极601之上的栅极绝缘层101；
形成于所述栅极绝缘层101之上的像素电极400；
形成于所述栅极绝缘层101之上的有源层504；
形成于所述栅极绝缘层101之上的源极502、漏极503和数据线300，其中所述数据线300与所述栅线200交叉设置，所述像素电极400位于所述数据线300与所述栅线200交叉形成的子像素内，且所述数据线300位于所述第一屏蔽电极601的上方，所述源极502和所述漏极503分别连接在所述有源层504的两侧，所述源极502与所述数据线300连接，所述漏极503与所述像素电极400连接；
覆盖所述源极502、所述漏极503、所述数据线300及所述像素电极400之上的钝化层801；
覆盖于所述钝化层801之上的平坦层802，其中所述栅极绝缘层101、所述钝化层801、所述平坦层802与在所述公共电极线600对应位置形成有过孔900；
形成于所述平坦层802之上的公共电极700，所述公共电极700设置于所述像素电极400上方，且所述公共电极700与所述公共电极线600通过栅极绝缘层101、所述钝化层801、与所述平坦层802上的过孔900相连接，所述公共电极700上设有第一狭缝701。
本实用新型优选实施例所提供的阵列基板中，所述栅线200、所述公共电极线600、所述数据线300可以采用金属材料(如：铜、铝、锰、钛、铬、钨等)制作而成，也可以采用合金材料制成；
栅线200可以是单层结构，也可以采用多层结构；
栅极绝缘层101可以采用氮化硅或氧化硅制作；
栅极绝缘层101可以是单层结构，也可以是多层结构；
有源层可以采用非晶硅或氧化物半导体制作；
钝化层801可以采用无机物如氮化硅制成；
平坦层802可以采用有机物如树脂等制成；
像素电极400可以采用ITO(氧化铟锡)、IZO(铟掺杂氧化锌)或其他透明金属氧化物导电材料制作；
公共电极700可以采用ITO(氧化铟锡)、IZO(铟掺杂氧化锌)或其他透明金属氧化物导电材料制作。
以下说明上述优选实施例中的阵列基板的一种制作方法。
本实用新型优选实施例的阵列基板的制作方法包括：
提供一衬底基板100；
在所述衬底基板100上沉积金属层，并通过一次构图工艺在所述衬底基板100上形成栅线200、栅极501、公共电极线600及第一屏蔽电极601的图形；
在形成有栅线200、栅极501、公共电极线600及第一屏蔽电极601的衬底基板100上沉积形成栅极绝缘层101；
在所述栅极绝缘层101上沉积透明金属氧化物导电层，并通过一次构图工艺形成像素电极400的图形；
在所述栅极绝缘层101上沉积半导体层，并通过一次构图工艺形成有源层的图形；
在所述栅极绝缘层101上沉积金属层，并通过一次构图工艺形成源极502、漏极503和数据线300的图形；
在所述源极502、所述漏极503、所述数据线300及所述像素电极400之上沉积形成钝化层801；
在所述钝化层801之上沉积形成平坦层802，并通过一次构图工艺在所述所述栅极绝缘层101、钝化层801和所述平坦层802上与所述公共电极线600对应位置形成过孔900；
在所述平坦层802上沉积透明金属氧化物导电层，并通过一次构图工艺形成公共电极700的图形，所述公共电极700通过所述过孔900与所述公共电极线600连接。
此外，本实用新型还提供了一种显示面板，包括彩膜基板和本实用新型所提供的阵列基板。
此外，本实用新型还提供了一种显示装置，包括本实用新型所提供的阵列基板。
以上所述是本实用新型的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本实用新型所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本实用新型的保护范围。

Claims (11)

1.一种阵列基板，包括：
衬底基板；
形成于所述衬底基板上的多条栅线和多条数据线，多条所述栅线和多条所述数据线相互交叉形成多个子像素；
设置于所述子像素内的像素电极；
设置于所述子像素内与所述像素电极相对设置且相互绝缘的公共电极；
设置于所述子像素内的薄膜晶体管，与对应的数据线、栅线及像素电极连接；其特征在于，
至少一个所述子像素内还设置有公共电极线，且至少一个所述子像素内的所述公共电极线和与其位于同一子像素内的所述公共电极连接。
2.根据权利要求1所述的阵列基板，其特征在于，
所述公共电极线与所述栅线同层设置且相互绝缘，且所述公共电极线与所述公共电极处于不同层，并通过位于所述公共电极线与所述公共电极之间的绝缘层上的过孔相连接。
3.根据权利要求1所述的阵列基板，其特征在于，
所述阵列基板还包括第一屏蔽电极；
其中，所述第一屏蔽电极与所述数据线在所述衬底基板上的投影完全重合；
或者，所述第一屏蔽电极与所述数据线在所述衬底基板上的投影部分重合；
或者，所述第一屏蔽电极与所述数据线在所述衬底基板上的投影不重合。
4.根据权利要求3所述的阵列基板，其特征在于，
所述第一屏蔽电极与所述公共电极线同层设置，并与所述公共电极线直接连接。
5.根据权利要求1所述的阵列基板，其特征在于，
所述阵列基板还包括第二屏蔽电极；
其中，所述第二屏蔽电极与所述栅线在所述衬底基板上的投影完全重合；
或者，所述第二屏蔽电极与所述栅线在所述衬底基板上的投影部分重合；
或者，所述第二屏蔽电极与所述栅线在所述衬底基板上的投影不重合。
6.根据权利要求5所述的阵列基板，其特征在于，
所述第二屏蔽电极与所述公共电极线同层设置，且所述第二屏蔽电极与所述公共电极线连接。
7.根据权利要求1所述的阵列基板，其特征在于，
设置有所述公共电极线的子像素内的所述公共电极完全覆盖形成对应的子像素的所述数据线和/或所述栅线；
或者，设置有所述公共电极线的子像素内的所述公共电极部分覆盖形成对应的子像素的所述数据线和/或所述栅线；
或者，设置有所述公共电极线的子像素内的所述公共电极未覆盖形成对应的子像素的所述数据线和/或所述栅线。
8.根据权利要求1所述的阵列基板，其特征在于，
所述公共电极在与同一子像素内的所述薄膜晶体管所对应的位置上形成有切口部。
9.根据权利要求1所述的阵列基板，其特征在于，
所述公共电极上设有第一狭缝；
所述像素电极上设有第二狭缝或者所述像素电极为板状电极。
10.一种显示面板，包括彩膜基板，其特征在于，还包括如权利要求1至9任一项所述的阵列基板。
11.一种显示装置，其特征在于，包括如权利要求1至9任一项所述的阵列基板。
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