WO2013029262A1 - 薄膜晶体管阵列基板 - Google Patents

薄膜晶体管阵列基板 Download PDF

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Publication number
WO2013029262A1
WO2013029262A1 PCT/CN2011/079250 CN2011079250W WO2013029262A1 WO 2013029262 A1 WO2013029262 A1 WO 2013029262A1 CN 2011079250 W CN2011079250 W CN 2011079250W WO 2013029262 A1 WO2013029262 A1 WO 2013029262A1
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WIPO (PCT)
Prior art keywords
thin film
film transistor
array substrate
transistor array
shielding layer
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PCT/CN2011/079250
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English (en)
French (fr)
Inventor
陈世烽
施明宏
何海英
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深圳市华星光电技术有限公司
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Priority to US13/264,577 priority Critical patent/US20140167160A1/en
Publication of WO2013029262A1 publication Critical patent/WO2013029262A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
    • G02F1/133509—Filters, e.g. light shielding masks
    • G02F1/133512—Light shielding layers, e.g. black matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the present invention relates to a substrate, and more particularly to a thin film transistor array substrate for a liquid crystal display.
  • the liquid crystal display needs to use a backlight module as a light source, and the light source penetrates various layers of the liquid crystal display, such as a thin film transistor (thin film) Transistor, TFT) array substrate, polarizer, color filter (color filter, CF) and other materials, the true display brightness is only about 10% of the original light source. Also, because of insufficient display brightness, if the brightness of the backlight module is increased, although the brightness of the panel can be increased, the power consumption of the backlight module is also increased.
  • the aperture ratio is defined as an area ratio of the light-transmitting region (opening portion) to the pixel, wherein the light-transmitting region may be a region of the pixel with the remaining portion of the following region: a data line region, a TFT region, a gate region, and a storage capacitor region. And a black matrix on the CF substrate to shield light from leaking around the pixel electrode (Black Matrix, BM) area.
  • BM Black Matrix
  • the accuracy of the alignment of the TFT array substrate and the CF substrate also affects the aperture ratio.
  • the existing alignment method is to align with the TFT array substrate through the BM on the CF substrate.
  • a liquid crystal layer is further interposed between the CF substrate and the TFT array substrate, the two are not easily aligned, and the aperture ratio is caused. decline.
  • the liquid crystal display device of the present invention adopts the following technical solution: a thin film transistor array substrate comprising a plurality of scan lines, data lines and common electrode lines formed on a substrate, the plurality of scan lines and data lines being alternately defined A plurality of pixel regions are formed with thin film transistors interlaced therebetween, and a plurality of pixel electrodes are formed in the plurality of pixel regions.
  • the thin film transistor array substrate further includes a patterned shielding layer, and the patterned shielding layer is disposed insulatively under the plurality of data lines. Specifically, an insulating layer is disposed between the patterned shielding layer and the plurality of data lines.
  • the patterned masking layer is used to mask the backlight from the bottom of the substrate.
  • the patterned masking layer is opaque and the patterned masking layer is made of metal.
  • the plurality of data lines completely overlap the patterned shielding layer, and the patterned shielding layer is electrically connected to the plurality of common electrode lines.
  • an insulating layer is disposed between the patterned shielding layer and the plurality of data lines.
  • the patterned masking layer is made of metal.
  • the plurality of data lines partially overlap the patterned shielding layer, and the patterned shielding layer is electrically connected to the plurality of common electrode lines.
  • an insulating layer is disposed between the patterned shielding layer and the plurality of data lines.
  • the patterned masking layer is made of metal.
  • the patterned shielding layer is a plurality of strip structures, and the plurality of strip structures are parallel to the plurality of data lines.
  • the patterned shielding layer of the present invention can directly cover the backlight, and can reduce the black matrix area on the CF substrate and increase the aperture ratio.
  • the patterned shielding layer is electrically connected to the common electrode line, the resistance of the common electrode line becomes large, and the RC value of the common electrode line is made close to but smaller than the reaction time of the liquid crystal. This reduces the load on the common electrode and allows the liquid crystal on the periphery of the patterned mask layer to be deflected into a black state without using BM to mask the backlight.
  • FIG. 1 is a schematic view of a thin film transistor array substrate in accordance with a preferred embodiment of the present invention.
  • Figure 2 is a cross-sectional view of Figure 1 taken along line AA'.
  • Figure 3 is a cross-sectional view of another embodiment of Figure 1 taken along line AA'.
  • FIG. 1 is a schematic diagram of a thin film transistor array substrate according to a preferred embodiment of the present invention.
  • the thin film transistor array substrate includes a substrate 100, a plurality of scan lines 120, a plurality of data lines 140, a common electrode line 160, and a patterned mask layer 180.
  • the thin film transistor array substrate of FIG. 1 is only representative of a single pixel unit.
  • the plurality of scan lines 120 and the data lines 140 are alternately defined with each other to define a plurality of pixel regions 200, and thin film transistors 150 are formed at the staggered portions thereof.
  • a plurality of pixel electrodes 220 are formed in the plurality of pixel regions 200.
  • the thin film transistor 150 has a gate, a source and a drain which are well known to those skilled in the art and will not be described in detail herein.
  • the gate, the source and the drain are connected to the scan line 120, the data line 140, and the pixel electrode 220, respectively.
  • the common electrode lines 160 are substantially parallel to the plurality of scan lines 120 and are alternately disposed in the pixel region 200 with the plurality of scan lines 120 and are interlaced with the plurality of data lines 140 to be spaced apart from each other. Further, the spacing is performed by providing an insulating layer (not shown) between the data line 140 and the common electrode line 160.
  • the storage capacitor is configured to allow the pixel electrode 220 to display the gray scale according to the data signal when the thin film transistor 150 is not driven by the scan line 120. Therefore, the pixel electrode 220 forms a storage capacitor at the overlap of the common electrode line 160. To store data signals.
  • FIG. 1 and FIG. 2 is a cross-sectional view taken along line AA' of FIG.
  • the patterned shielding layer 180 is disposed insulatively under the plurality of data lines 140, and the plurality of data lines 140 completely overlap the patterned shielding layer 180.
  • the patterned shielding layer 180 is electrically connected to the plurality of common electrode lines 160.
  • an insulating layer 240 is disposed between the patterned shielding layer 180 and the plurality of data lines 140.
  • the patterned shielding layer 180 and the common electrode line 160 are formed in the same mask manufacturing process.
  • the patterned shielding layer 180, the common electrode line 160 and the plurality of scanning lines 120 are formed in the same mask manufacturing process.
  • the patterned shielding layer 180 is a plurality of strip structures, and the plurality of strip structures are parallel to the plurality of data lines 140 .
  • FIG. 2 further illustrates the CF substrate 300, the ITO film 310, and the liquid crystal 400 sandwiched between the CF substrate 300 and the substrate 100.
  • the patterned masking layer 180 is opaque, such as made of metal.
  • the patterned masking layer 180 can be used to mask the backlight 10 from the bottom of the substrate 100.
  • the black matrix 350 in the CF substrate 300 can be omitted, and the aperture ratio is increased.
  • the distance between the patterned shielding layer 180 and the corresponding data line 140 is smaller than the distance between the common electrode line 160 and the corresponding pixel electrode 220.
  • the capacitance formula C ( ⁇ A)/d, where ⁇ is a dielectric constant, A is the area of the electrode, and d is the distance between the electrodes, and the patterned shielding layer 180 is between the data line 140 corresponding thereto.
  • the capacitance value is greater than the capacitance between the common electrode line 160 of the same area and its corresponding pixel electrode 220. Therefore, with the arrangement of the patterned shielding layer 180, the area of the common electrode line 160 in the light transmitting region can be reduced, and the aperture ratio is increased.
  • the patterned shielding layer 180 is electrically connected to the common electrode line 160, the patterned shielding layer 180 is at a common potential Vcom.
  • the ITO film 310 on the CF substrate 300 is also at the common potential Vcom. Therefore, it is known that there is substantially no voltage difference between the substrate 100 around the patterned shielding layer 180 and the CF substrate 300. Therefore, the liquid crystal 400 does not rotate, and the region is full. black.
  • the patterned shielding layer 180 is electrically connected to the common electrode line 160, the resistance of the common electrode line 160 becomes large, and the RC value (time constant) of the common electrode line 160 is close to but It is smaller than the reaction time of the liquid crystal 400.
  • Figure 3 is a cross-sectional view of another embodiment of Figure 1 taken along line AA'.
  • the plurality of data lines 180 partially overlap the patterned masking layer 180.
  • the patterned shielding layer 180 can be designed such that the backlight 10 still does not leak light after being incident, as shown in FIG. It is worth mentioning that the patterned shielding layer 180 can simulate the incidence of the backlight 10 in advance, and calculate an appropriate width so that the aperture ratio can be maximized.
  • the patterned shielding layer 180 of the present invention can directly cover the backlight, and can reduce the area of the black matrix 350 on the CF substrate 300, thereby increasing the aperture ratio.
  • the patterned shielding layer 180 is electrically connected to the common electrode line 160, the resistance of the common electrode line 160 becomes large, so that the RC value of the common electrode line is close to but smaller than the reaction time of the liquid crystal. . In this way, the load of the common electrode line 160 can be reduced, and the liquid crystal on the periphery of the patterned mask layer 180 can be prevented from being deflected into a black state without using the black matrix 350 to shield the backlight 10, thereby solving the above problem.

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Abstract

一种薄膜晶体管阵列基板，其包括形成在基板（100）上的多条扫描线（120）、数据线（140）及公共电极线（160），所述多条扫描线（120）及数据线（140）相互定义出多个像素区域（200）且其交错处形成有薄膜晶体管（150），并在所述多个像素区域（200）内形成有多个像素电极（220）。所述薄膜晶体管阵列基板还包括一图案化遮蔽层（180），所述图案化遮蔽层（180）绝缘地设置在所述多条数据线（140）之下。本发明的的图案化遮蔽层（180）可直接遮住背光（10），而可减少在CF基板（300）上的黑色矩阵（350）面积，而提高开口率。

Description

薄膜晶体管阵列基板 技术领域
本发明是有关于一种基板，且特别是有关于一种用于液晶显示器的薄膜晶体管阵列基板。
 背景技术
由于液晶本身不发光，使得液晶显示器需使用背光模组作为光源，所述光源穿透液晶显示器之各层，例如薄膜晶体管(thin film transistor, TFT)阵列基板、偏光片、彩色滤光片(color filter, CF)等等材质，真正显示的亮度大约只有原发光光源之百分之十左右。也因为显示亮度的不足，若提高背光模组亮度时，虽可让面板亮度增加，却也升高了背光模组之功率消耗。
因此，为了提高液晶屏的表面亮度，需要提高背光光源的利用率。这其中除了提高所用光学部件及其材料的透光率以外，特别要提高像素的开口率(aperture ratio)。开口率定义为透光区域(开口部)与该像素的面积比，其中透光区域可为像素的区域扣掉下述区域所剩部分：数据线区域、TFT区域、闸极区域、储存电容区域、及在CF基板用以遮蔽从像素电极周围漏出光的黑色矩阵(Black Matrix, BM)区域。由上可知，上述区域设计的越小，则开口率越大，越能获得更高的亮度。
除了减少上述区域的面积之外，TFT阵列基板与CF基板对位的精确度也会影响开口率的大小。现有对位方式是通过CF基板上的BM来与TFT阵列基板做对准，然而，由于CF基板与TFT阵列基板之间还隔有一液晶层，因此两者不易对准，而造成开口率的下降。
 技术问题
本发明的目的在于提供一种薄膜晶体管阵列基板，以解决提高液晶显示器像素的开口率的问题。
 技术解决方案
本发明的液晶显示装置采取以下技术方案：一种薄膜晶体管阵列基板，其包括形成在基板上的多条扫描线、数据线及公共电极线，所述多条扫描线及数据线相互交错定义出多个像素区域且其交错处形成有薄膜晶体管，并在所述多个像素区域内形成有多个像素电极。所述薄膜晶体管阵列基板还包括一图案化遮蔽层，所述图案化遮蔽层绝缘地设置在所述多条数据线之下。具体来说，所述图案化遮蔽层与所述多条数据线之间设有一绝缘层。所述图案化遮蔽层用于遮档来自基板底部的背光。例如，所述图案化遮蔽层是不透光的，且所述图案化遮蔽层由金属制成。
在一较佳实施例中，所述多条数据线与所述图案化遮蔽层完全重叠，且所述图案化遮蔽层电性连接至所述多条公共电极线。具体来说，所述图案化遮蔽层与所述多条数据线之间设有一绝缘层。优选地，所述图案化遮蔽层由金属制成。
在另一较佳实施例中，所述多条数据线与所述图案化遮蔽层部分重叠，且所述图案化遮蔽层电性连接至所述多条公共电极线。具体来说，所述图案化遮蔽层与所述多条数据线之间设有一绝缘层。优选地，所述图案化遮蔽层由金属制成。
优选地，所述图案化遮蔽层为多个条状结构，并且所述多个条状结构平行于所述多条数据线。
 有益效果
相较于现有技术，本发明的图案化遮蔽层可直接遮住背光，而可减少在CF基板上的黑色矩阵面积，而提高开口率。除此之外，由于图案化遮蔽层电性连接至所述公共电极线上，使得所述公共电极线的电阻变大，进而使公共电极线的RC值接近但小于液晶的反应时间。如此便可降低公共电极的负载，且可使图案化遮蔽层周围上的液晶不偏转而成黑色状态，而无需使用BM来遮档背光。
 附图说明
图1为本发明较佳实施例的薄膜晶体管阵列基板的示意图。
图2为图1沿AA’连线的截面图。
图3为图1沿AA’连线的另一实施例的截面图。
 本发明的最佳实施方式
请参照图1，图1为本发明较佳实施例的薄膜晶体管阵列基板的示意图。所述薄膜晶体管阵列基板包括基板100、多条扫描线120、多条数据线140、公共电极线160及图案化遮蔽层180。为了清楚说明，图1的薄膜晶体管阵列基板仅会示单一画素单元做为代表。所述多条扫描线120及数据线140相互交错定义出多个像素区域200，且其交错处形成有薄膜晶体管150。在所述多个像素区域200内形成有多个像素电极220。其中所述薄膜晶体管150具有本领域技术人员所熟知的栅极、源极及漏极，在此不详细说明。所述栅极、源极及漏极分别连接至所述扫描线120、数据线140及像素电极220。
所述公共电极线160大致上平行所述多条扫描线120，并与所述多条扫描线120交替设置于像素区域200中，且与所述多条数据线140交错而彼此隔开。进一步来说，所述隔开相交是通过设置一绝缘层（图未示）于数据线140及公共电极线160之间方式实施。所述储存电容是为了让像素电极220在没有扫描线120驱薄膜晶体管150时，仍能依据数据信号显示灰阶，所以像素电极220在所述公共电极线160重迭处会形成储存电容，用以储存数据信号。
请叁照图1及图2，图2为图1沿AA’连线的截面图。所述图案化遮蔽层180绝缘地设置在所述多条数据线140之下，并且所述多条数据线140与所述图案化遮蔽层180完全重叠。此外，所述图案化遮蔽层180电性连接至所述多条公共电极线160。同样地，所述图案化遮蔽层180与所述多条数据线140之间设有一绝缘层240。较佳地，所述图案化遮蔽层180与所述公共电极线160是在同一光罩制造过程所形成。更进一步地说，所述图案化遮蔽层180、所述公共电极线160及所述所述多条扫描线120是在同一光罩制造过程所形成。如图1所示，所述图案化遮蔽层180为多条条状结构，且所述多条条状结构平行于所述多条数据线140。
请再叁照图2，图2中进一步绘示出CF基板300、ITO薄膜310、及夹在CF基板300与基板100之间的液晶400。此较佳实施例中，所述图案化遮蔽层180是不透光的，例如由金属制成。因此所述图案化遮蔽层180可用于遮档来自基板100底部的背光10。由图2可知，在CF基板300中的黑色矩阵350就可省去，而增加了开口率。值得一提的是，所述图案化遮蔽层180与其所对应的所述数据线140之间的距离小于所述公共电极线160与其对应的所述像素电极220之间的距离。
根据电容公式C＝(εA)/d可知，其中ε为介电常数，A为电极的面积，d为电极间的距离，所述图案化遮蔽层180与其所对应的所述数据线140之间的电容值大于相同面积的公共电极线160与其所对应的像素电极220之间的电容直。因此，利用图案化遮蔽层180的设置，在透光区域的公共电极线160的面积可减少，而增加了开口率。此外，由于图案化遮蔽层180电性连接于公共电极线160，因此图案化遮蔽层180为公共电位Vcom。而CF基板300上的ITO薄膜310亦为公共电位Vcom，由此可知图案化遮蔽层180周围的基板100与CF基板300之间实质上没有电压差，因此液晶400不会转动，该区域为全黑的。除此之外，由于图案化遮蔽层180电性连接至所述公共电极线160上，使得所述公共电极线160的电阻变大，进而使公共电极线160的RC值（时间常数）接近但小于液晶400的反应时间。
请再叁照图3，图3为图1沿AA’连线的另一实施例的截面图。在另一实施例中，所述多条数据线180与所述图案化遮蔽层180部分重叠。具体来说，所述图案化遮蔽层180可设计成背光10入射后仍然不漏光为准，如图3所示。值得一提的是，所述图案化遮蔽层180可预先模拟背光10的入射，而计算出适当的宽度，使得开口率可以最大。
综上所述，本发明的图案化遮蔽层180可直接遮住背光，而可减少在CF基板300上的黑色矩阵350面积，而提高开口率。除此之外，由于图案化遮蔽层180电性连接至所述公共电极线160上，使得所述公共电极线160的电阻变大，进而使公共电极线的RC值接近但小于液晶的反应时间。如此便可降低公共电极线160的负载，且可使图案化遮蔽层180周围上的液晶不偏转而成黑色状态，而无需使用黑色矩阵350来遮档背光10，解决了上述问题。
虽然本发明已用优选实施例揭露如上，然其并非用以限定本发明，本发明所属技术领域的技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视后附的权利要求书所界定的为准。
 本发明的实施方式
工业实用性
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Claims (15)

  1. 一种薄膜晶体管阵列基板，包括形成在基板上的多条扫描线、数据线及公共电极线，所述多条扫描线及数据线相互交错定义出多个像素区域且其交错处形成有薄膜晶体管，并在所述多个像素区域内形成有多个像素电极，其特征在于，所述薄膜晶体管阵列基板还包括一图案化遮蔽层，所述图案化遮蔽层绝缘地设置在所述多条数据线之下。
  2. 根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述图案化遮蔽层用于遮档来自基板底部的背光。
  3. 根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述多条数据线与所述图案化遮蔽层完全重叠。
  4. 根据权利要求3所述的薄膜晶体管阵列基板，其特征在于，所述图案化遮蔽层电性连接至所述多条公共电极线。
  5. 根据权利要求4所述的薄膜晶体管阵列基板，其特征在于，所述图案化遮蔽层与所述多条数据线之间设有一绝缘层。
  6. 根据权利要求4所述的薄膜晶体管阵列基板，其特征在于，所述图案化遮蔽层由金属制成。
  7. 根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述多条数据线与所述图案化遮蔽层部分重叠。
  8. 根据权利要求7所述的薄膜晶体管阵列基板，其特征在于，所述图案化遮蔽层电性连接至所述多条公共电极线。
  9. 根据权利要求8所述的薄膜晶体管阵列基板，其特征在于，所述图案化遮蔽层与所述多条数据线之间设有一绝缘层。
  10. 根据权利要求8所述的薄膜晶体管阵列基板，其特征在于，所述图案化遮蔽层由金属制成。
  11. 根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述图案化遮蔽层为多个条状结构。
  12. 根据权利要求11所述的薄膜晶体管阵列基板，其特征在于，所述多个条状结构平行于所述多条数据线。
  13. 根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述图案化遮蔽层与所述多条数据线之间设有一绝缘层。
  14. 根据权利要求1所述的薄膜晶体管阵列基板，其特征在于，所述图案化遮蔽层是不透光的。
  15. 根据权利要求14所述的薄膜晶体管阵列基板，其特征在于，所述图案化遮蔽层由金属制成。
PCT/CN2011/079250 2011-08-31 2011-09-01 薄膜晶体管阵列基板 WO2013029262A1 (zh)

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