WO2017210943A1 - 像素结构、液晶显示面板及其驱动方法 - Google Patents

像素结构、液晶显示面板及其驱动方法 Download PDF

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Publication number
WO2017210943A1
WO2017210943A1 PCT/CN2016/088494 CN2016088494W WO2017210943A1 WO 2017210943 A1 WO2017210943 A1 WO 2017210943A1 CN 2016088494 W CN2016088494 W CN 2016088494W WO 2017210943 A1 WO2017210943 A1 WO 2017210943A1
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Prior art keywords
pixel
control switch
line
pixels
scan line
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PCT/CN2016/088494
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English (en)
French (fr)
Inventor
孙博
邹晓灵
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深圳市华星光电技术有限公司
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Priority to US15/115,243 priority Critical patent/US20180196299A1/en
Publication of WO2017210943A1 publication Critical patent/WO2017210943A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134336—Matrix
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134345—Subdivided pixels, e.g. for grey scale or redundancy
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G02F1/136295—Materials; Compositions; Manufacture processes
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
    • G02F2201/12—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode
    • G02F2201/123—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00 electrode pixel

Definitions

  • the present invention relates to the field of liquid crystal display technology, and in particular, to a pixel structure, a liquid crystal display panel, and a driving method thereof.
  • TFT Thin Film Transistor
  • LCD Liquid Crystal Display
  • TFT Thin Film Transistor
  • LCD Liquid Crystal Display
  • the color resistance of the three primary colors of red, green and blue (RGB) is placed on the light path, and different colors and different bright and dark pictures can be obtained.
  • RGB red, green and blue
  • the transmittance is different in each direction due to different angles, and the perceived deviation value is also different, so that the color shift (Color) mentioned in the industry is generated. Shift) phenomenon.
  • the multi-domain method is generally used, that is, the liquid crystal state observed by the observer in all directions is in a state of similar value, and the eight domains are generally used. structure.
  • one pixel 10 is divided into two sub-pixels, that is, a main pixel (Main Pixel) 100 and a sub-pixel 101, the main pixel 100 is driven by the thin film transistor 11, and the pixel 101 is passed through a shared TFT (Sharing) TFT) 12 drive.
  • Two gate lines (Gate) are required for each pixel, and a charge gate 13 is responsible for switching the thin film transistor 11 and sharing the gate (Share).
  • Gate) 14 is responsible for sharing TFT 12 switches, which will cause the pixel aperture rate to decrease.
  • the source of the shared TFT 12 is connected to the shared capacitor 15, that is, the potential from the pixel 101 is pulled low through the shared TFT 12 to realize eight domains. Since the nth row shares the gate 14 is connected to the charging gate 13 of the n+4 row at the periphery, which occupies an area of the peripheral design area, and it is difficult to realize a narrow border.
  • Embodiments of the present invention provide a pixel structure, a liquid crystal display panel, and a driving method thereof, which can improve an aperture ratio of a pixel without occupying a peripheral design area, and are advantageous for implementing a narrow side.
  • the present invention provides a pixel structure including a plurality of pixels arranged in a matrix, each pixel includes an adjacent main pixel area and a sub-pixel area, the main pixel area includes a first pixel electrode, and the first pixel electrode passes the first control
  • the switch is connected to the data line;
  • the slave pixel area includes a second pixel electrode, the second pixel electrode is connected to the data line through the second control switch and the first control switch;
  • the first scan line controls the first control switch, and the charge sharing line controls the second
  • the switch is controlled, and the charge sharing line is connected to the second scan line different from the first scan line.
  • the first control hole is provided with a first through hole
  • the charge sharing line is connected to the gate of the second control switch through the first through hole
  • the charge sharing line is connected to the second scan line through the second through hole.
  • the charge sharing line is an ITO film, and is patterned by using the same photomask as the first pixel electrode and the second pixel electrode.
  • the pixel structure includes adjacent first pixels and second pixels sharing the first scan line, the gates of the second control switches in the first pixels and the gates of the second control switches in the second pixels are the same, The opening of the first control switch in one pixel and the first control switch in the second pixel are opposite.
  • the pixel structure further includes adjacent third pixels and fourth pixels sharing the first scan line, the third pixel is adjacent to the second pixel, and the data lines of the second pixel and the third pixel are juxtaposed together, and the third pixel
  • the gate of the second control switch is shared with the fourth pixel.
  • the pixel structure includes a fifth pixel and a plurality of adjacent pixels sharing the data line with the fifth pixel.
  • the second control switch of the plurality of pixels is provided with a first through hole, and the scan line of the fifth pixel a second via hole is disposed, a gate of the second control switch of the plurality of pixels is connected to the charge sharing line through the first via hole, and the charge sharing line is connected to the scan line of the fifth pixel through the second via hole, wherein the fifth The pixel is adjacent to one of the plurality of pixels.
  • the number of the plurality of pixels is at least one of 1, 2, 3, and 4.
  • the main pixel area and the sub-pixel area are disposed on the array substrate, and the array substrate further includes a plurality of scanning lines disposed laterally and a plurality of data lines disposed longitudinally, wherein the scanning lines are intersected with the data lines, wherein: the plurality of pixels
  • the main pixel area and the sub-pixel area of the 2n-1th pixel and the main pixel area and the sub-pixel area of the 2nth pixel are both disposed on the 2n-1th scan line, the 2nth scan line, and the 2n-1th line
  • n is a positive integer.
  • the present invention also provides a liquid crystal display panel, the liquid crystal display panel includes a pixel structure, the pixel structure includes a plurality of pixels arranged in a matrix, each pixel includes an adjacent main pixel area and a sub-pixel area, and the main pixel area includes a a pixel electrode, the first pixel electrode is connected to the data line through the first control switch; the second pixel electrode is connected from the pixel region, and the second pixel electrode is connected to the data line through the second control switch and the first control switch; the first scan line
  • the first control switch is controlled, the charge sharing line controls the second control switch, and the charge sharing line is connected to the second scan line different from the first scan line.
  • the first control hole is provided with a first through hole
  • the charge sharing line is connected to the gate of the second control switch through the first through hole
  • the charge sharing line is connected to the second scan line through the second through hole.
  • the charge sharing line is an ITO film, and is patterned by using the same photomask as the first pixel electrode and the second pixel electrode.
  • the pixel structure includes adjacent first pixels and second pixels sharing the first scan line, the gates of the second control switches in the first pixels and the gates of the second control switches in the second pixels are the same, The opening of the first control switch in one pixel and the first control switch in the second pixel are opposite.
  • the pixel structure further includes adjacent third pixels and fourth pixels sharing the first scan line, the third pixel is adjacent to the second pixel, and the data lines of the second pixel and the third pixel are juxtaposed together, and the third pixel
  • the gate of the second control switch is shared with the fourth pixel.
  • the pixel structure includes a fifth pixel and a plurality of adjacent pixels sharing the data line with the fifth pixel.
  • the second control switch of the plurality of pixels is provided with a first through hole, and the scan line of the fifth pixel a second via hole is disposed, a gate of the second control switch of the plurality of pixels is connected to the charge sharing line through the first via hole, and the charge sharing line is connected to the scan line of the fifth pixel through the second via hole, wherein the fifth The pixel is adjacent to one of the plurality of pixels.
  • the number of the plurality of pixels is at least one of 1, 2, 3, and 4.
  • the main pixel area and the sub-pixel area are disposed on the array substrate, and the array substrate further includes a plurality of scanning lines disposed laterally and a plurality of data lines disposed longitudinally, wherein the scanning lines are intersected with the data lines, wherein: the plurality of pixels
  • the main pixel area and the sub-pixel area of the 2n-1th pixel and the main pixel area and the sub-pixel area of the 2nth pixel are both disposed on the 2n-1th scan line, the 2nth scan line, and the 2n-1th line
  • n is a positive integer.
  • the present invention also provides a driving method of a liquid crystal display panel.
  • the liquid crystal display panel includes a pixel structure.
  • the pixel structure includes a plurality of pixels arranged in a matrix, and each pixel includes an adjacent main pixel area and a sub-pixel area, and a main pixel area.
  • the first pixel electrode is connected to the data line through the first control switch; the second pixel electrode is connected from the pixel region, and the second pixel electrode is connected to the data line through the second control switch and the first control switch;
  • the first scan line controls the first control switch, the charge sharing line controls the second control switch, the charge sharing line is connected to the second scan line different from the first scan line, and the driving method of the liquid crystal display panel: using the first scan line control A control switch is turned on; the data line is used to charge the main pixel region such that the first pixel electrode forms a first equipotential; and the second control switch is controlled to be turned on by the charge sharing line to achieve charge sharing.
  • the pixel structure of the present invention includes a plurality of pixels arranged in a matrix, each pixel includes an adjacent main pixel area and a sub-pixel area, and the main pixel area includes a first pixel electrode.
  • the first pixel electrode is connected to the data line through the first control switch;
  • the second pixel electrode is connected from the pixel region, and the second pixel electrode is connected to the first pixel electrode data line through the second control switch and the first control switch;
  • the first scan line Controlling a gate of the first control switch to be connected to the first scan line, the charge share line controlling the gate of the second control switch to be connected to the second scan line, the second scan line charge sharing line being different from the first scan line
  • the second scan line is connected, which can increase the aperture ratio of the pixel, does not occupy the peripheral design area, and is advantageous for achieving a narrow side.
  • FIG. 1 is a schematic diagram of a pixel structure in the prior art
  • FIG. 2 is a schematic structural view of a liquid crystal display panel according to an embodiment of the present invention.
  • FIG. 3 is a schematic diagram of a pixel structure of a first embodiment of the present invention.
  • FIG. 4 is a schematic diagram of a pixel structure of a second embodiment of the present invention.
  • FIG. 5 is a schematic flow chart of a driving method of a liquid crystal display panel according to an embodiment of the present invention.
  • the liquid crystal display panel includes an array substrate 1, a color filter substrate 2 disposed opposite to the array substrate 1, and a liquid crystal layer 3 sandwiched between the array substrate 1 and the color filter substrate 2.
  • the pixel electrodes 4 are disposed in the array.
  • a common electrode 5 is provided on the color filter substrate 2.
  • the structure composed of the pixel electrodes 4 on the array substrate 1 is a pixel structure.
  • the pixel structure includes a plurality of pixels arranged in a matrix, and each of the pixels includes an adjacent main pixel region 200 and a slave pixel region 201.
  • the main pixel region 200 and the sub-pixel region 201 are disposed on the array substrate 1.
  • the array substrate 1 further includes a plurality of scanning lines disposed laterally and a plurality of data lines disposed longitudinally, the scanning lines each intersecting the data lines.
  • the main pixel area and the sub-pixel area of the 2n-1th pixel of the plurality of pixels and the main pixel area and the sub-pixel area of the 2nth pixel are both disposed on the 2n-1th scan line and the 2nth scan line.
  • n is a positive integer.
  • the main pixel region 200 includes a first pixel electrode 203 that is connected to the data line 22 through the first control switch 21.
  • the slave pixel region 201 includes a second pixel electrode 204 that is connected to the data line 22 through the second control switch 23 and the first control switch 21.
  • the source or the drain of the second control switch 23 forms a shared capacitance 205 with the scan line.
  • the first scan line 24 controls the first control switch 21
  • the charge share line 25 controls the charge share line of the second control switch 23, and the charge share line 25 is connected to the second scan line 26 different from the first scan line 24.
  • the charge sharing line 25 is an ITO thin film, and can be patterned by using the same photomask as the first pixel electrode 203 and the second pixel electrode 204 during the fabrication process. Of course, the charge sharing line 25 can also use other conductors as long as the resistivity is low.
  • the second control hole 23 is provided with a first through hole 230
  • the second scan line 26 is provided with a second through hole 260.
  • the charge sharing line 25 passes through the first through hole 230 and the first through hole 230.
  • the gates of the second control switch 23 are connected, and the charge sharing line 25 is connected to the second scan line 26 through the second via 260.
  • the second scan line 26 may be a scan line adjacent to the first scan line 24, such that the second control switch 23 is simultaneously turned on with the first control switch controlled by the adjacent second scan line 26 to achieve charge sharing. the goal of.
  • the data lines of the embodiments of the present invention are different from the conventional 1G1D mode.
  • the data lines of the adjacent two columns of pixels are juxtaposed together, and the opening directions of the adjacent first control switch and the second control switch are adjacent. in contrast.
  • the charge sharing line of the pixel of the Nth row and the scan line of the pixel of the N+1th row are connected in plane by the way of the via hole, so that the second control switch of the pixel of the Nth row and the pixel of the N+1th row of pixels
  • a control switch is turned on at the same time to achieve charge sharing (Charge The purpose of sharing, in turn, achieves the effect of reducing the color shift.
  • the first via connects the charge sharing line to the gate of the second control switch of the Nth row of pixels
  • the second via connects the charge sharing line and the scan line of the N+1th row of pixels.
  • the charge sharing line is an ITO film.
  • the pixel structure includes adjacent first and second pixels 241 and 242 sharing the first scan line 24, and a gate and a second pixel of the second control switch in the first pixel 241.
  • the second control switch of 241 has the same gate, and is connected to the shared charge line 25 through the first via 230.
  • the opening direction of the first control switch in the first pixel 241 and the first control switch in the second pixel 242 is opposite.
  • the pixel structure further includes adjacent third pixels 243 and fourth pixels 244 sharing the first scan line 24, the third pixel 243 is adjacent to the second pixel 242, and the data lines of the second pixel 242 and the third pixel 243 are juxtaposed. Together, the third pixel 243 and the fourth pixel 244 share the gate of the second control switch.
  • the plurality of pixels sharing the first scanning line 24 are arranged in a cycle of the first pixel 241, the second pixel 242, the third pixel 243, and the fourth pixel 244.
  • the second control switch of the Nth row is simultaneously turned on with the first control switch of the (N+1)th row.
  • Such a method can greatly reduce the area occupied by the original charge sharing line, and is advantageous for increasing the aperture ratio of the pixel. Since the charge sharing line of the Nth row is connected in-plane to the first scan line of the (N+1)th row, the peripheral design area is not occupied, which is advantageous for realizing a narrow bezel, and such a method does not require a multi-mask.
  • adjacent pixels may share one charge sharing line.
  • the pixel structure includes a fifth pixel 31 and a plurality of adjacent pixels 33 sharing the data line 32 with the fifth pixel 31.
  • a first via hole 331 is disposed on the gate of the second control switch 330 of the plurality of pixels 33, and a second via hole 311 is disposed on the scan line 310 of the fifth pixel 31, so that the gate of the second control switch 330 passes through the first
  • the via hole 331 is connected to the charge sharing line 332, and the charge connection line via second via hole 311 is connected to the scan line 310 of the fifth pixel 31, wherein the fifth pixel 31 is adjacent to at least one of the plurality of pixels 33.
  • the gates of the second control switches of the pixels 33, 34, 35 are all provided with first via holes such that the gate via first vias of the corresponding second control switches are connected to the charge sharing line 332.
  • the gate of the second control switch of the first three rows of pixels is controlled by the scan line of the fourth row of pixels with one pixel per four rows of pixels, and the number of corresponding shared shared charge lines is three.
  • the number of pixels sharing the shared charge line is at least one of 1, 2, 3, 4.
  • the period of the corresponding pixel structure is 2, 3, 4, 5.
  • the number of pixels corresponding to the gate of the second control switch controlled by the scan line of one pixel is not more, otherwise the load of the scan line is too large.
  • FIG. 5 is a schematic flow chart of a driving method of a liquid crystal display panel according to an embodiment of the present invention.
  • the liquid crystal display panel includes a pixel structure including a plurality of pixels arranged in a matrix. Each pixel includes an adjacent main pixel area and a sub-pixel area.
  • the main pixel region includes a first pixel electrode, and the first pixel electrode is connected to the data line through the first control switch.
  • the slave pixel region includes a second pixel electrode, and the second pixel electrode is connected to the data line through the second control switch and the first control switch.
  • the first scan line controls the first control switch
  • the charge share line controls the second control switch
  • the charge share line is connected to the second scan line different from the first scan line.
  • the driving method of the liquid crystal display panel As shown in FIG. 5, the driving method of the liquid crystal display panel:
  • Step S10 Controlling the first control switch to be turned on by using the first scan line.
  • the first scan line is a scan line corresponding to the first pixel electrode.
  • Step S11 charging the main pixel region with the data line such that the first pixel electrode forms a first equipotential.
  • Step S12 controlling the second control switch to be turned on by using the charge sharing line to implement charge sharing.
  • the charge sharing line is an ITO film, and can be patterned by using the same photomask as the first pixel electrode and the second pixel electrode during the fabrication process.
  • the charge sharing line can also use other conductors as long as the resistivity is low.
  • a first through hole is disposed on a gate of the second control switch, and a second through hole is disposed on the second scan line, and the charge sharing line passes through the first through hole and the gate of the second control switch Connected, the charge sharing line is connected to the second scan line through the second via.
  • the second scan line may be a scan line adjacent to the first scan line, such that the second control switch is simultaneously turned on with the first control switch controlled by the adjacent second scan line to achieve the purpose of charge sharing.
  • the data lines of the embodiments of the present invention are different from the conventional 1G1D mode.
  • the data lines of the adjacent two columns of pixels in the embodiment of the present invention are juxtaposed together, and the opening directions of the adjacent first control switch and the second control switch are opposite.
  • the charge sharing line of the pixel of the Nth row and the scan line of the pixel of the N+1th row are connected in plane by the way of the via hole, so that the second control switch of the pixel of the Nth row and the pixel of the N+1th row of pixels
  • a control switch is turned on at the same time to achieve charge sharing (Charge The purpose of sharing, in turn, achieves the effect of reducing the color shift.
  • the first via connects the charge sharing line to the gate of the second control switch of the Nth row of pixels
  • the second via connects the charge sharing line and the scan line of the N+1th row of pixels.
  • the charge sharing line is an ITO film.
  • the second control switch of the Nth row is simultaneously turned on with the first control switch of the (N+1)th row.
  • Such a method can greatly reduce the area occupied by the original charge sharing line, and is advantageous for increasing the aperture ratio of the pixel. Since the charge sharing line of the Nth row is connected in-plane to the first scan line of the (N+1)th row, the peripheral design area is not occupied, which is advantageous for realizing a narrow bezel, and such a method does not require a multi-mask.
  • the pixel structure includes adjacent first pixels and second pixels sharing a first scan line, a gate of a second control switch in the first pixel, and a second control switch in the second pixel
  • the gates are the same and are connected to the shared charge line through the first via.
  • the opening direction of the first control switch in the first pixel and the first control switch in the second pixel are opposite.
  • the pixel structure further includes adjacent third pixels and fourth pixels sharing the first scan line, the third pixel is adjacent to the second pixel, and the data lines of the second pixel and the third pixel are juxtaposed together, the third pixel and the third pixel
  • the four pixels share the gate of the second control switch.
  • the plurality of pixels sharing the first scan line are arranged in a cycle of the first pixel, the second pixel, the third pixel, and the fourth pixel.
  • adjacent pixels may share one charge sharing line.
  • the pixel structure includes a fifth pixel and a plurality of adjacent pixels that share the data line with the fifth pixel.
  • a first via hole is disposed on a gate of the second control switch of the plurality of pixels, and a second via hole is disposed on the scan line of the fifth pixel, so that a gate of the second control switch is connected to the charge sharing line through the first via hole
  • the charge connection line via hole is connected to the scan line of the fifth pixel, wherein the fifth pixel is adjacent to at least one of the plurality of pixels.
  • Three consecutively adjacent pixels share one charge sharing line.
  • the gate of the second control switch of the pixel is disposed with the first through hole such that the gate through hole of the corresponding second control switch is connected to the charge sharing line.
  • the gate of the second control switch of the first three rows of pixels is controlled by the scan line of the fourth row of pixels with one pixel per four rows of pixels, and the number of corresponding shared shared charge lines is three.
  • the number of pixels sharing the shared charge line is at least one of 1, 2, 3, 4.
  • the period of the corresponding pixel structure is 2, 3, 4, 5.
  • the number of pixels corresponding to the gate of the second control switch controlled by the scan line of one pixel is not more, otherwise the load of the scan line is too large.
  • the pixel structure of the present invention includes a plurality of pixels arranged in a matrix, each pixel includes an adjacent main pixel area and a sub-pixel area, the main pixel area includes a first pixel electrode, and the first pixel electrode passes through a control switch is connected to the data line; the slave pixel area includes a second pixel electrode, and the second pixel electrode is connected to the first pixel electrode through the second control switch and the first control switch; the gate of the first control switch is connected to the first scan line The gate of the second control switch is connected to the charge sharing line, and the charge sharing line is adjacent to the first scan line, which can improve the aperture ratio of the pixel, does not occupy the surrounding design area, and is beneficial to realize the narrow side.

Abstract

一种像素结构、液晶显示面板及其驱动方法。像素结构，包括矩阵排列的多个像素，每一像素中包括相邻设置的主像素区(200)以及从像素区(201)，主像素区(200)包括第一像素电极(203)，第一像素电极(203)通过第一控制开关(21)与数据线(22)连接；从像素区(201)包括第二像素电极(204)，第二像素电极(204)通过第二控制开关(23)以及第一控制开关(21)与数据线(22)连接；第一扫描线(24)控制第一控制开关(21)，电荷共享线(25)控制第二控制开关(23)，电荷共享线(25)与不同于第一扫描线(24)的第二扫描线(26)连接。通过以上方式，能够提高像素的开口率，不占用周边设计区域，有利于实现窄边框。

Description

像素结构、液晶显示面板及其驱动方法
【技术领域】
本发明涉及液晶显示技术领域，特别是涉及一种像素结构、液晶显示面板及其驱动方法。
【背景技术】
薄膜晶体管(Thin Film Transistor，TFT)-液晶显示器( Liquid Crystal Display ，LCD)是依靠液晶在不同的电场中有不同的取向，这时，由于液晶的光学双折射性，会使得背光源传入液晶中的光产生不同的透过率，进而产生灰阶，在光路上放置红绿蓝（RGB）三原色的色阻，则可以得到不同颜色，不同亮暗的画面。在大视角观看液晶显示器的时候，由于角度不同，因此各个方向上面的穿透率也不同，所感受到的偏差值也有差异，因此产生业界所说的色偏（Color shift）现象。为了克服液晶显示器的这一先天不良，形成了大量的方法，目前普遍使用的是多畴法，即使得观察者在各个方向看到的液晶状态处于一个均值差不多的状态，普遍使用的是八畴结构。
为了实现八畴结构，目前普遍采用的是电荷共享技术。如图1，将一个像素10分为两个子像素，即主像素（Main Pixel）100和从像素（Sub Pixel）101，主像素100通过薄膜晶体管11驱动，从像素101通过共享TFT（Sharing TFT）12驱动。每个像素需要两根栅极线（Gate），充电栅极（Charge Gate）13负责薄膜晶体管11的开关，共享栅极（Share Gate）14负责共享TFT 12的开关，这样会造成像素开口率降低。共享TFT12的源极连接共享电容15，即从像素101的电位会通过共享TFT12拉低，以实现八畴。由于第n行共享栅极 14在外围与n+4行的充电栅极13相连，造成占用外围设计区域面积，难以实现窄边框。
【发明内容】
本发明实施例提供了一种像素结构、液晶显示面板及其驱动方法，能够提高像素的开口率，不占用周边设计区域，有利于实现窄边。
本发明提供一种像素结构，包括矩阵排列的多个像素，每一像素中包括相邻设置的主像素区以及从像素区，主像素区包括第一像素电极，第一像素电极通过第一控制开关与数据线连接；从像素区包括第二像素电极，第二像素电极通过第二控制开关以及第一控制开关与数据线连接；第一扫描线控制第一控制开关，电荷共享线控制第二控制开关，电荷共享线与不同于第一扫描线的第二扫描线连接。
其中，第二控制开关的栅极上设置有第一通孔，电荷共享线通过第一通孔与第二控制开关的栅极连接，电荷共享线通过第二通孔与第二扫描线连接。
其中，电荷共享线为ITO薄膜，与第一像素电极、第二像素电极采用同一光罩进行图案化。
其中，像素结构包括共用第一扫描线的相邻的第一像素和第二像素，第一像素中的第二控制开关的栅极和第二像素中的第二控制开关的栅极相同，第一像素中的第一控制开关和第二像素中的第一控制开关的开口方向相反。
其中，像素结构还包括共用第一扫描线的相邻的第三像素和第四像素，第三像素与第二像素相邻，第二像素与第三像素的数据线并列在一起，第三像素和第四像素共用第二控制开关的栅极。
其中，像素结构包括第五像素以及与第五像素共用数据线的相邻的多个像素，多个像素的第二控制开关的栅极上设置有第一通孔，第五像素的扫描线上设置有第二通孔，多个像素中的第二控制开关的栅极通过第一通孔与电荷共享线连接，电荷共享线通过第二通孔与第五像素的扫描线连接，其中第五像素与多个像素中的一个像素相邻。
其中，多个像素的数量为1、2、3、4中的至少一个。
其中，主像素区以及次像素区设置在阵列基板上，阵列基板上还包括横向设置的多条扫描线和纵向设置的多条数据线，扫描线均与数据线相交，其中：多个像素中的第2n-1个像素的主像素区和次像素区以及第2n个像素的主像素区和次像素区均设置在第2n-1条扫描线、第2n条扫描线、第2n-1条数据线以及第2n条数据线所围成的区域内，n为正整数。
本发明还提供一种液晶显示面板，该液晶显示面板包括像素结构，像素结构包括矩阵排列的多个像素，每一像素中包括相邻设置的主像素区以及从像素区，主像素区包括第一像素电极，第一像素电极通过第一控制开关与数据线连接；从像素区包括第二像素电极，第二像素电极通过第二控制开关以及第一控制开关与数据线连接；第一扫描线控制第一控制开关，电荷共享线控制第二控制开关，电荷共享线与不同于第一扫描线的第二扫描线连接。
其中，第二控制开关的栅极上设置有第一通孔，电荷共享线通过第一通孔与第二控制开关的栅极连接，电荷共享线通过第二通孔与第二扫描线连接。
其中，电荷共享线为ITO薄膜，与第一像素电极、第二像素电极采用同一光罩进行图案化。
其中，像素结构包括共用第一扫描线的相邻的第一像素和第二像素，第一像素中的第二控制开关的栅极和第二像素中的第二控制开关的栅极相同，第一像素中的第一控制开关和第二像素中的第一控制开关的开口方向相反。
其中，像素结构还包括共用第一扫描线的相邻的第三像素和第四像素，第三像素与第二像素相邻，第二像素与第三像素的数据线并列在一起，第三像素和第四像素共用第二控制开关的栅极。
其中，像素结构包括第五像素以及与第五像素共用数据线的相邻的多个像素，多个像素的第二控制开关的栅极上设置有第一通孔，第五像素的扫描线上设置有第二通孔，多个像素中的第二控制开关的栅极通过第一通孔与电荷共享线连接，电荷共享线通过第二通孔与第五像素的扫描线连接，其中第五像素与多个像素中的一个像素相邻。
其中，多个像素的数量为1、2、3、4中的至少一个。
其中，主像素区以及次像素区设置在阵列基板上，阵列基板上还包括横向设置的多条扫描线和纵向设置的多条数据线，扫描线均与数据线相交，其中：多个像素中的第2n-1个像素的主像素区和次像素区以及第2n个像素的主像素区和次像素区均设置在第2n-1条扫描线、第2n条扫描线、第2n-1条数据线以及第2n条数据线所围成的区域内，n为正整数。
本发明还提供一种液晶显示面板的驱动方法，液晶显示面板包括像素结构，像素结构包括矩阵排列的多个像素，每一像素中包括相邻设置的主像素区以及从像素区，主像素区包括第一像素电极，第一像素电极通过第一控制开关与数据线连接；从像素区包括第二像素电极，第二像素电极通过第二控制开关以及第一控制开关与所述数据线连接；第一扫描线控制第一控制开关，电荷共享线控制第二控制开关，电荷共享线与不同于第一扫描线的第二扫描线连接，液晶显示面板的驱动方法：利用第一扫描线控制第一控制开关导通；利用数据线为主像素区充电以使得第一像素电极形成第一等电位；利用电荷共享线控制第二控制开关导通以实现电荷共享。
通过上述方案，本发明的有益效果是：本发明的像素结构包括矩阵排列的多个像素，每一像素中包括相邻设置的主像素区以及从像素区，主像素区包括第一像素电极，第一像素电极通过第一控制开关与数据线连接；从像素区包括第二像素电极，第二像素电极通过第二控制开关以及第一控制开关与第一像素电极数据线连接；第一扫描线控制第一控制开关的栅极连接第一扫描线，电荷共享线控制第二控制开关的栅极与第二扫描线连接，第二扫描线电荷共享线与不同于与第一扫描线相邻的第二扫描线连接，能够提高像素的开口率，不占用周边设计区域，有利于实现窄边。
【附图说明】
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。其中：
图1是现有技术中的像素结构示意图；
图2是本发明实施例的液晶显示面板的结构示意图；
图3是本发明第一实施例的像素结构示意图；
图4是本发明第二实施例的像素结构示意图；
图5是本发明实施例的液晶显示面板的驱动方法的流程示意图。
【具体实施方式】
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
图2是本发明实施例的液晶显示面板的结构示意图。如图2所示，液晶显示面板包括阵列基板1、与阵列基板1相对设置的彩膜基板2以及夹持在阵列基板1和彩膜基板2之间的液晶层3，像素电极4设置在阵列基板1上，彩膜基板2上设置有公共电极5。阵列基板1上的像素电极4组成的结构即为像素结构。
参见图3，像素结构包括矩阵排列的多个像素，每一像素中包括相邻设置的主像素区200以及从像素区201。主像素区200以及次像素区201设置在阵列基板1上。阵列基板1上还包括横向设置的多条扫描线和纵向设置的多条数据线，扫描线均与数据线相交。其中，多个像素中的第2n-1个像素的主像素区和次像素区以及第2n个像素的主像素区和次像素区均设置在第2n-1条扫描线、第2n条扫描线、第2n-1条数据线以及第2n条数据线所围成的区域内，n为正整数。
主像素区200包括第一像素电极203，第一像素电极203通过第一控制开关21与数据线22连接。从像素区201包括第二像素电极204，第二像素电极204通过第二控制开关23以及第一控制开关21与数据线22连接。第二控制开关23的源极或漏极与扫描线形成共享电容205。第一扫描线24控制第一控制开关21，电荷共享线25控制第二控制开关23电荷共享线，电荷共享线25与不同于第一扫描线24的第二扫描线26连接。其中，电荷共享线25为ITO薄膜，在制作过程中可以与第一像素电极203、第二像素电极204采用同一光罩进行图案化。当然，电荷共享线25也可以采用其他导体，只要是电阻率较低即可。
在本发明实施例中，第二控制开关23的栅极上设置有第一通孔230，第二扫描线26上设置有第二通孔260，电荷共享线25通过第一通孔230与第二控制开关23的栅极连接，电荷共享线25通过第二通孔260与第二扫描线26连接。参见图3，第二扫描线26可以是与第一扫描线24相邻的扫描线，使得第二控制开关23与相邻的第二扫描线26控制的第一控制开关同时打开，达到电荷共享的目的。
如此，本发明实施例的数据线的排布不同于传统的1G1D方式，本发明实施例的相邻两列像素的数据线并列在一起，相邻第一控制开关以及第二控制开关的开口方向相反。通过通孔的方式将第N行像素的电荷共享线与第N+1行像素的扫描线在面内连接在一起，使得第N行像素的第二控制开关与第N+1行像素的第一控制开关同时打开，达到电荷共享（Charge sharing）的目的，进而实现降低色偏的效果。其中第一通孔连接电荷共享线与第N行像素的第二控制开关的栅极，第二通孔连接电荷共享线与第N+1行像素的扫描线。电荷共享线为ITO薄膜。采用该设计时，数据线上面会有一层带扫描线电位的ITO薄膜，造成数据线负载（Data line Loading）较大，因此需要将数据线进行重新排列，参见图3。这样在连接用ITO薄膜下方无数据线，不会造成数据线负载增大，并且这样的设计相邻两列像素共用连接ITO薄膜就可以，而不需要每一列像素单独用一条ITO薄膜进行连接，减少了通孔的数量。
数据线的排列具体地参见图3，像素结构包括共用第一扫描线24的相邻的第一像素241和第二像素242，第一像素241中的第二控制开关的栅极和第二像素241中的第二控制开关的栅极相同，都通过第一通孔230与共享电荷线25连接。第一像素241中的第一控制开关和第二像素242中的第一控制开关的开口方向相反。像素结构还包括共用第一扫描线24的相邻的第三像素243和第四像素244，第三像素243与第二像素242相邻，第二像素242与第三像素243的数据线并列在一起，第三像素243和第四像素244共用第二控制开关的栅极。共用第一扫描线24的多个像素以第一像素241、第二像素242、第三像素243以及第四像素244为周期进行排列。
另外，第N行的第二控制开关与第N+1行的第一控制开关同时打开。这样的方式可以使得原来的电荷共享线所占的面积大幅度的降低，有利于提高像素的开口率。由于第N行的电荷共享线是在面内与第N+1行的第一扫描线相连的，不占用周边设计区域，有利于实现窄边框，并且这样的方式不需要多光罩。
在本发明实施例中，相邻的多个像素可以共用一条电荷共享线。参见图4，像素结构包括第五像素31以及与第五像素31共用数据线32的相邻的多个像素33。多个像素33中的第二控制开关330的栅极上设置第一通孔331，第五像素31的扫描线310上设置第二通孔311，使得第二控制开关330的栅极通过第一通孔331与电荷共享线332连接，电荷连接线通孔第二通孔311与第五像素31的扫描线310连接，其中第五像素31至少与多个像素33中的一个像素相邻。在图4中，连续相邻的3个像素33、34、35共用一条电荷共享线332。即像素33、34、35的第二控制开关的栅极都设置第一通孔，以使得对应的第二控制开关的栅极通孔第一通孔与电荷共享线332连接。如此，以每4行像素为一个周期，采用第4行像素的扫描线来控制前面三行像素的第二控制开关的栅极，对应的共用共享电荷线的像素的数量为3。在本发明的其他实施例中，共用共享电荷线的多个像素的数量为1、2、3、4中的至少一个。对应的像素结构的周期为2、3、4、5。一个像素的扫描线控制的第二控制开关的栅极所对应的像素的数量不宜再多，否则欠造成扫描线的负载过大。
图5是本发明实施例的液晶显示面板的驱动方法的流程示意图。液晶显示面板包括像素结构，像素结构包括矩阵排列的多个像素。每一像素中包括相邻设置的主像素区以及从像素区。主像素区包括第一像素电极，第一像素电极通过第一控制开关与数据线连接。从像素区包括第二像素电极，第二像素电极通过第二控制开关以及第一控制开关与数据线连接。第一扫描线控制第一控制开关，电荷共享线控制第二控制开关，电荷共享线与不同于第一扫描线的第二扫描线连接。如图5所示，液晶显示面板的驱动方法：
步骤S10：利用第一扫描线控制第一控制开关导通。其中第一扫描线为与第一像素电极对应的扫描线。
步骤S11：利用数据线为主像素区充电以使得第一像素电极形成第一等电位。
步骤S12：利用电荷共享线控制第二控制开关导通以实现电荷共享。
其中，电荷共享线为ITO薄膜，在制作过程中可以与第一像素电极、第二像素电极采用同一光罩进行图案化。当然，电荷共享线也可以采用其他导体，只要是电阻率较低即可。
在本发明实施例中，第二控制开关的栅极上设置有第一通孔，第二扫描线上设置有第二通孔，电荷共享线通过第一通孔与第二控制开关的栅极连接，电荷共享线通过第二通孔与第二扫描线连接。第二扫描线可以是与第一扫描线相邻的扫描线，使得第二控制开关与相邻的第二扫描线控制的第一控制开关同时打开，达到电荷共享的目的。
本发明实施例的数据线的排布不同于传统的1G1D方式，本发明实施例的相邻两列像素的数据线并列在一起，相邻第一控制开关以及第二控制开关的开口方向相反。通过通孔的方式将第N行像素的电荷共享线与第N+1行像素的扫描线在面内连接在一起，使得第N行像素的第二控制开关与第N+1行像素的第一控制开关同时打开，达到电荷共享（Charge sharing）的目的，进而实现降低色偏的效果。其中第一通孔连接电荷共享线与第N行像素的第二控制开关的栅极，第二通孔连接电荷共享线与第N+1行像素的扫描线。电荷共享线为ITO薄膜。采用该设计时，数据线上面会有一层带扫描线电位的ITO薄膜，造成数据线负载（Data line Loading）较大，因此需要将数据线进行重新排列，这样在连接用ITO薄膜下方无数据线，不会造成数据线负载增大，并且这样的设计相邻两列像素共用连接ITO薄膜就可以，而不需要每一列像素单独用一条ITO薄膜进行连接，减少了通孔的数量。
另外，第N行的第二控制开关与第N+1行的第一控制开关同时打开。这样的方式可以使得原来的电荷共享线所占的面积大幅度的降低，有利于提高像素的开口率。由于第N行的电荷共享线是在面内与第N+1行的第一扫描线相连的，不占用周边设计区域，有利于实现窄边框，并且这样的方式不需要多光罩。
在本发明实施例中，像素结构包括共用第一扫描线的相邻的第一像素和第二像素，第一像素中的第二控制开关的栅极和第二像素中的第二控制开关的栅极相同，都通过第一通孔与共享电荷线连接。第一像素中的第一控制开关和第二像素中的第一控制开关的开口方向相反。像素结构还包括共用第一扫描线的相邻的第三像素和第四像素，第三像素与第二像素相邻，第二像素与第三像素的数据线并列在一起，第三像素和第四像素共用第二控制开关的栅极。共用第一扫描线的多个像素以第一像素、第二像素、第三像素以及第四像素为周期进行排列。
在本发明实施例中，相邻的多个像素可以共用一条电荷共享线。像素结构包括第五像素以及与第五像素共用数据线的相邻的多个像素。多个像素中的第二控制开关的栅极上设置第一通孔，第五像素的扫描线上设置第二通孔，使得第二控制开关的栅极通过第一通孔与电荷共享线连接，电荷连接线通孔第二通孔与第五像素的扫描线连接，其中第五像素至少与多个像素中的一个像素相邻。连续相邻的3个像素共用一条电荷共享线。即像素的第二控制开关的栅极都设置第一通孔，以使得对应的第二控制开关的栅极通孔第一通孔与电荷共享线连接。如此，以每4行像素为一个周期，采用第4行像素的扫描线来控制前面三行像素的第二控制开关的栅极，对应的共用共享电荷线的像素的数量为3。在本发明的其他实施例中，共用共享电荷线的多个像素的数量为1、2、3、4中的至少一个。对应的像素结构的周期为2、3、4、5。一个像素的扫描线控制的第二控制开关的栅极所对应的像素的数量不宜再多，否则欠造成扫描线的负载过大。
综上所述，本发明的像素结构包括矩阵排列的多个像素，每一像素中包括相邻设置的主像素区以及从像素区，主像素区包括第一像素电极，第一像素电极通过第一控制开关与数据线连接；从像素区包括第二像素电极，第二像素电极通过第二控制开关以及第一控制开关与第一像素电极连接；第一控制开关的栅极连接第一扫描线，第二控制开关的栅极与电荷共享线连接，电荷共享线与第一扫描线相邻，能够提高像素的开口率，不占用周边设计区域，有利于实现窄边。
以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。

Claims (17)

  1. 一种像素结构，其中，所述像素结构包括矩阵排列的多个像素，每一像素中包括相邻设置的主像素区以及从像素区，所述主像素区包括第一像素电极，所述第一像素电极通过第一控制开关与数据线连接；所述从像素区包括第二像素电极，所述第二像素电极通过第二控制开关以及所述第一控制开关与所述数据线连接；
    第一扫描线控制所述第一控制开关，电荷共享线控制所述第二控制开关，所述电荷共享线与不同于所述第一扫描线的第二扫描线连接。
  2. 根据权利要求1所述的像素结构，其中，所述第二控制开关的栅极上设置有第一通孔，所述第二扫描线上设置有第二通孔，所述电荷共享线通过所述第一通孔与所述第二控制开关的栅极连接，所述电荷共享线通过所述第二通孔与所述第二扫描线连接。
  3. 根据权利要求2所述的像素结构，其中，所述电荷共享线为ITO薄膜，与所述第一像素电极、所述第二像素电极采用同一光罩进行图案化。
  4. 根据权利要求1所述的像素结构，其中，所述像素结构包括共用所述第一扫描线的相邻的第一像素和第二像素，所述第一像素中的所述第二控制开关的栅极和所述第二像素中的所述第二控制开关的栅极相同，所述第一像素中的所述第一控制开关和所述第二像素中的所述第一控制开关的开口方向相反。
  5. 根据权利要求4所述的像素结构，其中，所述像素结构还包括共用所述第一扫描线的相邻的第三像素和第四像素，所述第三像素与所述第二像素相邻，所述第二像素与所述第三像素的数据线并列在一起，所述第三像素和所述第四像素共用第二控制开关的栅极。
  6. 根据权利要求1所述的像素结构，其中，所述像素结构包括第五像素以及与所述第五像素共用所述数据线的相邻的多个像素，所述多个像素的所述第二控制开关的栅极上设置有第一通孔，所述第五像素的扫描线上设置有第二通孔，所述多个像素中的第二控制开关的栅极通过所述第一通孔与所述电荷共享线连接，所述电荷共享线通过所述第二通孔与所述第五像素的扫描线连接，其中所述第五像素与所述多个像素中的一个像素相邻。
  7. 根据权利要求6所述的像素结构，其中，多个像素的数量为1、2、3、4中的至少一个。
  8. 根据权利要求1所述的像素结构，其中，所述主像素区以及所述次像素区设置在阵列基板上，所述阵列基板上还包括横向设置的多条扫描线和纵向设置的多条数据线，所述扫描线均与所述数据线相交，其中：
    所述多个像素中的第2n-1个像素的主像素区和次像素区以及第2n个像素的主像素区和次像素区均设置在第2n-1条扫描线、第2n条扫描线、第2n-1条数据线以及第2n条数据线所围成的区域内，n为正整数。
  9. 一种液晶显示面板，其中，所述液晶显示面板包括像素结构，所述像素结构包括矩阵排列的多个像素，每一像素中包括相邻设置的主像素区以及从像素区，所述主像素区包括第一像素电极，所述第一像素电极通过第一控制开关与数据线连接；所述从像素区包括第二像素电极，所述第二像素电极通过第二控制开关以及所述第一控制开关与所述数据线连接；
    第一扫描线控制所述第一控制开关，电荷共享线控制所述第二控制开关，所述电荷共享线与不同于所述第一扫描线的第二扫描线连接。
  10. 根据权利要求9所述的液晶显示面板，其中，所述第二控制开关的栅极上设置有第一通孔，所述第二扫描线上设置有第二通孔，所述电荷共享线通过所述第一通孔与所述第二控制开关的栅极连接，所述电荷共享线通过所述第二通孔与所述第二扫描线连接。
  11. 根据权利要求10所述的液晶显示面板，其中，所述电荷共享线为ITO薄膜，与所述第一像素电极、所述第二像素电极采用同一光罩进行图案化。
  12. 根据权利要求9所述的液晶显示面板，其中，所述像素结构包括共用所述第一扫描线的相邻的第一像素和第二像素，所述第一像素中的所述第二控制开关的栅极和所述第二像素中的所述第二控制开关的栅极相同，所述第一像素中的所述第一控制开关和所述第二像素中的所述第一控制开关的开口方向相反。
  13. 根据权利要求12所述的液晶显示面板，其中，所述像素结构还包括共用所述第一扫描线的相邻的第三像素和第四像素，所述第三像素与所述第二像素相邻，所述第二像素与所述第三像素的数据线并列在一起，所述第三像素和所述第四像素共用第二控制开关的栅极。
  14. 根据权利要求9所述的液晶显示面板，其中，所述像素结构包括第五像素以及与所述第五像素共用所述数据线的相邻的多个像素，所述多个像素的所述第二控制开关的栅极上设置有第一通孔，所述第五像素的扫描线上设置有第二通孔，所述多个像素中的第二控制开关的栅极通过所述第一通孔与所述电荷共享线连接，所述电荷共享线通过所述第二通孔与所述第五像素的扫描线连接，其中所述第五像素与所述多个像素中的一个像素相邻。
  15. 根据权利要求14所述的液晶显示面板，其中，多个像素的数量为1、2、3、4中的至少一个。
  16. 根据权利要求9所述的液晶显示面板，其中，所述主像素区以及所述次像素区设置在阵列基板上，所述阵列基板上还包括横向设置的多条扫描线和纵向设置的多条数据线，所述扫描线均与所述数据线相交，其中：
    所述多个像素中的第2n-1个像素的主像素区和次像素区以及第2n个像素的主像素区和次像素区均设置在第2n-1条扫描线、第2n条扫描线、第2n-1条数据线以及第2n条数据线所围成的区域内，n为正整数。
  17. 一种液晶显示面板的驱动方法，其中，所述液晶显示面板包括像素结构，所述像素结构包括矩阵排列的多个像素，每一像素中包括相邻设置的主像素区以及从像素区，所述主像素区包括第一像素电极，所述第一像素电极通过第一控制开关与数据线连接；所述从像素区包括第二像素电极，所述第二像素电极通过第二控制开关以及所述第一控制开关与所述第一像素电极连接；第一扫描线控制所述第一控制开关，电荷共享线控制所述第二控制开关，所述电荷共享线与不同于所述第二扫描线连接。液晶显示面板的驱动方法：
    利用所述第一扫描线控制所述第一控制开关导通；
    利用所述数据线为所述主像素区充电以使得所述第一像素电极形成第一等电位；
    利用所述电荷共享线控制所述第二控制开关导通以实现电荷共享。
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